2 CPU C State control methods
4 Copyright (c) 2013-2015 Intel Corporation.
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
25 External(\_PR.CPU0, DeviceObj)
26 External (PDC0, IntObj)
27 External (CFGD, FieldUnitObj)
33 // If CMP is supported, and OSPM is not capable of independent C1, P, T state
34 // support for each processor for multi-processor configuration, we will just report
37 // PDCx[4] = Indicates whether OSPM is not capable of independent C1, P, T state
38 // support for each processor for multi-processor configuration.
40 If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10))))
46 ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
55 // If MWAIT extensions is supported and OSPM is capable of performing
56 // native C state instructions for the C2/C3 in multi-processor configuration,
57 // we report every c state with MWAIT extensions.
59 // PDCx[9] = Indicates whether OSPM is capable of performing native C state instructions
60 // for the C2/C3 in multi-processor configuration
62 If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200)))
65 // If C6 is supported, we report MWAIT C1,C2,C4,C6
73 { // MWAIT C1, hardware coordinated with no bus master avoidance
74 ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
80 { // MWAIT C2, hardware coordinated with no bus master avoidance
81 ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},
87 { // MWAIT C4, hardware coordinated with bus master avoidance enabled
88 ResourceTemplate(){Register(FFixedHW, 1, 2, 0x30, 3)},
94 { // MWAIT C6, hardware coordinated with bus master avoidance enabled
95 ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 3)},
103 // If C4 is supported, we report MWAIT C1,C2,C4
111 { // MWAIT C1, hardware coordinated with no bus master avoidance
112 ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
118 { // MWAIT C2, hardware coordinated with no bus master avoidance
119 ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},
125 { // MWAIT C4, hardware coordinated with bus master avoidance enabled
126 ResourceTemplate(){Register(FFixedHW, 1, 2, 0x30, 3)},
134 // If C2 is supported, we report MWAIT C1,C2
142 { // MWAIT C1, hardware coordinated with no bus master avoidance
143 ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
149 { // MWAIT C2, hardware coordinated with no bus master avoidance
150 ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},
158 // Else we only report MWAIT C1.
164 { // MWAIT C1, hardware coordinated with no bus master avoidance
165 ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
173 // If OSPM is only capable of performing native C state instructions for
174 // the C1 in multi-processor configuration, we report C1 with MWAIT, other
175 // C states with IO method.
177 // PDCx[8] = Indicates whether OSPM is capable of performing native C state instructions
178 // for the C1 in multi-processor configuration
180 If(LAnd(And(CFGD, 0x200000), And(PDC0,0x100)))
183 // If C6 is supported, we report MWAIT C1, IO C2,C4,C6
191 { // MWAIT C1, hardware coordinated with no bus master avoidance
192 ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
198 { // IO C2 ("PMBALVL2" will be updated at runtime)
199 ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},
205 { // IO C4 ("PMBALVL4" will be updated at runtime)
206 ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},
212 { // IO C6 ("PMBALVL6" will be updated at runtime)
213 ResourceTemplate () {Register(SystemIO, 8, 0, 0x364C564C41424D50)},
221 // If C4 is supported, we report MWAIT C1, IO C2,C4
229 { // MWAIT C1, hardware coordinated with no bus master avoidance
230 ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
236 { // IO C2 ("PMBALVL2" will be updated at runtime)
237 ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},
243 { // IO C4 ("PMBALVL4" will be updated at runtime)
244 ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},
252 // If C2 is supported, we report MWAIT C1, IO C2
260 { // MWAIT C1, hardware coordinated with no bus master avoidance
261 ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
267 { // IO C2 ("PMBALVL2" will be updated at runtime)
268 ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},
276 // Else we only report MWAIT C1.
282 { // MWAIT C1, hardware coordinated with no bus master avoidance
283 ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
292 // If MWAIT is not supported, we report all the c states with IO method
296 // If C6 is supported, we report C1 halt, IO C2,C4,C6
305 ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},
311 { // IO C2 ("PMBALVL2" will be updated at runtime)
312 ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},
318 { // IO C4 ("PMBALVL4" will be updated at runtime)
319 ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},
325 { // IO C6 ("PMBALVL6" will be updated at runtime)
326 ResourceTemplate () {Register(SystemIO, 8, 0, 0x364C564C41424D50)},
334 // If C4 is supported, we report C1 halt, IO C2,C4
343 ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},
349 { // IO C2 ("PMBALVL2" will be updated at runtime)
350 ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},
356 { // IO C4 ("PMBALVL4" will be updated at runtime)
357 ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},
366 // If C2 is supported, we report C1 halt, IO C2
375 ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},
381 { // IO C2 ("PMBALVL2" will be updated at runtime)
382 ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},
390 // Else we only report C1 halt.
397 ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},