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QuarkPlatformPkg: Add new package for Galileo boards
[mirror_edk2.git] / QuarkPlatformPkg / Library / PlatformHelperLib / PlatformHelperDxe.c
1 /** @file
2 Implementation of helper routines for DXE environment.
3
4 Copyright (c) 2013 Intel Corporation.
5
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #include <PiDxe.h>
17
18 #include <Library/UefiBootServicesTableLib.h>
19 #include <Library/S3BootScriptLib.h>
20 #include <Library/DxeServicesLib.h>
21 #include <Library/UefiRuntimeServicesTableLib.h>
22 #include <Library/I2cLib.h>
23 #include <Protocol/SmmBase2.h>
24 #include <Protocol/Spi.h>
25 #include <Protocol/VariableLock.h>
26
27 #include <Guid/MemoryConfigData.h>
28 #include <Guid/QuarkVariableLock.h>
29
30 #include "CommonHeader.h"
31
32 #define FLASH_BLOCK_SIZE SIZE_4KB
33
34 //
35 // Global variables.
36 //
37 EFI_SPI_PROTOCOL *mPlatHelpSpiProtocolRef = NULL;
38
39 //
40 // Routines defined in other source modules of this component.
41 //
42
43 //
44 // Routines local to this component.
45 //
46
47 //
48 // Routines shared with other souce modules in this component.
49 //
50
51 BOOLEAN
52 Pcal9555GetPortRegBit (
53 IN CONST UINT32 Pcal9555SlaveAddr,
54 IN CONST UINT32 GpioNum,
55 IN CONST UINT8 RegBase
56 )
57 {
58 EFI_STATUS Status;
59 UINTN ReadLength;
60 UINTN WriteLength;
61 UINT8 Data[2];
62 EFI_I2C_DEVICE_ADDRESS I2cDeviceAddr;
63 EFI_I2C_ADDR_MODE I2cAddrMode;
64 UINT8 *RegValuePtr;
65 UINT8 GpioNumMask;
66 UINT8 SubAddr;
67
68 I2cDeviceAddr.I2CDeviceAddress = (UINTN) Pcal9555SlaveAddr;
69 I2cAddrMode = EfiI2CSevenBitAddrMode;
70
71 if (GpioNum < 8) {
72 SubAddr = RegBase;
73 GpioNumMask = (UINT8) (1 << GpioNum);
74 } else {
75 SubAddr = RegBase + 1;
76 GpioNumMask = (UINT8) (1 << (GpioNum - 8));
77 }
78
79 //
80 // Output port value always at 2nd byte in Data variable.
81 //
82 RegValuePtr = &Data[1];
83
84 //
85 // On read entry sub address at 2nd byte, on read exit output
86 // port value in 2nd byte.
87 //
88 Data[1] = SubAddr;
89 WriteLength = 1;
90 ReadLength = 1;
91 Status = I2cReadMultipleByte (
92 I2cDeviceAddr,
93 I2cAddrMode,
94 &WriteLength,
95 &ReadLength,
96 &Data[1]
97 );
98 ASSERT_EFI_ERROR (Status);
99
100 //
101 // Adjust output port bit given callers request.
102 //
103 return ((*RegValuePtr & GpioNumMask) != 0);
104 }
105
106 VOID
107 Pcal9555SetPortRegBit (
108 IN CONST UINT32 Pcal9555SlaveAddr,
109 IN CONST UINT32 GpioNum,
110 IN CONST UINT8 RegBase,
111 IN CONST BOOLEAN LogicOne
112 )
113 {
114 EFI_STATUS Status;
115 UINTN ReadLength;
116 UINTN WriteLength;
117 UINT8 Data[2];
118 EFI_I2C_DEVICE_ADDRESS I2cDeviceAddr;
119 EFI_I2C_ADDR_MODE I2cAddrMode;
120 UINT8 *RegValuePtr;
121 UINT8 GpioNumMask;
122 UINT8 SubAddr;
123
124 I2cDeviceAddr.I2CDeviceAddress = (UINTN) Pcal9555SlaveAddr;
125 I2cAddrMode = EfiI2CSevenBitAddrMode;
126
127 if (GpioNum < 8) {
128 SubAddr = RegBase;
129 GpioNumMask = (UINT8) (1 << GpioNum);
130 } else {
131 SubAddr = RegBase + 1;
132 GpioNumMask = (UINT8) (1 << (GpioNum - 8));
133 }
134
135 //
136 // Output port value always at 2nd byte in Data variable.
137 //
138 RegValuePtr = &Data[1];
139
140 //
141 // On read entry sub address at 2nd byte, on read exit output
142 // port value in 2nd byte.
143 //
144 Data[1] = SubAddr;
145 WriteLength = 1;
146 ReadLength = 1;
147 Status = I2cReadMultipleByte (
148 I2cDeviceAddr,
149 I2cAddrMode,
150 &WriteLength,
151 &ReadLength,
152 &Data[1]
153 );
154 ASSERT_EFI_ERROR (Status);
155
156 //
157 // Adjust output port bit given callers request.
158 //
159 if (LogicOne) {
160 *RegValuePtr = *RegValuePtr | GpioNumMask;
161 } else {
162 *RegValuePtr = *RegValuePtr & ~(GpioNumMask);
163 }
164
165 //
166 // Update register. Sub address at 1st byte, value at 2nd byte.
167 //
168 WriteLength = 2;
169 Data[0] = SubAddr;
170 Status = I2cWriteMultipleByte (
171 I2cDeviceAddr,
172 I2cAddrMode,
173 &WriteLength,
174 Data
175 );
176 ASSERT_EFI_ERROR (Status);
177 }
178
179
180 EFI_SPI_PROTOCOL *
181 LocateSpiProtocol (
182 IN EFI_SMM_SYSTEM_TABLE2 *Smst
183 )
184 {
185 if (mPlatHelpSpiProtocolRef == NULL) {
186 if (Smst != NULL) {
187 Smst->SmmLocateProtocol (
188 &gEfiSmmSpiProtocolGuid,
189 NULL,
190 (VOID **) &mPlatHelpSpiProtocolRef
191 );
192 } else {
193 gBS->LocateProtocol (
194 &gEfiSpiProtocolGuid,
195 NULL,
196 (VOID **) &mPlatHelpSpiProtocolRef
197 );
198 }
199 ASSERT (mPlatHelpSpiProtocolRef != NULL);
200 }
201 return mPlatHelpSpiProtocolRef;
202 }
203
204 //
205 // Routines exported by this source module.
206 //
207
208 /**
209 Find pointer to RAW data in Firmware volume file.
210
211 @param FvNameGuid Firmware volume to search. If == NULL search all.
212 @param FileNameGuid Firmware volume file to search for.
213 @param SectionData Pointer to RAW data section of found file.
214 @param SectionDataSize Pointer to UNITN to get size of RAW data.
215
216 @retval EFI_SUCCESS Raw Data found.
217 @retval EFI_INVALID_PARAMETER FileNameGuid == NULL.
218 @retval EFI_NOT_FOUND Firmware volume file not found.
219 @retval EFI_UNSUPPORTED Unsupported in current enviroment (PEI or DXE).
220
221 **/
222 EFI_STATUS
223 EFIAPI
224 PlatformFindFvFileRawDataSection (
225 IN CONST EFI_GUID *FvNameGuid OPTIONAL,
226 IN CONST EFI_GUID *FileNameGuid,
227 OUT VOID **SectionData,
228 OUT UINTN *SectionDataSize
229 )
230 {
231 if (FileNameGuid == NULL || SectionData == NULL || SectionDataSize == NULL) {
232 return EFI_INVALID_PARAMETER;
233 }
234 if (FvNameGuid != NULL) {
235 return EFI_UNSUPPORTED; // Searching in specific FV unsupported in DXE.
236 }
237
238 return GetSectionFromAnyFv (FileNameGuid, EFI_SECTION_RAW, 0, SectionData, SectionDataSize);
239 }
240
241 /**
242 Find free spi protect register and write to it to protect a flash region.
243
244 @param DirectValue Value to directly write to register.
245 if DirectValue == 0 the use Base & Length below.
246 @param BaseAddress Base address of region in Flash Memory Map.
247 @param Length Length of region to protect.
248
249 @retval EFI_SUCCESS Free spi protect register found & written.
250 @retval EFI_NOT_FOUND Free Spi protect register not found.
251 @retval EFI_DEVICE_ERROR Unable to write to spi protect register.
252 **/
253 EFI_STATUS
254 EFIAPI
255 PlatformWriteFirstFreeSpiProtect (
256 IN CONST UINT32 DirectValue,
257 IN CONST UINT32 BaseAddress,
258 IN CONST UINT32 Length
259 )
260 {
261 UINT32 FreeOffset;
262 UINT32 PchRootComplexBar;
263 EFI_STATUS Status;
264
265 PchRootComplexBar = QNC_RCRB_BASE;
266
267 Status = WriteFirstFreeSpiProtect (
268 PchRootComplexBar,
269 DirectValue,
270 BaseAddress,
271 Length,
272 &FreeOffset
273 );
274
275 if (!EFI_ERROR (Status)) {
276 S3BootScriptSaveMemWrite (
277 S3BootScriptWidthUint32,
278 (UINTN) (PchRootComplexBar + FreeOffset),
279 1,
280 (VOID *) (UINTN) (PchRootComplexBar + FreeOffset)
281 );
282 }
283
284 return Status;
285 }
286
287 /**
288 Lock legacy SPI static configuration information.
289
290 Function will assert if unable to lock config.
291
292 **/
293 VOID
294 EFIAPI
295 PlatformFlashLockConfig (
296 VOID
297 )
298 {
299 EFI_STATUS Status;
300 EFI_SPI_PROTOCOL *SpiProtocol;
301
302 //
303 // Enable lock of legacy SPI static configuration information.
304 //
305
306 SpiProtocol = LocateSpiProtocol (NULL); // This routine will not be called in SMM.
307 ASSERT_EFI_ERROR (SpiProtocol != NULL);
308 if (SpiProtocol != NULL) {
309 Status = SpiProtocol->Lock (SpiProtocol);
310
311 if (!EFI_ERROR (Status)) {
312 DEBUG ((EFI_D_INFO, "Platform: Spi Config Locked Down\n"));
313 } else if (Status == EFI_ACCESS_DENIED) {
314 DEBUG ((EFI_D_INFO, "Platform: Spi Config already locked down\n"));
315 } else {
316 ASSERT_EFI_ERROR (Status);
317 }
318 }
319 }
320
321 /**
322 Platform Variable Lock.
323
324 @retval EFI_SUCCESS Platform Variable Lock successful.
325 @retval EFI_NOT_FOUND No protocol instances were found that match Protocol and
326 Registration.
327
328 **/
329 VOID
330 EFIAPI
331 PlatformVariableLock (
332 )
333 {
334 EFI_STATUS Status;
335 EDKII_VARIABLE_LOCK_PROTOCOL *VariableLockProtocol;
336
337 Status = gBS->LocateProtocol (&gEdkiiVariableLockProtocolGuid, NULL, (VOID **)&VariableLockProtocol);
338 ASSERT_EFI_ERROR (Status);
339
340 Status = VariableLockProtocol->RequestToLock (
341 VariableLockProtocol,
342 QUARK_VARIABLE_LOCK_NAME,
343 &gQuarkVariableLockGuid
344 );
345 ASSERT_EFI_ERROR (Status);
346
347 // Memory Config Data shouldn't be writable when Quark Variable Lock is enabled.
348 Status = VariableLockProtocol->RequestToLock (
349 VariableLockProtocol,
350 EFI_MEMORY_CONFIG_DATA_NAME,
351 &gEfiMemoryConfigDataGuid
352 );
353 ASSERT_EFI_ERROR (Status);
354 }
355
356 /**
357 Lock regions and config of SPI flash given the policy for this platform.
358
359 Function will assert if unable to lock regions or config.
360
361 @param PreBootPolicy If TRUE do Pre Boot Flash Lock Policy.
362
363 **/
364 VOID
365 EFIAPI
366 PlatformFlashLockPolicy (
367 IN CONST BOOLEAN PreBootPolicy
368 )
369 {
370 EFI_STATUS Status;
371 UINT64 CpuAddressNvStorage;
372 UINT64 CpuAddressFlashDevice;
373 UINT64 SpiAddress;
374 EFI_BOOT_MODE BootMode;
375 UINTN SpiFlashDeviceSize;
376
377 BootMode = GetBootModeHob ();
378
379 SpiFlashDeviceSize = (UINTN) PcdGet32 (PcdSpiFlashDeviceSize);
380 CpuAddressFlashDevice = SIZE_4GB - SpiFlashDeviceSize;
381 DEBUG (
382 (EFI_D_INFO,
383 "Platform:FlashDeviceSize = 0x%08x Bytes\n",
384 SpiFlashDeviceSize)
385 );
386
387 //
388 // If not in update or recovery mode, lock stuff down
389 //
390 if ((BootMode != BOOT_IN_RECOVERY_MODE) && (BootMode != BOOT_ON_FLASH_UPDATE)) {
391
392 //
393 // Lock regions
394 //
395 CpuAddressNvStorage = (UINT64) PcdGet32 (PcdFlashNvStorageVariableBase);
396
397 //
398 // Lock from start of flash device up to Smi writable flash storage areas.
399 //
400 SpiAddress = 0;
401 if (!PlatformIsSpiRangeProtected ((UINT32) SpiAddress, (UINT32) (CpuAddressNvStorage - CpuAddressFlashDevice))) {
402 DEBUG (
403 (EFI_D_INFO,
404 "Platform: Protect Region Base:Len 0x%08x:0x%08x\n",
405 (UINTN) SpiAddress, (UINTN)(CpuAddressNvStorage - CpuAddressFlashDevice))
406 );
407 Status = PlatformWriteFirstFreeSpiProtect (
408 0,
409 (UINT32) SpiAddress,
410 (UINT32) (CpuAddressNvStorage - CpuAddressFlashDevice)
411 );
412
413 ASSERT_EFI_ERROR (Status);
414 }
415 //
416 // Move Spi Address to after Smi writable flash storage areas.
417 //
418 SpiAddress = CpuAddressNvStorage - CpuAddressFlashDevice;
419 SpiAddress += ((UINT64) PcdGet32 (PcdFlashNvStorageVariableSize));
420
421 //
422 // Lock from end of OEM area to end of flash part.
423 //
424 if (!PlatformIsSpiRangeProtected ((UINT32) SpiAddress, SpiFlashDeviceSize - ((UINT32) SpiAddress))) {
425 DEBUG (
426 (EFI_D_INFO,
427 "Platform: Protect Region Base:Len 0x%08x:0x%08x\n",
428 (UINTN) SpiAddress,
429 (UINTN) (SpiFlashDeviceSize - ((UINT32) SpiAddress)))
430 );
431 ASSERT (SpiAddress < ((UINT64) SpiFlashDeviceSize));
432 Status = PlatformWriteFirstFreeSpiProtect (
433 0,
434 (UINT32) SpiAddress,
435 SpiFlashDeviceSize - ((UINT32) SpiAddress)
436 );
437
438 ASSERT_EFI_ERROR (Status);
439 }
440 }
441
442 //
443 // Always Lock flash config registers if about to boot a boot option
444 // else lock depending on boot mode.
445 //
446 if (PreBootPolicy || (BootMode != BOOT_ON_FLASH_UPDATE)) {
447 PlatformFlashLockConfig ();
448 }
449
450 //
451 // Enable Quark Variable lock if PreBootPolicy.
452 //
453 if (PreBootPolicy) {
454 PlatformVariableLock ();
455 }
456 }
457
458 /**
459 Erase and Write to platform flash.
460
461 Routine accesses one flash block at a time, each access consists
462 of an erase followed by a write of FLASH_BLOCK_SIZE. One or both
463 of DoErase & DoWrite params must be TRUE.
464
465 Limitations:-
466 CpuWriteAddress must be aligned to FLASH_BLOCK_SIZE.
467 DataSize must be a multiple of FLASH_BLOCK_SIZE.
468
469 @param Smst If != NULL then InSmm and use to locate
470 SpiProtocol.
471 @param CpuWriteAddress Address in CPU memory map of flash region.
472 @param Data The buffer containing the data to be written.
473 @param DataSize Amount of data to write.
474 @param DoErase Earse each block.
475 @param DoWrite Write to each block.
476
477 @retval EFI_SUCCESS Operation successful.
478 @retval EFI_NOT_READY Required resources not setup.
479 @retval EFI_INVALID_PARAMETER Invalid parameter.
480 @retval Others Unexpected error happened.
481
482 **/
483 EFI_STATUS
484 EFIAPI
485 PlatformFlashEraseWrite (
486 IN VOID *Smst,
487 IN UINTN CpuWriteAddress,
488 IN UINT8 *Data,
489 IN UINTN DataSize,
490 IN BOOLEAN DoErase,
491 IN BOOLEAN DoWrite
492 )
493 {
494 EFI_STATUS Status;
495 UINT64 CpuBaseAddress;
496 SPI_INIT_INFO *SpiInfo;
497 UINT8 *WriteBuf;
498 UINTN Index;
499 UINTN SpiWriteAddress;
500 EFI_SPI_PROTOCOL *SpiProtocol;
501
502 if (!DoErase && !DoWrite) {
503 return EFI_INVALID_PARAMETER;
504 }
505 if (DoWrite && Data == NULL) {
506 return EFI_INVALID_PARAMETER;
507 }
508 if ((CpuWriteAddress % FLASH_BLOCK_SIZE) != 0) {
509 return EFI_INVALID_PARAMETER;
510 }
511 if ((DataSize % FLASH_BLOCK_SIZE) != 0) {
512 return EFI_INVALID_PARAMETER;
513 }
514 SpiProtocol = LocateSpiProtocol ((EFI_SMM_SYSTEM_TABLE2 *)Smst);
515 if (SpiProtocol == NULL) {
516 return EFI_NOT_READY;
517 }
518
519 //
520 // Find info to allow usage of SpiProtocol->Execute.
521 //
522 Status = SpiProtocol->Info (
523 SpiProtocol,
524 &SpiInfo
525 );
526 if (EFI_ERROR(Status)) {
527 return Status;
528 }
529 ASSERT (SpiInfo->InitTable != NULL);
530 ASSERT (SpiInfo->EraseOpcodeIndex < SPI_NUM_OPCODE);
531 ASSERT (SpiInfo->ProgramOpcodeIndex < SPI_NUM_OPCODE);
532
533 CpuBaseAddress = PcdGet32 (PcdFlashAreaBaseAddress) - (UINT32)SpiInfo->InitTable->BiosStartOffset;
534 ASSERT(CpuBaseAddress >= (SIZE_4GB - SIZE_8MB));
535 if (CpuWriteAddress < CpuBaseAddress) {
536 return (EFI_INVALID_PARAMETER);
537 }
538
539 SpiWriteAddress = CpuWriteAddress - ((UINTN) CpuBaseAddress);
540 WriteBuf = Data;
541 DEBUG (
542 (EFI_D_INFO, "PlatformFlashWrite:SpiWriteAddress=%08x EraseIndex=%d WriteIndex=%d\n",
543 SpiWriteAddress,
544 (UINTN) SpiInfo->EraseOpcodeIndex,
545 (UINTN) SpiInfo->ProgramOpcodeIndex
546 ));
547 for (Index =0; Index < DataSize / FLASH_BLOCK_SIZE; Index++) {
548 if (DoErase) {
549 DEBUG (
550 (EFI_D_INFO, "PlatformFlashWrite:Erase[%04x] SpiWriteAddress=%08x\n",
551 Index,
552 SpiWriteAddress
553 ));
554 Status = SpiProtocol->Execute (
555 SpiProtocol,
556 SpiInfo->EraseOpcodeIndex,// OpcodeIndex
557 0, // PrefixOpcodeIndex
558 FALSE, // DataCycle
559 TRUE, // Atomic
560 FALSE, // ShiftOut
561 SpiWriteAddress, // Address
562 0, // Data Number
563 NULL,
564 EnumSpiRegionAll // SPI_REGION_TYPE
565 );
566 if (EFI_ERROR(Status)) {
567 return Status;
568 }
569 }
570
571 if (DoWrite) {
572 DEBUG (
573 (EFI_D_INFO, "PlatformFlashWrite:Write[%04x] SpiWriteAddress=%08x\n",
574 Index,
575 SpiWriteAddress
576 ));
577 Status = SpiProtocol->Execute (
578 SpiProtocol,
579 SpiInfo->ProgramOpcodeIndex, // OpcodeIndex
580 0, // PrefixOpcodeIndex
581 TRUE, // DataCycle
582 TRUE, // Atomic
583 TRUE, // ShiftOut
584 SpiWriteAddress, // Address
585 FLASH_BLOCK_SIZE, // Data Number
586 WriteBuf,
587 EnumSpiRegionAll
588 );
589 if (EFI_ERROR(Status)) {
590 return Status;
591 }
592 WriteBuf+=FLASH_BLOCK_SIZE;
593 }
594 SpiWriteAddress+=FLASH_BLOCK_SIZE;
595 }
596 return EFI_SUCCESS;
597 }
598
599 /** Check if System booted with recovery Boot Stage1 image.
600
601 @retval TRUE If system booted with recovery Boot Stage1 image.
602 @retval FALSE If system booted with normal stage1 image.
603
604 **/
605 BOOLEAN
606 EFIAPI
607 PlatformIsBootWithRecoveryStage1 (
608 VOID
609 )
610 {
611 ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
612 return FALSE;
613 }
614
615 /**
616 Set the direction of Pcal9555 IO Expander GPIO pin.
617
618 @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
619 @param GpioNum Gpio direction to configure - values 0-7 for Port0
620 and 8-15 for Port1.
621 @param CfgAsInput If TRUE set pin direction as input else set as output.
622
623 **/
624 VOID
625 EFIAPI
626 PlatformPcal9555GpioSetDir (
627 IN CONST UINT32 Pcal9555SlaveAddr,
628 IN CONST UINT32 GpioNum,
629 IN CONST BOOLEAN CfgAsInput
630 )
631 {
632 Pcal9555SetPortRegBit (
633 Pcal9555SlaveAddr,
634 GpioNum,
635 PCAL9555_REG_CFG_PORT0,
636 CfgAsInput
637 );
638 }
639
640 /**
641 Set the level of Pcal9555 IO Expander GPIO high or low.
642
643 @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
644 @param GpioNum Gpio to change values 0-7 for Port0 and 8-15
645 for Port1.
646 @param HighLevel If TRUE set pin high else set pin low.
647
648 **/
649 VOID
650 EFIAPI
651 PlatformPcal9555GpioSetLevel (
652 IN CONST UINT32 Pcal9555SlaveAddr,
653 IN CONST UINT32 GpioNum,
654 IN CONST BOOLEAN HighLevel
655 )
656 {
657 Pcal9555SetPortRegBit (
658 Pcal9555SlaveAddr,
659 GpioNum,
660 PCAL9555_REG_OUT_PORT0,
661 HighLevel
662 );
663 }
664
665 /**
666
667 Enable pull-up/pull-down resistors of Pcal9555 GPIOs.
668
669 @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
670 @param GpioNum Gpio to change values 0-7 for Port0 and 8-15
671 for Port1.
672
673 **/
674 VOID
675 EFIAPI
676 PlatformPcal9555GpioEnablePull (
677 IN CONST UINT32 Pcal9555SlaveAddr,
678 IN CONST UINT32 GpioNum
679 )
680 {
681 Pcal9555SetPortRegBit (
682 Pcal9555SlaveAddr,
683 GpioNum,
684 PCAL9555_REG_PULL_EN_PORT0,
685 TRUE
686 );
687 }
688
689 /**
690
691 Disable pull-up/pull-down resistors of Pcal9555 GPIOs.
692
693 @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
694 @param GpioNum Gpio to change values 0-7 for Port0 and 8-15
695 for Port1.
696
697 **/
698 VOID
699 EFIAPI
700 PlatformPcal9555GpioDisablePull (
701 IN CONST UINT32 Pcal9555SlaveAddr,
702 IN CONST UINT32 GpioNum
703 )
704 {
705 Pcal9555SetPortRegBit (
706 Pcal9555SlaveAddr,
707 GpioNum,
708 PCAL9555_REG_PULL_EN_PORT0,
709 FALSE
710 );
711 }
712
713 /**
714
715 Get state of Pcal9555 GPIOs.
716
717 @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
718 @param GpioNum Gpio to change values 0-7 for Port0 and 8-15
719 for Port1.
720
721 @retval TRUE GPIO pin is high
722 @retval FALSE GPIO pin is low
723 **/
724 BOOLEAN
725 EFIAPI
726 PlatformPcal9555GpioGetState (
727 IN CONST UINT32 Pcal9555SlaveAddr,
728 IN CONST UINT32 GpioNum
729 )
730 {
731 return Pcal9555GetPortRegBit (Pcal9555SlaveAddr, GpioNum, PCAL9555_REG_IN_PORT0);
732 }
EFI Development Kit II mirror for PVE