QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperLib.c

   1 /** @file
   2 Helper routines with common PEI / DXE implementation.
   3
   4 Copyright (c) 2013-2015 Intel Corporation.
   5
   6 This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #include "CommonHeader.h"
  17
  18 CHAR16 *mPlatTypeNameTable[]  = { EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION };
  19 UINTN mPlatTypeNameTableLen  = ((sizeof(mPlatTypeNameTable)) / sizeof (CHAR16 *));
  20
  21 //
  22 // Routines defined in other source modules of this component.
  23 //
  24
  25 //
  26 // Routines local to this source module.
  27 //
  28
  29 //
  30 // Routines shared with other souce modules in this component.
  31 //
  32
  33 EFI_STATUS
  34 WriteFirstFreeSpiProtect (
  35   IN CONST UINT32                         PchRootComplexBar,
  36   IN CONST UINT32                         DirectValue,
  37   IN CONST UINT32                         BaseAddress,
  38   IN CONST UINT32                         Length,
  39   OUT UINT32                              *OffsetPtr
  40   )
  41 {
  42   UINT32                            RegVal;
  43   UINT32                            Offset;
  44   UINT32                            StepLen;
  45
  46   ASSERT (PchRootComplexBar > 0);
  47
  48   Offset = 0;
  49   if (OffsetPtr != NULL) {
  50     *OffsetPtr = Offset;
  51   }
  52   if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) == 0) {
  53     Offset = R_QNC_RCRB_SPIPBR0;
  54   } else {
  55     if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR1) == 0) {
  56       Offset = R_QNC_RCRB_SPIPBR1;
  57     } else {
  58       if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR2) == 0) {
  59         Offset = R_QNC_RCRB_SPIPBR2;
  60       }
  61     }
  62   }
  63   if (Offset != 0) {
  64     if (DirectValue == 0) {
  65       StepLen = ALIGN_VALUE (Length,SIZE_4KB);   // Bring up to 4K boundary.
  66       RegVal = BaseAddress + StepLen - 1;
  67       RegVal &= 0x00FFF000;                     // Set EDS Protected Range Limit (PRL).
  68       RegVal |= ((BaseAddress >> 12) & 0xfff);  // or in EDS Protected Range Base (PRB).
  69     } else {
  70       RegVal = DirectValue;
  71     }
  72     //
  73     // Enable protection.
  74     //
  75     RegVal |= B_QNC_RCRB_SPIPBRn_WPE;
  76     MmioWrite32 (PchRootComplexBar + Offset, RegVal);
  77     if (RegVal == MmioRead32 (PchRootComplexBar + Offset)) {
  78       if (OffsetPtr != NULL) {
  79         *OffsetPtr = Offset;
  80       }
  81       return EFI_SUCCESS;
  82     }
  83     return EFI_DEVICE_ERROR;
  84   }
  85   return EFI_NOT_FOUND;
  86 }
  87
  88 //
  89 // Routines exported by this component.
  90 //
  91
  92 /**
  93   Read 8bit character from debug stream.
  94
  95   Block until character is read.
  96
  97   @return 8bit character read from debug stream.
  98
  99 **/
 100 CHAR8
 101 EFIAPI
 102 PlatformDebugPortGetChar8 (
 103   VOID
 104   )
 105 {
 106   CHAR8                             Got;
 107
 108   do {
 109     if (SerialPortPoll ()) {
 110       if (SerialPortRead ((UINT8 *) &Got, 1) == 1) {
 111         break;
 112       }
 113     }
 114   } while (TRUE);
 115
 116   return Got;
 117 }
 118
 119 /**
 120   Clear SPI Protect registers.
 121
 122   @retval EFI_SUCCESS        SPI protect registers cleared.
 123   @retval EFI_ACCESS_DENIED  Unable to clear SPI protect registers.
 124 **/
 125
 126 EFI_STATUS
 127 EFIAPI
 128 PlatformClearSpiProtect (
 129   VOID
 130   )
 131 {
 132   UINT32                            PchRootComplexBar;
 133
 134   PchRootComplexBar = QNC_RCRB_BASE;
 135   //
 136   // Check if the SPI interface has been locked-down.
 137   //
 138   if ((MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS) & B_QNC_RCRB_SPIS_SCL) != 0) {
 139     return EFI_ACCESS_DENIED;
 140   }
 141   MmioWrite32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0, 0);
 142   if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) {
 143     return EFI_ACCESS_DENIED;
 144   }
 145   MmioWrite32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR1, 0);
 146   if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) {
 147     return EFI_ACCESS_DENIED;
 148   }
 149   MmioWrite32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR2, 0);
 150   if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) {
 151     return EFI_ACCESS_DENIED;
 152   }
 153   return EFI_SUCCESS;
 154 }
 155
 156 /**
 157   Determine if an SPI address range is protected.
 158
 159   @param  SpiBaseAddress  Base of SPI range.
 160   @param  Length          Length of SPI range.
 161
 162   @retval TRUE       Range is protected.
 163   @retval FALSE      Range is not protected.
 164 **/
 165 BOOLEAN
 166 EFIAPI
 167 PlatformIsSpiRangeProtected (
 168   IN CONST UINT32                         SpiBaseAddress,
 169   IN CONST UINT32                         Length
 170   )
 171 {
 172   UINT32                            RegVal;
 173   UINT32                            Offset;
 174   UINT32                            Limit;
 175   UINT32                            ProtectedBase;
 176   UINT32                            ProtectedLimit;
 177   UINT32                            PchRootComplexBar;
 178
 179   PchRootComplexBar = QNC_RCRB_BASE;
 180
 181   if (Length > 0) {
 182     Offset = R_QNC_RCRB_SPIPBR0;
 183     Limit = SpiBaseAddress + (Length - 1);
 184     do {
 185       RegVal = MmioRead32 (PchRootComplexBar + Offset);
 186       if ((RegVal & B_QNC_RCRB_SPIPBRn_WPE) != 0) {
 187         ProtectedBase = (RegVal & 0xfff) << 12;
 188         ProtectedLimit = (RegVal & 0x00fff000) + 0xfff;
 189         if (SpiBaseAddress >= ProtectedBase && Limit <= ProtectedLimit) {
 190           return TRUE;
 191         }
 192       }
 193       if (Offset == R_QNC_RCRB_SPIPBR0) {
 194         Offset = R_QNC_RCRB_SPIPBR1;
 195       } else if (Offset == R_QNC_RCRB_SPIPBR1) {
 196         Offset = R_QNC_RCRB_SPIPBR2;
 197       } else {
 198         break;
 199       }
 200     } while (TRUE);
 201   }
 202   return FALSE;
 203 }
 204
 205 /**
 206   Set Legacy GPIO Level
 207
 208   @param  LevelRegOffset      GPIO level register Offset from GPIO Base Address.
 209   @param  GpioNum             GPIO bit to change.
 210   @param  HighLevel           If TRUE set GPIO High else Set GPIO low.
 211
 212 **/
 213 VOID
 214 EFIAPI
 215 PlatformLegacyGpioSetLevel (
 216   IN CONST UINT32       LevelRegOffset,
 217   IN CONST UINT32       GpioNum,
 218   IN CONST BOOLEAN      HighLevel
 219   )
 220 {
 221   UINT32  RegValue;
 222   UINT32  GpioBaseAddress;
 223   UINT32  GpioNumMask;
 224
 225   GpioBaseAddress =  LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK;
 226   ASSERT (GpioBaseAddress > 0);
 227
 228   RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset);
 229   GpioNumMask = (1 << GpioNum);
 230   if (HighLevel) {
 231     RegValue |= (GpioNumMask);
 232   } else {
 233     RegValue &= ~(GpioNumMask);
 234   }
 235   IoWrite32 (GpioBaseAddress + LevelRegOffset, RegValue);
 236 }
 237
 238 /**
 239   Get Legacy GPIO Level
 240
 241   @param  LevelRegOffset      GPIO level register Offset from GPIO Base Address.
 242   @param  GpioNum             GPIO bit to check.
 243
 244   @retval TRUE       If bit is SET.
 245   @retval FALSE      If bit is CLEAR.
 246
 247 **/
 248 BOOLEAN
 249 EFIAPI
 250 PlatformLegacyGpioGetLevel (
 251   IN CONST UINT32       LevelRegOffset,
 252   IN CONST UINT32       GpioNum
 253   )
 254 {
 255   UINT32  RegValue;
 256   UINT32  GpioBaseAddress;
 257   UINT32  GpioNumMask;
 258
 259   GpioBaseAddress =  LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK;
 260   RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset);
 261   GpioNumMask = (1 << GpioNum);
 262   return ((RegValue & GpioNumMask) != 0);
 263 }