2 Essential platform configuration.
4 Copyright (c) 2013 Intel Corporation.
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include "PlatformInitDxe.h"
20 // The protocols, PPI and GUID defintions for this module
24 // The Library classes this module consumes
28 // RTC:28208 - System hang/crash when entering probe mode(ITP) when relocating SMBASE
29 // Workaround to make default SMRAM UnCachable
31 #define SMM_DEFAULT_SMBASE 0x30000 // Default SMBASE address
32 #define SMM_DEFAULT_SMBASE_SIZE_BYTES 0x10000 // Size in bytes of default SMRAM
34 BOOLEAN mMemCfgDone
= FALSE
;
35 UINT8 ChipsetDefaultMac
[6] = {0xff,0xff,0xff,0xff,0xff,0xff};
39 PlatformInitializeUart0MuxGalileo (
47 This is the routine to initialize UART0 for DBG2 support. The hardware used in this process is a
48 Legacy Bridge (Legacy GPIO), I2C controller, a bi-directional MUX and a Cypress CY8C9540A chip.
61 EFI_I2C_DEVICE_ADDRESS I2CSlaveAddress
;
65 if (PlatformLegacyGpioGetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL
, GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO
)) {
66 I2CSlaveAddress
.I2CDeviceAddress
= GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR
;
68 I2CSlaveAddress
.I2CDeviceAddress
= GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR
;
72 // Set GPIO_SUS<2> as an output, raise voltage to Vdd.
74 PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL
, 2, TRUE
);
80 Buffer
[0] = 0x18; //sub-address
81 Buffer
[1] = 0x03; //data
83 Status
= I2cWriteMultipleByte (
85 EfiI2CSevenBitAddrMode
,
89 ASSERT_EFI_ERROR (Status
);
92 // Set "Pin Direction" bit4 and bit5 as outputs
95 Buffer
[0] = 0x1C; //sub-address
96 Buffer
[1] = 0xCF; //data
98 Status
= I2cWriteMultipleByte (
100 EfiI2CSevenBitAddrMode
,
104 ASSERT_EFI_ERROR (Status
);
107 // Lower GPORT3 bit4 and bit5 to Vss
110 Buffer
[0] = 0x0B; //sub-address
111 Buffer
[1] = 0xCF; //data
113 Status
= I2cWriteMultipleByte (
115 EfiI2CSevenBitAddrMode
,
119 ASSERT_EFI_ERROR (Status
);
124 PlatformInitializeUart0MuxGalileoGen2 (
132 This is the routine to initialize UART0 on GalileoGen2. The hardware used in this process is
133 I2C controller and the configuring the following IO Expander signal.
135 EXP1.P1_5 should be configured as an output & driven high.
136 EXP1.P0_0 should be configured as an output & driven high.
137 EXP0.P1_4 should be configured as an output, driven low.
138 EXP1.P0_1 pullup should be disabled.
139 EXP0.P1_5 Pullup should be disabled.
153 // EXP1.P1_5 should be configured as an output & driven high.
155 PlatformPcal9555GpioSetDir (
156 GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR
, // IO Expander 1.
160 PlatformPcal9555GpioSetLevel (
161 GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR
, // IO Expander 1.
167 // EXP1.P0_0 should be configured as an output & driven high.
169 PlatformPcal9555GpioSetDir (
170 GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR
, // IO Expander 0.
174 PlatformPcal9555GpioSetLevel (
175 GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR
, // IO Expander 0.
181 // EXP0.P1_4 should be configured as an output, driven low.
183 PlatformPcal9555GpioSetDir (
184 GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR
, // IO Expander 0.
188 PlatformPcal9555GpioSetLevel ( // IO Expander 0.
189 GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR
, // P1-4
195 // EXP1.P0_1 pullup should be disabled.
197 PlatformPcal9555GpioDisablePull (
198 GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR
, // IO Expander 1.
203 // EXP0.P1_5 Pullup should be disabled.
205 PlatformPcal9555GpioDisablePull (
206 GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR
, // IO Expander 0.
213 PlatformConfigOnSmmConfigurationProtocol (
221 Function runs in PI-DXE to perform platform specific config when
222 SmmConfigurationProtocol is installed.
225 Event - The event that occured.
226 Context - For EFI compatiblity. Not used.
239 Status
= gBS
->LocateProtocol (&gEfiSmmConfigurationProtocolGuid
, NULL
, &SmmCfgProt
);
240 if (Status
!= EFI_SUCCESS
){
241 DEBUG ((DEBUG_INFO
, "gEfiSmmConfigurationProtocolGuid triggered but not valid.\n"));
245 DEBUG ((DEBUG_INFO
, "Platform DXE Mem config already done.\n"));
250 // Disable eSram block (this will also clear/zero eSRAM)
251 // We only use eSRAM in the PEI phase. Disable now that we are in the DXE phase
253 NewValue
= QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID
, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK
);
254 NewValue
|= BLOCK_DISABLE_PG
;
255 QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID
, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK
, NewValue
);
258 // Update HMBOUND to top of DDR3 memory and LOCK
259 // We disabled eSRAM so now we move HMBOUND down to top of DDR3
261 QNCGetTSEGMemoryRange (&BaseAddress
, &SmramLength
);
262 NewValue
= (UINT32
)(BaseAddress
+ SmramLength
);
263 DEBUG ((EFI_D_INFO
,"Locking HMBOUND at: = 0x%8x\n",NewValue
));
264 QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID
, QUARK_NC_HOST_BRIDGE_HMBOUND_REG
, (NewValue
| HMBOUND_LOCK
));
267 // Lock IMR5 now that HMBOUND is locked (legacy S3 region)
269 NewValue
= QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID
, QUARK_NC_MEMORY_MANAGER_IMR5
+QUARK_NC_MEMORY_MANAGER_IMRXL
);
270 NewValue
|= IMR_LOCK
;
271 QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID
, QUARK_NC_MEMORY_MANAGER_IMR5
+QUARK_NC_MEMORY_MANAGER_IMRXL
, NewValue
);
274 // Lock IMR6 now that HMBOUND is locked (ACPI Reclaim/ACPI/Runtime services/Reserved)
276 NewValue
= QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID
, QUARK_NC_MEMORY_MANAGER_IMR6
+QUARK_NC_MEMORY_MANAGER_IMRXL
);
277 NewValue
|= IMR_LOCK
;
278 QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID
, QUARK_NC_MEMORY_MANAGER_IMR6
+QUARK_NC_MEMORY_MANAGER_IMRXL
, NewValue
);
281 // Disable IMR2 memory protection (RMU Main Binary)
284 QUARK_NC_MEMORY_MANAGER_IMR2
,
285 (UINT32
)(IMRL_RESET
& ~IMR_EN
),
287 (UINT32
)IMRX_ALL_ACCESS
,
288 (UINT32
)IMRX_ALL_ACCESS
292 // Disable IMR3 memory protection (Default SMRAM)
295 QUARK_NC_MEMORY_MANAGER_IMR3
,
296 (UINT32
)(IMRL_RESET
& ~IMR_EN
),
298 (UINT32
)IMRX_ALL_ACCESS
,
299 (UINT32
)IMRX_ALL_ACCESS
303 // Disable IMR4 memory protection (eSRAM).
306 QUARK_NC_MEMORY_MANAGER_IMR4
,
307 (UINT32
)(IMRL_RESET
& ~IMR_EN
),
309 (UINT32
)IMRX_ALL_ACCESS
,
310 (UINT32
)IMRX_ALL_ACCESS
314 // RTC:28208 - System hang/crash when entering probe mode(ITP) when relocating SMBASE
315 // Workaround to make default SMRAM UnCachable
317 Status
= gDS
->SetMemorySpaceAttributes (
318 (EFI_PHYSICAL_ADDRESS
) SMM_DEFAULT_SMBASE
,
319 SMM_DEFAULT_SMBASE_SIZE_BYTES
,
322 ASSERT_EFI_ERROR (Status
);
329 PlatformConfigOnSpiReady (
337 Function runs in PI-DXE to perform platform specific config when SPI
341 Event - The event that occured.
342 Context - For EFI compatiblity. Not used.
350 VOID
*SpiReadyProt
= NULL
;
351 EFI_PLATFORM_TYPE Type
;
352 EFI_BOOT_MODE BootMode
;
354 BootMode
= GetBootModeHob ();
356 Status
= gBS
->LocateProtocol (&gEfiSmmSpiReadyProtocolGuid
, NULL
, &SpiReadyProt
);
357 if (Status
!= EFI_SUCCESS
){
358 DEBUG ((DEBUG_INFO
, "gEfiSmmSpiReadyProtocolGuid triggered but not valid.\n"));
363 // Lock regions SPI flash.
365 PlatformFlashLockPolicy (FALSE
);
368 // Configurations and checks to be done when DXE tracing available.
372 // Platform specific Signal routing.
376 // Skip any signal not needed for recovery and flash update.
378 if (BootMode
!= BOOT_ON_FLASH_UPDATE
&& BootMode
!= BOOT_IN_RECOVERY_MODE
) {
381 // Galileo Platform UART0 support.
383 Type
= (EFI_PLATFORM_TYPE
)PcdGet16 (PcdPlatformType
);
384 if (Type
== Galileo
) {
386 // Use MUX to connect out UART0 pins.
388 PlatformInitializeUart0MuxGalileo ();
392 // GalileoGen2 Platform UART0 support.
394 if (Type
== GalileoGen2
) {
396 // Use route out UART0 pins.
398 PlatformInitializeUart0MuxGalileoGen2 ();
420 EFI_EVENT EventSmmCfg
;
421 EFI_EVENT EventSpiReady
;
422 VOID
*RegistrationSmmCfg
;
423 VOID
*RegistrationSpiReady
;
426 // Schedule callback for when SmmConfigurationProtocol installed.
428 EventSmmCfg
= EfiCreateProtocolNotifyEvent (
429 &gEfiSmmConfigurationProtocolGuid
,
431 PlatformConfigOnSmmConfigurationProtocol
,
435 ASSERT (EventSmmCfg
!= NULL
);
438 // Schedule callback to setup SPI Flash Policy when SPI interface ready.
440 EventSpiReady
= EfiCreateProtocolNotifyEvent (
441 &gEfiSmmSpiReadyProtocolGuid
,
443 PlatformConfigOnSpiReady
,
445 &RegistrationSpiReady
447 ASSERT (EventSpiReady
!= NULL
);