QuarkPlatformPkg/PlatformInit: Fix recovery detection issues
[mirror_edk2.git] / QuarkPlatformPkg / Platform / Pei / PlatformInit / MrcWrapper.h
1 /** @file
2 Framework PEIM to initialize memory on an DDR2 SDRAM Memory Controller.
3
4 Copyright (c) 2013 - 2016 Intel Corporation.
5
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #ifndef _MRC_WRAPPER_H
17 #define _MRC_WRAPPER_H
18
19 #include <Ppi/QNCMemoryInit.h>
20 #include "PlatformEarlyInit.h"
21
22 //
23 // Define the default memory areas required
24 //
25 #define EDKII_RESERVED_SIZE_PAGES 0x20
26 #define ACPI_NVS_SIZE_PAGES 0x60
27 #define RUNTIME_SERVICES_DATA_SIZE_PAGES 0x20
28 #define RUNTIME_SERVICES_CODE_SIZE_PAGES 0x80
29 #define ACPI_RECLAIM_SIZE_PAGES 0x20
30 #define EDKII_DXE_MEM_SIZE_PAGES 0x20
31
32 //
33 // Maximum number of "Socket Sets", where a "Socket Set is a set of matching
34 // DIMM's from the various channels
35 //
36 #define MAX_SOCKET_SETS 2
37
38 //
39 // Maximum number of memory ranges supported by the memory controller
40 //
41 #define MAX_RANGES (MAX_ROWS + 5)
42
43 //
44 // Min. of 48MB PEI phase
45 //
46 #define PEI_MIN_MEMORY_SIZE (6 * 0x800000)
47 #define PEI_RECOVERY_MIN_MEMORY_SIZE (6 * 0x800000)
48
49 #define PEI_MEMORY_RANGE_OPTION_ROM UINT32
50 #define PEI_MR_OPTION_ROM_NONE 0x00000000
51
52 //
53 // SMRAM Memory Range
54 //
55 #define PEI_MEMORY_RANGE_SMRAM UINT32
56 #define PEI_MR_SMRAM_ALL 0xFFFFFFFF
57 #define PEI_MR_SMRAM_NONE 0x00000000
58 #define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000
59 #define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000
60 #define PEI_MR_SMRAM_ABSEG_MASK 0x00010000
61 #define PEI_MR_SMRAM_HSEG_MASK 0x00020000
62 #define PEI_MR_SMRAM_TSEG_MASK 0x00040000
63 //
64 // SMRAM Size is a multiple of 128KB.
65 //
66 #define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF
67
68 //
69 // Pci Memory Hole
70 //
71 #define PEI_MEMORY_RANGE_PCI_MEMORY UINT32
72
73 typedef enum {
74 Ignore,
75 Quick,
76 Sparse,
77 Extensive
78 } PEI_MEMORY_TEST_OP;
79
80 //
81 // MRC Params Variable structure.
82 //
83
84 typedef struct {
85 MrcTimings_t timings; // Actual MRC config values saved in variable store.
86 UINT8 VariableStorePad[8]; // Allow for data stored in variable is required to be multiple of 8bytes.
87 } PLATFORM_VARIABLE_MEMORY_CONFIG_DATA;
88
89 ///
90 /// MRC Params Platform Data Flags bits
91 ///
92 #define PDAT_MRC_FLAG_ECC_EN BIT0
93 #define PDAT_MRC_FLAG_SCRAMBLE_EN BIT1
94 #define PDAT_MRC_FLAG_MEMTEST_EN BIT2
95 #define PDAT_MRC_FLAG_TOP_TREE_EN BIT3 ///< 0b DDR "fly-by" topology else 1b DDR "tree" topology.
96 #define PDAT_MRC_FLAG_WR_ODT_EN BIT4 ///< If set ODR signal is asserted to DRAM devices on writes.
97
98 ///
99 /// MRC Params Platform Data.
100 ///
101 typedef struct {
102 UINT32 Flags; ///< Bitmap of PDAT_MRC_FLAG_XXX defs above.
103 UINT8 DramWidth; ///< 0=x8, 1=x16, others=RESERVED.
104 UINT8 DramSpeed; ///< 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory.
105 UINT8 DramType; ///< 0=DDR3,1=DDR3L, others=RESERVED.
106 UINT8 RankMask; ///< bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED.
107 UINT8 ChanMask; ///< bit[0] CHAN0_EN, others=RESERVED.
108 UINT8 ChanWidth; ///< 1=x16, others=RESERVED.
109 UINT8 AddrMode; ///< 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED.
110 UINT8 SrInt; ///< 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE.
111 UINT8 SrTemp; ///< 0=normal, 1=extended, others=RESERVED.
112 UINT8 DramRonVal; ///< 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control.
113 UINT8 DramRttNomVal; ///< 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED.
114 UINT8 DramRttWrVal; ///< 0=off others=RESERVED.
115 UINT8 SocRdOdtVal; ///< 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED.
116 UINT8 SocWrRonVal; ///< 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED.
117 UINT8 SocWrSlewRate; ///< 0=2.5V/ns, 1=4V/ns, others=RESERVED.
118 UINT8 DramDensity; ///< 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED.
119 UINT32 tRAS; ///< ACT to PRE command period in picoseconds.
120 UINT32 tWTR; ///< Delay from start of internal write transaction to internal read command in picoseconds.
121 UINT32 tRRD; ///< ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds.
122 UINT32 tFAW; ///< Four activate window (JESD79 specific to page size 1K/2K) in picoseconds.
123 UINT8 tCL; ///< DRAM CAS Latency in clocks.
124 } PDAT_MRC_ITEM;
125
126 //
127 // Memory range types
128 //
129 typedef enum {
130 DualChannelDdrMainMemory,
131 DualChannelDdrSmramCacheable,
132 DualChannelDdrSmramNonCacheable,
133 DualChannelDdrGraphicsMemoryCacheable,
134 DualChannelDdrGraphicsMemoryNonCacheable,
135 DualChannelDdrReservedMemory,
136 DualChannelDdrMaxMemoryRangeType
137 } PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;
138
139 //
140 // Memory map range information
141 //
142 typedef struct {
143 EFI_PHYSICAL_ADDRESS PhysicalAddress;
144 EFI_PHYSICAL_ADDRESS CpuAddress;
145 EFI_PHYSICAL_ADDRESS RangeLength;
146 PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE Type;
147 } PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;
148
149 //
150 // Function prototypes.
151 //
152
153 EFI_STATUS
154 InstallEfiMemory (
155 IN EFI_PEI_SERVICES **PeiServices,
156 IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,
157 IN EFI_BOOT_MODE BootMode,
158 IN UINT32 TotalMemorySize
159 );
160
161 EFI_STATUS
162 InstallS3Memory (
163 IN EFI_PEI_SERVICES **PeiServices,
164 IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,
165 IN UINT32 TotalMemorySize
166 );
167
168 EFI_STATUS
169 MemoryInit (
170 IN EFI_PEI_SERVICES **PeiServices
171 );
172
173
174 EFI_STATUS
175 LoadConfig (
176 IN EFI_PEI_SERVICES **PeiServices,
177 IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,
178 IN OUT MRCParams_t *MrcData
179 );
180
181 EFI_STATUS
182 SaveConfig (
183 IN MRCParams_t *MrcData
184 );
185
186 EFI_STATUS
187 GetMemoryMap (
188 IN EFI_PEI_SERVICES **PeiServices,
189 IN UINT32 TotalMemorySize,
190 IN OUT PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *MemoryMap,
191 IN OUT UINT8 *NumRanges
192 );
193
194 EFI_STATUS
195 ChooseRanges (
196 IN OUT PEI_MEMORY_RANGE_OPTION_ROM *OptionRomMask,
197 IN OUT PEI_MEMORY_RANGE_SMRAM *SmramMask,
198 IN OUT PEI_MEMORY_RANGE_PCI_MEMORY *PciMemoryMask
199 );
200
201 EFI_STATUS
202 GetPlatformMemorySize (
203 IN EFI_PEI_SERVICES **PeiServices,
204 IN EFI_BOOT_MODE BootMode,
205 IN OUT UINT64 *MemorySize
206 );
207
208 EFI_STATUS
209 BaseMemoryTest (
210 IN EFI_PEI_SERVICES **PeiServices,
211 IN EFI_PHYSICAL_ADDRESS BeginAddress,
212 IN UINT64 MemoryLength,
213 IN PEI_MEMORY_TEST_OP Operation,
214 OUT EFI_PHYSICAL_ADDRESS *ErrorAddress
215 );
216
217 EFI_STATUS
218 SetPlatformImrPolicy (
219 IN EFI_PHYSICAL_ADDRESS PeiMemoryBaseAddress,
220 IN UINT64 PeiMemoryLength
221 );
222
223 VOID
224 EFIAPI
225 InfoPostInstallMemory (
226 OUT UINT32 *RmuBaseAddressPtr OPTIONAL,
227 OUT EFI_SMRAM_DESCRIPTOR **SmramDescriptorPtr OPTIONAL,
228 OUT UINTN *NumSmramRegionsPtr OPTIONAL
229 );
230
231 #endif