QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.h

   1 /** @file
   2 Framework PEIM to initialize memory on an DDR2 SDRAM Memory Controller.
   3
   4 Copyright (c) 2013 Intel Corporation.
   5
   6 This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef _MRC_WRAPPER_H
  17 #define _MRC_WRAPPER_H
  18
  19 #include <Ppi/QNCMemoryInit.h>
  20 #include "PlatformEarlyInit.h"
  21
  22 //
  23 // Define the default memory areas required
  24 //
  25 #define EDKII_RESERVED_SIZE_PAGES         0x40
  26 #define ACPI_NVS_SIZE_PAGES               0x40
  27 #define RUNTIME_SERVICES_DATA_SIZE_PAGES  0x20
  28 #define RUNTIME_SERVICES_CODE_SIZE_PAGES  0x60
  29 #define ACPI_RECLAIM_SIZE_PAGES           0x10
  30 #define EDKII_DXE_MEM_SIZE_PAGES          0x20
  31
  32 #define AP_STARTUP_VECTOR                 0x00097000
  33
  34 //
  35 // Maximum number of "Socket Sets", where a "Socket Set is a set of matching
  36 // DIMM's from the various channels
  37 //
  38 #define MAX_SOCKET_SETS      2
  39
  40 //
  41 // Maximum number of memory ranges supported by the memory controller
  42 //
  43 #define MAX_RANGES (MAX_ROWS + 5)
  44
  45 //
  46 // Min. of 48MB PEI phase
  47 //
  48 #define  PEI_MIN_MEMORY_SIZE               (6 * 0x800000)
  49 #define  PEI_RECOVERY_MIN_MEMORY_SIZE      (6 * 0x800000)
  50
  51 #define PEI_MEMORY_RANGE_OPTION_ROM UINT32
  52 #define PEI_MR_OPTION_ROM_NONE      0x00000000
  53
  54 //
  55 // SMRAM Memory Range
  56 //
  57 #define PEI_MEMORY_RANGE_SMRAM      UINT32
  58 #define PEI_MR_SMRAM_ALL            0xFFFFFFFF
  59 #define PEI_MR_SMRAM_NONE           0x00000000
  60 #define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000
  61 #define PEI_MR_SMRAM_SEGTYPE_MASK   0x00FF0000
  62 #define PEI_MR_SMRAM_ABSEG_MASK     0x00010000
  63 #define PEI_MR_SMRAM_HSEG_MASK      0x00020000
  64 #define PEI_MR_SMRAM_TSEG_MASK      0x00040000
  65 //
  66 // SMRAM Size is a multiple of 128KB.
  67 //
  68 #define PEI_MR_SMRAM_SIZE_MASK          0x0000FFFF
  69
  70 //
  71 // Pci Memory Hole
  72 //
  73 #define PEI_MEMORY_RANGE_PCI_MEMORY       UINT32
  74
  75 typedef enum {
  76   Ignore,
  77   Quick,
  78   Sparse,
  79   Extensive
  80 } PEI_MEMORY_TEST_OP;
  81
  82 //
  83 // MRC Params Variable structure.
  84 //
  85
  86 typedef struct {
  87   MrcTimings_t timings;              // Actual MRC config values saved in variable store.
  88   UINT8        VariableStorePad[8];  // Allow for data stored in variable is required to be multiple of 8bytes.
  89 } PLATFORM_VARIABLE_MEMORY_CONFIG_DATA;
  90
  91 ///
  92 /// MRC Params Platform Data Flags bits
  93 ///
  94 #define PDAT_MRC_FLAG_ECC_EN            BIT0
  95 #define PDAT_MRC_FLAG_SCRAMBLE_EN       BIT1
  96 #define PDAT_MRC_FLAG_MEMTEST_EN        BIT2
  97 #define PDAT_MRC_FLAG_TOP_TREE_EN       BIT3  ///< 0b DDR "fly-by" topology else 1b DDR "tree" topology.
  98 #define PDAT_MRC_FLAG_WR_ODT_EN         BIT4  ///< If set ODR signal is asserted to DRAM devices on writes.
  99
 100 ///
 101 /// MRC Params Platform Data.
 102 ///
 103 typedef struct {
 104   UINT32       Flags;                   ///< Bitmap of PDAT_MRC_FLAG_XXX defs above.
 105   UINT8        DramWidth;               ///< 0=x8, 1=x16, others=RESERVED.
 106   UINT8        DramSpeed;               ///< 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory.
 107   UINT8        DramType;                ///< 0=DDR3,1=DDR3L, others=RESERVED.
 108   UINT8        RankMask;                ///< bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED.
 109   UINT8        ChanMask;                ///< bit[0] CHAN0_EN, others=RESERVED.
 110   UINT8        ChanWidth;               ///< 1=x16, others=RESERVED.
 111   UINT8        AddrMode;                ///< 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED.
 112   UINT8        SrInt;                   ///< 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE.
 113   UINT8        SrTemp;                  ///< 0=normal, 1=extended, others=RESERVED.
 114   UINT8        DramRonVal;              ///< 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control.
 115   UINT8        DramRttNomVal;           ///< 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED.
 116   UINT8        DramRttWrVal;            ///< 0=off others=RESERVED.
 117   UINT8        SocRdOdtVal;             ///< 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED.
 118   UINT8        SocWrRonVal;             ///< 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED.
 119   UINT8        SocWrSlewRate;           ///< 0=2.5V/ns, 1=4V/ns, others=RESERVED.
 120   UINT8        DramDensity;             ///< 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED.
 121   UINT32       tRAS;                    ///< ACT to PRE command period in picoseconds.
 122   UINT32       tWTR;                    ///< Delay from start of internal write transaction to internal read command in picoseconds.
 123   UINT32       tRRD;                    ///< ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds.
 124   UINT32       tFAW;                    ///< Four activate window (JESD79 specific to page size 1K/2K) in picoseconds.
 125   UINT8        tCL;                     ///< DRAM CAS Latency in clocks.
 126 } PDAT_MRC_ITEM;
 127
 128 //
 129 // Memory range types
 130 //
 131 typedef enum {
 132   DualChannelDdrMainMemory,
 133   DualChannelDdrSmramCacheable,
 134   DualChannelDdrSmramNonCacheable,
 135   DualChannelDdrGraphicsMemoryCacheable,
 136   DualChannelDdrGraphicsMemoryNonCacheable,
 137   DualChannelDdrReservedMemory,
 138   DualChannelDdrMaxMemoryRangeType
 139 } PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;
 140
 141 //
 142 // Memory map range information
 143 //
 144 typedef struct {
 145   EFI_PHYSICAL_ADDRESS                          PhysicalAddress;
 146   EFI_PHYSICAL_ADDRESS                          CpuAddress;
 147   EFI_PHYSICAL_ADDRESS                          RangeLength;
 148   PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE        Type;
 149 } PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;
 150
 151 //
 152 // Function prototypes.
 153 //
 154
 155 EFI_STATUS
 156 InstallEfiMemory (
 157   IN      EFI_PEI_SERVICES                           **PeiServices,
 158   IN      EFI_PEI_READ_ONLY_VARIABLE2_PPI            *VariableServices,
 159   IN      EFI_BOOT_MODE                              BootMode,
 160   IN      UINT32                                     TotalMemorySize
 161   );
 162
 163 EFI_STATUS
 164 InstallS3Memory (
 165   IN      EFI_PEI_SERVICES                      **PeiServices,
 166   IN      EFI_PEI_READ_ONLY_VARIABLE2_PPI       *VariableServices,
 167   IN      UINT32                                TotalMemorySize
 168   );
 169
 170 EFI_STATUS
 171 MemoryInit (
 172   IN EFI_PEI_SERVICES                       **PeiServices
 173   );
 174
 175
 176 EFI_STATUS
 177 LoadConfig (
 178   IN      EFI_PEI_SERVICES                        **PeiServices,
 179   IN      EFI_PEI_READ_ONLY_VARIABLE2_PPI         *VariableServices,
 180   IN OUT  MRCParams_t                             *MrcData
 181   );
 182
 183 EFI_STATUS
 184 SaveConfig (
 185   IN      MRCParams_t                      *MrcData
 186   );
 187
 188 VOID
 189 RetriveRequiredMemorySize (
 190   IN      EFI_PEI_SERVICES                  **PeiServices,
 191   OUT     UINTN                             *Size
 192   );
 193
 194 EFI_STATUS
 195 GetMemoryMap (
 196   IN     EFI_PEI_SERVICES                                    **PeiServices,
 197   IN     UINT32                                              TotalMemorySize,
 198   IN OUT PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE               *MemoryMap,
 199   IN OUT UINT8                                               *NumRanges
 200   );
 201
 202 EFI_STATUS
 203 ChooseRanges (
 204   IN OUT   PEI_MEMORY_RANGE_OPTION_ROM      *OptionRomMask,
 205   IN OUT   PEI_MEMORY_RANGE_SMRAM           *SmramMask,
 206   IN OUT   PEI_MEMORY_RANGE_PCI_MEMORY      *PciMemoryMask
 207   );
 208
 209 EFI_STATUS
 210 GetPlatformMemorySize (
 211   IN      EFI_PEI_SERVICES                       **PeiServices,
 212   IN      EFI_BOOT_MODE                          BootMode,
 213   IN OUT  UINT64                                 *MemorySize
 214   );
 215
 216 EFI_STATUS
 217 BaseMemoryTest (
 218   IN  EFI_PEI_SERVICES                   **PeiServices,
 219   IN  EFI_PHYSICAL_ADDRESS               BeginAddress,
 220   IN  UINT64                             MemoryLength,
 221   IN  PEI_MEMORY_TEST_OP                 Operation,
 222   OUT EFI_PHYSICAL_ADDRESS               *ErrorAddress
 223   );
 224
 225 EFI_STATUS
 226 SetPlatformImrPolicy (
 227   IN      EFI_PHYSICAL_ADDRESS    PeiMemoryBaseAddress,
 228   IN      UINT64                  PeiMemoryLength,
 229   IN      UINTN                   RequiredMemSize
 230   );
 231
 232 VOID
 233 EFIAPI
 234 InfoPostInstallMemory (
 235   OUT     UINT32                  *RmuBaseAddressPtr OPTIONAL,
 236   OUT     EFI_SMRAM_DESCRIPTOR    **SmramDescriptorPtr OPTIONAL,
 237   OUT     UINTN                   *NumSmramRegionsPtr OPTIONAL
 238   );
 239
 240 #endif