QuarkSocPkg/SmmCpuFeaturesLib: Add SMRR PhysBase/PhysMask fields check
[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Library / SmmCpuFeaturesLib / SmmCpuFeaturesLib.c
1 /** @file
2 The Quark CPU specific programming for PiSmmCpuDxeSmm module.
3
4 Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include <PiSmm.h>
16 #include <Library/SmmCpuFeaturesLib.h>
17 #include <Register/SmramSaveStateMap.h>
18 #include <Library/BaseLib.h>
19 #include <Library/DebugLib.h>
20 #include <Library/QNCAccessLib.h>
21
22 #define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11
23 #define EFI_MSR_SMRR_MASK 0xFFFFF000
24
25 /**
26 Called during the very first SMI into System Management Mode to initialize
27 CPU features, including SMBASE, for the currently executing CPU. Since this
28 is the first SMI, the SMRAM Save State Map is at the default address of
29 SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing
30 CPU is specified by CpuIndex and CpuIndex can be used to access information
31 about the currently executing CPU in the ProcessorInfo array and the
32 HotPlugCpuData data structure.
33
34 @param[in] CpuIndex The index of the CPU to initialize. The value
35 must be between 0 and the NumberOfCpus field in
36 the System Management System Table (SMST).
37 @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that
38 was elected as monarch during System Management
39 Mode initialization.
40 FALSE if the CpuIndex is not the index of the CPU
41 that was elected as monarch during System
42 Management Mode initialization.
43 @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION
44 structures. ProcessorInfo[CpuIndex] contains the
45 information for the currently executing CPU.
46 @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that
47 contains the ApidId and SmBase arrays.
48 **/
49 VOID
50 EFIAPI
51 SmmCpuFeaturesInitializeProcessor (
52 IN UINTN CpuIndex,
53 IN BOOLEAN IsMonarch,
54 IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,
55 IN CPU_HOT_PLUG_DATA *CpuHotPlugData
56 )
57 {
58 SMRAM_SAVE_STATE_MAP *CpuState;
59
60 //
61 // Configure SMBASE.
62 //
63 CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
64 CpuState->x86.SMBASE = CpuHotPlugData->SmBase[CpuIndex];
65
66 //
67 // SMRR size cannot be less than 4-KBytes
68 // SMRR size must be of length 2^n
69 // SMRR base alignment cannot be less than SMRR length
70 //
71 if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||
72 (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||
73 ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) {
74 DEBUG ((EFI_D_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));
75 CpuDeadLoop ();
76 }
77
78 //
79 // Use QNC to initialize SMRR on Quark
80 //
81 QNCPortWrite(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE, CpuHotPlugData->SmrrBase);
82 QNCPortWrite(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK) | EFI_MSR_SMRR_PHYS_MASK_VALID);
83 }
84
85 /**
86 This function updates the SMRAM save state on the currently executing CPU
87 to resume execution at a specific address after an RSM instruction. This
88 function must evaluate the SMRAM save state to determine the execution mode
89 the RSM instruction resumes and update the resume execution address with
90 either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart
91 flag in the SMRAM save state must always be cleared. This function returns
92 the value of the instruction pointer from the SMRAM save state that was
93 replaced. If this function returns 0, then the SMRAM save state was not
94 modified.
95
96 This function is called during the very first SMI on each CPU after
97 SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
98 to signal that the SMBASE of each CPU has been updated before the default
99 SMBASE address is used for the first SMI to the next CPU.
100
101 @param[in] CpuIndex The index of the CPU to hook. The value
102 must be between 0 and the NumberOfCpus
103 field in the System Management System Table
104 (SMST).
105 @param[in] CpuState Pointer to SMRAM Save State Map for the
106 currently executing CPU.
107 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
108 32-bit execution mode from 64-bit SMM.
109 @param[in] NewInstructionPointer Instruction pointer to use if resuming to
110 same execution mode as SMM.
111
112 @retval 0 This function did modify the SMRAM save state.
113 @retval > 0 The original instruction pointer value from the SMRAM save state
114 before it was replaced.
115 **/
116 UINT64
117 EFIAPI
118 SmmCpuFeaturesHookReturnFromSmm (
119 IN UINTN CpuIndex,
120 IN SMRAM_SAVE_STATE_MAP *CpuState,
121 IN UINT64 NewInstructionPointer32,
122 IN UINT64 NewInstructionPointer
123 )
124 {
125 return 0;
126 }
127
128 /**
129 Hook point in normal execution mode that allows the one CPU that was elected
130 as monarch during System Management Mode initialization to perform additional
131 initialization actions immediately after all of the CPUs have processed their
132 first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE
133 into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().
134 **/
135 VOID
136 EFIAPI
137 SmmCpuFeaturesSmmRelocationComplete (
138 VOID
139 )
140 {
141 }
142
143 /**
144 Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is
145 returned, then a custom SMI handler is not provided by this library,
146 and the default SMI handler must be used.
147
148 @retval 0 Use the default SMI handler.
149 @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()
150 The caller is required to allocate enough SMRAM for each CPU to
151 support the size of the custom SMI handler.
152 **/
153 UINTN
154 EFIAPI
155 SmmCpuFeaturesGetSmiHandlerSize (
156 VOID
157 )
158 {
159 return 0;
160 }
161
162 /**
163 Install a custom SMI handler for the CPU specified by CpuIndex. This function
164 is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater
165 than zero and is called by the CPU that was elected as monarch during System
166 Management Mode initialization.
167
168 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.
169 The value must be between 0 and the NumberOfCpus field
170 in the System Management System Table (SMST).
171 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
172 @param[in] SmiStack The stack to use when an SMI is processed by the
173 the CPU specified by CpuIndex.
174 @param[in] StackSize The size, in bytes, if the stack used when an SMI is
175 processed by the CPU specified by CpuIndex.
176 @param[in] GdtBase The base address of the GDT to use when an SMI is
177 processed by the CPU specified by CpuIndex.
178 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
179 processed by the CPU specified by CpuIndex.
180 @param[in] IdtBase The base address of the IDT to use when an SMI is
181 processed by the CPU specified by CpuIndex.
182 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
183 processed by the CPU specified by CpuIndex.
184 @param[in] Cr3 The base address of the page tables to use when an SMI
185 is processed by the CPU specified by CpuIndex.
186 **/
187 VOID
188 EFIAPI
189 SmmCpuFeaturesInstallSmiHandler (
190 IN UINTN CpuIndex,
191 IN UINT32 SmBase,
192 IN VOID *SmiStack,
193 IN UINTN StackSize,
194 IN UINTN GdtBase,
195 IN UINTN GdtSize,
196 IN UINTN IdtBase,
197 IN UINTN IdtSize,
198 IN UINT32 Cr3
199 )
200 {
201 }
202
203 /**
204 Determines if MTRR registers must be configured to set SMRAM cache-ability
205 when executing in System Management Mode.
206
207 @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.
208 @retval FALSE MTRR registers do not need to be configured to set SMRAM
209 cache-ability.
210 **/
211 BOOLEAN
212 EFIAPI
213 SmmCpuFeaturesNeedConfigureMtrrs (
214 VOID
215 )
216 {
217 return TRUE;
218 }
219
220 /**
221 Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
222 returns TRUE.
223 **/
224 VOID
225 EFIAPI
226 SmmCpuFeaturesDisableSmrr (
227 VOID
228 )
229 {
230 //
231 // Use QNC to disable SMRR on Quark
232 //
233 QNCPortWrite(
234 QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
235 QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK,
236 QNCPortRead(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK) & ~EFI_MSR_SMRR_PHYS_MASK_VALID
237 );
238 }
239
240 /**
241 Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
242 returns TRUE.
243 **/
244 VOID
245 EFIAPI
246 SmmCpuFeaturesReenableSmrr (
247 VOID
248 )
249 {
250 //
251 // Use QNC to enable SMRR on Quark
252 //
253 QNCPortWrite(
254 QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
255 QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK,
256 QNCPortRead(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK) | EFI_MSR_SMRR_PHYS_MASK_VALID
257 );
258 }
259
260 /**
261 Processor specific hook point each time a CPU enters System Management Mode.
262
263 @param[in] CpuIndex The index of the CPU that has entered SMM. The value
264 must be between 0 and the NumberOfCpus field in the
265 System Management System Table (SMST).
266 **/
267 VOID
268 EFIAPI
269 SmmCpuFeaturesRendezvousEntry (
270 IN UINTN CpuIndex
271 )
272 {
273 }
274
275 /**
276 Processor specific hook point each time a CPU exits System Management Mode.
277
278 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value must
279 be between 0 and the NumberOfCpus field in the System
280 Management System Table (SMST).
281 **/
282 VOID
283 EFIAPI
284 SmmCpuFeaturesRendezvousExit (
285 IN UINTN CpuIndex
286 )
287 {
288 }
289
290 /**
291 Check to see if an SMM register is supported by a specified CPU.
292
293 @param[in] CpuIndex The index of the CPU to check for SMM register support.
294 The value must be between 0 and the NumberOfCpus field
295 in the System Management System Table (SMST).
296 @param[in] RegName Identifies the SMM register to check for support.
297
298 @retval TRUE The SMM register specified by RegName is supported by the CPU
299 specified by CpuIndex.
300 @retval FALSE The SMM register specified by RegName is not supported by the
301 CPU specified by CpuIndex.
302 **/
303 BOOLEAN
304 EFIAPI
305 SmmCpuFeaturesIsSmmRegisterSupported (
306 IN UINTN CpuIndex,
307 IN SMM_REG_NAME RegName
308 )
309 {
310 return FALSE;
311 }
312
313 /**
314 Returns the current value of the SMM register for the specified CPU.
315 If the SMM register is not supported, then 0 is returned.
316
317 @param[in] CpuIndex The index of the CPU to read the SMM register. The
318 value must be between 0 and the NumberOfCpus field in
319 the System Management System Table (SMST).
320 @param[in] RegName Identifies the SMM register to read.
321
322 @return The value of the SMM register specified by RegName from the CPU
323 specified by CpuIndex.
324 **/
325 UINT64
326 EFIAPI
327 SmmCpuFeaturesGetSmmRegister (
328 IN UINTN CpuIndex,
329 IN SMM_REG_NAME RegName
330 )
331 {
332 return 0;
333 }
334
335 /**
336 Sets the value of an SMM register on a specified CPU.
337 If the SMM register is not supported, then no action is performed.
338
339 @param[in] CpuIndex The index of the CPU to write the SMM register. The
340 value must be between 0 and the NumberOfCpus field in
341 the System Management System Table (SMST).
342 @param[in] RegName Identifies the SMM register to write.
343 registers are read-only.
344 @param[in] Value The value to write to the SMM register.
345 **/
346 VOID
347 EFIAPI
348 SmmCpuFeaturesSetSmmRegister (
349 IN UINTN CpuIndex,
350 IN SMM_REG_NAME RegName,
351 IN UINT64 Value
352 )
353 {
354 }
355
356 /**
357 Read an SMM Save State register on the target processor. If this function
358 returns EFI_UNSUPPORTED, then the caller is responsible for reading the
359 SMM Save Sate register.
360
361 @param[in] CpuIndex The index of the CPU to read the SMM Save State. The
362 value must be between 0 and the NumberOfCpus field in
363 the System Management System Table (SMST).
364 @param[in] Register The SMM Save State register to read.
365 @param[in] Width The number of bytes to read from the CPU save state.
366 @param[out] Buffer Upon return, this holds the CPU register value read
367 from the save state.
368
369 @retval EFI_SUCCESS The register was read from Save State.
370 @retval EFI_INVALID_PARAMTER Buffer is NULL.
371 @retval EFI_UNSUPPORTED This function does not support reading Register.
372
373 **/
374 EFI_STATUS
375 EFIAPI
376 SmmCpuFeaturesReadSaveStateRegister (
377 IN UINTN CpuIndex,
378 IN EFI_SMM_SAVE_STATE_REGISTER Register,
379 IN UINTN Width,
380 OUT VOID *Buffer
381 )
382 {
383 return EFI_UNSUPPORTED;
384 }
385
386 /**
387 Writes an SMM Save State register on the target processor. If this function
388 returns EFI_UNSUPPORTED, then the caller is responsible for writing the
389 SMM Save Sate register.
390
391 @param[in] CpuIndex The index of the CPU to write the SMM Save State. The
392 value must be between 0 and the NumberOfCpus field in
393 the System Management System Table (SMST).
394 @param[in] Register The SMM Save State register to write.
395 @param[in] Width The number of bytes to write to the CPU save state.
396 @param[in] Buffer Upon entry, this holds the new CPU register value.
397
398 @retval EFI_SUCCESS The register was written to Save State.
399 @retval EFI_INVALID_PARAMTER Buffer is NULL.
400 @retval EFI_UNSUPPORTED This function does not support writing Register.
401 **/
402 EFI_STATUS
403 EFIAPI
404 SmmCpuFeaturesWriteSaveStateRegister (
405 IN UINTN CpuIndex,
406 IN EFI_SMM_SAVE_STATE_REGISTER Register,
407 IN UINTN Width,
408 IN CONST VOID *Buffer
409 )
410 {
411 return EFI_UNSUPPORTED;
412 }
413
414 /**
415 This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
416 notification is completely processed.
417 **/
418 VOID
419 EFIAPI
420 SmmCpuFeaturesCompleteSmmReadyToLock (
421 VOID
422 )
423 {
424 }
425
426 /**
427 This API provides a method for a CPU to allocate a specific region for storing page tables.
428
429 This API can be called more once to allocate memory for page tables.
430
431 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
432 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
433 is returned. If there is not enough memory remaining to satisfy the request, then NULL is
434 returned.
435
436 This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.
437
438 @param Pages The number of 4 KB pages to allocate.
439
440 @return A pointer to the allocated buffer for page tables.
441 @retval NULL Fail to allocate a specific region for storing page tables,
442 Or there is no preference on where the page tables are allocated in SMRAM.
443
444 **/
445 VOID *
446 EFIAPI
447 SmmCpuFeaturesAllocatePageTableMemory (
448 IN UINTN Pages
449 )
450 {
451 return NULL;
452 }