QuarkSocPkg/QuarkNorthCluster/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c

   1 /** @file
   2 The Quark CPU specific programming for PiSmmCpuDxeSmm module.
   3
   4 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include <PiSmm.h>
  16 #include <Library/SmmCpuFeaturesLib.h>
  17 #include <Register/SmramSaveStateMap.h>
  18 #include <Library/QNCAccessLib.h>
  19
  20 #define  EFI_MSR_SMRR_PHYS_MASK_VALID          BIT11
  21 #define  EFI_MSR_SMRR_MASK                     0xFFFFF000
  22
  23 /**
  24   Called during the very first SMI into System Management Mode to initialize
  25   CPU features, including SMBASE, for the currently executing CPU.  Since this
  26   is the first SMI, the SMRAM Save State Map is at the default address of
  27   SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET.  The currently executing
  28   CPU is specified by CpuIndex and CpuIndex can be used to access information
  29   about the currently executing CPU in the ProcessorInfo array and the
  30   HotPlugCpuData data structure.
  31
  32   @param[in] CpuIndex        The index of the CPU to initialize.  The value
  33                              must be between 0 and the NumberOfCpus field in
  34                              the System Management System Table (SMST).
  35   @param[in] IsMonarch       TRUE if the CpuIndex is the index of the CPU that
  36                              was elected as monarch during System Management
  37                              Mode initialization.
  38                              FALSE if the CpuIndex is not the index of the CPU
  39                              that was elected as monarch during System
  40                              Management Mode initialization.
  41   @param[in] ProcessorInfo   Pointer to an array of EFI_PROCESSOR_INFORMATION
  42                              structures.  ProcessorInfo[CpuIndex] contains the
  43                              information for the currently executing CPU.
  44   @param[in] CpuHotPlugData  Pointer to the CPU_HOT_PLUG_DATA structure that
  45                              contains the ApidId and SmBase arrays.
  46 **/
  47 VOID
  48 EFIAPI
  49 SmmCpuFeaturesInitializeProcessor (
  50   IN UINTN                      CpuIndex,
  51   IN BOOLEAN                    IsMonarch,
  52   IN EFI_PROCESSOR_INFORMATION  *ProcessorInfo,
  53   IN CPU_HOT_PLUG_DATA          *CpuHotPlugData
  54   )
  55 {
  56   SMRAM_SAVE_STATE_MAP  *CpuState;
  57
  58   //
  59   // Configure SMBASE.
  60   //
  61   CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
  62   CpuState->x86.SMBASE = CpuHotPlugData->SmBase[CpuIndex];
  63
  64   //
  65   // Use QNC to initialize SMRR on Quark
  66   //
  67   QNCPortWrite(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE, CpuHotPlugData->SmrrBase);
  68   QNCPortWrite(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK) | EFI_MSR_SMRR_PHYS_MASK_VALID);
  69 }
  70
  71 /**
  72   This function updates the SMRAM save state on the currently executing CPU
  73   to resume execution at a specific address after an RSM instruction.  This
  74   function must evaluate the SMRAM save state to determine the execution mode
  75   the RSM instruction resumes and update the resume execution address with
  76   either NewInstructionPointer32 or NewInstructionPoint.  The auto HALT restart
  77   flag in the SMRAM save state must always be cleared.  This function returns
  78   the value of the instruction pointer from the SMRAM save state that was
  79   replaced.  If this function returns 0, then the SMRAM save state was not
  80   modified.
  81
  82   This function is called during the very first SMI on each CPU after
  83   SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
  84   to signal that the SMBASE of each CPU has been updated before the default
  85   SMBASE address is used for the first SMI to the next CPU.
  86
  87   @param[in] CpuIndex                 The index of the CPU to hook.  The value
  88                                       must be between 0 and the NumberOfCpus
  89                                       field in the System Management System Table
  90                                       (SMST).
  91   @param[in] CpuState                 Pointer to SMRAM Save State Map for the
  92                                       currently executing CPU.
  93   @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to
  94                                       32-bit execution mode from 64-bit SMM.
  95   @param[in] NewInstructionPointer    Instruction pointer to use if resuming to
  96                                       same execution mode as SMM.
  97
  98   @retval 0    This function did modify the SMRAM save state.
  99   @retval > 0  The original instruction pointer value from the SMRAM save state
 100                before it was replaced.
 101 **/
 102 UINT64
 103 EFIAPI
 104 SmmCpuFeaturesHookReturnFromSmm (
 105   IN UINTN                 CpuIndex,
 106   IN SMRAM_SAVE_STATE_MAP  *CpuState,
 107   IN UINT64                NewInstructionPointer32,
 108   IN UINT64                NewInstructionPointer
 109   )
 110 {
 111   return 0;
 112 }
 113
 114 /**
 115   Hook point in normal execution mode that allows the one CPU that was elected
 116   as monarch during System Management Mode initialization to perform additional
 117   initialization actions immediately after all of the CPUs have processed their
 118   first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE
 119   into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().
 120 **/
 121 VOID
 122 EFIAPI
 123 SmmCpuFeaturesSmmRelocationComplete (
 124   VOID
 125   )
 126 {
 127 }
 128
 129 /**
 130   Return the size, in bytes, of a custom SMI Handler in bytes.  If 0 is
 131   returned, then a custom SMI handler is not provided by this library,
 132   and the default SMI handler must be used.
 133
 134   @retval 0    Use the default SMI handler.
 135   @retval > 0  Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()
 136                The caller is required to allocate enough SMRAM for each CPU to
 137                support the size of the custom SMI handler.
 138 **/
 139 UINTN
 140 EFIAPI
 141 SmmCpuFeaturesGetSmiHandlerSize (
 142   VOID
 143   )
 144 {
 145   return 0;
 146 }
 147
 148 /**
 149   Install a custom SMI handler for the CPU specified by CpuIndex.  This function
 150   is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater
 151   than zero and is called by the CPU that was elected as monarch during System
 152   Management Mode initialization.
 153
 154   @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.
 155                         The value must be between 0 and the NumberOfCpus field
 156                         in the System Management System Table (SMST).
 157   @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.
 158   @param[in] SmiStack   The stack to use when an SMI is processed by the
 159                         the CPU specified by CpuIndex.
 160   @param[in] StackSize  The size, in bytes, if the stack used when an SMI is
 161                         processed by the CPU specified by CpuIndex.
 162   @param[in] GdtBase    The base address of the GDT to use when an SMI is
 163                         processed by the CPU specified by CpuIndex.
 164   @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is
 165                         processed by the CPU specified by CpuIndex.
 166   @param[in] IdtBase    The base address of the IDT to use when an SMI is
 167                         processed by the CPU specified by CpuIndex.
 168   @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is
 169                         processed by the CPU specified by CpuIndex.
 170   @param[in] Cr3        The base address of the page tables to use when an SMI
 171                         is processed by the CPU specified by CpuIndex.
 172 **/
 173 VOID
 174 EFIAPI
 175 SmmCpuFeaturesInstallSmiHandler (
 176   IN UINTN   CpuIndex,
 177   IN UINT32  SmBase,
 178   IN VOID    *SmiStack,
 179   IN UINTN   StackSize,
 180   IN UINTN   GdtBase,
 181   IN UINTN   GdtSize,
 182   IN UINTN   IdtBase,
 183   IN UINTN   IdtSize,
 184   IN UINT32  Cr3
 185   )
 186 {
 187 }
 188
 189 /**
 190   Determines if MTRR registers must be configured to set SMRAM cache-ability
 191   when executing in System Management Mode.
 192
 193   @retval TRUE   MTRR registers must be configured to set SMRAM cache-ability.
 194   @retval FALSE  MTRR registers do not need to be configured to set SMRAM
 195                    cache-ability.
 196 **/
 197 BOOLEAN
 198 EFIAPI
 199 SmmCpuFeaturesNeedConfigureMtrrs (
 200   VOID
 201   )
 202 {
 203   return TRUE;
 204 }
 205
 206 /**
 207   Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
 208   returns TRUE.
 209 **/
 210 VOID
 211 EFIAPI
 212 SmmCpuFeaturesDisableSmrr (
 213   VOID
 214   )
 215 {
 216   //
 217   // Use QNC to disable SMRR on Quark
 218   //
 219   QNCPortWrite(
 220     QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
 221     QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK,
 222     QNCPortRead(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK) & ~EFI_MSR_SMRR_PHYS_MASK_VALID
 223     );
 224 }
 225
 226 /**
 227   Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
 228   returns TRUE.
 229 **/
 230 VOID
 231 EFIAPI
 232 SmmCpuFeaturesReenableSmrr (
 233   VOID
 234   )
 235 {
 236   //
 237   // Use QNC to enable SMRR on Quark
 238   //
 239   QNCPortWrite(
 240     QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
 241     QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK,
 242     QNCPortRead(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK) | EFI_MSR_SMRR_PHYS_MASK_VALID
 243     );
 244 }
 245
 246 /**
 247   Processor specific hook point each time a CPU enters System Management Mode.
 248
 249   @param[in] CpuIndex  The index of the CPU that has entered SMM.  The value
 250                        must be between 0 and the NumberOfCpus field in the
 251                        System Management System Table (SMST).
 252 **/
 253 VOID
 254 EFIAPI
 255 SmmCpuFeaturesRendezvousEntry (
 256   IN UINTN  CpuIndex
 257   )
 258 {
 259 }
 260
 261 /**
 262   Processor specific hook point each time a CPU exits System Management Mode.
 263
 264   @param[in] CpuIndex  The index of the CPU that is exiting SMM.  The value must
 265                        be between 0 and the NumberOfCpus field in the System
 266                        Management System Table (SMST).
 267 **/
 268 VOID
 269 EFIAPI
 270 SmmCpuFeaturesRendezvousExit (
 271   IN UINTN  CpuIndex
 272   )
 273 {
 274 }
 275
 276 /**
 277   Check to see if an SMM register is supported by a specified CPU.
 278
 279   @param[in] CpuIndex  The index of the CPU to check for SMM register support.
 280                        The value must be between 0 and the NumberOfCpus field
 281                        in the System Management System Table (SMST).
 282   @param[in] RegName   Identifies the SMM register to check for support.
 283
 284   @retval TRUE   The SMM register specified by RegName is supported by the CPU
 285                  specified by CpuIndex.
 286   @retval FALSE  The SMM register specified by RegName is not supported by the
 287                  CPU specified by CpuIndex.
 288 **/
 289 BOOLEAN
 290 EFIAPI
 291 SmmCpuFeaturesIsSmmRegisterSupported (
 292   IN UINTN         CpuIndex,
 293   IN SMM_REG_NAME  RegName
 294   )
 295 {
 296   return FALSE;
 297 }
 298
 299 /**
 300   Returns the current value of the SMM register for the specified CPU.
 301   If the SMM register is not supported, then 0 is returned.
 302
 303   @param[in] CpuIndex  The index of the CPU to read the SMM register.  The
 304                        value must be between 0 and the NumberOfCpus field in
 305                        the System Management System Table (SMST).
 306   @param[in] RegName   Identifies the SMM register to read.
 307
 308   @return  The value of the SMM register specified by RegName from the CPU
 309            specified by CpuIndex.
 310 **/
 311 UINT64
 312 EFIAPI
 313 SmmCpuFeaturesGetSmmRegister (
 314   IN UINTN         CpuIndex,
 315   IN SMM_REG_NAME  RegName
 316   )
 317 {
 318   return 0;
 319 }
 320
 321 /**
 322   Sets the value of an SMM register on a specified CPU.
 323   If the SMM register is not supported, then no action is performed.
 324
 325   @param[in] CpuIndex  The index of the CPU to write the SMM register.  The
 326                        value must be between 0 and the NumberOfCpus field in
 327                        the System Management System Table (SMST).
 328   @param[in] RegName   Identifies the SMM register to write.
 329                        registers are read-only.
 330   @param[in] Value     The value to write to the SMM register.
 331 **/
 332 VOID
 333 EFIAPI
 334 SmmCpuFeaturesSetSmmRegister (
 335   IN UINTN         CpuIndex,
 336   IN SMM_REG_NAME  RegName,
 337   IN UINT64        Value
 338   )
 339 {
 340 }
 341
 342 /**
 343   Read an SMM Save State register on the target processor.  If this function
 344   returns EFI_UNSUPPORTED, then the caller is responsible for reading the
 345   SMM Save Sate register.
 346
 347   @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The
 348                         value must be between 0 and the NumberOfCpus field in
 349                         the System Management System Table (SMST).
 350   @param[in]  Register  The SMM Save State register to read.
 351   @param[in]  Width     The number of bytes to read from the CPU save state.
 352   @param[out] Buffer    Upon return, this holds the CPU register value read
 353                         from the save state.
 354
 355   @retval EFI_SUCCESS           The register was read from Save State.
 356   @retval EFI_INVALID_PARAMTER  Buffer is NULL.
 357   @retval EFI_UNSUPPORTED       This function does not support reading Register.
 358
 359 **/
 360 EFI_STATUS
 361 EFIAPI
 362 SmmCpuFeaturesReadSaveStateRegister (
 363   IN  UINTN                        CpuIndex,
 364   IN  EFI_SMM_SAVE_STATE_REGISTER  Register,
 365   IN  UINTN                        Width,
 366   OUT VOID                         *Buffer
 367   )
 368 {
 369   return EFI_UNSUPPORTED;
 370 }
 371
 372 /**
 373   Writes an SMM Save State register on the target processor.  If this function
 374   returns EFI_UNSUPPORTED, then the caller is responsible for writing the
 375   SMM Save Sate register.
 376
 377   @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The
 378                        value must be between 0 and the NumberOfCpus field in
 379                        the System Management System Table (SMST).
 380   @param[in] Register  The SMM Save State register to write.
 381   @param[in] Width     The number of bytes to write to the CPU save state.
 382   @param[in] Buffer    Upon entry, this holds the new CPU register value.
 383
 384   @retval EFI_SUCCESS           The register was written to Save State.
 385   @retval EFI_INVALID_PARAMTER  Buffer is NULL.
 386   @retval EFI_UNSUPPORTED       This function does not support writing Register.
 387 **/
 388 EFI_STATUS
 389 EFIAPI
 390 SmmCpuFeaturesWriteSaveStateRegister (
 391   IN UINTN                        CpuIndex,
 392   IN EFI_SMM_SAVE_STATE_REGISTER  Register,
 393   IN UINTN                        Width,
 394   IN CONST VOID                   *Buffer
 395   )
 396 {
 397   return EFI_UNSUPPORTED;
 398 }
 399
 400 /**
 401   This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
 402   notification is completely processed.
 403 **/
 404 VOID
 405 EFIAPI
 406 SmmCpuFeaturesCompleteSmmReadyToLock (
 407   VOID
 408   )
 409 {
 410 }
 411
 412 /**
 413   This API provides a method for a CPU to allocate a specific region for storing page tables.
 414
 415   This API can be called more once to allocate memory for page tables.
 416
 417   Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
 418   allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL
 419   is returned.  If there is not enough memory remaining to satisfy the request, then NULL is
 420   returned.
 421
 422   This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.
 423
 424   @param  Pages                 The number of 4 KB pages to allocate.
 425
 426   @return A pointer to the allocated buffer for page tables.
 427   @retval NULL      Fail to allocate a specific region for storing page tables,
 428                     Or there is no preference on where the page tables are allocated in SMRAM.
 429
 430 **/
 431 VOID *
 432 EFIAPI
 433 SmmCpuFeaturesAllocatePageTableMemory (
 434   IN UINTN           Pages
 435   )
 436 {
 437   return NULL;
 438 }