2 This library is only intended to be used by TPM modules.
3 It provides basic TPM Interface Specification (TIS) and Command functions.
5 Copyright (c) 2005 - 2018, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
10 #ifndef _TPM_COMM_LIB_H_
11 #define _TPM_COMM_LIB_H_
13 #include <IndustryStandard/Tpm12.h>
15 typedef EFI_HANDLE TIS_TPM_HANDLE
;
18 /// TPM register base address.
20 #define TPM_BASE_ADDRESS 0xfed40000
23 // Set structure alignment to 1-byte
28 // Register set map as specified in TIS specification Chapter 10
32 /// Used to gain ownership for this particular port.
35 UINT8 Reserved1
[7]; // 1
37 /// Controls interrupts.
39 UINT32 IntEnable
; // 8
41 /// SIRQ vector to be used by the TPM.
43 UINT8 IntVector
; // 0ch
44 UINT8 Reserved2
[3]; // 0dh
46 /// What caused interrupt.
50 /// Shows which interrupts are supported by that particular TPM.
52 UINT32 IntfCapability
; // 14h
54 /// Status Register. Provides status of the TPM.
58 /// Number of consecutive writes that can be done to the TPM.
60 UINT16 BurstCount
; // 19h
63 /// Read or write FIFO, depending on transaction.
65 UINT32 DataFifo
; // 24
66 UINT8 Reserved4
[0xed8]; // 28h
80 /// TCG defined configuration registers.
82 UINT8 TcgDefined
[0x7b]; // 0f05h
84 /// Alias to I/O legacy space.
86 UINT32 LegacyAddress1
; // 0f80h
88 /// Additional 8 bits for I/O legacy space extension.
90 UINT32 LegacyAddress1Ex
; // 0f84h
92 /// Alias to second I/O legacy space.
94 UINT32 LegacyAddress2
; // 0f88h
96 /// Additional 8 bits for second I/O legacy space extension.
98 UINT32 LegacyAddress2Ex
; // 0f8ch
100 /// Vendor-defined configuration registers.
102 UINT8 VendorDefined
[0x70];// 0f90h
106 // Restore original structure alignment
111 // Define pointer types used to access TIS registers on PC
113 typedef TIS_PC_REGISTERS
*TIS_PC_REGISTERS_PTR
;
116 // TCG Platform Type based on TCG ACPI Specification Version 1.00
118 #define TCG_PLATFORM_TYPE_CLIENT 0
119 #define TCG_PLATFORM_TYPE_SERVER 1
122 // Define bits of ACCESS and STATUS registers
126 /// This bit is a 1 to indicate that the other bits in this register are valid.
128 #define TIS_PC_VALID BIT7
130 /// Indicate that this locality is active.
132 #define TIS_PC_ACC_ACTIVE BIT5
134 /// Set to 1 to indicate that this locality had the TPM taken away while
135 /// this locality had the TIS_PC_ACC_ACTIVE bit set.
137 #define TIS_PC_ACC_SEIZED BIT4
139 /// Set to 1 to indicate that TPM MUST reset the
140 /// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
141 /// locality that is writing this bit.
143 #define TIS_PC_ACC_SEIZE BIT3
145 /// When this bit is 1, another locality is requesting usage of the TPM.
147 #define TIS_PC_ACC_PENDIND BIT2
149 /// Set to 1 to indicate that this locality is requesting to use TPM.
151 #define TIS_PC_ACC_RQUUSE BIT1
153 /// A value of 1 indicates that a T/OS has not been established on the platform
155 #define TIS_PC_ACC_ESTABLISH BIT0
158 /// When this bit is 1, TPM is in the Ready state,
159 /// indicating it is ready to receive a new command.
161 #define TIS_PC_STS_READY BIT6
163 /// Write a 1 to this bit to cause the TPM to execute that command.
165 #define TIS_PC_STS_GO BIT5
167 /// This bit indicates that the TPM has data available as a response.
169 #define TIS_PC_STS_DATA BIT4
171 /// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
173 #define TIS_PC_STS_EXPECT BIT3
175 /// Writes a 1 to this bit to force the TPM to re-send the response.
177 #define TIS_PC_STS_RETRY BIT1
180 // Default TimeOut value
182 #define TIS_TIMEOUT_A 750 * 1000 // 750ms
183 #define TIS_TIMEOUT_B 2000 * 1000 // 2s
184 #define TIS_TIMEOUT_C 750 * 1000 // 750ms
185 #define TIS_TIMEOUT_D 750 * 1000 // 750ms
188 // Max TPM command/reponse length
190 #define TPMCMDBUFLENGTH 1024
193 Check whether the value of a TPM chip register satisfies the input BIT setting.
195 @param[in] Register Address port of register to be checked.
196 @param[in] BitSet Check these data bits are set.
197 @param[in] BitClear Check these data bits are clear.
198 @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.
200 @retval EFI_SUCCESS The register satisfies the check bit.
201 @retval EFI_TIMEOUT The register can't run into the expected status in time.
205 TisPcWaitRegisterBits (
213 Get BurstCount by reading the burstCount field of a TIS regiger
214 in the time of default TIS_TIMEOUT_D.
216 @param[in] TisReg Pointer to TIS register.
217 @param[out] BurstCount Pointer to a buffer to store the got BurstCount.
219 @retval EFI_SUCCESS Get BurstCount.
220 @retval EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.
221 @retval EFI_TIMEOUT BurstCount can't be got in time.
225 TisPcReadBurstCount (
226 IN TIS_PC_REGISTERS_PTR TisReg
,
227 OUT UINT16
*BurstCount
231 Set TPM chip to ready state by sending ready command TIS_PC_STS_READY
232 to Status Register in time.
234 @param[in] TisReg Pointer to TIS register.
236 @retval EFI_SUCCESS TPM chip enters into ready state.
237 @retval EFI_INVALID_PARAMETER TisReg is NULL.
238 @retval EFI_TIMEOUT TPM chip can't be set to ready state in time.
242 TisPcPrepareCommand (
243 IN TIS_PC_REGISTERS_PTR TisReg
247 Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE
248 to ACCESS Register in the time of default TIS_TIMEOUT_D.
250 @param[in] TisReg Pointer to TIS register.
252 @retval EFI_SUCCESS Get the control of TPM chip.
253 @retval EFI_INVALID_PARAMETER TisReg is NULL.
254 @retval EFI_NOT_FOUND TPM chip doesn't exit.
255 @retval EFI_TIMEOUT Can't get the TPM control in time.
260 IN TIS_PC_REGISTERS_PTR TisReg
264 Single function calculates SHA1 digest value for all raw data. It
265 combines Sha1Init(), Sha1Update() and Sha1Final().
267 @param[in] Data Raw data to be digested.
268 @param[in] DataLen Size of the raw data.
269 @param[out] Digest Pointer to a buffer that stores the final digest.
271 @retval EFI_SUCCESS Always successfully calculate the final digest.
276 IN CONST UINT8
*Data
,
278 OUT TPM_DIGEST
*Digest