2ad5345927661d1d343e044140f4ac9d21f526fb
[mirror_edk2.git] / SecurityPkg / Library / Tpm12DeviceLibDTpm / Tpm12Tis.c
1 /** @file
2 TIS (TPM Interface Specification) functions used by TPM1.2.
3
4 Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include <Uefi.h>
16 #include <IndustryStandard/Tpm12.h>
17 #include <Library/BaseLib.h>
18 #include <Library/BaseMemoryLib.h>
19 #include <Library/IoLib.h>
20 #include <Library/TimerLib.h>
21 #include <Library/DebugLib.h>
22 #include <Library/Tpm12CommandLib.h>
23 #include <Library/PcdLib.h>
24
25 //
26 // Set structure alignment to 1-byte
27 //
28 #pragma pack (1)
29
30 //
31 // Register set map as specified in TIS specification Chapter 10
32 //
33 typedef struct {
34 ///
35 /// Used to gain ownership for this particular port.
36 ///
37 UINT8 Access; // 0
38 UINT8 Reserved1[7]; // 1
39 ///
40 /// Controls interrupts.
41 ///
42 UINT32 IntEnable; // 8
43 ///
44 /// SIRQ vector to be used by the TPM.
45 ///
46 UINT8 IntVector; // 0ch
47 UINT8 Reserved2[3]; // 0dh
48 ///
49 /// What caused interrupt.
50 ///
51 UINT32 IntSts; // 10h
52 ///
53 /// Shows which interrupts are supported by that particular TPM.
54 ///
55 UINT32 IntfCapability; // 14h
56 ///
57 /// Status Register. Provides status of the TPM.
58 ///
59 UINT8 Status; // 18h
60 ///
61 /// Number of consecutive writes that can be done to the TPM.
62 ///
63 UINT16 BurstCount; // 19h
64 UINT8 Reserved3[9];
65 ///
66 /// Read or write FIFO, depending on transaction.
67 ///
68 UINT32 DataFifo; // 24h
69 UINT8 Reserved4[0xed8]; // 28h
70 ///
71 /// Vendor ID
72 ///
73 UINT16 Vid; // 0f00h
74 ///
75 /// Device ID
76 ///
77 UINT16 Did; // 0f02h
78 ///
79 /// Revision ID
80 ///
81 UINT8 Rid; // 0f04h
82 ///
83 /// TCG defined configuration registers.
84 ///
85 UINT8 TcgDefined[0x7b]; // 0f05h
86 ///
87 /// Alias to I/O legacy space.
88 ///
89 UINT32 LegacyAddress1; // 0f80h
90 ///
91 /// Additional 8 bits for I/O legacy space extension.
92 ///
93 UINT32 LegacyAddress1Ex; // 0f84h
94 ///
95 /// Alias to second I/O legacy space.
96 ///
97 UINT32 LegacyAddress2; // 0f88h
98 ///
99 /// Additional 8 bits for second I/O legacy space extension.
100 ///
101 UINT32 LegacyAddress2Ex; // 0f8ch
102 ///
103 /// Vendor-defined configuration registers.
104 ///
105 UINT8 VendorDefined[0x70];// 0f90h
106 } TIS_PC_REGISTERS;
107
108 //
109 // Restore original structure alignment
110 //
111 #pragma pack ()
112
113 //
114 // Define pointer types used to access TIS registers on PC
115 //
116 typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;
117
118 //
119 // Define bits of ACCESS and STATUS registers
120 //
121
122 ///
123 /// This bit is a 1 to indicate that the other bits in this register are valid.
124 ///
125 #define TIS_PC_VALID BIT7
126 ///
127 /// Indicate that this locality is active.
128 ///
129 #define TIS_PC_ACC_ACTIVE BIT5
130 ///
131 /// Set to 1 to indicate that this locality had the TPM taken away while
132 /// this locality had the TIS_PC_ACC_ACTIVE bit set.
133 ///
134 #define TIS_PC_ACC_SEIZED BIT4
135 ///
136 /// Set to 1 to indicate that TPM MUST reset the
137 /// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
138 /// locality that is writing this bit.
139 ///
140 #define TIS_PC_ACC_SEIZE BIT3
141 ///
142 /// When this bit is 1, another locality is requesting usage of the TPM.
143 ///
144 #define TIS_PC_ACC_PENDIND BIT2
145 ///
146 /// Set to 1 to indicate that this locality is requesting to use TPM.
147 ///
148 #define TIS_PC_ACC_RQUUSE BIT1
149 ///
150 /// A value of 1 indicates that a T/OS has not been established on the platform
151 ///
152 #define TIS_PC_ACC_ESTABLISH BIT0
153
154 ///
155 /// When this bit is 1, TPM is in the Ready state,
156 /// indicating it is ready to receive a new command.
157 ///
158 #define TIS_PC_STS_READY BIT6
159 ///
160 /// Write a 1 to this bit to cause the TPM to execute that command.
161 ///
162 #define TIS_PC_STS_GO BIT5
163 ///
164 /// This bit indicates that the TPM has data available as a response.
165 ///
166 #define TIS_PC_STS_DATA BIT4
167 ///
168 /// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
169 ///
170 #define TIS_PC_STS_EXPECT BIT3
171 ///
172 /// Writes a 1 to this bit to force the TPM to re-send the response.
173 ///
174 #define TIS_PC_STS_RETRY BIT1
175
176 //
177 // Default TimeOut value
178 //
179 #define TIS_TIMEOUT_A (750 * 1000) // 750ms
180 #define TIS_TIMEOUT_B (2000 * 1000) // 2s
181 #define TIS_TIMEOUT_C (750 * 1000) // 750ms
182 #define TIS_TIMEOUT_D (750 * 1000) // 750ms
183
184 //
185 // Max TPM command/reponse length
186 //
187 #define TPMCMDBUFLENGTH 1024
188
189 /**
190 Check whether TPM chip exist.
191
192 @param[in] TisReg Pointer to TIS register.
193
194 @retval TRUE TPM chip exists.
195 @retval FALSE TPM chip is not found.
196 **/
197 BOOLEAN
198 Tpm12TisPcPresenceCheck (
199 IN TIS_PC_REGISTERS_PTR TisReg
200 )
201 {
202 UINT8 RegRead;
203
204 RegRead = MmioRead8 ((UINTN)&TisReg->Access);
205 return (BOOLEAN)(RegRead != (UINT8)-1);
206 }
207
208 /**
209 Check whether the value of a TPM chip register satisfies the input BIT setting.
210
211 @param[in] Register Address port of register to be checked.
212 @param[in] BitSet Check these data bits are set.
213 @param[in] BitClear Check these data bits are clear.
214 @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.
215
216 @retval EFI_SUCCESS The register satisfies the check bit.
217 @retval EFI_TIMEOUT The register can't run into the expected status in time.
218 **/
219 EFI_STATUS
220 EFIAPI
221 Tpm12TisPcWaitRegisterBits (
222 IN UINT8 *Register,
223 IN UINT8 BitSet,
224 IN UINT8 BitClear,
225 IN UINT32 TimeOut
226 )
227 {
228 UINT8 RegRead;
229 UINT32 WaitTime;
230
231 for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
232 RegRead = MmioRead8 ((UINTN)Register);
233 if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)
234 return EFI_SUCCESS;
235 MicroSecondDelay (30);
236 }
237 return EFI_TIMEOUT;
238 }
239
240 /**
241 Get BurstCount by reading the burstCount field of a TIS regiger
242 in the time of default TIS_TIMEOUT_D.
243
244 @param[in] TisReg Pointer to TIS register.
245 @param[out] BurstCount Pointer to a buffer to store the got BurstConut.
246
247 @retval EFI_SUCCESS Get BurstCount.
248 @retval EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.
249 @retval EFI_TIMEOUT BurstCount can't be got in time.
250 **/
251 EFI_STATUS
252 EFIAPI
253 Tpm12TisPcReadBurstCount (
254 IN TIS_PC_REGISTERS_PTR TisReg,
255 OUT UINT16 *BurstCount
256 )
257 {
258 UINT32 WaitTime;
259 UINT8 DataByte0;
260 UINT8 DataByte1;
261
262 if (BurstCount == NULL || TisReg == NULL) {
263 return EFI_INVALID_PARAMETER;
264 }
265
266 WaitTime = 0;
267 do {
268 //
269 // TIS_PC_REGISTERS_PTR->burstCount is UINT16, but it is not 2bytes aligned,
270 // so it needs to use MmioRead8 to read two times
271 //
272 DataByte0 = MmioRead8 ((UINTN)&TisReg->BurstCount);
273 DataByte1 = MmioRead8 ((UINTN)&TisReg->BurstCount + 1);
274 *BurstCount = (UINT16)((DataByte1 << 8) + DataByte0);
275 if (*BurstCount != 0) {
276 return EFI_SUCCESS;
277 }
278 MicroSecondDelay (30);
279 WaitTime += 30;
280 } while (WaitTime < TIS_TIMEOUT_D);
281
282 return EFI_TIMEOUT;
283 }
284
285 /**
286 Set TPM chip to ready state by sending ready command TIS_PC_STS_READY
287 to Status Register in time.
288
289 @param[in] TisReg Pointer to TIS register.
290
291 @retval EFI_SUCCESS TPM chip enters into ready state.
292 @retval EFI_INVALID_PARAMETER TisReg is NULL.
293 @retval EFI_TIMEOUT TPM chip can't be set to ready state in time.
294 **/
295 EFI_STATUS
296 EFIAPI
297 Tpm12TisPcPrepareCommand (
298 IN TIS_PC_REGISTERS_PTR TisReg
299 )
300 {
301 EFI_STATUS Status;
302
303 if (TisReg == NULL) {
304 return EFI_INVALID_PARAMETER;
305 }
306
307 MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
308 Status = Tpm12TisPcWaitRegisterBits (
309 &TisReg->Status,
310 TIS_PC_STS_READY,
311 0,
312 TIS_TIMEOUT_B
313 );
314 return Status;
315 }
316
317 /**
318 Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE
319 to ACCESS Register in the time of default TIS_TIMEOUT_A.
320
321 @param[in] TisReg Pointer to TIS register.
322
323 @retval EFI_SUCCESS Get the control of TPM chip.
324 @retval EFI_INVALID_PARAMETER TisReg is NULL.
325 @retval EFI_NOT_FOUND TPM chip doesn't exit.
326 @retval EFI_TIMEOUT Can't get the TPM control in time.
327 **/
328 EFI_STATUS
329 EFIAPI
330 Tpm12TisPcRequestUseTpm (
331 IN TIS_PC_REGISTERS_PTR TisReg
332 )
333 {
334 EFI_STATUS Status;
335
336 if (TisReg == NULL) {
337 return EFI_INVALID_PARAMETER;
338 }
339
340 if (!Tpm12TisPcPresenceCheck (TisReg)) {
341 return EFI_NOT_FOUND;
342 }
343
344 MmioWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);
345 Status = Tpm12TisPcWaitRegisterBits (
346 &TisReg->Access,
347 (UINT8)(TIS_PC_ACC_ACTIVE |TIS_PC_VALID),
348 0,
349 TIS_TIMEOUT_A
350 );
351 return Status;
352 }
353
354 /**
355 Send a command to TPM for execution and return response data.
356
357 @param[in] TisReg TPM register space base address.
358 @param[in] BufferIn Buffer for command data.
359 @param[in] SizeIn Size of command data.
360 @param[in, out] BufferOut Buffer for response data.
361 @param[in, out] SizeOut Size of response data.
362
363 @retval EFI_SUCCESS Operation completed successfully.
364 @retval EFI_TIMEOUT The register can't run into the expected status in time.
365 @retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.
366 @retval EFI_DEVICE_ERROR Unexpected device behavior.
367 @retval EFI_UNSUPPORTED Unsupported TPM version
368
369 **/
370 EFI_STATUS
371 Tpm12TisTpmCommand (
372 IN TIS_PC_REGISTERS_PTR TisReg,
373 IN UINT8 *BufferIn,
374 IN UINT32 SizeIn,
375 IN OUT UINT8 *BufferOut,
376 IN OUT UINT32 *SizeOut
377 )
378 {
379 EFI_STATUS Status;
380 UINT16 BurstCount;
381 UINT32 Index;
382 UINT32 TpmOutSize;
383 UINT16 Data16;
384 UINT32 Data32;
385
386 DEBUG_CODE (
387 UINTN DebugSize;
388
389 DEBUG ((EFI_D_INFO, "Tpm12TisTpmCommand Send - "));
390 if (SizeIn > 0x100) {
391 DebugSize = 0x40;
392 } else {
393 DebugSize = SizeIn;
394 }
395 for (Index = 0; Index < DebugSize; Index++) {
396 DEBUG ((EFI_D_INFO, "%02x ", BufferIn[Index]));
397 }
398 if (DebugSize != SizeIn) {
399 DEBUG ((EFI_D_INFO, "...... "));
400 for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {
401 DEBUG ((EFI_D_INFO, "%02x ", BufferIn[Index]));
402 }
403 }
404 DEBUG ((EFI_D_INFO, "\n"));
405 );
406 TpmOutSize = 0;
407
408 Status = Tpm12TisPcPrepareCommand (TisReg);
409 if (EFI_ERROR (Status)){
410 DEBUG ((DEBUG_ERROR, "Tpm12 is not ready for command!\n"));
411 return Status;
412 }
413 //
414 // Send the command data to Tpm
415 //
416 Index = 0;
417 while (Index < SizeIn) {
418 Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);
419 if (EFI_ERROR (Status)) {
420 Status = EFI_TIMEOUT;
421 goto Exit;
422 }
423 for (; BurstCount > 0 && Index < SizeIn; BurstCount--) {
424 MmioWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));
425 Index++;
426 }
427 }
428 //
429 // Check the Tpm status STS_EXPECT change from 1 to 0
430 //
431 Status = Tpm12TisPcWaitRegisterBits (
432 &TisReg->Status,
433 (UINT8) TIS_PC_VALID,
434 TIS_PC_STS_EXPECT,
435 TIS_TIMEOUT_C
436 );
437 if (EFI_ERROR (Status)) {
438 DEBUG ((DEBUG_ERROR, "Tpm12 The send buffer too small!\n"));
439 Status = EFI_BUFFER_TOO_SMALL;
440 goto Exit;
441 }
442 //
443 // Executed the TPM command and waiting for the response data ready
444 //
445 MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);
446 Status = Tpm12TisPcWaitRegisterBits (
447 &TisReg->Status,
448 (UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA),
449 0,
450 TIS_TIMEOUT_B
451 );
452 if (EFI_ERROR (Status)) {
453 DEBUG ((DEBUG_ERROR, "Wait for Tpm12 response data time out!!\n"));
454 Status = EFI_TIMEOUT;
455 goto Exit;
456 }
457 //
458 // Get response data header
459 //
460 Index = 0;
461 BurstCount = 0;
462 while (Index < sizeof (TPM_RSP_COMMAND_HDR)) {
463 Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);
464 if (EFI_ERROR (Status)) {
465 Status = EFI_TIMEOUT;
466 goto Exit;
467 }
468 for (; BurstCount > 0; BurstCount--) {
469 *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
470 Index++;
471 if (Index == sizeof (TPM_RSP_COMMAND_HDR)) break;
472 }
473 }
474 DEBUG_CODE (
475 DEBUG ((EFI_D_INFO, "Tpm12TisTpmCommand ReceiveHeader - "));
476 for (Index = 0; Index < sizeof (TPM_RSP_COMMAND_HDR); Index++) {
477 DEBUG ((EFI_D_INFO, "%02x ", BufferOut[Index]));
478 }
479 DEBUG ((EFI_D_INFO, "\n"));
480 );
481 //
482 // Check the reponse data header (tag,parasize and returncode )
483 //
484 CopyMem (&Data16, BufferOut, sizeof (UINT16));
485 if (SwapBytes16 (Data16) != TPM_TAG_RSP_COMMAND) {
486 DEBUG ((EFI_D_ERROR, "TPM12: TPM_ST_RSP error - %x\n", TPM_TAG_RSP_COMMAND));
487 Status = EFI_UNSUPPORTED;
488 goto Exit;
489 }
490
491 CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));
492 TpmOutSize = SwapBytes32 (Data32);
493 if (*SizeOut < TpmOutSize) {
494 Status = EFI_BUFFER_TOO_SMALL;
495 goto Exit;
496 }
497 *SizeOut = TpmOutSize;
498 //
499 // Continue reading the remaining data
500 //
501 while ( Index < TpmOutSize ) {
502 for (; BurstCount > 0; BurstCount--) {
503 *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
504 Index++;
505 if (Index == TpmOutSize) {
506 Status = EFI_SUCCESS;
507 goto Exit;
508 }
509 }
510 Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);
511 if (EFI_ERROR (Status)) {
512 Status = EFI_TIMEOUT;
513 goto Exit;
514 }
515 }
516 Exit:
517 DEBUG_CODE (
518 DEBUG ((EFI_D_INFO, "Tpm12TisTpmCommand Receive - "));
519 for (Index = 0; Index < TpmOutSize; Index++) {
520 DEBUG ((EFI_D_INFO, "%02x ", BufferOut[Index]));
521 }
522 DEBUG ((EFI_D_INFO, "\n"));
523 );
524 MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
525 return Status;
526 }
527
528 /**
529 This service enables the sending of commands to the TPM12.
530
531 @param[in] InputParameterBlockSize Size of the TPM12 input parameter block.
532 @param[in] InputParameterBlock Pointer to the TPM12 input parameter block.
533 @param[in,out] OutputParameterBlockSize Size of the TPM12 output parameter block.
534 @param[in] OutputParameterBlock Pointer to the TPM12 output parameter block.
535
536 @retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.
537 @retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.
538 @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small.
539 **/
540 EFI_STATUS
541 EFIAPI
542 Tpm12SubmitCommand (
543 IN UINT32 InputParameterBlockSize,
544 IN UINT8 *InputParameterBlock,
545 IN OUT UINT32 *OutputParameterBlockSize,
546 IN UINT8 *OutputParameterBlock
547 )
548 {
549 return Tpm12TisTpmCommand (
550 (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),
551 InputParameterBlock,
552 InputParameterBlockSize,
553 OutputParameterBlock,
554 OutputParameterBlockSize
555 );
556 }
557
558 /**
559 This service requests use TPM12.
560
561 @retval EFI_SUCCESS Get the control of TPM12 chip.
562 @retval EFI_NOT_FOUND TPM12 not found.
563 @retval EFI_DEVICE_ERROR Unexpected device behavior.
564 **/
565 EFI_STATUS
566 EFIAPI
567 Tpm12RequestUseTpm (
568 VOID
569 )
570 {
571 return Tpm12TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
572 }