Handle TPM device error and avoid deadloop in BDS.
[mirror_edk2.git] / SecurityPkg / Library / Tpm12DeviceLibDTpm / Tpm12Tis.c
1 /** @file
2 TIS (TPM Interface Specification) functions used by TPM1.2.
3
4 Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include <Uefi.h>
16 #include <IndustryStandard/Tpm12.h>
17 #include <Library/BaseLib.h>
18 #include <Library/BaseMemoryLib.h>
19 #include <Library/IoLib.h>
20 #include <Library/TimerLib.h>
21 #include <Library/DebugLib.h>
22 #include <Library/Tpm12CommandLib.h>
23 #include <Library/PcdLib.h>
24
25 //
26 // Set structure alignment to 1-byte
27 //
28 #pragma pack (1)
29
30 //
31 // Register set map as specified in TIS specification Chapter 10
32 //
33 typedef struct {
34 ///
35 /// Used to gain ownership for this particular port.
36 ///
37 UINT8 Access; // 0
38 UINT8 Reserved1[7]; // 1
39 ///
40 /// Controls interrupts.
41 ///
42 UINT32 IntEnable; // 8
43 ///
44 /// SIRQ vector to be used by the TPM.
45 ///
46 UINT8 IntVector; // 0ch
47 UINT8 Reserved2[3]; // 0dh
48 ///
49 /// What caused interrupt.
50 ///
51 UINT32 IntSts; // 10h
52 ///
53 /// Shows which interrupts are supported by that particular TPM.
54 ///
55 UINT32 IntfCapability; // 14h
56 ///
57 /// Status Register. Provides status of the TPM.
58 ///
59 UINT8 Status; // 18h
60 ///
61 /// Number of consecutive writes that can be done to the TPM.
62 ///
63 UINT16 BurstCount; // 19h
64 UINT8 Reserved3[9];
65 ///
66 /// Read or write FIFO, depending on transaction.
67 ///
68 UINT32 DataFifo; // 24h
69 UINT8 Reserved4[0xed8]; // 28h
70 ///
71 /// Vendor ID
72 ///
73 UINT16 Vid; // 0f00h
74 ///
75 /// Device ID
76 ///
77 UINT16 Did; // 0f02h
78 ///
79 /// Revision ID
80 ///
81 UINT8 Rid; // 0f04h
82 ///
83 /// TCG defined configuration registers.
84 ///
85 UINT8 TcgDefined[0x7b]; // 0f05h
86 ///
87 /// Alias to I/O legacy space.
88 ///
89 UINT32 LegacyAddress1; // 0f80h
90 ///
91 /// Additional 8 bits for I/O legacy space extension.
92 ///
93 UINT32 LegacyAddress1Ex; // 0f84h
94 ///
95 /// Alias to second I/O legacy space.
96 ///
97 UINT32 LegacyAddress2; // 0f88h
98 ///
99 /// Additional 8 bits for second I/O legacy space extension.
100 ///
101 UINT32 LegacyAddress2Ex; // 0f8ch
102 ///
103 /// Vendor-defined configuration registers.
104 ///
105 UINT8 VendorDefined[0x70];// 0f90h
106 } TIS_PC_REGISTERS;
107
108 //
109 // Restore original structure alignment
110 //
111 #pragma pack ()
112
113 //
114 // Define pointer types used to access TIS registers on PC
115 //
116 typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;
117
118 //
119 // Define bits of ACCESS and STATUS registers
120 //
121
122 ///
123 /// This bit is a 1 to indicate that the other bits in this register are valid.
124 ///
125 #define TIS_PC_VALID BIT7
126 ///
127 /// Indicate that this locality is active.
128 ///
129 #define TIS_PC_ACC_ACTIVE BIT5
130 ///
131 /// Set to 1 to indicate that this locality had the TPM taken away while
132 /// this locality had the TIS_PC_ACC_ACTIVE bit set.
133 ///
134 #define TIS_PC_ACC_SEIZED BIT4
135 ///
136 /// Set to 1 to indicate that TPM MUST reset the
137 /// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
138 /// locality that is writing this bit.
139 ///
140 #define TIS_PC_ACC_SEIZE BIT3
141 ///
142 /// When this bit is 1, another locality is requesting usage of the TPM.
143 ///
144 #define TIS_PC_ACC_PENDIND BIT2
145 ///
146 /// Set to 1 to indicate that this locality is requesting to use TPM.
147 ///
148 #define TIS_PC_ACC_RQUUSE BIT1
149 ///
150 /// A value of 1 indicates that a T/OS has not been established on the platform
151 ///
152 #define TIS_PC_ACC_ESTABLISH BIT0
153
154 ///
155 /// When this bit is 1, TPM is in the Ready state,
156 /// indicating it is ready to receive a new command.
157 ///
158 #define TIS_PC_STS_READY BIT6
159 ///
160 /// Write a 1 to this bit to cause the TPM to execute that command.
161 ///
162 #define TIS_PC_STS_GO BIT5
163 ///
164 /// This bit indicates that the TPM has data available as a response.
165 ///
166 #define TIS_PC_STS_DATA BIT4
167 ///
168 /// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
169 ///
170 #define TIS_PC_STS_EXPECT BIT3
171 ///
172 /// Writes a 1 to this bit to force the TPM to re-send the response.
173 ///
174 #define TIS_PC_STS_RETRY BIT1
175
176 //
177 // Default TimeOut value
178 //
179 #define TIS_TIMEOUT_A (750 * 1000) // 750ms
180 #define TIS_TIMEOUT_B (2000 * 1000) // 2s
181 #define TIS_TIMEOUT_C (750 * 1000) // 750ms
182 #define TIS_TIMEOUT_D (750 * 1000) // 750ms
183
184 //
185 // Max TPM command/reponse length
186 //
187 #define TPMCMDBUFLENGTH 1024
188
189 /**
190 Check whether TPM chip exist.
191
192 @param[in] TisReg Pointer to TIS register.
193
194 @retval TRUE TPM chip exists.
195 @retval FALSE TPM chip is not found.
196 **/
197 BOOLEAN
198 Tpm12TisPcPresenceCheck (
199 IN TIS_PC_REGISTERS_PTR TisReg
200 )
201 {
202 UINT8 RegRead;
203
204 RegRead = MmioRead8 ((UINTN)&TisReg->Access);
205 return (BOOLEAN)(RegRead != (UINT8)-1);
206 }
207
208 /**
209 Check whether the value of a TPM chip register satisfies the input BIT setting.
210
211 @param[in] Register Address port of register to be checked.
212 @param[in] BitSet Check these data bits are set.
213 @param[in] BitClear Check these data bits are clear.
214 @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.
215
216 @retval EFI_SUCCESS The register satisfies the check bit.
217 @retval EFI_TIMEOUT The register can't run into the expected status in time.
218 **/
219 EFI_STATUS
220 Tpm12TisPcWaitRegisterBits (
221 IN UINT8 *Register,
222 IN UINT8 BitSet,
223 IN UINT8 BitClear,
224 IN UINT32 TimeOut
225 )
226 {
227 UINT8 RegRead;
228 UINT32 WaitTime;
229
230 for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
231 RegRead = MmioRead8 ((UINTN)Register);
232 if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)
233 return EFI_SUCCESS;
234 MicroSecondDelay (30);
235 }
236 return EFI_TIMEOUT;
237 }
238
239 /**
240 Get BurstCount by reading the burstCount field of a TIS regiger
241 in the time of default TIS_TIMEOUT_D.
242
243 @param[in] TisReg Pointer to TIS register.
244 @param[out] BurstCount Pointer to a buffer to store the got BurstConut.
245
246 @retval EFI_SUCCESS Get BurstCount.
247 @retval EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.
248 @retval EFI_TIMEOUT BurstCount can't be got in time.
249 **/
250 EFI_STATUS
251 Tpm12TisPcReadBurstCount (
252 IN TIS_PC_REGISTERS_PTR TisReg,
253 OUT UINT16 *BurstCount
254 )
255 {
256 UINT32 WaitTime;
257 UINT8 DataByte0;
258 UINT8 DataByte1;
259
260 if (BurstCount == NULL || TisReg == NULL) {
261 return EFI_INVALID_PARAMETER;
262 }
263
264 WaitTime = 0;
265 do {
266 //
267 // TIS_PC_REGISTERS_PTR->burstCount is UINT16, but it is not 2bytes aligned,
268 // so it needs to use MmioRead8 to read two times
269 //
270 DataByte0 = MmioRead8 ((UINTN)&TisReg->BurstCount);
271 DataByte1 = MmioRead8 ((UINTN)&TisReg->BurstCount + 1);
272 *BurstCount = (UINT16)((DataByte1 << 8) + DataByte0);
273 if (*BurstCount != 0) {
274 return EFI_SUCCESS;
275 }
276 MicroSecondDelay (30);
277 WaitTime += 30;
278 } while (WaitTime < TIS_TIMEOUT_D);
279
280 return EFI_TIMEOUT;
281 }
282
283 /**
284 Set TPM chip to ready state by sending ready command TIS_PC_STS_READY
285 to Status Register in time.
286
287 @param[in] TisReg Pointer to TIS register.
288
289 @retval EFI_SUCCESS TPM chip enters into ready state.
290 @retval EFI_INVALID_PARAMETER TisReg is NULL.
291 @retval EFI_TIMEOUT TPM chip can't be set to ready state in time.
292 **/
293 EFI_STATUS
294 Tpm12TisPcPrepareCommand (
295 IN TIS_PC_REGISTERS_PTR TisReg
296 )
297 {
298 EFI_STATUS Status;
299
300 if (TisReg == NULL) {
301 return EFI_INVALID_PARAMETER;
302 }
303
304 MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
305 Status = Tpm12TisPcWaitRegisterBits (
306 &TisReg->Status,
307 TIS_PC_STS_READY,
308 0,
309 TIS_TIMEOUT_B
310 );
311 return Status;
312 }
313
314 /**
315 Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE
316 to ACCESS Register in the time of default TIS_TIMEOUT_A.
317
318 @param[in] TisReg Pointer to TIS register.
319
320 @retval EFI_SUCCESS Get the control of TPM chip.
321 @retval EFI_INVALID_PARAMETER TisReg is NULL.
322 @retval EFI_NOT_FOUND TPM chip doesn't exit.
323 @retval EFI_TIMEOUT Can't get the TPM control in time.
324 **/
325 EFI_STATUS
326 Tpm12TisPcRequestUseTpm (
327 IN TIS_PC_REGISTERS_PTR TisReg
328 )
329 {
330 EFI_STATUS Status;
331
332 if (TisReg == NULL) {
333 return EFI_INVALID_PARAMETER;
334 }
335
336 if (!Tpm12TisPcPresenceCheck (TisReg)) {
337 return EFI_NOT_FOUND;
338 }
339
340 MmioWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);
341 Status = Tpm12TisPcWaitRegisterBits (
342 &TisReg->Access,
343 (UINT8)(TIS_PC_ACC_ACTIVE |TIS_PC_VALID),
344 0,
345 TIS_TIMEOUT_A
346 );
347 return Status;
348 }
349
350 /**
351 Send a command to TPM for execution and return response data.
352
353 @param[in] TisReg TPM register space base address.
354 @param[in] BufferIn Buffer for command data.
355 @param[in] SizeIn Size of command data.
356 @param[in, out] BufferOut Buffer for response data.
357 @param[in, out] SizeOut Size of response data.
358
359 @retval EFI_SUCCESS Operation completed successfully.
360 @retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.
361 @retval EFI_DEVICE_ERROR Unexpected device behavior.
362 @retval EFI_UNSUPPORTED Unsupported TPM version
363
364 **/
365 EFI_STATUS
366 Tpm12TisTpmCommand (
367 IN TIS_PC_REGISTERS_PTR TisReg,
368 IN UINT8 *BufferIn,
369 IN UINT32 SizeIn,
370 IN OUT UINT8 *BufferOut,
371 IN OUT UINT32 *SizeOut
372 )
373 {
374 EFI_STATUS Status;
375 UINT16 BurstCount;
376 UINT32 Index;
377 UINT32 TpmOutSize;
378 UINT16 Data16;
379 UINT32 Data32;
380
381 DEBUG_CODE (
382 UINTN DebugSize;
383
384 DEBUG ((EFI_D_INFO, "Tpm12TisTpmCommand Send - "));
385 if (SizeIn > 0x100) {
386 DebugSize = 0x40;
387 } else {
388 DebugSize = SizeIn;
389 }
390 for (Index = 0; Index < DebugSize; Index++) {
391 DEBUG ((EFI_D_INFO, "%02x ", BufferIn[Index]));
392 }
393 if (DebugSize != SizeIn) {
394 DEBUG ((EFI_D_INFO, "...... "));
395 for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {
396 DEBUG ((EFI_D_INFO, "%02x ", BufferIn[Index]));
397 }
398 }
399 DEBUG ((EFI_D_INFO, "\n"));
400 );
401 TpmOutSize = 0;
402
403 Status = Tpm12TisPcPrepareCommand (TisReg);
404 if (EFI_ERROR (Status)){
405 DEBUG ((DEBUG_ERROR, "Tpm12 is not ready for command!\n"));
406 return EFI_DEVICE_ERROR;
407 }
408 //
409 // Send the command data to Tpm
410 //
411 Index = 0;
412 while (Index < SizeIn) {
413 Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);
414 if (EFI_ERROR (Status)) {
415 Status = EFI_DEVICE_ERROR;
416 goto Exit;
417 }
418 for (; BurstCount > 0 && Index < SizeIn; BurstCount--) {
419 MmioWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));
420 Index++;
421 }
422 }
423 //
424 // Check the Tpm status STS_EXPECT change from 1 to 0
425 //
426 Status = Tpm12TisPcWaitRegisterBits (
427 &TisReg->Status,
428 (UINT8) TIS_PC_VALID,
429 TIS_PC_STS_EXPECT,
430 TIS_TIMEOUT_C
431 );
432 if (EFI_ERROR (Status)) {
433 DEBUG ((DEBUG_ERROR, "Tpm12 The send buffer too small!\n"));
434 Status = EFI_BUFFER_TOO_SMALL;
435 goto Exit;
436 }
437 //
438 // Executed the TPM command and waiting for the response data ready
439 //
440 MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);
441 Status = Tpm12TisPcWaitRegisterBits (
442 &TisReg->Status,
443 (UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA),
444 0,
445 TIS_TIMEOUT_B
446 );
447 if (EFI_ERROR (Status)) {
448 DEBUG ((DEBUG_ERROR, "Wait for Tpm12 response data time out!!\n"));
449 Status = EFI_DEVICE_ERROR;
450 goto Exit;
451 }
452 //
453 // Get response data header
454 //
455 Index = 0;
456 BurstCount = 0;
457 while (Index < sizeof (TPM_RSP_COMMAND_HDR)) {
458 Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);
459 if (EFI_ERROR (Status)) {
460 Status = EFI_DEVICE_ERROR;
461 goto Exit;
462 }
463 for (; BurstCount > 0; BurstCount--) {
464 *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
465 Index++;
466 if (Index == sizeof (TPM_RSP_COMMAND_HDR)) break;
467 }
468 }
469 DEBUG_CODE (
470 DEBUG ((EFI_D_INFO, "Tpm12TisTpmCommand ReceiveHeader - "));
471 for (Index = 0; Index < sizeof (TPM_RSP_COMMAND_HDR); Index++) {
472 DEBUG ((EFI_D_INFO, "%02x ", BufferOut[Index]));
473 }
474 DEBUG ((EFI_D_INFO, "\n"));
475 );
476 //
477 // Check the reponse data header (tag,parasize and returncode )
478 //
479 CopyMem (&Data16, BufferOut, sizeof (UINT16));
480 if (SwapBytes16 (Data16) != TPM_TAG_RSP_COMMAND) {
481 DEBUG ((EFI_D_ERROR, "TPM12: TPM_ST_RSP error - %x\n", TPM_TAG_RSP_COMMAND));
482 Status = EFI_UNSUPPORTED;
483 goto Exit;
484 }
485
486 CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));
487 TpmOutSize = SwapBytes32 (Data32);
488 if (*SizeOut < TpmOutSize) {
489 Status = EFI_BUFFER_TOO_SMALL;
490 goto Exit;
491 }
492 *SizeOut = TpmOutSize;
493 //
494 // Continue reading the remaining data
495 //
496 while ( Index < TpmOutSize ) {
497 for (; BurstCount > 0; BurstCount--) {
498 *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
499 Index++;
500 if (Index == TpmOutSize) {
501 Status = EFI_SUCCESS;
502 goto Exit;
503 }
504 }
505 Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);
506 if (EFI_ERROR (Status)) {
507 Status = EFI_DEVICE_ERROR;
508 goto Exit;
509 }
510 }
511 Exit:
512 DEBUG_CODE (
513 DEBUG ((EFI_D_INFO, "Tpm12TisTpmCommand Receive - "));
514 for (Index = 0; Index < TpmOutSize; Index++) {
515 DEBUG ((EFI_D_INFO, "%02x ", BufferOut[Index]));
516 }
517 DEBUG ((EFI_D_INFO, "\n"));
518 );
519 MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
520 return Status;
521 }
522
523 /**
524 This service enables the sending of commands to the TPM12.
525
526 @param[in] InputParameterBlockSize Size of the TPM12 input parameter block.
527 @param[in] InputParameterBlock Pointer to the TPM12 input parameter block.
528 @param[in,out] OutputParameterBlockSize Size of the TPM12 output parameter block.
529 @param[in] OutputParameterBlock Pointer to the TPM12 output parameter block.
530
531 @retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.
532 @retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.
533 @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small.
534 **/
535 EFI_STATUS
536 EFIAPI
537 Tpm12SubmitCommand (
538 IN UINT32 InputParameterBlockSize,
539 IN UINT8 *InputParameterBlock,
540 IN OUT UINT32 *OutputParameterBlockSize,
541 IN UINT8 *OutputParameterBlock
542 )
543 {
544 return Tpm12TisTpmCommand (
545 (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),
546 InputParameterBlock,
547 InputParameterBlockSize,
548 OutputParameterBlock,
549 OutputParameterBlockSize
550 );
551 }
552
553 /**
554 This service requests use TPM12.
555
556 @retval EFI_SUCCESS Get the control of TPM12 chip.
557 @retval EFI_NOT_FOUND TPM12 not found.
558 @retval EFI_DEVICE_ERROR Unexpected device behavior.
559 **/
560 EFI_STATUS
561 EFIAPI
562 Tpm12RequestUseTpm (
563 VOID
564 )
565 {
566 return Tpm12TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
567 }