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SecurityPkg: Add TPM PTP detection in TPM12 device lib.
[mirror_edk2.git] / SecurityPkg / Library / Tpm12DeviceLibDTpm / Tpm12Tis.c
1 /** @file
2 TIS (TPM Interface Specification) functions used by TPM1.2.
3
4 Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #include <Uefi.h>
17 #include <IndustryStandard/Tpm12.h>
18 #include <Library/BaseLib.h>
19 #include <Library/BaseMemoryLib.h>
20 #include <Library/IoLib.h>
21 #include <Library/TimerLib.h>
22 #include <Library/DebugLib.h>
23 #include <Library/Tpm12CommandLib.h>
24 #include <Library/PcdLib.h>
25
26 #include <IndustryStandard/TpmPtp.h>
27 #include <IndustryStandard/TpmTis.h>
28
29 typedef enum {
30 PtpInterfaceTis,
31 PtpInterfaceFifo,
32 PtpInterfaceCrb,
33 PtpInterfaceMax,
34 } PTP_INTERFACE_TYPE;
35
36 //
37 // Max TPM command/reponse length
38 //
39 #define TPMCMDBUFLENGTH 1024
40
41 /**
42 Check whether TPM chip exist.
43
44 @param[in] TisReg Pointer to TIS register.
45
46 @retval TRUE TPM chip exists.
47 @retval FALSE TPM chip is not found.
48 **/
49 BOOLEAN
50 Tpm12TisPcPresenceCheck (
51 IN TIS_PC_REGISTERS_PTR TisReg
52 )
53 {
54 UINT8 RegRead;
55
56 RegRead = MmioRead8 ((UINTN)&TisReg->Access);
57 return (BOOLEAN)(RegRead != (UINT8)-1);
58 }
59
60 /**
61 Check whether the value of a TPM chip register satisfies the input BIT setting.
62
63 @param[in] Register Address port of register to be checked.
64 @param[in] BitSet Check these data bits are set.
65 @param[in] BitClear Check these data bits are clear.
66 @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.
67
68 @retval EFI_SUCCESS The register satisfies the check bit.
69 @retval EFI_TIMEOUT The register can't run into the expected status in time.
70 **/
71 EFI_STATUS
72 Tpm12TisPcWaitRegisterBits (
73 IN UINT8 *Register,
74 IN UINT8 BitSet,
75 IN UINT8 BitClear,
76 IN UINT32 TimeOut
77 )
78 {
79 UINT8 RegRead;
80 UINT32 WaitTime;
81
82 for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
83 RegRead = MmioRead8 ((UINTN)Register);
84 if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)
85 return EFI_SUCCESS;
86 MicroSecondDelay (30);
87 }
88 return EFI_TIMEOUT;
89 }
90
91 /**
92 Get BurstCount by reading the burstCount field of a TIS regiger
93 in the time of default TIS_TIMEOUT_D.
94
95 @param[in] TisReg Pointer to TIS register.
96 @param[out] BurstCount Pointer to a buffer to store the got BurstConut.
97
98 @retval EFI_SUCCESS Get BurstCount.
99 @retval EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.
100 @retval EFI_TIMEOUT BurstCount can't be got in time.
101 **/
102 EFI_STATUS
103 Tpm12TisPcReadBurstCount (
104 IN TIS_PC_REGISTERS_PTR TisReg,
105 OUT UINT16 *BurstCount
106 )
107 {
108 UINT32 WaitTime;
109 UINT8 DataByte0;
110 UINT8 DataByte1;
111
112 if (BurstCount == NULL || TisReg == NULL) {
113 return EFI_INVALID_PARAMETER;
114 }
115
116 WaitTime = 0;
117 do {
118 //
119 // TIS_PC_REGISTERS_PTR->burstCount is UINT16, but it is not 2bytes aligned,
120 // so it needs to use MmioRead8 to read two times
121 //
122 DataByte0 = MmioRead8 ((UINTN)&TisReg->BurstCount);
123 DataByte1 = MmioRead8 ((UINTN)&TisReg->BurstCount + 1);
124 *BurstCount = (UINT16)((DataByte1 << 8) + DataByte0);
125 if (*BurstCount != 0) {
126 return EFI_SUCCESS;
127 }
128 MicroSecondDelay (30);
129 WaitTime += 30;
130 } while (WaitTime < TIS_TIMEOUT_D);
131
132 return EFI_TIMEOUT;
133 }
134
135 /**
136 Set TPM chip to ready state by sending ready command TIS_PC_STS_READY
137 to Status Register in time.
138
139 @param[in] TisReg Pointer to TIS register.
140
141 @retval EFI_SUCCESS TPM chip enters into ready state.
142 @retval EFI_INVALID_PARAMETER TisReg is NULL.
143 @retval EFI_TIMEOUT TPM chip can't be set to ready state in time.
144 **/
145 EFI_STATUS
146 Tpm12TisPcPrepareCommand (
147 IN TIS_PC_REGISTERS_PTR TisReg
148 )
149 {
150 EFI_STATUS Status;
151
152 if (TisReg == NULL) {
153 return EFI_INVALID_PARAMETER;
154 }
155
156 MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
157 Status = Tpm12TisPcWaitRegisterBits (
158 &TisReg->Status,
159 TIS_PC_STS_READY,
160 0,
161 TIS_TIMEOUT_B
162 );
163 return Status;
164 }
165
166 /**
167 Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE
168 to ACCESS Register in the time of default TIS_TIMEOUT_A.
169
170 @param[in] TisReg Pointer to TIS register.
171
172 @retval EFI_SUCCESS Get the control of TPM chip.
173 @retval EFI_INVALID_PARAMETER TisReg is NULL.
174 @retval EFI_NOT_FOUND TPM chip doesn't exit.
175 @retval EFI_TIMEOUT Can't get the TPM control in time.
176 **/
177 EFI_STATUS
178 Tpm12TisPcRequestUseTpm (
179 IN TIS_PC_REGISTERS_PTR TisReg
180 )
181 {
182 EFI_STATUS Status;
183
184 if (TisReg == NULL) {
185 return EFI_INVALID_PARAMETER;
186 }
187
188 if (!Tpm12TisPcPresenceCheck (TisReg)) {
189 return EFI_NOT_FOUND;
190 }
191
192 MmioWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);
193 Status = Tpm12TisPcWaitRegisterBits (
194 &TisReg->Access,
195 (UINT8)(TIS_PC_ACC_ACTIVE |TIS_PC_VALID),
196 0,
197 TIS_TIMEOUT_A
198 );
199 return Status;
200 }
201
202 /**
203 Send a command to TPM for execution and return response data.
204
205 @param[in] TisReg TPM register space base address.
206 @param[in] BufferIn Buffer for command data.
207 @param[in] SizeIn Size of command data.
208 @param[in, out] BufferOut Buffer for response data.
209 @param[in, out] SizeOut Size of response data.
210
211 @retval EFI_SUCCESS Operation completed successfully.
212 @retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.
213 @retval EFI_DEVICE_ERROR Unexpected device behavior.
214 @retval EFI_UNSUPPORTED Unsupported TPM version
215
216 **/
217 EFI_STATUS
218 Tpm12TisTpmCommand (
219 IN TIS_PC_REGISTERS_PTR TisReg,
220 IN UINT8 *BufferIn,
221 IN UINT32 SizeIn,
222 IN OUT UINT8 *BufferOut,
223 IN OUT UINT32 *SizeOut
224 )
225 {
226 EFI_STATUS Status;
227 UINT16 BurstCount;
228 UINT32 Index;
229 UINT32 TpmOutSize;
230 UINT16 Data16;
231 UINT32 Data32;
232
233 DEBUG_CODE (
234 UINTN DebugSize;
235
236 DEBUG ((EFI_D_VERBOSE, "Tpm12TisTpmCommand Send - "));
237 if (SizeIn > 0x100) {
238 DebugSize = 0x40;
239 } else {
240 DebugSize = SizeIn;
241 }
242 for (Index = 0; Index < DebugSize; Index++) {
243 DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));
244 }
245 if (DebugSize != SizeIn) {
246 DEBUG ((EFI_D_VERBOSE, "...... "));
247 for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {
248 DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));
249 }
250 }
251 DEBUG ((EFI_D_VERBOSE, "\n"));
252 );
253 TpmOutSize = 0;
254
255 Status = Tpm12TisPcPrepareCommand (TisReg);
256 if (EFI_ERROR (Status)){
257 DEBUG ((DEBUG_ERROR, "Tpm12 is not ready for command!\n"));
258 return EFI_DEVICE_ERROR;
259 }
260 //
261 // Send the command data to Tpm
262 //
263 Index = 0;
264 while (Index < SizeIn) {
265 Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);
266 if (EFI_ERROR (Status)) {
267 Status = EFI_DEVICE_ERROR;
268 goto Exit;
269 }
270 for (; BurstCount > 0 && Index < SizeIn; BurstCount--) {
271 MmioWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));
272 Index++;
273 }
274 }
275 //
276 // Check the Tpm status STS_EXPECT change from 1 to 0
277 //
278 Status = Tpm12TisPcWaitRegisterBits (
279 &TisReg->Status,
280 (UINT8) TIS_PC_VALID,
281 TIS_PC_STS_EXPECT,
282 TIS_TIMEOUT_C
283 );
284 if (EFI_ERROR (Status)) {
285 DEBUG ((DEBUG_ERROR, "Tpm12 The send buffer too small!\n"));
286 Status = EFI_BUFFER_TOO_SMALL;
287 goto Exit;
288 }
289 //
290 // Executed the TPM command and waiting for the response data ready
291 //
292 MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);
293 Status = Tpm12TisPcWaitRegisterBits (
294 &TisReg->Status,
295 (UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA),
296 0,
297 TIS_TIMEOUT_B
298 );
299 if (EFI_ERROR (Status)) {
300 DEBUG ((DEBUG_ERROR, "Wait for Tpm12 response data time out!!\n"));
301 Status = EFI_DEVICE_ERROR;
302 goto Exit;
303 }
304 //
305 // Get response data header
306 //
307 Index = 0;
308 BurstCount = 0;
309 while (Index < sizeof (TPM_RSP_COMMAND_HDR)) {
310 Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);
311 if (EFI_ERROR (Status)) {
312 Status = EFI_DEVICE_ERROR;
313 goto Exit;
314 }
315 for (; BurstCount > 0; BurstCount--) {
316 *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
317 Index++;
318 if (Index == sizeof (TPM_RSP_COMMAND_HDR)) break;
319 }
320 }
321 DEBUG_CODE (
322 DEBUG ((EFI_D_VERBOSE, "Tpm12TisTpmCommand ReceiveHeader - "));
323 for (Index = 0; Index < sizeof (TPM_RSP_COMMAND_HDR); Index++) {
324 DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));
325 }
326 DEBUG ((EFI_D_VERBOSE, "\n"));
327 );
328 //
329 // Check the reponse data header (tag,parasize and returncode )
330 //
331 CopyMem (&Data16, BufferOut, sizeof (UINT16));
332 if (SwapBytes16 (Data16) != TPM_TAG_RSP_COMMAND) {
333 DEBUG ((EFI_D_ERROR, "TPM12: TPM_ST_RSP error - %x\n", TPM_TAG_RSP_COMMAND));
334 Status = EFI_UNSUPPORTED;
335 goto Exit;
336 }
337
338 CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));
339 TpmOutSize = SwapBytes32 (Data32);
340 if (*SizeOut < TpmOutSize) {
341 Status = EFI_BUFFER_TOO_SMALL;
342 goto Exit;
343 }
344 *SizeOut = TpmOutSize;
345 //
346 // Continue reading the remaining data
347 //
348 while ( Index < TpmOutSize ) {
349 for (; BurstCount > 0; BurstCount--) {
350 *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
351 Index++;
352 if (Index == TpmOutSize) {
353 Status = EFI_SUCCESS;
354 goto Exit;
355 }
356 }
357 Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);
358 if (EFI_ERROR (Status)) {
359 Status = EFI_DEVICE_ERROR;
360 goto Exit;
361 }
362 }
363 Exit:
364 DEBUG_CODE (
365 DEBUG ((EFI_D_VERBOSE, "Tpm12TisTpmCommand Receive - "));
366 for (Index = 0; Index < TpmOutSize; Index++) {
367 DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));
368 }
369 DEBUG ((EFI_D_VERBOSE, "\n"));
370 );
371 MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
372 return Status;
373 }
374
375 /**
376 This service enables the sending of commands to the TPM12.
377
378 @param[in] InputParameterBlockSize Size of the TPM12 input parameter block.
379 @param[in] InputParameterBlock Pointer to the TPM12 input parameter block.
380 @param[in,out] OutputParameterBlockSize Size of the TPM12 output parameter block.
381 @param[in] OutputParameterBlock Pointer to the TPM12 output parameter block.
382
383 @retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.
384 @retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.
385 @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small.
386 **/
387 EFI_STATUS
388 EFIAPI
389 Tpm12SubmitCommand (
390 IN UINT32 InputParameterBlockSize,
391 IN UINT8 *InputParameterBlock,
392 IN OUT UINT32 *OutputParameterBlockSize,
393 IN UINT8 *OutputParameterBlock
394 )
395 {
396 return Tpm12TisTpmCommand (
397 (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),
398 InputParameterBlock,
399 InputParameterBlockSize,
400 OutputParameterBlock,
401 OutputParameterBlockSize
402 );
403 }
404
405 /**
406 Return PTP interface type.
407
408 @param[in] Register Pointer to PTP register.
409
410 @return PTP interface type.
411 **/
412 PTP_INTERFACE_TYPE
413 Tpm12GetPtpInterface (
414 IN VOID *Register
415 )
416 {
417 PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;
418 PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;
419
420 if (!Tpm12TisPcPresenceCheck (Register)) {
421 return PtpInterfaceMax;
422 }
423 //
424 // Check interface id
425 //
426 InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
427 InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
428
429 if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&
430 (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&
431 (InterfaceId.Bits.CapCRB != 0)) {
432 return PtpInterfaceCrb;
433 }
434 if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO) &&
435 (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO) &&
436 (InterfaceId.Bits.CapFIFO != 0) &&
437 (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP)) {
438 return PtpInterfaceFifo;
439 }
440 return PtpInterfaceTis;
441 }
442
443 /**
444 Check whether the value of a TPM chip register satisfies the input BIT setting.
445
446 @param[in] Register Address port of register to be checked.
447 @param[in] BitSet Check these data bits are set.
448 @param[in] BitClear Check these data bits are clear.
449 @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.
450
451 @retval EFI_SUCCESS The register satisfies the check bit.
452 @retval EFI_TIMEOUT The register can't run into the expected status in time.
453 **/
454 EFI_STATUS
455 Tpm12PtpCrbWaitRegisterBits (
456 IN UINT32 *Register,
457 IN UINT32 BitSet,
458 IN UINT32 BitClear,
459 IN UINT32 TimeOut
460 )
461 {
462 UINT32 RegRead;
463 UINT32 WaitTime;
464
465 for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
466 RegRead = MmioRead32 ((UINTN)Register);
467 if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {
468 return EFI_SUCCESS;
469 }
470 MicroSecondDelay (30);
471 }
472 return EFI_TIMEOUT;
473 }
474
475 /**
476 Get the control of TPM chip.
477
478 @param[in] CrbReg Pointer to CRB register.
479
480 @retval EFI_SUCCESS Get the control of TPM chip.
481 @retval EFI_INVALID_PARAMETER CrbReg is NULL.
482 @retval EFI_NOT_FOUND TPM chip doesn't exit.
483 @retval EFI_TIMEOUT Can't get the TPM control in time.
484 **/
485 EFI_STATUS
486 Tpm12PtpCrbRequestUseTpm (
487 IN PTP_CRB_REGISTERS_PTR CrbReg
488 )
489 {
490 EFI_STATUS Status;
491
492 MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);
493 Status = Tpm12PtpCrbWaitRegisterBits (
494 &CrbReg->LocalityStatus,
495 PTP_CRB_LOCALITY_STATUS_GRANTED,
496 0,
497 PTP_TIMEOUT_A
498 );
499 return Status;
500 }
501
502 /**
503 This service requests use TPM12.
504
505 @retval EFI_SUCCESS Get the control of TPM12 chip.
506 @retval EFI_NOT_FOUND TPM12 not found.
507 @retval EFI_DEVICE_ERROR Unexpected device behavior.
508 **/
509 EFI_STATUS
510 EFIAPI
511 Tpm12RequestUseTpm (
512 VOID
513 )
514 {
515 PTP_INTERFACE_TYPE PtpInterface;
516
517 //
518 // Special handle for TPM1.2 to check PTP too, because PTP/TIS share same register address.
519 // Some other program might leverage this function to check the existence of TPM chip.
520 //
521 PtpInterface = Tpm12GetPtpInterface ((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));
522 switch (PtpInterface) {
523 case PtpInterfaceCrb:
524 return Tpm12PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
525 case PtpInterfaceFifo:
526 case PtpInterfaceTis:
527 return Tpm12TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
528 default:
529 return EFI_NOT_FOUND;
530 }
531 }
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