SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c

   1 /** @file
   2   PTP (Platform TPM Profile) CRB (Command Response Buffer) interface used by dTPM2.0 library.
   3
   4 Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
   5 SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #include <IndustryStandard/Tpm20.h>
  10
  11 #include <Library/BaseLib.h>
  12 #include <Library/BaseMemoryLib.h>
  13 #include <Library/IoLib.h>
  14 #include <Library/TimerLib.h>
  15 #include <Library/DebugLib.h>
  16 #include <Library/Tpm2DeviceLib.h>
  17 #include <Library/PcdLib.h>
  18
  19 #include <IndustryStandard/TpmPtp.h>
  20 #include <IndustryStandard/TpmTis.h>
  21
  22 //
  23 // Execution of the command may take from several seconds to minutes for certain
  24 // commands, such as key generation.
  25 //
  26 #define PTP_TIMEOUT_MAX             (90000 * 1000)  // 90s
  27
  28 //
  29 // Max TPM command/reponse length
  30 //
  31 #define TPMCMDBUFLENGTH             0x500
  32
  33 /**
  34   Check whether TPM PTP register exist.
  35
  36   @param[in] Reg  Pointer to PTP register.
  37
  38   @retval    TRUE    TPM PTP exists.
  39   @retval    FALSE   TPM PTP is not found.
  40 **/
  41 BOOLEAN
  42 Tpm2IsPtpPresence (
  43   IN VOID *Reg
  44   )
  45 {
  46   UINT8                             RegRead;
  47
  48   RegRead = MmioRead8 ((UINTN)Reg);
  49   if (RegRead == 0xFF) {
  50     //
  51     // No TPM chip
  52     //
  53     return FALSE;
  54   }
  55   return TRUE;
  56 }
  57
  58 /**
  59   Check whether the value of a TPM chip register satisfies the input BIT setting.
  60
  61   @param[in]  Register     Address port of register to be checked.
  62   @param[in]  BitSet       Check these data bits are set.
  63   @param[in]  BitClear     Check these data bits are clear.
  64   @param[in]  TimeOut      The max wait time (unit MicroSecond) when checking register.
  65
  66   @retval     EFI_SUCCESS  The register satisfies the check bit.
  67   @retval     EFI_TIMEOUT  The register can't run into the expected status in time.
  68 **/
  69 EFI_STATUS
  70 PtpCrbWaitRegisterBits (
  71   IN      UINT32                    *Register,
  72   IN      UINT32                    BitSet,
  73   IN      UINT32                    BitClear,
  74   IN      UINT32                    TimeOut
  75   )
  76 {
  77   UINT32                            RegRead;
  78   UINT32                            WaitTime;
  79
  80   for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
  81     RegRead = MmioRead32 ((UINTN)Register);
  82     if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {
  83       return EFI_SUCCESS;
  84     }
  85     MicroSecondDelay (30);
  86   }
  87   return EFI_TIMEOUT;
  88 }
  89
  90 /**
  91   Get the control of TPM chip.
  92
  93   @param[in] CrbReg                Pointer to CRB register.
  94
  95   @retval    EFI_SUCCESS           Get the control of TPM chip.
  96   @retval    EFI_INVALID_PARAMETER CrbReg is NULL.
  97   @retval    EFI_NOT_FOUND         TPM chip doesn't exit.
  98   @retval    EFI_TIMEOUT           Can't get the TPM control in time.
  99 **/
 100 EFI_STATUS
 101 PtpCrbRequestUseTpm (
 102   IN      PTP_CRB_REGISTERS_PTR      CrbReg
 103   )
 104 {
 105   EFI_STATUS                        Status;
 106
 107   if (!Tpm2IsPtpPresence (CrbReg)) {
 108     return EFI_NOT_FOUND;
 109   }
 110
 111   MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);
 112   Status = PtpCrbWaitRegisterBits (
 113              &CrbReg->LocalityStatus,
 114              PTP_CRB_LOCALITY_STATUS_GRANTED,
 115              0,
 116              PTP_TIMEOUT_A
 117              );
 118   return Status;
 119 }
 120
 121 /**
 122   Send a command to TPM for execution and return response data.
 123
 124   @param[in]      CrbReg        TPM register space base address.
 125   @param[in]      BufferIn      Buffer for command data.
 126   @param[in]      SizeIn        Size of command data.
 127   @param[in, out] BufferOut     Buffer for response data.
 128   @param[in, out] SizeOut       Size of response data.
 129
 130   @retval EFI_SUCCESS           Operation completed successfully.
 131   @retval EFI_BUFFER_TOO_SMALL  Response data buffer is too small.
 132   @retval EFI_DEVICE_ERROR      Unexpected device behavior.
 133   @retval EFI_UNSUPPORTED       Unsupported TPM version
 134
 135 **/
 136 EFI_STATUS
 137 PtpCrbTpmCommand (
 138   IN     PTP_CRB_REGISTERS_PTR      CrbReg,
 139   IN     UINT8                      *BufferIn,
 140   IN     UINT32                     SizeIn,
 141   IN OUT UINT8                      *BufferOut,
 142   IN OUT UINT32                     *SizeOut
 143   )
 144 {
 145   EFI_STATUS                        Status;
 146   UINT32                            Index;
 147   UINT32                            TpmOutSize;
 148   UINT16                            Data16;
 149   UINT32                            Data32;
 150
 151   DEBUG_CODE (
 152     UINTN  DebugSize;
 153
 154     DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand Send - "));
 155     if (SizeIn > 0x100) {
 156       DebugSize = 0x40;
 157     } else {
 158       DebugSize = SizeIn;
 159     }
 160     for (Index = 0; Index < DebugSize; Index++) {
 161       DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));
 162     }
 163     if (DebugSize != SizeIn) {
 164       DEBUG ((EFI_D_VERBOSE, "...... "));
 165       for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {
 166         DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));
 167       }
 168     }
 169     DEBUG ((EFI_D_VERBOSE, "\n"));
 170   );
 171   TpmOutSize         = 0;
 172
 173   //
 174   // STEP 0:
 175   // if CapCRbIdelByPass == 0, enforce Idle state before sending command
 176   //
 177   if (PcdGet8(PcdCRBIdleByPass) == 0 && (MmioRead32((UINTN)&CrbReg->CrbControlStatus) & PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE) == 0){
 178     Status = PtpCrbWaitRegisterBits (
 179               &CrbReg->CrbControlStatus,
 180               PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,
 181               0,
 182               PTP_TIMEOUT_C
 183               );
 184     if (EFI_ERROR (Status)) {
 185       //
 186       // Try to goIdle to recover TPM
 187       //
 188       Status = EFI_DEVICE_ERROR;
 189       goto GoIdle_Exit;
 190     }
 191   }
 192
 193   //
 194   // STEP 1:
 195   // Ready is any time the TPM is ready to receive a command, following a write
 196   // of 1 by software to Request.cmdReady, as indicated by the Status field
 197   // being cleared to 0.
 198   //
 199   MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);
 200   Status = PtpCrbWaitRegisterBits (
 201              &CrbReg->CrbControlRequest,
 202              0,
 203              PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY,
 204              PTP_TIMEOUT_C
 205              );
 206   if (EFI_ERROR (Status)) {
 207     Status = EFI_DEVICE_ERROR;
 208     goto GoIdle_Exit;
 209   }
 210   Status = PtpCrbWaitRegisterBits (
 211              &CrbReg->CrbControlStatus,
 212              0,
 213              PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,
 214              PTP_TIMEOUT_C
 215              );
 216   if (EFI_ERROR (Status)) {
 217     Status = EFI_DEVICE_ERROR;
 218     goto GoIdle_Exit;
 219   }
 220
 221   //
 222   // STEP 2:
 223   // Command Reception occurs following a Ready state between the write of the
 224   // first byte of a command to the Command Buffer and the receipt of a write
 225   // of 1 to Start.
 226   //
 227   for (Index = 0; Index < SizeIn; Index++) {
 228     MmioWrite8 ((UINTN)&CrbReg->CrbDataBuffer[Index], BufferIn[Index]);
 229   }
 230   MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressHigh, (UINT32)RShiftU64 ((UINTN)CrbReg->CrbDataBuffer, 32));
 231   MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressLow, (UINT32)(UINTN)CrbReg->CrbDataBuffer);
 232   MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandSize, sizeof(CrbReg->CrbDataBuffer));
 233
 234   MmioWrite64 ((UINTN)&CrbReg->CrbControlResponseAddrss, (UINT32)(UINTN)CrbReg->CrbDataBuffer);
 235   MmioWrite32 ((UINTN)&CrbReg->CrbControlResponseSize, sizeof(CrbReg->CrbDataBuffer));
 236
 237   //
 238   // STEP 3:
 239   // Command Execution occurs after receipt of a 1 to Start and the TPM
 240   // clearing Start to 0.
 241   //
 242   MmioWrite32((UINTN)&CrbReg->CrbControlStart, PTP_CRB_CONTROL_START);
 243   Status = PtpCrbWaitRegisterBits (
 244              &CrbReg->CrbControlStart,
 245              0,
 246              PTP_CRB_CONTROL_START,
 247              PTP_TIMEOUT_MAX
 248              );
 249   if (EFI_ERROR (Status)) {
 250     //
 251     // Command Completion check timeout. Cancel the currently executing command by writing TPM_CRB_CTRL_CANCEL,
 252     // Expect TPM_RC_CANCELLED or successfully completed response.
 253     //
 254     MmioWrite32((UINTN)&CrbReg->CrbControlCancel, PTP_CRB_CONTROL_CANCEL);
 255     Status = PtpCrbWaitRegisterBits (
 256                &CrbReg->CrbControlStart,
 257                0,
 258                PTP_CRB_CONTROL_START,
 259                PTP_TIMEOUT_B
 260                );
 261     MmioWrite32((UINTN)&CrbReg->CrbControlCancel, 0);
 262
 263     if (EFI_ERROR(Status)) {
 264       //
 265       // Still in Command Execution state. Try to goIdle, the behavior is agnostic.
 266       //
 267       Status = EFI_DEVICE_ERROR;
 268       goto GoIdle_Exit;
 269     }
 270   }
 271
 272   //
 273   // STEP 4:
 274   // Command Completion occurs after completion of a command (indicated by the
 275   // TPM clearing TPM_CRB_CTRL_Start_x to 0) and before a write of a 1 by the
 276   // software to Request.goIdle.
 277   //
 278
 279   //
 280   // Get response data header
 281   //
 282   for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {
 283     BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);
 284   }
 285   DEBUG_CODE (
 286     DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand ReceiveHeader - "));
 287     for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {
 288       DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));
 289     }
 290     DEBUG ((EFI_D_VERBOSE, "\n"));
 291   );
 292   //
 293   // Check the reponse data header (tag, parasize and returncode)
 294   //
 295   CopyMem (&Data16, BufferOut, sizeof (UINT16));
 296   // TPM2 should not use this RSP_COMMAND
 297   if (SwapBytes16 (Data16) == TPM_ST_RSP_COMMAND) {
 298     DEBUG ((EFI_D_ERROR, "TPM2: TPM_ST_RSP error - %x\n", TPM_ST_RSP_COMMAND));
 299     Status = EFI_UNSUPPORTED;
 300     goto GoIdle_Exit;
 301   }
 302
 303   CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));
 304   TpmOutSize  = SwapBytes32 (Data32);
 305   if (*SizeOut < TpmOutSize) {
 306     //
 307     // Command completed, but buffer is not enough
 308     //
 309     Status = EFI_BUFFER_TOO_SMALL;
 310     goto GoReady_Exit;
 311   }
 312   *SizeOut = TpmOutSize;
 313   //
 314   // Continue reading the remaining data
 315   //
 316   for (Index = sizeof (TPM2_RESPONSE_HEADER); Index < TpmOutSize; Index++) {
 317     BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);
 318   }
 319
 320   DEBUG_CODE (
 321     DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand Receive - "));
 322     for (Index = 0; Index < TpmOutSize; Index++) {
 323       DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));
 324     }
 325     DEBUG ((EFI_D_VERBOSE, "\n"));
 326   );
 327
 328 GoReady_Exit:
 329   //
 330   // Goto Ready State if command is completed succesfully and TPM support IdleBypass
 331   // If not supported. flow down to GoIdle
 332   //
 333   if (PcdGet8(PcdCRBIdleByPass) == 1) {
 334     MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);
 335     return Status;
 336   }
 337
 338   //
 339   // Do not wait for state transition for TIMEOUT_C
 340   // This function will try to wait 2 TIMEOUT_C at the beginning in next call.
 341   //
 342 GoIdle_Exit:
 343
 344   //
 345   //  Return to Idle state by setting TPM_CRB_CTRL_STS_x.Status.goIdle to 1.
 346   //
 347   MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);
 348
 349   //
 350   // Only enforce Idle state transition if execution fails when CRBIndleBypass==1
 351   // Leave regular Idle delay at the beginning of next command execution
 352   //
 353   if (PcdGet8(PcdCRBIdleByPass) == 1){
 354     Status = PtpCrbWaitRegisterBits (
 355                &CrbReg->CrbControlStatus,
 356                PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,
 357                0,
 358                PTP_TIMEOUT_C
 359                );
 360   }
 361
 362   return Status;
 363 }
 364
 365 /**
 366   Send a command to TPM for execution and return response data.
 367
 368   @param[in]      TisReg        TPM register space base address.
 369   @param[in]      BufferIn      Buffer for command data.
 370   @param[in]      SizeIn        Size of command data.
 371   @param[in, out] BufferOut     Buffer for response data.
 372   @param[in, out] SizeOut       Size of response data.
 373
 374   @retval EFI_SUCCESS           Operation completed successfully.
 375   @retval EFI_BUFFER_TOO_SMALL  Response data buffer is too small.
 376   @retval EFI_DEVICE_ERROR      Unexpected device behavior.
 377   @retval EFI_UNSUPPORTED       Unsupported TPM version
 378
 379 **/
 380 EFI_STATUS
 381 Tpm2TisTpmCommand (
 382   IN     TIS_PC_REGISTERS_PTR       TisReg,
 383   IN     UINT8                      *BufferIn,
 384   IN     UINT32                     SizeIn,
 385   IN OUT UINT8                      *BufferOut,
 386   IN OUT UINT32                     *SizeOut
 387   );
 388
 389 /**
 390   Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE
 391   to ACCESS Register in the time of default TIS_TIMEOUT_A.
 392
 393   @param[in] TisReg                Pointer to TIS register.
 394
 395   @retval    EFI_SUCCESS           Get the control of TPM chip.
 396   @retval    EFI_INVALID_PARAMETER TisReg is NULL.
 397   @retval    EFI_NOT_FOUND         TPM chip doesn't exit.
 398   @retval    EFI_TIMEOUT           Can't get the TPM control in time.
 399 **/
 400 EFI_STATUS
 401 TisPcRequestUseTpm (
 402   IN     TIS_PC_REGISTERS_PTR       TisReg
 403   );
 404
 405 /**
 406   Return PTP interface type.
 407
 408   @param[in] Register                Pointer to PTP register.
 409
 410   @return PTP interface type.
 411 **/
 412 TPM2_PTP_INTERFACE_TYPE
 413 Tpm2GetPtpInterface (
 414   IN VOID *Register
 415   )
 416 {
 417   PTP_CRB_INTERFACE_IDENTIFIER  InterfaceId;
 418   PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;
 419
 420   if (!Tpm2IsPtpPresence (Register)) {
 421     return Tpm2PtpInterfaceMax;
 422   }
 423   //
 424   // Check interface id
 425   //
 426   InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
 427   InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
 428
 429   if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&
 430       (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&
 431       (InterfaceId.Bits.CapCRB != 0)) {
 432     return Tpm2PtpInterfaceCrb;
 433   }
 434   if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO) &&
 435       (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO) &&
 436       (InterfaceId.Bits.CapFIFO != 0) &&
 437       (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP)) {
 438     return Tpm2PtpInterfaceFifo;
 439   }
 440   return Tpm2PtpInterfaceTis;
 441 }
 442
 443 /**
 444   Return PTP CRB interface IdleByPass state.
 445
 446   @param[in] Register                Pointer to PTP register.
 447
 448   @return PTP CRB interface IdleByPass state.
 449 **/
 450 UINT8
 451 Tpm2GetIdleByPass (
 452   IN VOID *Register
 453   )
 454 {
 455   PTP_CRB_INTERFACE_IDENTIFIER  InterfaceId;
 456
 457   //
 458   // Check interface id
 459   //
 460   InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
 461
 462   return (UINT8)(InterfaceId.Bits.CapCRBIdleBypass);
 463 }
 464
 465 /**
 466   Dump PTP register information.
 467
 468   @param[in] Register                Pointer to PTP register.
 469 **/
 470 VOID
 471 DumpPtpInfo (
 472   IN VOID *Register
 473   )
 474 {
 475   PTP_CRB_INTERFACE_IDENTIFIER  InterfaceId;
 476   PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;
 477   UINT8                         StatusEx;
 478   UINT16                        Vid;
 479   UINT16                        Did;
 480   UINT8                         Rid;
 481   TPM2_PTP_INTERFACE_TYPE       PtpInterface;
 482
 483   if (!Tpm2IsPtpPresence (Register)) {
 484     return ;
 485   }
 486
 487   InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
 488   InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
 489   StatusEx = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->StatusEx);
 490
 491   //
 492   // Dump InterfaceId Register for PTP
 493   //
 494   DEBUG ((EFI_D_INFO, "InterfaceId - 0x%08x\n", InterfaceId.Uint32));
 495   DEBUG ((EFI_D_INFO, "  InterfaceType    - 0x%02x\n", InterfaceId.Bits.InterfaceType));
 496   if (InterfaceId.Bits.InterfaceType != PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) {
 497     DEBUG ((EFI_D_INFO, "  InterfaceVersion - 0x%02x\n", InterfaceId.Bits.InterfaceVersion));
 498     DEBUG ((EFI_D_INFO, "  CapFIFO          - 0x%x\n", InterfaceId.Bits.CapFIFO));
 499     DEBUG ((EFI_D_INFO, "  CapCRB           - 0x%x\n", InterfaceId.Bits.CapCRB));
 500   }
 501
 502   //
 503   // Dump Capability Register for TIS and FIFO
 504   //
 505   DEBUG ((EFI_D_INFO, "InterfaceCapability - 0x%08x\n", InterfaceCapability.Uint32));
 506   if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) ||
 507       (InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO)) {
 508     DEBUG ((EFI_D_INFO, "  InterfaceVersion - 0x%x\n", InterfaceCapability.Bits.InterfaceVersion));
 509   }
 510
 511   //
 512   // Dump StatusEx Register for PTP FIFO
 513   //
 514   DEBUG ((EFI_D_INFO, "StatusEx - 0x%02x\n", StatusEx));
 515   if (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP) {
 516     DEBUG ((EFI_D_INFO, "  TpmFamily - 0x%x\n", (StatusEx & PTP_FIFO_STS_EX_TPM_FAMILY) >> PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET));
 517   }
 518
 519   Vid = 0xFFFF;
 520   Did = 0xFFFF;
 521   Rid = 0xFF;
 522   PtpInterface = PcdGet8(PcdActiveTpmInterfaceType);
 523   DEBUG ((EFI_D_INFO, "PtpInterface - %x\n", PtpInterface));
 524   switch (PtpInterface) {
 525   case Tpm2PtpInterfaceCrb:
 526     Vid = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Vid);
 527     Did = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Did);
 528     Rid = (UINT8)InterfaceId.Bits.Rid;
 529     break;
 530   case Tpm2PtpInterfaceFifo:
 531   case Tpm2PtpInterfaceTis:
 532     Vid = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Vid);
 533     Did = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Did);
 534     Rid = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Rid);
 535     break;
 536   default:
 537     break;
 538   }
 539   DEBUG ((EFI_D_INFO, "VID - 0x%04x\n", Vid));
 540   DEBUG ((EFI_D_INFO, "DID - 0x%04x\n", Did));
 541   DEBUG ((EFI_D_INFO, "RID - 0x%02x\n", Rid));
 542 }
 543
 544 /**
 545   This service enables the sending of commands to the TPM2.
 546
 547   @param[in]      InputParameterBlockSize  Size of the TPM2 input parameter block.
 548   @param[in]      InputParameterBlock      Pointer to the TPM2 input parameter block.
 549   @param[in,out]  OutputParameterBlockSize Size of the TPM2 output parameter block.
 550   @param[in]      OutputParameterBlock     Pointer to the TPM2 output parameter block.
 551
 552   @retval EFI_SUCCESS            The command byte stream was successfully sent to the device and a response was successfully received.
 553   @retval EFI_DEVICE_ERROR       The command was not successfully sent to the device or a response was not successfully received from the device.
 554   @retval EFI_BUFFER_TOO_SMALL   The output parameter block is too small.
 555 **/
 556 EFI_STATUS
 557 EFIAPI
 558 DTpm2SubmitCommand (
 559   IN UINT32            InputParameterBlockSize,
 560   IN UINT8             *InputParameterBlock,
 561   IN OUT UINT32        *OutputParameterBlockSize,
 562   IN UINT8             *OutputParameterBlock
 563   )
 564 {
 565   TPM2_PTP_INTERFACE_TYPE  PtpInterface;
 566
 567   PtpInterface = PcdGet8(PcdActiveTpmInterfaceType);
 568   switch (PtpInterface) {
 569   case Tpm2PtpInterfaceCrb:
 570     return PtpCrbTpmCommand (
 571            (PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),
 572            InputParameterBlock,
 573            InputParameterBlockSize,
 574            OutputParameterBlock,
 575            OutputParameterBlockSize
 576            );
 577   case Tpm2PtpInterfaceFifo:
 578   case Tpm2PtpInterfaceTis:
 579     return Tpm2TisTpmCommand (
 580            (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),
 581            InputParameterBlock,
 582            InputParameterBlockSize,
 583            OutputParameterBlock,
 584            OutputParameterBlockSize
 585            );
 586   default:
 587     return EFI_NOT_FOUND;
 588   }
 589 }
 590
 591 /**
 592   This service requests use TPM2.
 593
 594   @retval EFI_SUCCESS      Get the control of TPM2 chip.
 595   @retval EFI_NOT_FOUND    TPM2 not found.
 596   @retval EFI_DEVICE_ERROR Unexpected device behavior.
 597 **/
 598 EFI_STATUS
 599 EFIAPI
 600 DTpm2RequestUseTpm (
 601   VOID
 602   )
 603 {
 604   TPM2_PTP_INTERFACE_TYPE  PtpInterface;
 605
 606   PtpInterface = PcdGet8(PcdActiveTpmInterfaceType);
 607   switch (PtpInterface) {
 608   case Tpm2PtpInterfaceCrb:
 609     return PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
 610   case Tpm2PtpInterfaceFifo:
 611   case Tpm2PtpInterfaceTis:
 612     return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
 613   default:
 614     return EFI_NOT_FOUND;
 615   }
 616 }