SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c

   1 /** @file
   2   PTP (Platform TPM Profile) CRB (Command Response Buffer) interface used by dTPM2.0 library.
   3
   4 Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include <IndustryStandard/Tpm20.h>
  16
  17 #include <Library/BaseLib.h>
  18 #include <Library/BaseMemoryLib.h>
  19 #include <Library/IoLib.h>
  20 #include <Library/TimerLib.h>
  21 #include <Library/DebugLib.h>
  22 #include <Library/Tpm2DeviceLib.h>
  23 #include <Library/PcdLib.h>
  24
  25 #include <IndustryStandard/TpmPtp.h>
  26 #include <IndustryStandard/TpmTis.h>
  27
  28 //
  29 // Execution of the command may take from several seconds to minutes for certain
  30 // commands, such as key generation.
  31 //
  32 #define PTP_TIMEOUT_MAX             (90000 * 1000)  // 90s
  33
  34 //
  35 // Max TPM command/reponse length
  36 //
  37 #define TPMCMDBUFLENGTH             0x500
  38
  39 /**
  40   Check whether TPM PTP register exist.
  41
  42   @param[in] Reg  Pointer to PTP register.
  43
  44   @retval    TRUE    TPM PTP exists.
  45   @retval    FALSE   TPM PTP is not found.
  46 **/
  47 BOOLEAN
  48 Tpm2IsPtpPresence (
  49   IN VOID *Reg
  50   )
  51 {
  52   UINT8                             RegRead;
  53
  54   RegRead = MmioRead8 ((UINTN)Reg);
  55   if (RegRead == 0xFF) {
  56     //
  57     // No TPM chip
  58     //
  59     return FALSE;
  60   }
  61   return TRUE;
  62 }
  63
  64 /**
  65   Check whether the value of a TPM chip register satisfies the input BIT setting.
  66
  67   @param[in]  Register     Address port of register to be checked.
  68   @param[in]  BitSet       Check these data bits are set.
  69   @param[in]  BitClear     Check these data bits are clear.
  70   @param[in]  TimeOut      The max wait time (unit MicroSecond) when checking register.
  71
  72   @retval     EFI_SUCCESS  The register satisfies the check bit.
  73   @retval     EFI_TIMEOUT  The register can't run into the expected status in time.
  74 **/
  75 EFI_STATUS
  76 PtpCrbWaitRegisterBits (
  77   IN      UINT32                    *Register,
  78   IN      UINT32                    BitSet,
  79   IN      UINT32                    BitClear,
  80   IN      UINT32                    TimeOut
  81   )
  82 {
  83   UINT32                            RegRead;
  84   UINT32                            WaitTime;
  85
  86   for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
  87     RegRead = MmioRead32 ((UINTN)Register);
  88     if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {
  89       return EFI_SUCCESS;
  90     }
  91     MicroSecondDelay (30);
  92   }
  93   return EFI_TIMEOUT;
  94 }
  95
  96 /**
  97   Get the control of TPM chip.
  98
  99   @param[in] CrbReg                Pointer to CRB register.
 100
 101   @retval    EFI_SUCCESS           Get the control of TPM chip.
 102   @retval    EFI_INVALID_PARAMETER CrbReg is NULL.
 103   @retval    EFI_NOT_FOUND         TPM chip doesn't exit.
 104   @retval    EFI_TIMEOUT           Can't get the TPM control in time.
 105 **/
 106 EFI_STATUS
 107 PtpCrbRequestUseTpm (
 108   IN      PTP_CRB_REGISTERS_PTR      CrbReg
 109   )
 110 {
 111   EFI_STATUS                        Status;
 112
 113   if (!Tpm2IsPtpPresence (CrbReg)) {
 114     return EFI_NOT_FOUND;
 115   }
 116
 117   MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);
 118   Status = PtpCrbWaitRegisterBits (
 119              &CrbReg->LocalityStatus,
 120              PTP_CRB_LOCALITY_STATUS_GRANTED,
 121              0,
 122              PTP_TIMEOUT_A
 123              );
 124   return Status;
 125 }
 126
 127 /**
 128   Send a command to TPM for execution and return response data.
 129
 130   @param[in]      CrbReg        TPM register space base address.
 131   @param[in]      BufferIn      Buffer for command data.
 132   @param[in]      SizeIn        Size of command data.
 133   @param[in, out] BufferOut     Buffer for response data.
 134   @param[in, out] SizeOut       Size of response data.
 135
 136   @retval EFI_SUCCESS           Operation completed successfully.
 137   @retval EFI_BUFFER_TOO_SMALL  Response data buffer is too small.
 138   @retval EFI_DEVICE_ERROR      Unexpected device behavior.
 139   @retval EFI_UNSUPPORTED       Unsupported TPM version
 140
 141 **/
 142 EFI_STATUS
 143 PtpCrbTpmCommand (
 144   IN     PTP_CRB_REGISTERS_PTR      CrbReg,
 145   IN     UINT8                      *BufferIn,
 146   IN     UINT32                     SizeIn,
 147   IN OUT UINT8                      *BufferOut,
 148   IN OUT UINT32                     *SizeOut
 149   )
 150 {
 151   EFI_STATUS                        Status;
 152   UINT32                            Index;
 153   UINT32                            TpmOutSize;
 154   UINT16                            Data16;
 155   UINT32                            Data32;
 156
 157   DEBUG_CODE (
 158     UINTN  DebugSize;
 159
 160     DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand Send - "));
 161     if (SizeIn > 0x100) {
 162       DebugSize = 0x40;
 163     } else {
 164       DebugSize = SizeIn;
 165     }
 166     for (Index = 0; Index < DebugSize; Index++) {
 167       DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));
 168     }
 169     if (DebugSize != SizeIn) {
 170       DEBUG ((EFI_D_VERBOSE, "...... "));
 171       for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {
 172         DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));
 173       }
 174     }
 175     DEBUG ((EFI_D_VERBOSE, "\n"));
 176   );
 177   TpmOutSize         = 0;
 178
 179   //
 180   // STEP 0:
 181   // if CapCRbIdelByPass == 0, enforce Idle state before sending command
 182   //
 183   if (PcdGet8(PcdCRBIdleByPass) == 0 && (MmioRead32((UINTN)&CrbReg->CrbControlStatus) & PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE) == 0){
 184     Status = PtpCrbWaitRegisterBits (
 185               &CrbReg->CrbControlStatus,
 186               PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,
 187               0,
 188               PTP_TIMEOUT_C
 189               );
 190     if (EFI_ERROR (Status)) {
 191       //
 192       // Try to goIdle to recover TPM
 193       //
 194       Status = EFI_DEVICE_ERROR;
 195       goto GoIdle_Exit;
 196     }
 197   }
 198
 199   //
 200   // STEP 1:
 201   // Ready is any time the TPM is ready to receive a command, following a write
 202   // of 1 by software to Request.cmdReady, as indicated by the Status field
 203   // being cleared to 0.
 204   //
 205   MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);
 206   Status = PtpCrbWaitRegisterBits (
 207              &CrbReg->CrbControlRequest,
 208              0,
 209              PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY,
 210              PTP_TIMEOUT_C
 211              );
 212   if (EFI_ERROR (Status)) {
 213     Status = EFI_DEVICE_ERROR;
 214     goto GoIdle_Exit;
 215   }
 216   Status = PtpCrbWaitRegisterBits (
 217              &CrbReg->CrbControlStatus,
 218              0,
 219              PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,
 220              PTP_TIMEOUT_C
 221              );
 222   if (EFI_ERROR (Status)) {
 223     Status = EFI_DEVICE_ERROR;
 224     goto GoIdle_Exit;
 225   }
 226
 227   //
 228   // STEP 2:
 229   // Command Reception occurs following a Ready state between the write of the
 230   // first byte of a command to the Command Buffer and the receipt of a write
 231   // of 1 to Start.
 232   //
 233   for (Index = 0; Index < SizeIn; Index++) {
 234     MmioWrite8 ((UINTN)&CrbReg->CrbDataBuffer[Index], BufferIn[Index]);
 235   }
 236   MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressHigh, (UINT32)RShiftU64 ((UINTN)CrbReg->CrbDataBuffer, 32));
 237   MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressLow, (UINT32)(UINTN)CrbReg->CrbDataBuffer);
 238   MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandSize, sizeof(CrbReg->CrbDataBuffer));
 239
 240   MmioWrite64 ((UINTN)&CrbReg->CrbControlResponseAddrss, (UINT32)(UINTN)CrbReg->CrbDataBuffer);
 241   MmioWrite32 ((UINTN)&CrbReg->CrbControlResponseSize, sizeof(CrbReg->CrbDataBuffer));
 242
 243   //
 244   // STEP 3:
 245   // Command Execution occurs after receipt of a 1 to Start and the TPM
 246   // clearing Start to 0.
 247   //
 248   MmioWrite32((UINTN)&CrbReg->CrbControlStart, PTP_CRB_CONTROL_START);
 249   Status = PtpCrbWaitRegisterBits (
 250              &CrbReg->CrbControlStart,
 251              0,
 252              PTP_CRB_CONTROL_START,
 253              PTP_TIMEOUT_MAX
 254              );
 255   if (EFI_ERROR (Status)) {
 256     //
 257     // Command Completion check timeout. Cancel the currently executing command by writing TPM_CRB_CTRL_CANCEL,
 258     // Expect TPM_RC_CANCELLED or successfully completed response.
 259     //
 260     MmioWrite32((UINTN)&CrbReg->CrbControlCancel, PTP_CRB_CONTROL_CANCEL);
 261     Status = PtpCrbWaitRegisterBits (
 262                &CrbReg->CrbControlStart,
 263                0,
 264                PTP_CRB_CONTROL_START,
 265                PTP_TIMEOUT_B
 266                );
 267     MmioWrite32((UINTN)&CrbReg->CrbControlCancel, 0);
 268
 269     if (EFI_ERROR(Status)) {
 270       //
 271       // Still in Command Execution state. Try to goIdle, the behavior is agnostic.
 272       //
 273       Status = EFI_DEVICE_ERROR;
 274       goto GoIdle_Exit;
 275     }
 276   }
 277
 278   //
 279   // STEP 4:
 280   // Command Completion occurs after completion of a command (indicated by the
 281   // TPM clearing TPM_CRB_CTRL_Start_x to 0) and before a write of a 1 by the
 282   // software to Request.goIdle.
 283   //
 284
 285   //
 286   // Get response data header
 287   //
 288   for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {
 289     BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);
 290   }
 291   DEBUG_CODE (
 292     DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand ReceiveHeader - "));
 293     for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {
 294       DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));
 295     }
 296     DEBUG ((EFI_D_VERBOSE, "\n"));
 297   );
 298   //
 299   // Check the reponse data header (tag, parasize and returncode)
 300   //
 301   CopyMem (&Data16, BufferOut, sizeof (UINT16));
 302   // TPM2 should not use this RSP_COMMAND
 303   if (SwapBytes16 (Data16) == TPM_ST_RSP_COMMAND) {
 304     DEBUG ((EFI_D_ERROR, "TPM2: TPM_ST_RSP error - %x\n", TPM_ST_RSP_COMMAND));
 305     Status = EFI_UNSUPPORTED;
 306     goto GoIdle_Exit;
 307   }
 308
 309   CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));
 310   TpmOutSize  = SwapBytes32 (Data32);
 311   if (*SizeOut < TpmOutSize) {
 312     //
 313     // Command completed, but buffer is not enough
 314     //
 315     Status = EFI_BUFFER_TOO_SMALL;
 316     goto GoReady_Exit;
 317   }
 318   *SizeOut = TpmOutSize;
 319   //
 320   // Continue reading the remaining data
 321   //
 322   for (Index = sizeof (TPM2_RESPONSE_HEADER); Index < TpmOutSize; Index++) {
 323     BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);
 324   }
 325
 326   DEBUG_CODE (
 327     DEBUG ((EFI_D_VERBOSE, "PtpCrbTpmCommand Receive - "));
 328     for (Index = 0; Index < TpmOutSize; Index++) {
 329       DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));
 330     }
 331     DEBUG ((EFI_D_VERBOSE, "\n"));
 332   );
 333
 334 GoReady_Exit:
 335   //
 336   // Goto Ready State if command is completed succesfully and TPM support IdleBypass
 337   // If not supported. flow down to GoIdle
 338   //
 339   if (PcdGet8(PcdCRBIdleByPass) == 1) {
 340     MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);
 341     return Status;
 342   }
 343
 344   //
 345   // Do not wait for state transition for TIMEOUT_C
 346   // This function will try to wait 2 TIMEOUT_C at the beginning in next call.
 347   //
 348 GoIdle_Exit:
 349
 350   //
 351   //  Return to Idle state by setting TPM_CRB_CTRL_STS_x.Status.goIdle to 1.
 352   //
 353   MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);
 354
 355   //
 356   // Only enforce Idle state transition if execution fails when CRBIndleBypass==1
 357   // Leave regular Idle delay at the beginning of next command execution
 358   //
 359   if (PcdGet8(PcdCRBIdleByPass) == 1){
 360     Status = PtpCrbWaitRegisterBits (
 361                &CrbReg->CrbControlStatus,
 362                PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,
 363                0,
 364                PTP_TIMEOUT_C
 365                );
 366   }
 367
 368   return Status;
 369 }
 370
 371 /**
 372   Send a command to TPM for execution and return response data.
 373
 374   @param[in]      TisReg        TPM register space base address.
 375   @param[in]      BufferIn      Buffer for command data.
 376   @param[in]      SizeIn        Size of command data.
 377   @param[in, out] BufferOut     Buffer for response data.
 378   @param[in, out] SizeOut       Size of response data.
 379
 380   @retval EFI_SUCCESS           Operation completed successfully.
 381   @retval EFI_BUFFER_TOO_SMALL  Response data buffer is too small.
 382   @retval EFI_DEVICE_ERROR      Unexpected device behavior.
 383   @retval EFI_UNSUPPORTED       Unsupported TPM version
 384
 385 **/
 386 EFI_STATUS
 387 Tpm2TisTpmCommand (
 388   IN     TIS_PC_REGISTERS_PTR       TisReg,
 389   IN     UINT8                      *BufferIn,
 390   IN     UINT32                     SizeIn,
 391   IN OUT UINT8                      *BufferOut,
 392   IN OUT UINT32                     *SizeOut
 393   );
 394
 395 /**
 396   Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE
 397   to ACCESS Register in the time of default TIS_TIMEOUT_A.
 398
 399   @param[in] TisReg                Pointer to TIS register.
 400
 401   @retval    EFI_SUCCESS           Get the control of TPM chip.
 402   @retval    EFI_INVALID_PARAMETER TisReg is NULL.
 403   @retval    EFI_NOT_FOUND         TPM chip doesn't exit.
 404   @retval    EFI_TIMEOUT           Can't get the TPM control in time.
 405 **/
 406 EFI_STATUS
 407 TisPcRequestUseTpm (
 408   IN     TIS_PC_REGISTERS_PTR       TisReg
 409   );
 410
 411 /**
 412   Return PTP interface type.
 413
 414   @param[in] Register                Pointer to PTP register.
 415
 416   @return PTP interface type.
 417 **/
 418 TPM2_PTP_INTERFACE_TYPE
 419 Tpm2GetPtpInterface (
 420   IN VOID *Register
 421   )
 422 {
 423   PTP_CRB_INTERFACE_IDENTIFIER  InterfaceId;
 424   PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;
 425
 426   if (!Tpm2IsPtpPresence (Register)) {
 427     return Tpm2PtpInterfaceMax;
 428   }
 429   //
 430   // Check interface id
 431   //
 432   InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
 433   InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
 434
 435   if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&
 436       (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&
 437       (InterfaceId.Bits.CapCRB != 0)) {
 438     return Tpm2PtpInterfaceCrb;
 439   }
 440   if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO) &&
 441       (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO) &&
 442       (InterfaceId.Bits.CapFIFO != 0) &&
 443       (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP)) {
 444     return Tpm2PtpInterfaceFifo;
 445   }
 446   return Tpm2PtpInterfaceTis;
 447 }
 448
 449 /**
 450   Return PTP CRB interface IdleByPass state.
 451
 452   @param[in] Register                Pointer to PTP register.
 453
 454   @return PTP CRB interface IdleByPass state.
 455 **/
 456 UINT8
 457 Tpm2GetIdleByPass (
 458   IN VOID *Register
 459   )
 460 {
 461   PTP_CRB_INTERFACE_IDENTIFIER  InterfaceId;
 462
 463   //
 464   // Check interface id
 465   //
 466   InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
 467
 468   return (UINT8)(InterfaceId.Bits.CapCRBIdleBypass);
 469 }
 470
 471 /**
 472   Dump PTP register information.
 473
 474   @param[in] Register                Pointer to PTP register.
 475 **/
 476 VOID
 477 DumpPtpInfo (
 478   IN VOID *Register
 479   )
 480 {
 481   PTP_CRB_INTERFACE_IDENTIFIER  InterfaceId;
 482   PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;
 483   UINT8                         StatusEx;
 484   UINT16                        Vid;
 485   UINT16                        Did;
 486   UINT8                         Rid;
 487   TPM2_PTP_INTERFACE_TYPE       PtpInterface;
 488
 489   if (!Tpm2IsPtpPresence (Register)) {
 490     return ;
 491   }
 492
 493   InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
 494   InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
 495   StatusEx = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->StatusEx);
 496
 497   //
 498   // Dump InterfaceId Register for PTP
 499   //
 500   DEBUG ((EFI_D_INFO, "InterfaceId - 0x%08x\n", InterfaceId.Uint32));
 501   DEBUG ((EFI_D_INFO, "  InterfaceType    - 0x%02x\n", InterfaceId.Bits.InterfaceType));
 502   if (InterfaceId.Bits.InterfaceType != PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) {
 503     DEBUG ((EFI_D_INFO, "  InterfaceVersion - 0x%02x\n", InterfaceId.Bits.InterfaceVersion));
 504     DEBUG ((EFI_D_INFO, "  CapFIFO          - 0x%x\n", InterfaceId.Bits.CapFIFO));
 505     DEBUG ((EFI_D_INFO, "  CapCRB           - 0x%x\n", InterfaceId.Bits.CapCRB));
 506   }
 507
 508   //
 509   // Dump Capability Register for TIS and FIFO
 510   //
 511   DEBUG ((EFI_D_INFO, "InterfaceCapability - 0x%08x\n", InterfaceCapability.Uint32));
 512   if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) ||
 513       (InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO)) {
 514     DEBUG ((EFI_D_INFO, "  InterfaceVersion - 0x%x\n", InterfaceCapability.Bits.InterfaceVersion));
 515   }
 516
 517   //
 518   // Dump StatusEx Register for PTP FIFO
 519   //
 520   DEBUG ((EFI_D_INFO, "StatusEx - 0x%02x\n", StatusEx));
 521   if (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP) {
 522     DEBUG ((EFI_D_INFO, "  TpmFamily - 0x%x\n", (StatusEx & PTP_FIFO_STS_EX_TPM_FAMILY) >> PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET));
 523   }
 524
 525   Vid = 0xFFFF;
 526   Did = 0xFFFF;
 527   Rid = 0xFF;
 528   PtpInterface = PcdGet8(PcdActiveTpmInterfaceType);
 529   DEBUG ((EFI_D_INFO, "PtpInterface - %x\n", PtpInterface));
 530   switch (PtpInterface) {
 531   case Tpm2PtpInterfaceCrb:
 532     Vid = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Vid);
 533     Did = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Did);
 534     Rid = (UINT8)InterfaceId.Bits.Rid;
 535     break;
 536   case Tpm2PtpInterfaceFifo:
 537   case Tpm2PtpInterfaceTis:
 538     Vid = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Vid);
 539     Did = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Did);
 540     Rid = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Rid);
 541     break;
 542   default:
 543     break;
 544   }
 545   DEBUG ((EFI_D_INFO, "VID - 0x%04x\n", Vid));
 546   DEBUG ((EFI_D_INFO, "DID - 0x%04x\n", Did));
 547   DEBUG ((EFI_D_INFO, "RID - 0x%02x\n", Rid));
 548 }
 549
 550 /**
 551   This service enables the sending of commands to the TPM2.
 552
 553   @param[in]      InputParameterBlockSize  Size of the TPM2 input parameter block.
 554   @param[in]      InputParameterBlock      Pointer to the TPM2 input parameter block.
 555   @param[in,out]  OutputParameterBlockSize Size of the TPM2 output parameter block.
 556   @param[in]      OutputParameterBlock     Pointer to the TPM2 output parameter block.
 557
 558   @retval EFI_SUCCESS            The command byte stream was successfully sent to the device and a response was successfully received.
 559   @retval EFI_DEVICE_ERROR       The command was not successfully sent to the device or a response was not successfully received from the device.
 560   @retval EFI_BUFFER_TOO_SMALL   The output parameter block is too small.
 561 **/
 562 EFI_STATUS
 563 EFIAPI
 564 DTpm2SubmitCommand (
 565   IN UINT32            InputParameterBlockSize,
 566   IN UINT8             *InputParameterBlock,
 567   IN OUT UINT32        *OutputParameterBlockSize,
 568   IN UINT8             *OutputParameterBlock
 569   )
 570 {
 571   TPM2_PTP_INTERFACE_TYPE  PtpInterface;
 572
 573   PtpInterface = PcdGet8(PcdActiveTpmInterfaceType);
 574   switch (PtpInterface) {
 575   case Tpm2PtpInterfaceCrb:
 576     return PtpCrbTpmCommand (
 577            (PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),
 578            InputParameterBlock,
 579            InputParameterBlockSize,
 580            OutputParameterBlock,
 581            OutputParameterBlockSize
 582            );
 583   case Tpm2PtpInterfaceFifo:
 584   case Tpm2PtpInterfaceTis:
 585     return Tpm2TisTpmCommand (
 586            (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),
 587            InputParameterBlock,
 588            InputParameterBlockSize,
 589            OutputParameterBlock,
 590            OutputParameterBlockSize
 591            );
 592   default:
 593     return EFI_NOT_FOUND;
 594   }
 595 }
 596
 597 /**
 598   This service requests use TPM2.
 599
 600   @retval EFI_SUCCESS      Get the control of TPM2 chip.
 601   @retval EFI_NOT_FOUND    TPM2 not found.
 602   @retval EFI_DEVICE_ERROR Unexpected device behavior.
 603 **/
 604 EFI_STATUS
 605 EFIAPI
 606 DTpm2RequestUseTpm (
 607   VOID
 608   )
 609 {
 610   TPM2_PTP_INTERFACE_TYPE  PtpInterface;
 611
 612   PtpInterface = PcdGet8(PcdActiveTpmInterfaceType);
 613   switch (PtpInterface) {
 614   case Tpm2PtpInterfaceCrb:
 615     return PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
 616   case Tpm2PtpInterfaceFifo:
 617   case Tpm2PtpInterfaceTis:
 618     return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
 619   default:
 620     return EFI_NOT_FOUND;
 621   }
 622 }