1276aea9c237827e5d86652235bef0b1236776d2
[mirror_edk2.git] / SecurityPkg / Library / Tpm2DeviceLibDTpm / Tpm2Tis.c
1 /** @file
2 TIS (TPM Interface Specification) functions used by dTPM2.0 library.
3
4 Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #include <IndustryStandard/Tpm20.h>
17
18 #include <Library/BaseLib.h>
19 #include <Library/BaseMemoryLib.h>
20 #include <Library/IoLib.h>
21 #include <Library/TimerLib.h>
22 #include <Library/DebugLib.h>
23 #include <Library/Tpm2DeviceLib.h>
24 #include <Library/PcdLib.h>
25
26 //
27 // Set structure alignment to 1-byte
28 //
29 #pragma pack (1)
30
31 //
32 // Register set map as specified in TIS specification Chapter 10
33 //
34 typedef struct {
35 ///
36 /// Used to gain ownership for this particular port.
37 ///
38 UINT8 Access; // 0
39 UINT8 Reserved1[7]; // 1
40 ///
41 /// Controls interrupts.
42 ///
43 UINT32 IntEnable; // 8
44 ///
45 /// SIRQ vector to be used by the TPM.
46 ///
47 UINT8 IntVector; // 0ch
48 UINT8 Reserved2[3]; // 0dh
49 ///
50 /// What caused interrupt.
51 ///
52 UINT32 IntSts; // 10h
53 ///
54 /// Shows which interrupts are supported by that particular TPM.
55 ///
56 UINT32 IntfCapability; // 14h
57 ///
58 /// Status Register. Provides status of the TPM.
59 ///
60 UINT8 Status; // 18h
61 ///
62 /// Number of consecutive writes that can be done to the TPM.
63 ///
64 UINT16 BurstCount; // 19h
65 ///
66 /// TPM2 support CANCEL at BIT[24] of STATUS register (WO)
67 ///
68 UINT8 StatusEx; // 1Bh
69 UINT8 Reserved3[8];
70 ///
71 /// Read or write FIFO, depending on transaction.
72 ///
73 UINT32 DataFifo; // 24h
74 UINT8 Reserved4[0xed8]; // 28h
75 ///
76 /// Vendor ID
77 ///
78 UINT16 Vid; // 0f00h
79 ///
80 /// Device ID
81 ///
82 UINT16 Did; // 0f02h
83 ///
84 /// Revision ID
85 ///
86 UINT8 Rid; // 0f04h
87 ///
88 /// TCG defined configuration registers.
89 ///
90 UINT8 TcgDefined[0x7b]; // 0f05h
91 ///
92 /// Alias to I/O legacy space.
93 ///
94 UINT32 LegacyAddress1; // 0f80h
95 ///
96 /// Additional 8 bits for I/O legacy space extension.
97 ///
98 UINT32 LegacyAddress1Ex; // 0f84h
99 ///
100 /// Alias to second I/O legacy space.
101 ///
102 UINT32 LegacyAddress2; // 0f88h
103 ///
104 /// Additional 8 bits for second I/O legacy space extension.
105 ///
106 UINT32 LegacyAddress2Ex; // 0f8ch
107 ///
108 /// Vendor-defined configuration registers.
109 ///
110 UINT8 VendorDefined[0x70];// 0f90h
111 } TIS_PC_REGISTERS;
112
113 //
114 // Restore original structure alignment
115 //
116 #pragma pack ()
117
118 //
119 // Define pointer types used to access TIS registers on PC
120 //
121 typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;
122
123 //
124 // Define bits of ACCESS and STATUS registers
125 //
126
127 ///
128 /// This bit is a 1 to indicate that the other bits in this register are valid.
129 ///
130 #define TIS_PC_VALID BIT7
131 ///
132 /// Indicate that this locality is active.
133 ///
134 #define TIS_PC_ACC_ACTIVE BIT5
135 ///
136 /// Set to 1 to indicate that this locality had the TPM taken away while
137 /// this locality had the TIS_PC_ACC_ACTIVE bit set.
138 ///
139 #define TIS_PC_ACC_SEIZED BIT4
140 ///
141 /// Set to 1 to indicate that TPM MUST reset the
142 /// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
143 /// locality that is writing this bit.
144 ///
145 #define TIS_PC_ACC_SEIZE BIT3
146 ///
147 /// When this bit is 1, another locality is requesting usage of the TPM.
148 ///
149 #define TIS_PC_ACC_PENDIND BIT2
150 ///
151 /// Set to 1 to indicate that this locality is requesting to use TPM.
152 ///
153 #define TIS_PC_ACC_RQUUSE BIT1
154 ///
155 /// A value of 1 indicates that a T/OS has not been established on the platform
156 ///
157 #define TIS_PC_ACC_ESTABLISH BIT0
158
159 ///
160 /// When this bit is 1, TPM is in the Ready state,
161 /// indicating it is ready to receive a new command.
162 ///
163 #define TIS_PC_STS_READY BIT6
164 ///
165 /// Write a 1 to this bit to cause the TPM to execute that command.
166 ///
167 #define TIS_PC_STS_GO BIT5
168 ///
169 /// This bit indicates that the TPM has data available as a response.
170 ///
171 #define TIS_PC_STS_DATA BIT4
172 ///
173 /// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
174 ///
175 #define TIS_PC_STS_EXPECT BIT3
176 ///
177 /// Writes a 1 to this bit to force the TPM to re-send the response.
178 ///
179 #define TIS_PC_STS_RETRY BIT1
180
181 //
182 // Default TimeOut value
183 //
184 #define TIS_TIMEOUT_A (1000 * 1000) // 1s
185 #define TIS_TIMEOUT_B (2000 * 1000) // 2s
186 #define TIS_TIMEOUT_C (1000 * 1000) // 1s
187 #define TIS_TIMEOUT_D (1000 * 1000) // 1s
188
189 #define TIS_TIMEOUT_MAX (90000 * 1000) // 90s
190
191 //
192 // Max TPM command/reponse length
193 //
194 #define TPMCMDBUFLENGTH 0x500
195
196 /**
197 Check whether TPM chip exist.
198
199 @param[in] TisReg Pointer to TIS register.
200
201 @retval TRUE TPM chip exists.
202 @retval FALSE TPM chip is not found.
203 **/
204 BOOLEAN
205 TisPcPresenceCheck (
206 IN TIS_PC_REGISTERS_PTR TisReg
207 )
208 {
209 UINT8 RegRead;
210
211 RegRead = MmioRead8 ((UINTN)&TisReg->Access);
212 return (BOOLEAN)(RegRead != (UINT8)-1);
213 }
214
215 /**
216 Check whether the value of a TPM chip register satisfies the input BIT setting.
217
218 @param[in] Register Address port of register to be checked.
219 @param[in] BitSet Check these data bits are set.
220 @param[in] BitClear Check these data bits are clear.
221 @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.
222
223 @retval EFI_SUCCESS The register satisfies the check bit.
224 @retval EFI_TIMEOUT The register can't run into the expected status in time.
225 **/
226 EFI_STATUS
227 TisPcWaitRegisterBits (
228 IN UINT8 *Register,
229 IN UINT8 BitSet,
230 IN UINT8 BitClear,
231 IN UINT32 TimeOut
232 )
233 {
234 UINT8 RegRead;
235 UINT32 WaitTime;
236
237 for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
238 RegRead = MmioRead8 ((UINTN)Register);
239 if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)
240 return EFI_SUCCESS;
241 MicroSecondDelay (30);
242 }
243 return EFI_TIMEOUT;
244 }
245
246 /**
247 Get BurstCount by reading the burstCount field of a TIS regiger
248 in the time of default TIS_TIMEOUT_D.
249
250 @param[in] TisReg Pointer to TIS register.
251 @param[out] BurstCount Pointer to a buffer to store the got BurstConut.
252
253 @retval EFI_SUCCESS Get BurstCount.
254 @retval EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.
255 @retval EFI_TIMEOUT BurstCount can't be got in time.
256 **/
257 EFI_STATUS
258 TisPcReadBurstCount (
259 IN TIS_PC_REGISTERS_PTR TisReg,
260 OUT UINT16 *BurstCount
261 )
262 {
263 UINT32 WaitTime;
264 UINT8 DataByte0;
265 UINT8 DataByte1;
266
267 if (BurstCount == NULL || TisReg == NULL) {
268 return EFI_INVALID_PARAMETER;
269 }
270
271 WaitTime = 0;
272 do {
273 //
274 // TIS_PC_REGISTERS_PTR->burstCount is UINT16, but it is not 2bytes aligned,
275 // so it needs to use MmioRead8 to read two times
276 //
277 DataByte0 = MmioRead8 ((UINTN)&TisReg->BurstCount);
278 DataByte1 = MmioRead8 ((UINTN)&TisReg->BurstCount + 1);
279 *BurstCount = (UINT16)((DataByte1 << 8) + DataByte0);
280 if (*BurstCount != 0) {
281 return EFI_SUCCESS;
282 }
283 MicroSecondDelay (30);
284 WaitTime += 30;
285 } while (WaitTime < TIS_TIMEOUT_D);
286
287 return EFI_TIMEOUT;
288 }
289
290 /**
291 Set TPM chip to ready state by sending ready command TIS_PC_STS_READY
292 to Status Register in time.
293
294 @param[in] TisReg Pointer to TIS register.
295
296 @retval EFI_SUCCESS TPM chip enters into ready state.
297 @retval EFI_INVALID_PARAMETER TisReg is NULL.
298 @retval EFI_TIMEOUT TPM chip can't be set to ready state in time.
299 **/
300 EFI_STATUS
301 TisPcPrepareCommand (
302 IN TIS_PC_REGISTERS_PTR TisReg
303 )
304 {
305 EFI_STATUS Status;
306
307 if (TisReg == NULL) {
308 return EFI_INVALID_PARAMETER;
309 }
310
311 MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
312 Status = TisPcWaitRegisterBits (
313 &TisReg->Status,
314 TIS_PC_STS_READY,
315 0,
316 TIS_TIMEOUT_B
317 );
318 return Status;
319 }
320
321 /**
322 Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE
323 to ACCESS Register in the time of default TIS_TIMEOUT_A.
324
325 @param[in] TisReg Pointer to TIS register.
326
327 @retval EFI_SUCCESS Get the control of TPM chip.
328 @retval EFI_INVALID_PARAMETER TisReg is NULL.
329 @retval EFI_NOT_FOUND TPM chip doesn't exit.
330 @retval EFI_TIMEOUT Can't get the TPM control in time.
331 **/
332 EFI_STATUS
333 TisPcRequestUseTpm (
334 IN TIS_PC_REGISTERS_PTR TisReg
335 )
336 {
337 EFI_STATUS Status;
338
339 if (TisReg == NULL) {
340 return EFI_INVALID_PARAMETER;
341 }
342
343 if (!TisPcPresenceCheck (TisReg)) {
344 return EFI_NOT_FOUND;
345 }
346
347 MmioWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);
348 Status = TisPcWaitRegisterBits (
349 &TisReg->Access,
350 (UINT8)(TIS_PC_ACC_ACTIVE |TIS_PC_VALID),
351 0,
352 TIS_TIMEOUT_A
353 );
354 return Status;
355 }
356
357 /**
358 Send a command to TPM for execution and return response data.
359
360 @param[in] TisReg TPM register space base address.
361 @param[in] BufferIn Buffer for command data.
362 @param[in] SizeIn Size of command data.
363 @param[in, out] BufferOut Buffer for response data.
364 @param[in, out] SizeOut Size of response data.
365
366 @retval EFI_SUCCESS Operation completed successfully.
367 @retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.
368 @retval EFI_DEVICE_ERROR Unexpected device behavior.
369 @retval EFI_UNSUPPORTED Unsupported TPM version
370
371 **/
372 EFI_STATUS
373 Tpm2TisTpmCommand (
374 IN TIS_PC_REGISTERS_PTR TisReg,
375 IN UINT8 *BufferIn,
376 IN UINT32 SizeIn,
377 IN OUT UINT8 *BufferOut,
378 IN OUT UINT32 *SizeOut
379 )
380 {
381 EFI_STATUS Status;
382 UINT16 BurstCount;
383 UINT32 Index;
384 UINT32 TpmOutSize;
385 UINT16 Data16;
386 UINT32 Data32;
387
388 DEBUG_CODE (
389 UINTN DebugSize;
390
391 DEBUG ((EFI_D_VERBOSE, "Tpm2TisTpmCommand Send - "));
392 if (SizeIn > 0x100) {
393 DebugSize = 0x40;
394 } else {
395 DebugSize = SizeIn;
396 }
397 for (Index = 0; Index < DebugSize; Index++) {
398 DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));
399 }
400 if (DebugSize != SizeIn) {
401 DEBUG ((EFI_D_VERBOSE, "...... "));
402 for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {
403 DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));
404 }
405 }
406 DEBUG ((EFI_D_VERBOSE, "\n"));
407 );
408 TpmOutSize = 0;
409
410 Status = TisPcPrepareCommand (TisReg);
411 if (EFI_ERROR (Status)){
412 DEBUG ((DEBUG_ERROR, "Tpm2 is not ready for command!\n"));
413 return EFI_DEVICE_ERROR;
414 }
415 //
416 // Send the command data to Tpm
417 //
418 Index = 0;
419 while (Index < SizeIn) {
420 Status = TisPcReadBurstCount (TisReg, &BurstCount);
421 if (EFI_ERROR (Status)) {
422 Status = EFI_DEVICE_ERROR;
423 goto Exit;
424 }
425 for (; BurstCount > 0 && Index < SizeIn; BurstCount--) {
426 MmioWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));
427 Index++;
428 }
429 }
430 //
431 // Check the Tpm status STS_EXPECT change from 1 to 0
432 //
433 Status = TisPcWaitRegisterBits (
434 &TisReg->Status,
435 (UINT8) TIS_PC_VALID,
436 TIS_PC_STS_EXPECT,
437 TIS_TIMEOUT_C
438 );
439 if (EFI_ERROR (Status)) {
440 DEBUG ((DEBUG_ERROR, "Tpm2 The send buffer too small!\n"));
441 Status = EFI_BUFFER_TOO_SMALL;
442 goto Exit;
443 }
444 //
445 // Executed the TPM command and waiting for the response data ready
446 //
447 MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);
448
449 //
450 // NOTE: That may take many seconds to minutes for certain commands, such as key generation.
451 //
452 Status = TisPcWaitRegisterBits (
453 &TisReg->Status,
454 (UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA),
455 0,
456 TIS_TIMEOUT_MAX
457 );
458 if (EFI_ERROR (Status)) {
459 DEBUG ((DEBUG_ERROR, "Wait for Tpm2 response data time out!!\n"));
460 Status = EFI_DEVICE_ERROR;
461 goto Exit;
462 }
463 //
464 // Get response data header
465 //
466 Index = 0;
467 BurstCount = 0;
468 while (Index < sizeof (TPM2_RESPONSE_HEADER)) {
469 Status = TisPcReadBurstCount (TisReg, &BurstCount);
470 if (EFI_ERROR (Status)) {
471 Status = EFI_DEVICE_ERROR;
472 goto Exit;
473 }
474 for (; BurstCount > 0; BurstCount--) {
475 *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
476 Index++;
477 if (Index == sizeof (TPM2_RESPONSE_HEADER)) break;
478 }
479 }
480 DEBUG_CODE (
481 DEBUG ((EFI_D_VERBOSE, "Tpm2TisTpmCommand ReceiveHeader - "));
482 for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {
483 DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));
484 }
485 DEBUG ((EFI_D_VERBOSE, "\n"));
486 );
487 //
488 // Check the reponse data header (tag,parasize and returncode )
489 //
490 CopyMem (&Data16, BufferOut, sizeof (UINT16));
491 // TPM2 should not use this RSP_COMMAND
492 if (SwapBytes16 (Data16) == TPM_ST_RSP_COMMAND) {
493 DEBUG ((EFI_D_ERROR, "TPM2: TPM_ST_RSP error - %x\n", TPM_ST_RSP_COMMAND));
494 Status = EFI_UNSUPPORTED;
495 goto Exit;
496 }
497
498 CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));
499 TpmOutSize = SwapBytes32 (Data32);
500 if (*SizeOut < TpmOutSize) {
501 Status = EFI_BUFFER_TOO_SMALL;
502 goto Exit;
503 }
504 *SizeOut = TpmOutSize;
505 //
506 // Continue reading the remaining data
507 //
508 while ( Index < TpmOutSize ) {
509 for (; BurstCount > 0; BurstCount--) {
510 *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
511 Index++;
512 if (Index == TpmOutSize) {
513 Status = EFI_SUCCESS;
514 goto Exit;
515 }
516 }
517 Status = TisPcReadBurstCount (TisReg, &BurstCount);
518 if (EFI_ERROR (Status)) {
519 Status = EFI_DEVICE_ERROR;
520 goto Exit;
521 }
522 }
523 Exit:
524 DEBUG_CODE (
525 DEBUG ((EFI_D_VERBOSE, "Tpm2TisTpmCommand Receive - "));
526 for (Index = 0; Index < TpmOutSize; Index++) {
527 DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));
528 }
529 DEBUG ((EFI_D_VERBOSE, "\n"));
530 );
531 MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
532 return Status;
533 }
534
535 /**
536 This service enables the sending of commands to the TPM2.
537
538 @param[in] InputParameterBlockSize Size of the TPM2 input parameter block.
539 @param[in] InputParameterBlock Pointer to the TPM2 input parameter block.
540 @param[in,out] OutputParameterBlockSize Size of the TPM2 output parameter block.
541 @param[in] OutputParameterBlock Pointer to the TPM2 output parameter block.
542
543 @retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.
544 @retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.
545 @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small.
546 **/
547 EFI_STATUS
548 EFIAPI
549 DTpm2SubmitCommand (
550 IN UINT32 InputParameterBlockSize,
551 IN UINT8 *InputParameterBlock,
552 IN OUT UINT32 *OutputParameterBlockSize,
553 IN UINT8 *OutputParameterBlock
554 )
555 {
556 return Tpm2TisTpmCommand (
557 (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),
558 InputParameterBlock,
559 InputParameterBlockSize,
560 OutputParameterBlock,
561 OutputParameterBlockSize
562 );
563 }
564
565 /**
566 This service requests use TPM2.
567
568 @retval EFI_SUCCESS Get the control of TPM2 chip.
569 @retval EFI_NOT_FOUND TPM2 not found.
570 @retval EFI_DEVICE_ERROR Unexpected device behavior.
571 **/
572 EFI_STATUS
573 EFIAPI
574 DTpm2RequestUseTpm (
575 VOID
576 )
577 {
578 return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
579 }