ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c

   1 /** @file
   2   Main file for Pci shell Debug1 function.
   3
   4   Copyright (c) 2005 - 2011, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include "UefiShellDebug1CommandsLib.h"
  16 #include <Protocol/PciRootBridgeIo.h>
  17 #include <Library/ShellLib.h>
  18 #include <IndustryStandard/Pci.h>
  19 #include <IndustryStandard/Acpi.h>
  20 #include "Pci.h"
  21
  22 #define PCI_CLASS_STRING_LIMIT  54
  23 //
  24 // Printable strings for Pci class code
  25 //
  26 typedef struct {
  27   CHAR16  *BaseClass; // Pointer to the PCI base class string
  28   CHAR16  *SubClass;  // Pointer to the PCI sub class string
  29   CHAR16  *PIFClass;  // Pointer to the PCI programming interface string
  30 } PCI_CLASS_STRINGS;
  31
  32 //
  33 // a structure holding a single entry, which also points to its lower level
  34 // class
  35 //
  36 typedef struct PCI_CLASS_ENTRY_TAG {
  37   UINT8                       Code;             // Class, subclass or I/F code
  38   CHAR16                      *DescText;        // Description string
  39   struct PCI_CLASS_ENTRY_TAG  *LowerLevelClass; // Subclass or I/F if any
  40 } PCI_CLASS_ENTRY;
  41
  42 //
  43 // Declarations of entries which contain printable strings for class codes
  44 // in PCI configuration space
  45 //
  46 PCI_CLASS_ENTRY PCIBlankEntry[];
  47 PCI_CLASS_ENTRY PCISubClass_00[];
  48 PCI_CLASS_ENTRY PCISubClass_01[];
  49 PCI_CLASS_ENTRY PCISubClass_02[];
  50 PCI_CLASS_ENTRY PCISubClass_03[];
  51 PCI_CLASS_ENTRY PCISubClass_04[];
  52 PCI_CLASS_ENTRY PCISubClass_05[];
  53 PCI_CLASS_ENTRY PCISubClass_06[];
  54 PCI_CLASS_ENTRY PCISubClass_07[];
  55 PCI_CLASS_ENTRY PCISubClass_08[];
  56 PCI_CLASS_ENTRY PCISubClass_09[];
  57 PCI_CLASS_ENTRY PCISubClass_0a[];
  58 PCI_CLASS_ENTRY PCISubClass_0b[];
  59 PCI_CLASS_ENTRY PCISubClass_0c[];
  60 PCI_CLASS_ENTRY PCISubClass_0d[];
  61 PCI_CLASS_ENTRY PCISubClass_0e[];
  62 PCI_CLASS_ENTRY PCISubClass_0f[];
  63 PCI_CLASS_ENTRY PCISubClass_10[];
  64 PCI_CLASS_ENTRY PCISubClass_11[];
  65 PCI_CLASS_ENTRY PCIPIFClass_0101[];
  66 PCI_CLASS_ENTRY PCIPIFClass_0300[];
  67 PCI_CLASS_ENTRY PCIPIFClass_0604[];
  68 PCI_CLASS_ENTRY PCIPIFClass_0700[];
  69 PCI_CLASS_ENTRY PCIPIFClass_0701[];
  70 PCI_CLASS_ENTRY PCIPIFClass_0703[];
  71 PCI_CLASS_ENTRY PCIPIFClass_0800[];
  72 PCI_CLASS_ENTRY PCIPIFClass_0801[];
  73 PCI_CLASS_ENTRY PCIPIFClass_0802[];
  74 PCI_CLASS_ENTRY PCIPIFClass_0803[];
  75 PCI_CLASS_ENTRY PCIPIFClass_0904[];
  76 PCI_CLASS_ENTRY PCIPIFClass_0c00[];
  77 PCI_CLASS_ENTRY PCIPIFClass_0c03[];
  78 PCI_CLASS_ENTRY PCIPIFClass_0e00[];
  79
  80 //
  81 // Base class strings entries
  82 //
  83 PCI_CLASS_ENTRY gClassStringList[] = {
  84   {
  85     0x00,
  86     L"Pre 2.0 device",
  87     PCISubClass_00
  88   },
  89   {
  90     0x01,
  91     L"Mass Storage Controller",
  92     PCISubClass_01
  93   },
  94   {
  95     0x02,
  96     L"Network Controller",
  97     PCISubClass_02
  98   },
  99   {
 100     0x03,
 101     L"Display Controller",
 102     PCISubClass_03
 103   },
 104   {
 105     0x04,
 106     L"Multimedia Device",
 107     PCISubClass_04
 108   },
 109   {
 110     0x05,
 111     L"Memory Controller",
 112     PCISubClass_05
 113   },
 114   {
 115     0x06,
 116     L"Bridge Device",
 117     PCISubClass_06
 118   },
 119   {
 120     0x07,
 121     L"Simple Communications Controllers",
 122     PCISubClass_07
 123   },
 124   {
 125     0x08,
 126     L"Base System Peripherals",
 127     PCISubClass_08
 128   },
 129   {
 130     0x09,
 131     L"Input Devices",
 132     PCISubClass_09
 133   },
 134   {
 135     0x0a,
 136     L"Docking Stations",
 137     PCISubClass_0a
 138   },
 139   {
 140     0x0b,
 141     L"Processors",
 142     PCISubClass_0b
 143   },
 144   {
 145     0x0c,
 146     L"Serial Bus Controllers",
 147     PCISubClass_0c
 148   },
 149   {
 150     0x0d,
 151     L"Wireless Controllers",
 152     PCISubClass_0d
 153   },
 154   {
 155     0x0e,
 156     L"Intelligent IO Controllers",
 157     PCISubClass_0e
 158   },
 159   {
 160     0x0f,
 161     L"Satellite Communications Controllers",
 162     PCISubClass_0f
 163   },
 164   {
 165     0x10,
 166     L"Encryption/Decryption Controllers",
 167     PCISubClass_10
 168   },
 169   {
 170     0x11,
 171     L"Data Acquisition & Signal Processing Controllers",
 172     PCISubClass_11
 173   },
 174   {
 175     0xff,
 176     L"Device does not fit in any defined classes",
 177     PCIBlankEntry
 178   },
 179   {
 180     0x00,
 181     NULL,
 182     /* null string ends the list */NULL
 183   }
 184 };
 185
 186 //
 187 // Subclass strings entries
 188 //
 189 PCI_CLASS_ENTRY PCIBlankEntry[] = {
 190   {
 191     0x00,
 192     L"",
 193     PCIBlankEntry
 194   },
 195   {
 196     0x00,
 197     NULL,
 198     /* null string ends the list */NULL
 199   }
 200 };
 201
 202 PCI_CLASS_ENTRY PCISubClass_00[] = {
 203   {
 204     0x00,
 205     L"All devices other than VGA",
 206     PCIBlankEntry
 207   },
 208   {
 209     0x01,
 210     L"VGA-compatible devices",
 211     PCIBlankEntry
 212   },
 213   {
 214     0x00,
 215     NULL,
 216     /* null string ends the list */NULL
 217   }
 218 };
 219
 220 PCI_CLASS_ENTRY PCISubClass_01[] = {
 221   {
 222     0x00,
 223     L"SCSI controller",
 224     PCIBlankEntry
 225   },
 226   {
 227     0x01,
 228     L"IDE controller",
 229     PCIPIFClass_0101
 230   },
 231   {
 232     0x02,
 233     L"Floppy disk controller",
 234     PCIBlankEntry
 235   },
 236   {
 237     0x03,
 238     L"IPI controller",
 239     PCIBlankEntry
 240   },
 241   {
 242     0x04,
 243     L"RAID controller",
 244     PCIBlankEntry
 245   },
 246   {
 247     0x80,
 248     L"Other mass storage controller",
 249     PCIBlankEntry
 250   },
 251   {
 252     0x00,
 253     NULL,
 254     /* null string ends the list */NULL
 255   }
 256 };
 257
 258 PCI_CLASS_ENTRY PCISubClass_02[] = {
 259   {
 260     0x00,
 261     L"Ethernet controller",
 262     PCIBlankEntry
 263   },
 264   {
 265     0x01,
 266     L"Token ring controller",
 267     PCIBlankEntry
 268   },
 269   {
 270     0x02,
 271     L"FDDI controller",
 272     PCIBlankEntry
 273   },
 274   {
 275     0x03,
 276     L"ATM controller",
 277     PCIBlankEntry
 278   },
 279   {
 280     0x04,
 281     L"ISDN controller",
 282     PCIBlankEntry
 283   },
 284   {
 285     0x80,
 286     L"Other network controller",
 287     PCIBlankEntry
 288   },
 289   {
 290     0x00,
 291     NULL,
 292     /* null string ends the list */NULL
 293   }
 294 };
 295
 296 PCI_CLASS_ENTRY PCISubClass_03[] = {
 297   {
 298     0x00,
 299     L"VGA/8514 controller",
 300     PCIPIFClass_0300
 301   },
 302   {
 303     0x01,
 304     L"XGA controller",
 305     PCIBlankEntry
 306   },
 307   {
 308     0x02,
 309     L"3D controller",
 310     PCIBlankEntry
 311   },
 312   {
 313     0x80,
 314     L"Other display controller",
 315     PCIBlankEntry
 316   },
 317   {
 318     0x00,
 319     NULL,
 320     /* null string ends the list */PCIBlankEntry
 321   }
 322 };
 323
 324 PCI_CLASS_ENTRY PCISubClass_04[] = {
 325   {
 326     0x00,
 327     L"Video device",
 328     PCIBlankEntry
 329   },
 330   {
 331     0x01,
 332     L"Audio device",
 333     PCIBlankEntry
 334   },
 335   {
 336     0x02,
 337     L"Computer Telephony device",
 338     PCIBlankEntry
 339   },
 340   {
 341     0x80,
 342     L"Other multimedia device",
 343     PCIBlankEntry
 344   },
 345   {
 346     0x00,
 347     NULL,
 348     /* null string ends the list */NULL
 349   }
 350 };
 351
 352 PCI_CLASS_ENTRY PCISubClass_05[] = {
 353   {
 354     0x00,
 355     L"RAM memory controller",
 356     PCIBlankEntry
 357   },
 358   {
 359     0x01,
 360     L"Flash memory controller",
 361     PCIBlankEntry
 362   },
 363   {
 364     0x80,
 365     L"Other memory controller",
 366     PCIBlankEntry
 367   },
 368   {
 369     0x00,
 370     NULL,
 371     /* null string ends the list */NULL
 372   }
 373 };
 374
 375 PCI_CLASS_ENTRY PCISubClass_06[] = {
 376   {
 377     0x00,
 378     L"Host/PCI bridge",
 379     PCIBlankEntry
 380   },
 381   {
 382     0x01,
 383     L"PCI/ISA bridge",
 384     PCIBlankEntry
 385   },
 386   {
 387     0x02,
 388     L"PCI/EISA bridge",
 389     PCIBlankEntry
 390   },
 391   {
 392     0x03,
 393     L"PCI/Micro Channel bridge",
 394     PCIBlankEntry
 395   },
 396   {
 397     0x04,
 398     L"PCI/PCI bridge",
 399     PCIPIFClass_0604
 400   },
 401   {
 402     0x05,
 403     L"PCI/PCMCIA bridge",
 404     PCIBlankEntry
 405   },
 406   {
 407     0x06,
 408     L"NuBus bridge",
 409     PCIBlankEntry
 410   },
 411   {
 412     0x07,
 413     L"CardBus bridge",
 414     PCIBlankEntry
 415   },
 416   {
 417     0x08,
 418     L"RACEway bridge",
 419     PCIBlankEntry
 420   },
 421   {
 422     0x80,
 423     L"Other bridge type",
 424     PCIBlankEntry
 425   },
 426   {
 427     0x00,
 428     NULL,
 429     /* null string ends the list */NULL
 430   }
 431 };
 432
 433 PCI_CLASS_ENTRY PCISubClass_07[] = {
 434   {
 435     0x00,
 436     L"Serial controller",
 437     PCIPIFClass_0700
 438   },
 439   {
 440     0x01,
 441     L"Parallel port",
 442     PCIPIFClass_0701
 443   },
 444   {
 445     0x02,
 446     L"Multiport serial controller",
 447     PCIBlankEntry
 448   },
 449   {
 450     0x03,
 451     L"Modem",
 452     PCIPIFClass_0703
 453   },
 454   {
 455     0x80,
 456     L"Other communication device",
 457     PCIBlankEntry
 458   },
 459   {
 460     0x00,
 461     NULL,
 462     /* null string ends the list */NULL
 463   }
 464 };
 465
 466 PCI_CLASS_ENTRY PCISubClass_08[] = {
 467   {
 468     0x00,
 469     L"PIC",
 470     PCIPIFClass_0800
 471   },
 472   {
 473     0x01,
 474     L"DMA controller",
 475     PCIPIFClass_0801
 476   },
 477   {
 478     0x02,
 479     L"System timer",
 480     PCIPIFClass_0802
 481   },
 482   {
 483     0x03,
 484     L"RTC controller",
 485     PCIPIFClass_0803
 486   },
 487   {
 488     0x04,
 489     L"Generic PCI Hot-Plug controller",
 490     PCIBlankEntry
 491   },
 492   {
 493     0x80,
 494     L"Other system peripheral",
 495     PCIBlankEntry
 496   },
 497   {
 498     0x00,
 499     NULL,
 500     /* null string ends the list */NULL
 501   }
 502 };
 503
 504 PCI_CLASS_ENTRY PCISubClass_09[] = {
 505   {
 506     0x00,
 507     L"Keyboard controller",
 508     PCIBlankEntry
 509   },
 510   {
 511     0x01,
 512     L"Digitizer (pen)",
 513     PCIBlankEntry
 514   },
 515   {
 516     0x02,
 517     L"Mouse controller",
 518     PCIBlankEntry
 519   },
 520   {
 521     0x03,
 522     L"Scanner controller",
 523     PCIBlankEntry
 524   },
 525   {
 526     0x04,
 527     L"Gameport controller",
 528     PCIPIFClass_0904
 529   },
 530   {
 531     0x80,
 532     L"Other input controller",
 533     PCIBlankEntry
 534   },
 535   {
 536     0x00,
 537     NULL,
 538     /* null string ends the list */NULL
 539   }
 540 };
 541
 542 PCI_CLASS_ENTRY PCISubClass_0a[] = {
 543   {
 544     0x00,
 545     L"Generic docking station",
 546     PCIBlankEntry
 547   },
 548   {
 549     0x80,
 550     L"Other type of docking station",
 551     PCIBlankEntry
 552   },
 553   {
 554     0x00,
 555     NULL,
 556     /* null string ends the list */NULL
 557   }
 558 };
 559
 560 PCI_CLASS_ENTRY PCISubClass_0b[] = {
 561   {
 562     0x00,
 563     L"386",
 564     PCIBlankEntry
 565   },
 566   {
 567     0x01,
 568     L"486",
 569     PCIBlankEntry
 570   },
 571   {
 572     0x02,
 573     L"Pentium",
 574     PCIBlankEntry
 575   },
 576   {
 577     0x10,
 578     L"Alpha",
 579     PCIBlankEntry
 580   },
 581   {
 582     0x20,
 583     L"PowerPC",
 584     PCIBlankEntry
 585   },
 586   {
 587     0x30,
 588     L"MIPS",
 589     PCIBlankEntry
 590   },
 591   {
 592     0x40,
 593     L"Co-processor",
 594     PCIBlankEntry
 595   },
 596   {
 597     0x80,
 598     L"Other processor",
 599     PCIBlankEntry
 600   },
 601   {
 602     0x00,
 603     NULL,
 604     /* null string ends the list */NULL
 605   }
 606 };
 607
 608 PCI_CLASS_ENTRY PCISubClass_0c[] = {
 609   {
 610     0x00,
 611     L"Firewire(IEEE 1394)",
 612     PCIPIFClass_0c03
 613   },
 614   {
 615     0x01,
 616     L"ACCESS.bus",
 617     PCIBlankEntry
 618   },
 619   {
 620     0x02,
 621     L"SSA",
 622     PCIBlankEntry
 623   },
 624   {
 625     0x03,
 626     L"USB",
 627     PCIPIFClass_0c00
 628   },
 629   {
 630     0x04,
 631     L"Fibre Channel",
 632     PCIBlankEntry
 633   },
 634   {
 635     0x05,
 636     L"System Management Bus",
 637     PCIBlankEntry
 638   },
 639   {
 640     0x80,
 641     L"Other bus type",
 642     PCIBlankEntry
 643   },
 644   {
 645     0x00,
 646     NULL,
 647     /* null string ends the list */NULL
 648   }
 649 };
 650
 651 PCI_CLASS_ENTRY PCISubClass_0d[] = {
 652   {
 653     0x00,
 654     L"iRDA compatible controller",
 655     PCIBlankEntry
 656   },
 657   {
 658     0x01,
 659     L"Consumer IR controller",
 660     PCIBlankEntry
 661   },
 662   {
 663     0x10,
 664     L"RF controller",
 665     PCIBlankEntry
 666   },
 667   {
 668     0x80,
 669     L"Other type of wireless controller",
 670     PCIBlankEntry
 671   },
 672   {
 673     0x00,
 674     NULL,
 675     /* null string ends the list */NULL
 676   }
 677 };
 678
 679 PCI_CLASS_ENTRY PCISubClass_0e[] = {
 680   {
 681     0x00,
 682     L"I2O Architecture",
 683     PCIPIFClass_0e00
 684   },
 685   {
 686     0x00,
 687     NULL,
 688     /* null string ends the list */NULL
 689   }
 690 };
 691
 692 PCI_CLASS_ENTRY PCISubClass_0f[] = {
 693   {
 694     0x00,
 695     L"TV",
 696     PCIBlankEntry
 697   },
 698   {
 699     0x01,
 700     L"Audio",
 701     PCIBlankEntry
 702   },
 703   {
 704     0x02,
 705     L"Voice",
 706     PCIBlankEntry
 707   },
 708   {
 709     0x03,
 710     L"Data",
 711     PCIBlankEntry
 712   },
 713   {
 714     0x00,
 715     NULL,
 716     /* null string ends the list */NULL
 717   }
 718 };
 719
 720 PCI_CLASS_ENTRY PCISubClass_10[] = {
 721   {
 722     0x00,
 723     L"Network & computing Encrypt/Decrypt",
 724     PCIBlankEntry
 725   },
 726   {
 727     0x01,
 728     L"Entertainment Encrypt/Decrypt",
 729     PCIBlankEntry
 730   },
 731   {
 732     0x80,
 733     L"Other Encrypt/Decrypt",
 734     PCIBlankEntry
 735   },
 736   {
 737     0x00,
 738     NULL,
 739     /* null string ends the list */NULL
 740   }
 741 };
 742
 743 PCI_CLASS_ENTRY PCISubClass_11[] = {
 744   {
 745     0x00,
 746     L"DPIO modules",
 747     PCIBlankEntry
 748   },
 749   {
 750     0x80,
 751     L"Other DAQ & SP controllers",
 752     PCIBlankEntry
 753   },
 754   {
 755     0x00,
 756     NULL,
 757     /* null string ends the list */NULL
 758   }
 759 };
 760
 761 //
 762 // Programming Interface entries
 763 //
 764 PCI_CLASS_ENTRY PCIPIFClass_0101[] = {
 765   {
 766     0x00,
 767     L"",
 768     PCIBlankEntry
 769   },
 770   {
 771     0x01,
 772     L"OM-primary",
 773     PCIBlankEntry
 774   },
 775   {
 776     0x02,
 777     L"PI-primary",
 778     PCIBlankEntry
 779   },
 780   {
 781     0x03,
 782     L"OM/PI-primary",
 783     PCIBlankEntry
 784   },
 785   {
 786     0x04,
 787     L"OM-secondary",
 788     PCIBlankEntry
 789   },
 790   {
 791     0x05,
 792     L"OM-primary, OM-secondary",
 793     PCIBlankEntry
 794   },
 795   {
 796     0x06,
 797     L"PI-primary, OM-secondary",
 798     PCIBlankEntry
 799   },
 800   {
 801     0x07,
 802     L"OM/PI-primary, OM-secondary",
 803     PCIBlankEntry
 804   },
 805   {
 806     0x08,
 807     L"OM-secondary",
 808     PCIBlankEntry
 809   },
 810   {
 811     0x09,
 812     L"OM-primary, PI-secondary",
 813     PCIBlankEntry
 814   },
 815   {
 816     0x0a,
 817     L"PI-primary, PI-secondary",
 818     PCIBlankEntry
 819   },
 820   {
 821     0x0b,
 822     L"OM/PI-primary, PI-secondary",
 823     PCIBlankEntry
 824   },
 825   {
 826     0x0c,
 827     L"OM-secondary",
 828     PCIBlankEntry
 829   },
 830   {
 831     0x0d,
 832     L"OM-primary, OM/PI-secondary",
 833     PCIBlankEntry
 834   },
 835   {
 836     0x0e,
 837     L"PI-primary, OM/PI-secondary",
 838     PCIBlankEntry
 839   },
 840   {
 841     0x0f,
 842     L"OM/PI-primary, OM/PI-secondary",
 843     PCIBlankEntry
 844   },
 845   {
 846     0x80,
 847     L"Master",
 848     PCIBlankEntry
 849   },
 850   {
 851     0x81,
 852     L"Master, OM-primary",
 853     PCIBlankEntry
 854   },
 855   {
 856     0x82,
 857     L"Master, PI-primary",
 858     PCIBlankEntry
 859   },
 860   {
 861     0x83,
 862     L"Master, OM/PI-primary",
 863     PCIBlankEntry
 864   },
 865   {
 866     0x84,
 867     L"Master, OM-secondary",
 868     PCIBlankEntry
 869   },
 870   {
 871     0x85,
 872     L"Master, OM-primary, OM-secondary",
 873     PCIBlankEntry
 874   },
 875   {
 876     0x86,
 877     L"Master, PI-primary, OM-secondary",
 878     PCIBlankEntry
 879   },
 880   {
 881     0x87,
 882     L"Master, OM/PI-primary, OM-secondary",
 883     PCIBlankEntry
 884   },
 885   {
 886     0x88,
 887     L"Master, OM-secondary",
 888     PCIBlankEntry
 889   },
 890   {
 891     0x89,
 892     L"Master, OM-primary, PI-secondary",
 893     PCIBlankEntry
 894   },
 895   {
 896     0x8a,
 897     L"Master, PI-primary, PI-secondary",
 898     PCIBlankEntry
 899   },
 900   {
 901     0x8b,
 902     L"Master, OM/PI-primary, PI-secondary",
 903     PCIBlankEntry
 904   },
 905   {
 906     0x8c,
 907     L"Master, OM-secondary",
 908     PCIBlankEntry
 909   },
 910   {
 911     0x8d,
 912     L"Master, OM-primary, OM/PI-secondary",
 913     PCIBlankEntry
 914   },
 915   {
 916     0x8e,
 917     L"Master, PI-primary, OM/PI-secondary",
 918     PCIBlankEntry
 919   },
 920   {
 921     0x8f,
 922     L"Master, OM/PI-primary, OM/PI-secondary",
 923     PCIBlankEntry
 924   },
 925   {
 926     0x00,
 927     NULL,
 928     /* null string ends the list */NULL
 929   }
 930 };
 931
 932 PCI_CLASS_ENTRY PCIPIFClass_0300[] = {
 933   {
 934     0x00,
 935     L"VGA compatible",
 936     PCIBlankEntry
 937   },
 938   {
 939     0x01,
 940     L"8514 compatible",
 941     PCIBlankEntry
 942   },
 943   {
 944     0x00,
 945     NULL,
 946     /* null string ends the list */NULL
 947   }
 948 };
 949
 950 PCI_CLASS_ENTRY PCIPIFClass_0604[] = {
 951   {
 952     0x00,
 953     L"",
 954     PCIBlankEntry
 955   },
 956   {
 957     0x01,
 958     L"Subtractive decode",
 959     PCIBlankEntry
 960   },
 961   {
 962     0x00,
 963     NULL,
 964     /* null string ends the list */NULL
 965   }
 966 };
 967
 968 PCI_CLASS_ENTRY PCIPIFClass_0700[] = {
 969   {
 970     0x00,
 971     L"Generic XT-compatible",
 972     PCIBlankEntry
 973   },
 974   {
 975     0x01,
 976     L"16450-compatible",
 977     PCIBlankEntry
 978   },
 979   {
 980     0x02,
 981     L"16550-compatible",
 982     PCIBlankEntry
 983   },
 984   {
 985     0x03,
 986     L"16650-compatible",
 987     PCIBlankEntry
 988   },
 989   {
 990     0x04,
 991     L"16750-compatible",
 992     PCIBlankEntry
 993   },
 994   {
 995     0x05,
 996     L"16850-compatible",
 997     PCIBlankEntry
 998   },
 999   {
1000     0x06,
1001     L"16950-compatible",
1002     PCIBlankEntry
1003   },
1004   {
1005     0x00,
1006     NULL,
1007     /* null string ends the list */NULL
1008   }
1009 };
1010
1011 PCI_CLASS_ENTRY PCIPIFClass_0701[] = {
1012   {
1013     0x00,
1014     L"",
1015     PCIBlankEntry
1016   },
1017   {
1018     0x01,
1019     L"Bi-directional",
1020     PCIBlankEntry
1021   },
1022   {
1023     0x02,
1024     L"ECP 1.X-compliant",
1025     PCIBlankEntry
1026   },
1027   {
1028     0x03,
1029     L"IEEE 1284",
1030     PCIBlankEntry
1031   },
1032   {
1033     0xfe,
1034     L"IEEE 1284 target (not a controller)",
1035     PCIBlankEntry
1036   },
1037   {
1038     0x00,
1039     NULL,
1040     /* null string ends the list */NULL
1041   }
1042 };
1043
1044 PCI_CLASS_ENTRY PCIPIFClass_0703[] = {
1045   {
1046     0x00,
1047     L"Generic",
1048     PCIBlankEntry
1049   },
1050   {
1051     0x01,
1052     L"Hayes-compatible 16450",
1053     PCIBlankEntry
1054   },
1055   {
1056     0x02,
1057     L"Hayes-compatible 16550",
1058     PCIBlankEntry
1059   },
1060   {
1061     0x03,
1062     L"Hayes-compatible 16650",
1063     PCIBlankEntry
1064   },
1065   {
1066     0x04,
1067     L"Hayes-compatible 16750",
1068     PCIBlankEntry
1069   },
1070   {
1071     0x00,
1072     NULL,
1073     /* null string ends the list */NULL
1074   }
1075 };
1076
1077 PCI_CLASS_ENTRY PCIPIFClass_0800[] = {
1078   {
1079     0x00,
1080     L"Generic 8259",
1081     PCIBlankEntry
1082   },
1083   {
1084     0x01,
1085     L"ISA",
1086     PCIBlankEntry
1087   },
1088   {
1089     0x02,
1090     L"EISA",
1091     PCIBlankEntry
1092   },
1093   {
1094     0x10,
1095     L"IO APIC",
1096     PCIBlankEntry
1097   },
1098   {
1099     0x20,
1100     L"IO(x) APIC interrupt controller",
1101     PCIBlankEntry
1102   },
1103   {
1104     0x00,
1105     NULL,
1106     /* null string ends the list */NULL
1107   }
1108 };
1109
1110 PCI_CLASS_ENTRY PCIPIFClass_0801[] = {
1111   {
1112     0x00,
1113     L"Generic 8237",
1114     PCIBlankEntry
1115   },
1116   {
1117     0x01,
1118     L"ISA",
1119     PCIBlankEntry
1120   },
1121   {
1122     0x02,
1123     L"EISA",
1124     PCIBlankEntry
1125   },
1126   {
1127     0x00,
1128     NULL,
1129     /* null string ends the list */NULL
1130   }
1131 };
1132
1133 PCI_CLASS_ENTRY PCIPIFClass_0802[] = {
1134   {
1135     0x00,
1136     L"Generic 8254",
1137     PCIBlankEntry
1138   },
1139   {
1140     0x01,
1141     L"ISA",
1142     PCIBlankEntry
1143   },
1144   {
1145     0x02,
1146     L"EISA",
1147     PCIBlankEntry
1148   },
1149   {
1150     0x00,
1151     NULL,
1152     /* null string ends the list */NULL
1153   }
1154 };
1155
1156 PCI_CLASS_ENTRY PCIPIFClass_0803[] = {
1157   {
1158     0x00,
1159     L"Generic",
1160     PCIBlankEntry
1161   },
1162   {
1163     0x01,
1164     L"ISA",
1165     PCIBlankEntry
1166   },
1167   {
1168     0x02,
1169     L"EISA",
1170     PCIBlankEntry
1171   },
1172   {
1173     0x00,
1174     NULL,
1175     /* null string ends the list */NULL
1176   }
1177 };
1178
1179 PCI_CLASS_ENTRY PCIPIFClass_0904[] = {
1180   {
1181     0x00,
1182     L"Generic",
1183     PCIBlankEntry
1184   },
1185   {
1186     0x10,
1187     L"",
1188     PCIBlankEntry
1189   },
1190   {
1191     0x00,
1192     NULL,
1193     /* null string ends the list */NULL
1194   }
1195 };
1196
1197 PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {
1198   {
1199     0x00,
1200     L"Universal Host Controller spec",
1201     PCIBlankEntry
1202   },
1203   {
1204     0x10,
1205     L"Open Host Controller spec",
1206     PCIBlankEntry
1207   },
1208   {
1209     0x80,
1210     L"No specific programming interface",
1211     PCIBlankEntry
1212   },
1213   {
1214     0xfe,
1215     L"(Not Host Controller)",
1216     PCIBlankEntry
1217   },
1218   {
1219     0x00,
1220     NULL,
1221     /* null string ends the list */NULL
1222   }
1223 };
1224
1225 PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {
1226   {
1227     0x00,
1228     L"",
1229     PCIBlankEntry
1230   },
1231   {
1232     0x10,
1233     L"Using 1394 OpenHCI spec",
1234     PCIBlankEntry
1235   },
1236   {
1237     0x00,
1238     NULL,
1239     /* null string ends the list */NULL
1240   }
1241 };
1242
1243 PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {
1244   {
1245     0x00,
1246     L"Message FIFO at offset 40h",
1247     PCIBlankEntry
1248   },
1249   {
1250     0x01,
1251     L"",
1252     PCIBlankEntry
1253   },
1254   {
1255     0x00,
1256     NULL,
1257     /* null string ends the list */NULL
1258   }
1259 };
1260
1261 #define EFI_HEX_DISP_SIZE   32
1262 BOOLEAN
1263 PrivateDumpHex (
1264   IN UINTN        Indent,
1265   IN UINTN        Offset,
1266   IN UINTN        DataSize,
1267   IN VOID         *UserData
1268   )
1269 /*++
1270
1271 Routine Description:
1272
1273   Add page break feature to the DumpHex
1274
1275 Arguments:
1276   Indent           - The indent space
1277
1278   Offset           - The offset
1279
1280   DataSize         - The data size
1281
1282   UserData         - The data
1283
1284 Returns:
1285
1286   TRUE             - The dump is broke
1287   FALSE            - The dump is completed
1288
1289 **/
1290 {
1291   UINTN DispSize;
1292   UINT8 *DispData;
1293
1294   DispSize  = EFI_HEX_DISP_SIZE;
1295   DispData  = (UINT8 *) UserData;
1296
1297   while (DataSize!=0) {
1298     if (ShellGetExecutionBreakFlag ()) {
1299       return TRUE;
1300     }
1301
1302     if (DataSize > EFI_HEX_DISP_SIZE) {
1303       DataSize -= EFI_HEX_DISP_SIZE;
1304     } else {
1305       DispSize  = DataSize;
1306       DataSize  = 0;
1307     }
1308
1309     DumpHex (Indent, Offset + DispData - (UINT8 *) UserData, DispSize, DispData);
1310     DispData += DispSize;
1311   }
1312
1313   return FALSE;
1314 }
1315
1316 //
1317 // Implemetations
1318 //
1319 VOID
1320 PciGetClassStrings (
1321   IN      UINT32               ClassCode,
1322   IN OUT  PCI_CLASS_STRINGS    *ClassStrings
1323   )
1324 /*++
1325 Routine Description:
1326
1327   Generates printable Unicode strings that represent PCI device class,
1328   subclass and programmed I/F based on a value passed to the function.
1329
1330 Arguments:
1331
1332   ClassCode      Value representing the PCI "Class Code" register read from a
1333                  PCI device. The encodings are:
1334                      bits 23:16 - Base Class Code
1335                      bits 15:8  - Sub-Class Code
1336                      bits  7:0  - Programming Interface
1337   ClassStrings   Pointer of PCI_CLASS_STRINGS structure, which contains
1338                  printable class strings corresponding to ClassCode. The
1339                  caller must not modify the strings that are pointed by
1340                  the fields in ClassStrings.
1341 Returns:
1342
1343   None
1344 **/
1345 {
1346   INTN            Index;
1347   UINT8           Code;
1348   PCI_CLASS_ENTRY *CurrentClass;
1349
1350   //
1351   // Assume no strings found
1352   //
1353   ClassStrings->BaseClass = L"UNDEFINED";
1354   ClassStrings->SubClass  = L"UNDEFINED";
1355   ClassStrings->PIFClass  = L"UNDEFINED";
1356
1357   CurrentClass = gClassStringList;
1358   Code = (UINT8) (ClassCode >> 16);
1359   Index = 0;
1360
1361   //
1362   // Go through all entries of the base class, until the entry with a matching
1363   // base class code is found. If reaches an entry with a null description
1364   // text, the last entry is met, which means no text for the base class was
1365   // found, so no more action is needed.
1366   //
1367   while (Code != CurrentClass[Index].Code) {
1368     if (NULL == CurrentClass[Index].DescText) {
1369       return ;
1370     }
1371
1372     Index++;
1373   }
1374   //
1375   // A base class was found. Assign description, and check if this class has
1376   // sub-class defined. If sub-class defined, no more action is needed,
1377   // otherwise, continue to find description for the sub-class code.
1378   //
1379   ClassStrings->BaseClass = CurrentClass[Index].DescText;
1380   if (NULL == CurrentClass[Index].LowerLevelClass) {
1381     return ;
1382   }
1383   //
1384   // find Subclass entry
1385   //
1386   CurrentClass  = CurrentClass[Index].LowerLevelClass;
1387   Code          = (UINT8) (ClassCode >> 8);
1388   Index         = 0;
1389
1390   //
1391   // Go through all entries of the sub-class, until the entry with a matching
1392   // sub-class code is found. If reaches an entry with a null description
1393   // text, the last entry is met, which means no text for the sub-class was
1394   // found, so no more action is needed.
1395   //
1396   while (Code != CurrentClass[Index].Code) {
1397     if (NULL == CurrentClass[Index].DescText) {
1398       return ;
1399     }
1400
1401     Index++;
1402   }
1403   //
1404   // A class was found for the sub-class code. Assign description, and check if
1405   // this sub-class has programming interface defined. If no, no more action is
1406   // needed, otherwise, continue to find description for the programming
1407   // interface.
1408   //
1409   ClassStrings->SubClass = CurrentClass[Index].DescText;
1410   if (NULL == CurrentClass[Index].LowerLevelClass) {
1411     return ;
1412   }
1413   //
1414   // Find programming interface entry
1415   //
1416   CurrentClass  = CurrentClass[Index].LowerLevelClass;
1417   Code          = (UINT8) ClassCode;
1418   Index         = 0;
1419
1420   //
1421   // Go through all entries of the I/F entries, until the entry with a
1422   // matching I/F code is found. If reaches an entry with a null description
1423   // text, the last entry is met, which means no text was found, so no more
1424   // action is needed.
1425   //
1426   while (Code != CurrentClass[Index].Code) {
1427     if (NULL == CurrentClass[Index].DescText) {
1428       return ;
1429     }
1430
1431     Index++;
1432   }
1433   //
1434   // A class was found for the I/F code. Assign description, done!
1435   //
1436   ClassStrings->PIFClass = CurrentClass[Index].DescText;
1437   return ;
1438 }
1439
1440 VOID
1441 PciPrintClassCode (
1442   IN      UINT8               *ClassCodePtr,
1443   IN      BOOLEAN             IncludePIF
1444   )
1445 /*++
1446 Routine Description:
1447
1448   Print strings that represent PCI device class, subclass and programmed I/F
1449
1450 Arguments:
1451
1452   ClassCodePtr   Points to the memory which stores register Class Code in PCI
1453                  configuation space.
1454   IncludePIF     If the printed string should include the programming I/F part
1455 Returns:
1456
1457   None
1458 **/
1459 {
1460   UINT32            ClassCode;
1461   PCI_CLASS_STRINGS ClassStrings;
1462   CHAR16            OutputString[PCI_CLASS_STRING_LIMIT + 1];
1463
1464   ClassCode = 0;
1465   ClassCode |= ClassCodePtr[0];
1466   ClassCode |= (ClassCodePtr[1] << 8);
1467   ClassCode |= (ClassCodePtr[2] << 16);
1468
1469   //
1470   // Get name from class code
1471   //
1472   PciGetClassStrings (ClassCode, &ClassStrings);
1473
1474   if (IncludePIF) {
1475     //
1476     // Only print base class and sub class name
1477     //
1478     ShellPrintEx(-1,-1, L"%s - %s - %s",
1479       ClassStrings.BaseClass,
1480       ClassStrings.SubClass,
1481       ClassStrings.PIFClass
1482      );
1483
1484   } else {
1485     //
1486     // Print base class, sub class, and programming inferface name
1487     //
1488     UnicodeSPrint (
1489       OutputString,
1490       PCI_CLASS_STRING_LIMIT * sizeof (CHAR16),
1491       L"%s - %s",
1492       ClassStrings.BaseClass,
1493       ClassStrings.SubClass
1494      );
1495
1496     OutputString[PCI_CLASS_STRING_LIMIT] = 0;
1497     ShellPrintEx(-1,-1, L"%s", OutputString);
1498   }
1499 }
1500
1501 EFI_STATUS
1502 PciDump (
1503   IN EFI_HANDLE                             ImageHandle,
1504   IN EFI_SYSTEM_TABLE                       *SystemTable
1505   );
1506
1507 EFI_STATUS
1508 PciFindProtocolInterface (
1509   IN  EFI_HANDLE                            *HandleBuf,
1510   IN  UINTN                                 HandleCount,
1511   IN  UINT16                                Segment,
1512   IN  UINT16                                Bus,
1513   OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       **IoDev
1514   );
1515
1516 EFI_STATUS
1517 PciGetProtocolAndResource (
1518   IN  EFI_HANDLE                            Handle,
1519   OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       **IoDev,
1520   OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     **Descriptors
1521   );
1522
1523 EFI_STATUS
1524 PciGetNextBusRange (
1525   IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  **Descriptors,
1526   OUT    UINT16                             *MinBus,
1527   OUT    UINT16                             *MaxBus,
1528   OUT    BOOLEAN                            *IsEnd
1529   );
1530
1531 EFI_STATUS
1532 PciExplainData (
1533   IN PCI_CONFIG_SPACE                       *ConfigSpace,
1534   IN UINT64                                 Address,
1535   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *IoDev
1536   );
1537
1538 EFI_STATUS
1539 PciExplainDeviceData (
1540   IN PCI_DEVICE_HEADER                      *Device,
1541   IN UINT64                                 Address,
1542   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *IoDev
1543   );
1544
1545 EFI_STATUS
1546 PciExplainBridgeData (
1547   IN PCI_BRIDGE_HEADER                      *Bridge,
1548   IN UINT64                                 Address,
1549   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *IoDev
1550   );
1551
1552 EFI_STATUS
1553 PciExplainBar (
1554   IN UINT32                                 *Bar,
1555   IN UINT16                                 *Command,
1556   IN UINT64                                 Address,
1557   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *IoDev,
1558   IN OUT UINTN                              *Index
1559   );
1560
1561 EFI_STATUS
1562 PciExplainCardBusData (
1563   IN PCI_CARDBUS_HEADER                     *CardBus,
1564   IN UINT64                                 Address,
1565   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *IoDev
1566   );
1567
1568 EFI_STATUS
1569 PciExplainStatus (
1570   IN UINT16                                 *Status,
1571   IN BOOLEAN                                MainStatus,
1572   IN PCI_HEADER_TYPE                        HeaderType
1573   );
1574
1575 EFI_STATUS
1576 PciExplainCommand (
1577   IN UINT16                                 *Command
1578   );
1579
1580 EFI_STATUS
1581 PciExplainBridgeControl (
1582   IN UINT16                                 *BridgeControl,
1583   IN PCI_HEADER_TYPE                        HeaderType
1584   );
1585
1586 EFI_STATUS
1587 PciExplainCapabilityStruct (
1588   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         *IoDev,
1589   IN UINT64                                   Address,
1590   IN  UINT8                                   CapPtr
1591   );
1592
1593 EFI_STATUS
1594 PciExplainPciExpress (
1595   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         *IoDev,
1596   IN  UINT64                                  Address,
1597   IN  UINT8                                   CapabilityPtr
1598   );
1599
1600 EFI_STATUS
1601 ExplainPcieCapReg (
1602   IN PCIE_CAP_STURCTURE *PciExpressCap
1603 );
1604
1605 EFI_STATUS
1606 ExplainPcieDeviceCap (
1607   IN PCIE_CAP_STURCTURE *PciExpressCap
1608 );
1609
1610 EFI_STATUS
1611 ExplainPcieDeviceControl (
1612   IN PCIE_CAP_STURCTURE *PciExpressCap
1613 );
1614
1615 EFI_STATUS
1616 ExplainPcieDeviceStatus (
1617   IN PCIE_CAP_STURCTURE *PciExpressCap
1618 );
1619
1620 EFI_STATUS
1621 ExplainPcieLinkCap (
1622   IN PCIE_CAP_STURCTURE *PciExpressCap
1623 );
1624
1625 EFI_STATUS
1626 ExplainPcieLinkControl (
1627   IN PCIE_CAP_STURCTURE *PciExpressCap
1628 );
1629
1630 EFI_STATUS
1631 ExplainPcieLinkStatus (
1632   IN PCIE_CAP_STURCTURE *PciExpressCap
1633 );
1634
1635 EFI_STATUS
1636 ExplainPcieSlotCap (
1637   IN PCIE_CAP_STURCTURE *PciExpressCap
1638 );
1639
1640 EFI_STATUS
1641 ExplainPcieSlotControl (
1642   IN PCIE_CAP_STURCTURE *PciExpressCap
1643 );
1644
1645 EFI_STATUS
1646 ExplainPcieSlotStatus (
1647   IN PCIE_CAP_STURCTURE *PciExpressCap
1648 );
1649
1650 EFI_STATUS
1651 ExplainPcieRootControl (
1652   IN PCIE_CAP_STURCTURE *PciExpressCap
1653 );
1654
1655 EFI_STATUS
1656 ExplainPcieRootCap (
1657   IN PCIE_CAP_STURCTURE *PciExpressCap
1658 );
1659
1660 EFI_STATUS
1661 ExplainPcieRootStatus (
1662   IN PCIE_CAP_STURCTURE *PciExpressCap
1663 );
1664
1665 typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STURCTURE *PciExpressCap);
1666
1667 typedef enum {
1668   FieldWidthUINT8,
1669   FieldWidthUINT16,
1670   FieldWidthUINT32
1671 } PCIE_CAPREG_FIELD_WIDTH;
1672
1673 typedef enum {
1674   PcieExplainTypeCommon,
1675   PcieExplainTypeDevice,
1676   PcieExplainTypeLink,
1677   PcieExplainTypeSlot,
1678   PcieExplainTypeRoot,
1679   PcieExplainTypeMax
1680 } PCIE_EXPLAIN_TYPE;
1681
1682 typedef struct
1683 {
1684   UINT16                  Token;
1685   UINTN                   Offset;
1686   PCIE_CAPREG_FIELD_WIDTH Width;
1687   PCIE_EXPLAIN_FUNCTION   Func;
1688   PCIE_EXPLAIN_TYPE       Type;
1689 } PCIE_EXPLAIN_STRUCT;
1690
1691 PCIE_EXPLAIN_STRUCT PcieExplainList[] = {
1692   {
1693     STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),
1694     0x00,
1695     FieldWidthUINT8,
1696     NULL,
1697     PcieExplainTypeCommon
1698   },
1699   {
1700     STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR),
1701     0x01,
1702     FieldWidthUINT8,
1703     NULL,
1704     PcieExplainTypeCommon
1705   },
1706   {
1707     STRING_TOKEN (STR_PCIEX_CAP_REGISTER),
1708     0x02,
1709     FieldWidthUINT16,
1710     ExplainPcieCapReg,
1711     PcieExplainTypeCommon
1712   },
1713   {
1714     STRING_TOKEN (STR_PCIEX_DEVICE_CAP),
1715     0x04,
1716     FieldWidthUINT32,
1717     ExplainPcieDeviceCap,
1718     PcieExplainTypeDevice
1719   },
1720   {
1721     STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL),
1722     0x08,
1723     FieldWidthUINT16,
1724     ExplainPcieDeviceControl,
1725     PcieExplainTypeDevice
1726   },
1727   {
1728     STRING_TOKEN (STR_PCIEX_DEVICE_STATUS),
1729     0x0a,
1730     FieldWidthUINT16,
1731     ExplainPcieDeviceStatus,
1732     PcieExplainTypeDevice
1733   },
1734   {
1735     STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES),
1736     0x0c,
1737     FieldWidthUINT32,
1738     ExplainPcieLinkCap,
1739     PcieExplainTypeLink
1740   },
1741   {
1742     STRING_TOKEN (STR_PCIEX_LINK_CONTROL),
1743     0x10,
1744     FieldWidthUINT16,
1745     ExplainPcieLinkControl,
1746     PcieExplainTypeLink
1747   },
1748   {
1749     STRING_TOKEN (STR_PCIEX_LINK_STATUS),
1750     0x12,
1751     FieldWidthUINT16,
1752     ExplainPcieLinkStatus,
1753     PcieExplainTypeLink
1754   },
1755   {
1756     STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES),
1757     0x14,
1758     FieldWidthUINT32,
1759     ExplainPcieSlotCap,
1760     PcieExplainTypeSlot
1761   },
1762   {
1763     STRING_TOKEN (STR_PCIEX_SLOT_CONTROL),
1764     0x18,
1765     FieldWidthUINT16,
1766     ExplainPcieSlotControl,
1767     PcieExplainTypeSlot
1768   },
1769   {
1770     STRING_TOKEN (STR_PCIEX_SLOT_STATUS),
1771     0x1a,
1772     FieldWidthUINT16,
1773     ExplainPcieSlotStatus,
1774     PcieExplainTypeSlot
1775   },
1776   {
1777     STRING_TOKEN (STR_PCIEX_ROOT_CONTROL),
1778     0x1c,
1779     FieldWidthUINT16,
1780     ExplainPcieRootControl,
1781     PcieExplainTypeRoot
1782   },
1783   {
1784     STRING_TOKEN (STR_PCIEX_RSVDP),
1785     0x1e,
1786     FieldWidthUINT16,
1787     ExplainPcieRootCap,
1788     PcieExplainTypeRoot
1789   },
1790   {
1791     STRING_TOKEN (STR_PCIEX_ROOT_STATUS),
1792     0x20,
1793     FieldWidthUINT32,
1794     ExplainPcieRootStatus,
1795     PcieExplainTypeRoot
1796   },
1797   {
1798     0,
1799     0,
1800     (PCIE_CAPREG_FIELD_WIDTH)0,
1801     NULL,
1802     PcieExplainTypeMax
1803   }
1804 };
1805
1806 //
1807 // Global Variables
1808 //
1809 PCI_CONFIG_SPACE  *mConfigSpace = NULL;
1810 STATIC CONST SHELL_PARAM_ITEM ParamList[] = {
1811   {L"-s", TypeValue},
1812   {L"-i", TypeFlag},
1813   {NULL, TypeMax}
1814   };
1815
1816 CHAR16 *DevicePortTypeTable[] = {
1817   L"PCI Express Endpoint",
1818   L"Legacy PCI Express Endpoint",
1819   L"Unknown Type",
1820   L"Unknonw Type",
1821   L"Root Port of PCI Express Root Complex",
1822   L"Upstream Port of PCI Express Switch",
1823   L"Downstream Port of PCI Express Switch",
1824   L"PCI Express to PCI/PCI-X Bridge",
1825   L"PCI/PCI-X to PCI Express Bridge",
1826   L"Root Complex Integrated Endpoint",
1827   L"Root Complex Event Collector"
1828 };
1829
1830 CHAR16 *L0sLatencyStrTable[] = {
1831   L"Less than 64ns",
1832   L"64ns to less than 128ns",
1833   L"128ns to less than 256ns",
1834   L"256ns to less than 512ns",
1835   L"512ns to less than 1us",
1836   L"1us to less than 2us",
1837   L"2us-4us",
1838   L"More than 4us"
1839 };
1840
1841 CHAR16 *L1LatencyStrTable[] = {
1842   L"Less than 1us",
1843   L"1us to less than 2us",
1844   L"2us to less than 4us",
1845   L"4us to less than 8us",
1846   L"8us to less than 16us",
1847   L"16us to less than 32us",
1848   L"32us-64us",
1849   L"More than 64us"
1850 };
1851
1852 CHAR16 *ASPMCtrlStrTable[] = {
1853   L"Disabled",
1854   L"L0s Entry Enabled",
1855   L"L1 Entry Enabled",
1856   L"L0s and L1 Entry Enabled"
1857 };
1858
1859 CHAR16 *SlotPwrLmtScaleTable[] = {
1860   L"1.0x",
1861   L"0.1x",
1862   L"0.01x",
1863   L"0.001x"
1864 };
1865
1866 CHAR16 *IndicatorTable[] = {
1867   L"Reserved",
1868   L"On",
1869   L"Blink",
1870   L"Off"
1871 };
1872
1873
1874 SHELL_STATUS
1875 EFIAPI
1876 ShellCommandRunPci (
1877   IN EFI_HANDLE        ImageHandle,
1878   IN EFI_SYSTEM_TABLE  *SystemTable
1879   )
1880 {
1881   UINT16                            Segment;
1882   UINT16                            Bus;
1883   UINT16                            Device;
1884   UINT16                            Func;
1885   UINT64                            Address;
1886   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL   *IoDev;
1887   EFI_STATUS                        Status;
1888   PCI_COMMON_HEADER                 PciHeader;
1889   PCI_CONFIG_SPACE                  ConfigSpace;
1890   UINTN                             ScreenCount;
1891   UINTN                             TempColumn;
1892   UINTN                             ScreenSize;
1893   BOOLEAN                           ExplainData;
1894   UINTN                             Index;
1895   UINTN                             SizeOfHeader;
1896   BOOLEAN                           PrintTitle;
1897   UINTN                             HandleBufSize;
1898   EFI_HANDLE                        *HandleBuf;
1899   UINTN                             HandleCount;
1900   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
1901   UINT16                            MinBus;
1902   UINT16                            MaxBus;
1903   BOOLEAN                           IsEnd;
1904   LIST_ENTRY                        *Package;
1905   CHAR16                            *ProblemParam;
1906   SHELL_STATUS                      ShellStatus;
1907   UINTN                             Size;
1908   CONST CHAR16                      *Temp;
1909
1910   ShellStatus         = SHELL_SUCCESS;
1911   Status              = EFI_SUCCESS;
1912   Address             = 0;
1913   Size                = 0;
1914   IoDev               = NULL;
1915   HandleBuf           = NULL;
1916   Package             = NULL;
1917
1918   //
1919   // initialize the shell lib (we must be in non-auto-init...)
1920   //
1921   Status = ShellInitialize();
1922   ASSERT_EFI_ERROR(Status);
1923
1924   Status = CommandInit();
1925   ASSERT_EFI_ERROR(Status);
1926
1927   //
1928   // parse the command line
1929   //
1930   Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);
1931   if (EFI_ERROR(Status)) {
1932     if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {
1933       ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, ProblemParam);
1934       FreePool(ProblemParam);
1935       ShellStatus = SHELL_INVALID_PARAMETER;
1936     } else {
1937       ASSERT(FALSE);
1938     }
1939   } else {
1940
1941     if (ShellCommandLineGetCount(Package) == 2) {
1942       ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);
1943       ShellStatus = SHELL_INVALID_PARAMETER;
1944       goto Done;
1945     }
1946
1947     if (ShellCommandLineGetCount(Package) > 4) {
1948       ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);
1949       ShellStatus = SHELL_INVALID_PARAMETER;
1950       goto Done;
1951     }
1952     if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {
1953       ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"-s");
1954       ShellStatus = SHELL_INVALID_PARAMETER;
1955       goto Done;
1956     }
1957     //
1958     // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and
1959     // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough
1960     // space for handles and call it again.
1961     //
1962     HandleBufSize = sizeof (EFI_HANDLE);
1963     HandleBuf     = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);
1964     if (HandleBuf == NULL) {
1965       ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);
1966       ShellStatus = SHELL_OUT_OF_RESOURCES;
1967       goto Done;
1968     }
1969
1970     Status = gBS->LocateHandle (
1971                   ByProtocol,
1972                   &gEfiPciRootBridgeIoProtocolGuid,
1973                   NULL,
1974                   &HandleBufSize,
1975                   HandleBuf
1976                  );
1977
1978     if (Status == EFI_BUFFER_TOO_SMALL) {
1979       HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);
1980       if (HandleBuf == NULL) {
1981         ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);
1982         ShellStatus = SHELL_OUT_OF_RESOURCES;
1983         goto Done;
1984       }
1985
1986       Status = gBS->LocateHandle (
1987                     ByProtocol,
1988                     &gEfiPciRootBridgeIoProtocolGuid,
1989                     NULL,
1990                     &HandleBufSize,
1991                     HandleBuf
1992                    );
1993     }
1994
1995     if (EFI_ERROR (Status)) {
1996       ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle);
1997       ShellStatus = SHELL_NOT_FOUND;
1998       goto Done;
1999     }
2000
2001     HandleCount = HandleBufSize / sizeof (EFI_HANDLE);
2002     //
2003     // Argument Count == 1(no other argument): enumerate all pci functions
2004     //
2005     if (ShellCommandLineGetCount(Package) == 1) {
2006       gST->ConOut->QueryMode (
2007                     gST->ConOut,
2008                     gST->ConOut->Mode->Mode,
2009                     &TempColumn,
2010                     &ScreenSize
2011                    );
2012
2013       ScreenCount = 0;
2014       ScreenSize -= 4;
2015       if ((ScreenSize & 1) == 1) {
2016         ScreenSize -= 1;
2017       }
2018
2019       PrintTitle = TRUE;
2020
2021       //
2022       // For each handle, which decides a segment and a bus number range,
2023       // enumerate all devices on it.
2024       //
2025       for (Index = 0; Index < HandleCount; Index++) {
2026         Status = PciGetProtocolAndResource (
2027                   HandleBuf[Index],
2028                   &IoDev,
2029                   &Descriptors
2030                  );
2031         if (EFI_ERROR (Status)) {
2032           ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, Status);
2033           ShellStatus = SHELL_NOT_FOUND;
2034           goto Done;
2035         }
2036         //
2037         // No document say it's impossible for a RootBridgeIo protocol handle
2038         // to have more than one address space descriptors, so find out every
2039         // bus range and for each of them do device enumeration.
2040         //
2041         while (TRUE) {
2042           Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);
2043
2044           if (EFI_ERROR (Status)) {
2045             ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, Status);
2046             ShellStatus = SHELL_NOT_FOUND;
2047             goto Done;
2048           }
2049
2050           if (IsEnd) {
2051             break;
2052           }
2053
2054           for (Bus = MinBus; Bus <= MaxBus; Bus++) {
2055             //
2056             // For each devices, enumerate all functions it contains
2057             //
2058             for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
2059               //
2060               // For each function, read its configuration space and print summary
2061               //
2062               for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
2063                 if (ShellGetExecutionBreakFlag ()) {
2064                   ShellStatus = SHELL_ABORTED;
2065                   goto Done;
2066                 }
2067                 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);
2068                 IoDev->Pci.Read (
2069                             IoDev,
2070                             EfiPciWidthUint16,
2071                             Address,
2072                             1,
2073                             &PciHeader.VendorId
2074                            );
2075
2076                 //
2077                 // If VendorId = 0xffff, there does not exist a device at this
2078                 // location. For each device, if there is any function on it,
2079                 // there must be 1 function at Function 0. So if Func = 0, there
2080                 // will be no more functions in the same device, so we can break
2081                 // loop to deal with the next device.
2082                 //
2083                 if (PciHeader.VendorId == 0xffff && Func == 0) {
2084                   break;
2085                 }
2086
2087                 if (PciHeader.VendorId != 0xffff) {
2088
2089                   if (PrintTitle) {
2090                     ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);
2091                     PrintTitle = FALSE;
2092                   }
2093
2094                   IoDev->Pci.Read (
2095                               IoDev,
2096                               EfiPciWidthUint32,
2097                               Address,
2098                               sizeof (PciHeader) / sizeof (UINT32),
2099                               &PciHeader
2100                              );
2101
2102                   ShellPrintHiiEx(
2103                     -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P1), gShellDebug1HiiHandle,
2104                     IoDev->SegmentNumber,
2105                     Bus,
2106                     Device,
2107                     Func
2108                    );
2109
2110                   PciPrintClassCode (PciHeader.ClassCode, FALSE);
2111                   ShellPrintHiiEx(
2112                     -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P2), gShellDebug1HiiHandle,
2113                     PciHeader.VendorId,
2114                     PciHeader.DeviceId,
2115                     PciHeader.ClassCode[0]
2116                    );
2117
2118                   ScreenCount += 2;
2119                   if (ScreenCount >= ScreenSize && ScreenSize != 0) {
2120                     //
2121                     // If ScreenSize == 0 we have the console redirected so don't
2122                     //  block updates
2123                     //
2124                     ScreenCount = 0;
2125                   }
2126                   //
2127                   // If this is not a multi-function device, we can leave the loop
2128                   // to deal with the next device.
2129                   //
2130                   if (Func == 0 && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {
2131                     break;
2132                   }
2133                 }
2134               }
2135             }
2136           }
2137           //
2138           // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,
2139           // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all
2140           // devices on all bus, we can leave loop.
2141           //
2142           if (Descriptors == NULL) {
2143             break;
2144           }
2145         }
2146       }
2147
2148       Status = EFI_SUCCESS;
2149       goto Done;
2150     }
2151
2152     ExplainData                   = FALSE;
2153     Segment                       = 0;
2154     Bus                           = 0;
2155     Device                        = 0;
2156     Func                          = 0;
2157     if (ShellCommandLineGetFlag(Package, L"-i")) {
2158       ExplainData = TRUE;
2159     }
2160
2161     Temp = ShellCommandLineGetValue(Package, L"-s");
2162     if (Temp != NULL) {
2163       Segment = (UINT16) ShellStrToUintn (Temp);
2164     }
2165
2166     //
2167     // The first Argument(except "-i") is assumed to be Bus number, second
2168     // to be Device number, and third to be Func number.
2169     //
2170     Temp = ShellCommandLineGetRawValue(Package, 1);
2171     if (Temp != NULL) {
2172       Bus = (UINT16)ShellStrToUintn(Temp);
2173       if (Bus > MAX_BUS_NUMBER) {
2174         ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);
2175         ShellStatus = SHELL_INVALID_PARAMETER;
2176         goto Done;
2177       }
2178     }
2179     Temp = ShellCommandLineGetRawValue(Package, 2);
2180     if (Temp != NULL) {
2181       Device = (UINT16) ShellStrToUintn(Temp);
2182       if (Device > MAX_DEVICE_NUMBER){
2183         ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);
2184         ShellStatus = SHELL_INVALID_PARAMETER;
2185         goto Done;
2186       }
2187     }
2188
2189     Temp = ShellCommandLineGetRawValue(Package, 3);
2190     if (Temp != NULL) {
2191       Func = (UINT16) ShellStrToUintn(Temp);
2192       if (Func > MAX_FUNCTION_NUMBER){
2193         ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);
2194         ShellStatus = SHELL_INVALID_PARAMETER;
2195         goto Done;
2196       }
2197     }
2198
2199     //
2200     // Find the protocol interface who's in charge of current segment, and its
2201     // bus range covers the current bus
2202     //
2203     Status = PciFindProtocolInterface (
2204               HandleBuf,
2205               HandleCount,
2206               Segment,
2207               Bus,
2208               &IoDev
2209              );
2210
2211     if (EFI_ERROR (Status)) {
2212       ShellPrintHiiEx(
2213         -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,
2214         gShellDebug1HiiHandle,
2215         Segment,
2216         Bus
2217        );
2218       ShellStatus = SHELL_NOT_FOUND;
2219       goto Done;
2220     }
2221
2222     Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);
2223     Status = IoDev->Pci.Read (
2224                           IoDev,
2225                           EfiPciWidthUint8,
2226                           Address,
2227                           sizeof (ConfigSpace),
2228                           &ConfigSpace
2229                          );
2230
2231     if (EFI_ERROR (Status)) {
2232       ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, Status);
2233       ShellStatus = SHELL_ACCESS_DENIED;
2234       goto Done;
2235     }
2236
2237     mConfigSpace = &ConfigSpace;
2238     ShellPrintHiiEx(
2239       -1,
2240       -1,
2241       NULL,
2242       STRING_TOKEN (STR_PCI_INFO),
2243       gShellDebug1HiiHandle,
2244       Segment,
2245       Bus,
2246       Device,
2247       Func,
2248       Segment,
2249       Bus,
2250       Device,
2251       Func
2252      );
2253
2254     //
2255     // Dump standard header of configuration space
2256     //
2257     SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);
2258
2259     PrivateDumpHex (2, 0, SizeOfHeader, &ConfigSpace);
2260     ShellPrintEx(-1,-1, L"\r\n");
2261
2262     //
2263     // Dump device dependent Part of configuration space
2264     //
2265     PrivateDumpHex (
2266       2,
2267       SizeOfHeader,
2268       sizeof (ConfigSpace) - SizeOfHeader,
2269       ConfigSpace.Data
2270      );
2271
2272     //
2273     // If "-i" appears in command line, interpret data in configuration space
2274     //
2275     if (ExplainData) {
2276       Status = PciExplainData (&ConfigSpace, Address, IoDev);
2277     }
2278   }
2279 Done:
2280   if (HandleBuf != NULL) {
2281     FreePool (HandleBuf);
2282   }
2283   if (Package != NULL) {
2284     ShellCommandLineFreeVarList (Package);
2285   }
2286   mConfigSpace = NULL;
2287   return ShellStatus;
2288 }
2289
2290 EFI_STATUS
2291 PciFindProtocolInterface (
2292   IN  EFI_HANDLE                            *HandleBuf,
2293   IN  UINTN                                 HandleCount,
2294   IN  UINT16                                Segment,
2295   IN  UINT16                                Bus,
2296   OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       **IoDev
2297   )
2298 /*++
2299
2300 Routine Description:
2301
2302   This function finds out the protocol which is in charge of the given
2303   segment, and its bus range covers the current bus number. It lookes
2304   each instances of RootBridgeIoProtocol handle, until the one meets the
2305   criteria is found.
2306
2307 Arguments:
2308
2309   HandleBuf       Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles
2310   HandleCount     Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles
2311   Segment         Segment number of device we are dealing with
2312   Bus             Bus number of device we are dealing with
2313   IoDev           Handle used to access configuration space of PCI device
2314
2315 Returns:
2316
2317   EFI_SUCCESS           - The command completed successfully
2318   EFI_INVALID_PARAMETER - Invalid parameter
2319
2320 **/
2321 {
2322   UINTN                             Index;
2323   EFI_STATUS                        Status;
2324   BOOLEAN                           FoundInterface;
2325   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
2326   UINT16                            MinBus;
2327   UINT16                            MaxBus;
2328   BOOLEAN                           IsEnd;
2329
2330   FoundInterface = FALSE;
2331   //
2332   // Go through all handles, until the one meets the criteria is found
2333   //
2334   for (Index = 0; Index < HandleCount; Index++) {
2335     Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);
2336     if (EFI_ERROR (Status)) {
2337       return Status;
2338     }
2339     //
2340     // When Descriptors == NULL, the Configuration() is not implemented,
2341     // so we only check the Segment number
2342     //
2343     if (Descriptors == NULL && Segment == (*IoDev)->SegmentNumber) {
2344       return EFI_SUCCESS;
2345     }
2346
2347     if ((*IoDev)->SegmentNumber != Segment) {
2348       continue;
2349     }
2350
2351     while (TRUE) {
2352       Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);
2353       if (EFI_ERROR (Status)) {
2354         return Status;
2355       }
2356
2357       if (IsEnd) {
2358         break;
2359       }
2360
2361       if (MinBus <= Bus && MaxBus >= Bus) {
2362         FoundInterface = TRUE;
2363         break;
2364       }
2365     }
2366   }
2367
2368   if (FoundInterface) {
2369     return EFI_SUCCESS;
2370   } else {
2371     return EFI_INVALID_PARAMETER;
2372   }
2373 }
2374
2375 EFI_STATUS
2376 PciGetProtocolAndResource (
2377   IN  EFI_HANDLE                            Handle,
2378   OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       **IoDev,
2379   OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     **Descriptors
2380   )
2381 /*++
2382
2383 Routine Description:
2384
2385   This function gets the protocol interface from the given handle, and
2386   obtains its address space descriptors.
2387
2388 Arguments:
2389
2390   Handle          The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle
2391   IoDev           Handle used to access configuration space of PCI device
2392   Descriptors     Points to the address space descriptors
2393
2394 Returns:
2395
2396   EFI_SUCCESS     The command completed successfully
2397
2398 **/
2399 {
2400   EFI_STATUS  Status;
2401
2402   //
2403   // Get inferface from protocol
2404   //
2405   Status = gBS->HandleProtocol (
2406                 Handle,
2407                 &gEfiPciRootBridgeIoProtocolGuid,
2408                 (VOID**)IoDev
2409                );
2410
2411   if (EFI_ERROR (Status)) {
2412     return Status;
2413   }
2414   //
2415   // Call Configuration() to get address space descriptors
2416   //
2417   Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);
2418   if (Status == EFI_UNSUPPORTED) {
2419     *Descriptors = NULL;
2420     return EFI_SUCCESS;
2421
2422   } else {
2423     return Status;
2424   }
2425 }
2426
2427 EFI_STATUS
2428 PciGetNextBusRange (
2429   IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  **Descriptors,
2430   OUT    UINT16                             *MinBus,
2431   OUT    UINT16                             *MaxBus,
2432   OUT    BOOLEAN                            *IsEnd
2433   )
2434 /*++
2435
2436 Routine Description:
2437
2438   This function get the next bus range of given address space descriptors.
2439   It also moves the pointer backward a node, to get prepared to be called
2440   again.
2441
2442 Arguments:
2443
2444   Descriptors     points to current position of a serial of address space
2445                   descriptors
2446   MinBus          The lower range of bus number
2447   ManBus          The upper range of bus number
2448   IsEnd           Meet end of the serial of descriptors
2449
2450 Returns:
2451
2452   EFI_SUCCESS     The command completed successfully
2453
2454 **/
2455 {
2456   *IsEnd = FALSE;
2457
2458   //
2459   // When *Descriptors is NULL, Configuration() is not implemented, so assume
2460   // range is 0~PCI_MAX_BUS
2461   //
2462   if ((*Descriptors) == NULL) {
2463     *MinBus = 0;
2464     *MaxBus = PCI_MAX_BUS;
2465     return EFI_SUCCESS;
2466   }
2467   //
2468   // *Descriptors points to one or more address space descriptors, which
2469   // ends with a end tagged descriptor. Examine each of the descriptors,
2470   // if a bus typed one is found and its bus range covers bus, this handle
2471   // is the handle we are looking for.
2472   //
2473
2474   while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {
2475     if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {
2476       *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;
2477       *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;
2478       (*Descriptors)++;
2479       return (EFI_SUCCESS);
2480     }
2481
2482     (*Descriptors)++;
2483   }
2484
2485   if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {
2486     *IsEnd = TRUE;
2487   }
2488
2489   return EFI_SUCCESS;
2490 }
2491
2492 EFI_STATUS
2493 PciExplainData (
2494   IN PCI_CONFIG_SPACE                       *ConfigSpace,
2495   IN UINT64                                 Address,
2496   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *IoDev
2497   )
2498 /*++
2499
2500 Routine Description:
2501
2502   Explain the data in PCI configuration space. The part which is common for
2503   PCI device and bridge is interpreted in this function. It calls other
2504   functions to interpret data unique for device or bridge.
2505
2506 Arguments:
2507
2508   ConfigSpace     Data in PCI configuration space
2509   Address         Address used to access configuration space of this PCI device
2510   IoDev           Handle used to access configuration space of PCI device
2511
2512 Returns:
2513
2514   EFI_SUCCESS     The command completed successfully
2515
2516 **/
2517 {
2518   PCI_COMMON_HEADER *Common;
2519   PCI_HEADER_TYPE   HeaderType;
2520   EFI_STATUS        Status;
2521   UINT8             CapPtr;
2522
2523   Common = &(ConfigSpace->Common);
2524
2525   Print (L"\n");
2526
2527   //
2528   // Print Vendor Id and Device Id
2529   //
2530   ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_VID_DID), gShellDebug1HiiHandle,
2531     INDEX_OF (&(Common->VendorId)),
2532     Common->VendorId,
2533     INDEX_OF (&(Common->DeviceId)),
2534     Common->DeviceId
2535    );
2536
2537   //
2538   // Print register Command
2539   //
2540   PciExplainCommand (&(Common->Command));
2541
2542   //
2543   // Print register Status
2544   //
2545   PciExplainStatus (&(Common->Status), TRUE, PciUndefined);
2546
2547   //
2548   // Print register Revision ID
2549   //
2550   ShellPrintEx(-1, -1, L"/r/n");
2551   ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,
2552     INDEX_OF (&(Common->RevisionId)),
2553     Common->RevisionId
2554    );
2555
2556   //
2557   // Print register BIST
2558   //
2559   ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->BIST)));
2560   if ((Common->BIST & PCI_BIT_7) != 0) {
2561     ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->BIST);
2562   } else {
2563     ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);
2564   }
2565   //
2566   // Print register Cache Line Size
2567   //
2568   ShellPrintHiiEx(-1, -1, NULL,
2569     STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),
2570     gShellDebug1HiiHandle,
2571     INDEX_OF (&(Common->CacheLineSize)),
2572     Common->CacheLineSize
2573    );
2574
2575   //
2576   // Print register Latency Timer
2577   //
2578   ShellPrintHiiEx(-1, -1, NULL,
2579     STRING_TOKEN (STR_PCI2_LATENCY_TIMER),
2580     gShellDebug1HiiHandle,
2581     INDEX_OF (&(Common->PrimaryLatencyTimer)),
2582     Common->PrimaryLatencyTimer
2583    );
2584
2585   //
2586   // Print register Header Type
2587   //
2588   ShellPrintHiiEx(-1, -1, NULL,
2589     STRING_TOKEN (STR_PCI2_HEADER_TYPE),
2590     gShellDebug1HiiHandle,
2591     INDEX_OF (&(Common->HeaderType)),
2592     Common->HeaderType
2593    );
2594
2595   if ((Common->HeaderType & PCI_BIT_7) != 0) {
2596     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);
2597
2598   } else {
2599     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);
2600   }
2601
2602   HeaderType = (PCI_HEADER_TYPE)(UINT8) (Common->HeaderType & 0x7f);
2603   switch (HeaderType) {
2604   case PciDevice:
2605     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);
2606     break;
2607
2608   case PciP2pBridge:
2609     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);
2610     break;
2611
2612   case PciCardBusBridge:
2613     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);
2614     break;
2615
2616   default:
2617     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);
2618     HeaderType = PciUndefined;
2619   }
2620
2621   //
2622   // Print register Class Code
2623   //
2624   ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);
2625   PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);
2626   Print (L"\n");
2627
2628   if (ShellGetExecutionBreakFlag()) {
2629     return EFI_SUCCESS;
2630   }
2631
2632   //
2633   // Interpret remaining part of PCI configuration header depending on
2634   // HeaderType
2635   //
2636   CapPtr  = 0;
2637   Status  = EFI_SUCCESS;
2638   switch (HeaderType) {
2639   case PciDevice:
2640     Status = PciExplainDeviceData (
2641               &(ConfigSpace->NonCommon.Device),
2642               Address,
2643               IoDev
2644              );
2645     CapPtr = ConfigSpace->NonCommon.Device.CapabilitiesPtr;
2646     break;
2647
2648   case PciP2pBridge:
2649     Status = PciExplainBridgeData (
2650               &(ConfigSpace->NonCommon.Bridge),
2651               Address,
2652               IoDev
2653              );
2654     CapPtr = ConfigSpace->NonCommon.Bridge.CapabilitiesPtr;
2655     break;
2656
2657   case PciCardBusBridge:
2658     Status = PciExplainCardBusData (
2659               &(ConfigSpace->NonCommon.CardBus),
2660               Address,
2661               IoDev
2662              );
2663     CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;
2664     break;
2665   }
2666   //
2667   // If Status bit4 is 1, dump or explain capability structure
2668   //
2669   if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {
2670     PciExplainCapabilityStruct (IoDev, Address, CapPtr);
2671   }
2672
2673   return Status;
2674 }
2675
2676 EFI_STATUS
2677 PciExplainDeviceData (
2678   IN PCI_DEVICE_HEADER                      *Device,
2679   IN UINT64                                 Address,
2680   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *IoDev
2681   )
2682 /*++
2683
2684 Routine Description:
2685
2686   Explain the device specific part of data in PCI configuration space.
2687
2688 Arguments:
2689
2690   Device          Data in PCI configuration space
2691   Address         Address used to access configuration space of this PCI device
2692   IoDev           Handle used to access configuration space of PCI device
2693
2694 Returns:
2695
2696   EFI_SUCCESS     The command completed successfully
2697
2698 **/
2699 {
2700   UINTN       Index;
2701   BOOLEAN     BarExist;
2702   EFI_STATUS  Status;
2703   UINTN       BarCount;
2704
2705   //
2706   // Print Base Address Registers(Bar). When Bar = 0, this Bar does not
2707   // exist. If these no Bar for this function, print "none", otherwise
2708   // list detail information about this Bar.
2709   //
2710   ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));
2711
2712   BarExist  = FALSE;
2713   BarCount  = sizeof (Device->Bar) / sizeof (Device->Bar[0]);
2714   for (Index = 0; Index < BarCount; Index++) {
2715     if (Device->Bar[Index] == 0) {
2716       continue;
2717     }
2718
2719     if (!BarExist) {
2720       BarExist = TRUE;
2721       ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);
2722       Print (L"  --------------------------------------------------------------------------");
2723     }
2724
2725     Status = PciExplainBar (
2726               &(Device->Bar[Index]),
2727               &(mConfigSpace->Common.Command),
2728               Address,
2729               IoDev,
2730               &Index
2731              );
2732
2733     if (EFI_ERROR (Status)) {
2734       break;
2735     }
2736   }
2737
2738   if (!BarExist) {
2739     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);
2740
2741   } else {
2742     Print (L"\n  --------------------------------------------------------------------------");
2743   }
2744
2745   //
2746   // Print register Expansion ROM Base Address
2747   //
2748   if ((Device->ROMBar & PCI_BIT_0) == 0) {
2749     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ROMBar)));
2750
2751   } else {
2752     ShellPrintHiiEx(-1, -1, NULL,
2753       STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),
2754       gShellDebug1HiiHandle,
2755       INDEX_OF (&(Device->ROMBar)),
2756       Device->ROMBar
2757      );
2758   }
2759   //
2760   // Print register Cardbus CIS ptr
2761   //
2762   ShellPrintHiiEx(-1, -1, NULL,
2763     STRING_TOKEN (STR_PCI2_CARDBUS_CIS),
2764     gShellDebug1HiiHandle,
2765     INDEX_OF (&(Device->CardBusCISPtr)),
2766     Device->CardBusCISPtr
2767    );
2768
2769   //
2770   // Print register Sub-vendor ID and subsystem ID
2771   //
2772   ShellPrintHiiEx(-1, -1, NULL,
2773     STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),
2774     gShellDebug1HiiHandle,
2775     INDEX_OF (&(Device->SubVendorId)),
2776     Device->SubVendorId
2777    );
2778
2779   ShellPrintHiiEx(-1, -1, NULL,
2780     STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),
2781     gShellDebug1HiiHandle,
2782     INDEX_OF (&(Device->SubSystemId)),
2783     Device->SubSystemId
2784    );
2785
2786   //
2787   // Print register Capabilities Ptr
2788   //
2789   ShellPrintHiiEx(-1, -1, NULL,
2790     STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),
2791     gShellDebug1HiiHandle,
2792     INDEX_OF (&(Device->CapabilitiesPtr)),
2793     Device->CapabilitiesPtr
2794    );
2795
2796   //
2797   // Print register Interrupt Line and interrupt pin
2798   //
2799   ShellPrintHiiEx(-1, -1, NULL,
2800     STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),
2801     gShellDebug1HiiHandle,
2802     INDEX_OF (&(Device->InterruptLine)),
2803     Device->InterruptLine
2804    );
2805
2806   ShellPrintHiiEx(-1, -1, NULL,
2807     STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),
2808     gShellDebug1HiiHandle,
2809     INDEX_OF (&(Device->InterruptPin)),
2810     Device->InterruptPin
2811    );
2812
2813   //
2814   // Print register Min_Gnt and Max_Lat
2815   //
2816   ShellPrintHiiEx(-1, -1, NULL,
2817     STRING_TOKEN (STR_PCI2_MIN_GNT),
2818     gShellDebug1HiiHandle,
2819     INDEX_OF (&(Device->MinGnt)),
2820     Device->MinGnt
2821    );
2822
2823   ShellPrintHiiEx(-1, -1, NULL,
2824     STRING_TOKEN (STR_PCI2_MAX_LAT),
2825     gShellDebug1HiiHandle,
2826     INDEX_OF (&(Device->MaxLat)),
2827     Device->MaxLat
2828    );
2829
2830   return EFI_SUCCESS;
2831 }
2832
2833 EFI_STATUS
2834 PciExplainBridgeData (
2835   IN  PCI_BRIDGE_HEADER                     *Bridge,
2836   IN  UINT64                                Address,
2837   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       *IoDev
2838   )
2839 /*++
2840
2841 Routine Description:
2842
2843   Explain the bridge specific part of data in PCI configuration space.
2844
2845 Arguments:
2846
2847   Bridge          Bridge specific data region in PCI configuration space
2848   Address         Address used to access configuration space of this PCI device
2849   IoDev           Handle used to access configuration space of PCI device
2850
2851 Returns:
2852
2853   EFI_SUCCESS     The command completed successfully
2854
2855 **/
2856 {
2857   UINTN       Index;
2858   BOOLEAN     BarExist;
2859   UINTN       BarCount;
2860   UINT32      IoAddress32;
2861   EFI_STATUS  Status;
2862
2863   //
2864   // Print Base Address Registers. When Bar = 0, this Bar does not
2865   // exist. If these no Bar for this function, print "none", otherwise
2866   // list detail information about this Bar.
2867   //
2868   ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));
2869
2870   BarExist  = FALSE;
2871   BarCount  = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);
2872
2873   for (Index = 0; Index < BarCount; Index++) {
2874     if (Bridge->Bar[Index] == 0) {
2875       continue;
2876     }
2877
2878     if (!BarExist) {
2879       BarExist = TRUE;
2880       ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);
2881       Print (L"  --------------------------------------------------------------------------");
2882     }
2883
2884     Status = PciExplainBar (
2885               &(Bridge->Bar[Index]),
2886               &(mConfigSpace->Common.Command),
2887               Address,
2888               IoDev,
2889               &Index
2890              );
2891
2892     if (EFI_ERROR (Status)) {
2893       break;
2894     }
2895   }
2896
2897   if (!BarExist) {
2898     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);
2899   } else {
2900     Print (L"\n  --------------------------------------------------------------------------");
2901   }
2902
2903   //
2904   // Expansion register ROM Base Address
2905   //
2906   if ((Bridge->ROMBar & PCI_BIT_0) == 0) {
2907     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ROMBar)));
2908
2909   } else {
2910     ShellPrintHiiEx(-1, -1, NULL,
2911       STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),
2912       gShellDebug1HiiHandle,
2913       INDEX_OF (&(Bridge->ROMBar)),
2914       Bridge->ROMBar
2915      );
2916   }
2917   //
2918   // Print Bus Numbers(Primary, Secondary, and Subordinate
2919   //
2920   ShellPrintHiiEx(-1, -1, NULL,
2921     STRING_TOKEN (STR_PCI2_BUS_NUMBERS),
2922     gShellDebug1HiiHandle,
2923     INDEX_OF (&(Bridge->PrimaryBus)),
2924     INDEX_OF (&(Bridge->SecondaryBus)),
2925     INDEX_OF (&(Bridge->SubordinateBus))
2926    );
2927
2928   Print (L"               ------------------------------------------------------\n");
2929
2930   ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);
2931   ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);
2932   ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);
2933
2934   //
2935   // Print register Secondary Latency Timer
2936   //
2937   ShellPrintHiiEx(-1, -1, NULL,
2938     STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),
2939     gShellDebug1HiiHandle,
2940     INDEX_OF (&(Bridge->SecondaryLatencyTimer)),
2941     Bridge->SecondaryLatencyTimer
2942    );
2943
2944   //
2945   // Print register Secondary Status
2946   //
2947   PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);
2948
2949   //
2950   // Print I/O and memory ranges this bridge forwards. There are 3 resource
2951   // types: I/O, memory, and pre-fetchable memory. For each resource type,
2952   // base and limit address are listed.
2953   //
2954   ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);
2955   Print (L"----------------------------------------------------------------------\n");
2956
2957   //
2958   // IO Base & Limit
2959   //
2960   IoAddress32 = (Bridge->IoBaseUpper << 16 | Bridge->IoBase << 8);
2961   IoAddress32 &= 0xfffff000;
2962   ShellPrintHiiEx(-1, -1, NULL,
2963     STRING_TOKEN (STR_PCI2_TWO_VARS),
2964     gShellDebug1HiiHandle,
2965     INDEX_OF (&(Bridge->IoBase)),
2966     IoAddress32
2967    );
2968
2969   IoAddress32 = (Bridge->IoLimitUpper << 16 | Bridge->IoLimit << 8);
2970   IoAddress32 |= 0x00000fff;
2971   ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);
2972
2973   //
2974   // Memory Base & Limit
2975   //
2976   ShellPrintHiiEx(-1, -1, NULL,
2977     STRING_TOKEN (STR_PCI2_MEMORY),
2978     gShellDebug1HiiHandle,
2979     INDEX_OF (&(Bridge->MemoryBase)),
2980     (Bridge->MemoryBase << 16) & 0xfff00000
2981    );
2982
2983   ShellPrintHiiEx(-1, -1, NULL,
2984     STRING_TOKEN (STR_PCI2_ONE_VAR),
2985     gShellDebug1HiiHandle,
2986     (Bridge->MemoryLimit << 16) | 0x000fffff
2987    );
2988
2989   //
2990   // Pre-fetch-able Memory Base & Limit
2991   //
2992   ShellPrintHiiEx(-1, -1, NULL,
2993     STRING_TOKEN (STR_PCI2_PREFETCHABLE),
2994     gShellDebug1HiiHandle,
2995     INDEX_OF (&(Bridge->PrefetchableMemBase)),
2996     Bridge->PrefetchableBaseUpper,
2997     (Bridge->PrefetchableMemBase << 16) & 0xfff00000
2998    );
2999
3000   ShellPrintHiiEx(-1, -1, NULL,
3001     STRING_TOKEN (STR_PCI2_TWO_VARS_2),
3002     gShellDebug1HiiHandle,
3003     Bridge->PrefetchableLimitUpper,
3004     (Bridge->PrefetchableMemLimit << 16) | 0x000fffff
3005    );
3006
3007   //
3008   // Print register Capabilities Pointer
3009   //
3010   ShellPrintHiiEx(-1, -1, NULL,
3011     STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),
3012     gShellDebug1HiiHandle,
3013     INDEX_OF (&(Bridge->CapabilitiesPtr)),
3014     Bridge->CapabilitiesPtr
3015    );
3016
3017   //
3018   // Print register Bridge Control
3019   //
3020   PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);
3021
3022   //
3023   // Print register Interrupt Line & PIN
3024   //
3025   ShellPrintHiiEx(-1, -1, NULL,
3026     STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),
3027     gShellDebug1HiiHandle,
3028     INDEX_OF (&(Bridge->InterruptLine)),
3029     Bridge->InterruptLine
3030    );
3031
3032   ShellPrintHiiEx(-1, -1, NULL,
3033     STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),
3034     gShellDebug1HiiHandle,
3035     INDEX_OF (&(Bridge->InterruptPin)),
3036     Bridge->InterruptPin
3037    );
3038
3039   return EFI_SUCCESS;
3040 }
3041
3042 EFI_STATUS
3043 PciExplainBar (
3044   IN UINT32                                 *Bar,
3045   IN UINT16                                 *Command,
3046   IN UINT64                                 Address,
3047   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *IoDev,
3048   IN OUT UINTN                              *Index
3049   )
3050 /*++
3051
3052 Routine Description:
3053
3054   Explain the Base Address Register(Bar) in PCI configuration space.
3055
3056 Arguments:
3057
3058   Bar             Points to the Base Address Register intended to interpret
3059   Command         Points to the register Command
3060   Address         Address used to access configuration space of this PCI device
3061   IoDev           Handle used to access configuration space of PCI device
3062   Index           The Index
3063
3064 Returns:
3065
3066   EFI_SUCCESS     The command completed successfully
3067
3068 **/
3069 {
3070   UINT16  OldCommand;
3071   UINT16  NewCommand;
3072   UINT64  Bar64;
3073   UINT32  OldBar32;
3074   UINT32  NewBar32;
3075   UINT64  OldBar64;
3076   UINT64  NewBar64;
3077   BOOLEAN IsMem;
3078   BOOLEAN IsBar32;
3079   UINT64  RegAddress;
3080
3081   IsBar32   = TRUE;
3082   Bar64     = 0;
3083   NewBar32  = 0;
3084   NewBar64  = 0;
3085
3086   //
3087   // According the bar type, list detail about this bar, for example: 32 or
3088   // 64 bits; pre-fetchable or not.
3089   //
3090   if ((*Bar & PCI_BIT_0) == 0) {
3091     //
3092     // This bar is of memory type
3093     //
3094     IsMem = TRUE;
3095
3096     if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) == 0) {
3097       ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);
3098       ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);
3099       ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);
3100
3101     } else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {
3102       Bar64 = 0x0;
3103       CopyMem (&Bar64, Bar, sizeof (UINT64));
3104       ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, RShiftU64 ((Bar64 & 0xfffffffffffffff0), 32));
3105       ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0));
3106       ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);
3107       ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);
3108       IsBar32 = FALSE;
3109       *Index += 1;
3110
3111     } else {
3112       //
3113       // Reserved
3114       //
3115       ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);
3116       ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);
3117     }
3118
3119     if ((*Bar & PCI_BIT_3) == 0) {
3120       ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);
3121
3122     } else {
3123       ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);
3124     }
3125
3126   } else {
3127     //
3128     // This bar is of io type
3129     //
3130     IsMem = FALSE;
3131     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);
3132     Print (L"I/O                               ");
3133   }
3134
3135   //
3136   // Get BAR length(or the amount of resource this bar demands for). To get
3137   // Bar length, first we should temporarily disable I/O and memory access
3138   // of this function(by set bits in the register Command), then write all
3139   // "1"s to this bar. The bar value read back is the amount of resource
3140   // this bar demands for.
3141   //
3142   //
3143   // Disable io & mem access
3144   //
3145   OldCommand  = *Command;
3146   NewCommand  = (UINT16) (OldCommand & 0xfffc);
3147   RegAddress  = Address | INDEX_OF (Command);
3148   IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);
3149
3150   RegAddress = Address | INDEX_OF (Bar);
3151
3152   //
3153   // Read after write the BAR to get the size
3154   //
3155   if (IsBar32) {
3156     OldBar32  = *Bar;
3157     NewBar32  = 0xffffffff;
3158
3159     IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);
3160     IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);
3161     IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);
3162
3163     if (IsMem) {
3164       NewBar32  = NewBar32 & 0xfffffff0;
3165       NewBar32  = (~NewBar32) + 1;
3166
3167     } else {
3168       NewBar32  = NewBar32 & 0xfffffffc;
3169       NewBar32  = (~NewBar32) + 1;
3170       NewBar32  = NewBar32 & 0x0000ffff;
3171     }
3172   } else {
3173
3174     OldBar64 = 0x0;
3175     CopyMem (&OldBar64, Bar, sizeof (UINT64));
3176     NewBar64 = 0xffffffffffffffff;
3177
3178     IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);
3179     IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);
3180     IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);
3181
3182     if (IsMem) {
3183       NewBar64  = NewBar64 & 0xfffffffffffffff0;
3184       NewBar64  = (~NewBar64) + 1;
3185
3186     } else {
3187       NewBar64  = NewBar64 & 0xfffffffffffffffc;
3188       NewBar64  = (~NewBar64) + 1;
3189       NewBar64  = NewBar64 & 0x000000000000ffff;
3190     }
3191   }
3192   //
3193   // Enable io & mem access
3194   //
3195   RegAddress = Address | INDEX_OF (Command);
3196   IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);
3197
3198   if (IsMem) {
3199     if (IsBar32) {
3200       ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);
3201       ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);
3202
3203     } else {
3204       ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, RShiftU64 (NewBar64, 32));
3205       ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);
3206       Print (L"  ");
3207       ShellPrintHiiEx(-1, -1, NULL,
3208         STRING_TOKEN (STR_PCI2_RSHIFT),
3209         gShellDebug1HiiHandle,
3210         RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0) - 1), 32)
3211        );
3212       ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0) - 1));
3213
3214     }
3215   } else {
3216     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);
3217     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);
3218   }
3219
3220   return EFI_SUCCESS;
3221 }
3222
3223 EFI_STATUS
3224 PciExplainCardBusData (
3225   IN PCI_CARDBUS_HEADER                     *CardBus,
3226   IN UINT64                                 Address,
3227   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *IoDev
3228   )
3229 /*++
3230
3231 Routine Description:
3232
3233   Explain the cardbus specific part of data in PCI configuration space.
3234
3235 Arguments:
3236
3237   CardBus         CardBus specific region of PCI configuration space
3238   Address         Address used to access configuration space of this PCI device
3239   IoDev           Handle used to access configuration space of PCI device
3240
3241 Returns:
3242
3243   EFI_SUCCESS     The command completed successfully
3244
3245 **/
3246 {
3247   BOOLEAN           Io32Bit;
3248   PCI_CARDBUS_DATA  *CardBusData;
3249
3250   ShellPrintHiiEx(-1, -1, NULL,
3251     STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),
3252     gShellDebug1HiiHandle,
3253     INDEX_OF (&(CardBus->CardBusSocketReg)),
3254     CardBus->CardBusSocketReg
3255    );
3256
3257   //
3258   // Print Secondary Status
3259   //
3260   PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);
3261
3262   //
3263   // Print Bus Numbers(Primary bus number, CardBus bus number, and
3264   // Subordinate bus number
3265   //
3266   ShellPrintHiiEx(-1, -1, NULL,
3267     STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),
3268     gShellDebug1HiiHandle,
3269     INDEX_OF (&(CardBus->PciBusNumber)),
3270     INDEX_OF (&(CardBus->CardBusBusNumber)),
3271     INDEX_OF (&(CardBus->SubordinateBusNumber))
3272    );
3273
3274   Print (L"               ------------------------------------------------------\n");
3275
3276   ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);
3277   ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);
3278   ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);
3279
3280   //
3281   // Print CardBus Latency Timer
3282   //
3283   ShellPrintHiiEx(-1, -1, NULL,
3284     STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),
3285     gShellDebug1HiiHandle,
3286     INDEX_OF (&(CardBus->CardBusLatencyTimer)),
3287     CardBus->CardBusLatencyTimer
3288    );
3289
3290   //
3291   // Print Memory/Io ranges this cardbus bridge forwards
3292   //
3293   ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);
3294   Print (L"----------------------------------------------------------------------\n");
3295
3296   ShellPrintHiiEx(-1, -1, NULL,
3297     STRING_TOKEN (STR_PCI2_MEM_3),
3298     gShellDebug1HiiHandle,
3299     INDEX_OF (&(CardBus->MemoryBase0)),
3300     CardBus->BridgeControl & PCI_BIT_8 ? L"    Prefetchable" : L"Non-Prefetchable",
3301     CardBus->MemoryBase0 & 0xfffff000,
3302     CardBus->MemoryLimit0 | 0x00000fff
3303    );
3304
3305   ShellPrintHiiEx(-1, -1, NULL,
3306     STRING_TOKEN (STR_PCI2_MEM_3),
3307     gShellDebug1HiiHandle,
3308     INDEX_OF (&(CardBus->MemoryBase1)),
3309     CardBus->BridgeControl & PCI_BIT_9 ? L"    Prefetchable" : L"Non-Prefetchable",
3310     CardBus->MemoryBase1 & 0xfffff000,
3311     CardBus->MemoryLimit1 | 0x00000fff
3312    );
3313
3314   Io32Bit = (BOOLEAN) (CardBus->IoBase0 & PCI_BIT_0);
3315   ShellPrintHiiEx(-1, -1, NULL,
3316     STRING_TOKEN (STR_PCI2_IO_2),
3317     gShellDebug1HiiHandle,
3318     INDEX_OF (&(CardBus->IoBase0)),
3319     Io32Bit ? L"          32 bit" : L"          16 bit",
3320     CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),
3321     CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff) | 0x00000003
3322    );
3323
3324   Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);
3325   ShellPrintHiiEx(-1, -1, NULL,
3326     STRING_TOKEN (STR_PCI2_IO_2),
3327     gShellDebug1HiiHandle,
3328     INDEX_OF (&(CardBus->IoBase1)),
3329     Io32Bit ? L"          32 bit" : L"          16 bit",
3330     CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),
3331     CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff) | 0x00000003
3332    );
3333
3334   //
3335   // Print register Interrupt Line & PIN
3336   //
3337   ShellPrintHiiEx(-1, -1, NULL,
3338     STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),
3339     gShellDebug1HiiHandle,
3340     INDEX_OF (&(CardBus->InterruptLine)),
3341     CardBus->InterruptLine,
3342     INDEX_OF (&(CardBus->InterruptPin)),
3343     CardBus->InterruptPin
3344    );
3345
3346   //
3347   // Print register Bridge Control
3348   //
3349   PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);
3350
3351   //
3352   // Print some registers in data region of PCI configuration space for cardbus
3353   // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base
3354   // Address.
3355   //
3356   CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_HEADER));
3357
3358   ShellPrintHiiEx(-1, -1, NULL,
3359     STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),
3360     gShellDebug1HiiHandle,
3361     INDEX_OF (&(CardBusData->SubVendorId)),
3362     CardBusData->SubVendorId,
3363     INDEX_OF (&(CardBusData->SubSystemId)),
3364     CardBusData->SubSystemId
3365    );
3366
3367   ShellPrintHiiEx(-1, -1, NULL,
3368     STRING_TOKEN (STR_PCI2_OPTIONAL),
3369     gShellDebug1HiiHandle,
3370     INDEX_OF (&(CardBusData->LegacyBase)),
3371     CardBusData->LegacyBase
3372    );
3373
3374   return EFI_SUCCESS;
3375 }
3376
3377 EFI_STATUS
3378 PciExplainStatus (
3379   IN UINT16                                 *Status,
3380   IN BOOLEAN                                MainStatus,
3381   IN PCI_HEADER_TYPE                        HeaderType
3382   )
3383 /*++
3384
3385 Routine Description:
3386
3387   Explain each meaningful bit of register Status. The definition of Status is
3388   slightly different depending on the PCI header type.
3389
3390 Arguments:
3391
3392   Status          Points to the content of register Status
3393   MainStatus      Indicates if this register is main status(not secondary
3394                   status)
3395   HeaderType      Header type of this PCI device
3396
3397 Returns:
3398
3399   EFI_SUCCESS     The command completed successfully
3400
3401 **/
3402 {
3403   if (MainStatus) {
3404     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);
3405
3406   } else {
3407     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);
3408   }
3409
3410   ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & PCI_BIT_4) != 0);
3411
3412   //
3413   // Bit 5 is meaningless for CardBus Bridge
3414   //
3415   if (HeaderType == PciCardBusBridge) {
3416     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);
3417
3418   } else {
3419     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);
3420   }
3421
3422   ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & PCI_BIT_7) != 0);
3423
3424   ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & PCI_BIT_8) != 0);
3425   //
3426   // Bit 9 and bit 10 together decides the DEVSEL timing
3427   //
3428   ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);
3429   if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) == 0) {
3430     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);
3431
3432   } else if ((*Status & PCI_BIT_9) != 0 && (*Status & PCI_BIT_10) == 0) {
3433     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);
3434
3435   } else if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) != 0) {
3436     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);
3437
3438   } else {
3439     ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);
3440   }
3441
3442   ShellPrintHiiEx(-1, -1, NULL,
3443     STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),
3444     gShellDebug1HiiHandle,
3445     (*Status & PCI_BIT_11) != 0
3446    );
3447
3448   ShellPrintHiiEx(-1, -1, NULL,
3449     STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),
3450     gShellDebug1HiiHandle,
3451     (*Status & PCI_BIT_12) != 0
3452    );
3453
3454   ShellPrintHiiEx(-1, -1, NULL,
3455     STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),
3456     gShellDebug1HiiHandle,
3457     (*Status & PCI_BIT_13) != 0
3458    );
3459
3460   if (MainStatus) {
3461     ShellPrintHiiEx(-1, -1, NULL,
3462       STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),
3463       gShellDebug1HiiHandle,
3464       (*Status & PCI_BIT_14) != 0
3465      );
3466
3467   } else {
3468     ShellPrintHiiEx(-1, -1, NULL,
3469       STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),
3470       gShellDebug1HiiHandle,
3471       (*Status & PCI_BIT_14) != 0
3472      );
3473   }
3474
3475   ShellPrintHiiEx(-1, -1, NULL,
3476     STRING_TOKEN (STR_PCI2_DETECTED_ERROR),
3477     gShellDebug1HiiHandle,
3478     (*Status & PCI_BIT_15) != 0
3479    );
3480
3481   return EFI_SUCCESS;
3482 }
3483
3484 EFI_STATUS
3485 PciExplainCommand (
3486   IN UINT16                                 *Command
3487   )
3488 /*++
3489
3490 Routine Description:
3491
3492   Explain each meaningful bit of register Command.
3493
3494 Arguments:
3495
3496   Command         Points to the content of register Command
3497
3498 Returns:
3499
3500   EFI_SUCCESS     The command completed successfully
3501
3502 **/
3503 {
3504   //
3505   // Print the binary value of register Command
3506   //
3507   ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);
3508
3509   //
3510   // Explain register Command bit by bit
3511   //
3512   ShellPrintHiiEx(-1, -1, NULL,
3513     STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),
3514     gShellDebug1HiiHandle,
3515     (*Command & PCI_BIT_0) != 0
3516    );
3517
3518   ShellPrintHiiEx(-1, -1, NULL,
3519     STRING_TOKEN (STR_PCI2_MEMORY_SPACE),
3520     gShellDebug1HiiHandle,
3521     (*Command & PCI_BIT_1) != 0
3522    );
3523
3524   ShellPrintHiiEx(-1, -1, NULL,
3525     STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),
3526     gShellDebug1HiiHandle,
3527     (*Command & PCI_BIT_2) != 0
3528    );
3529
3530   ShellPrintHiiEx(-1, -1, NULL,
3531     STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),
3532     gShellDebug1HiiHandle,
3533     (*Command & PCI_BIT_3) != 0
3534    );
3535
3536   ShellPrintHiiEx(-1, -1, NULL,
3537     STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),
3538     gShellDebug1HiiHandle,
3539     (*Command & PCI_BIT_4) != 0
3540    );
3541
3542   ShellPrintHiiEx(-1, -1, NULL,
3543     STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),
3544     gShellDebug1HiiHandle,
3545     (*Command & PCI_BIT_5) != 0
3546    );
3547
3548   ShellPrintHiiEx(-1, -1, NULL,
3549     STRING_TOKEN (STR_PCI2_ASSERT_PERR),
3550     gShellDebug1HiiHandle,
3551     (*Command & PCI_BIT_6) != 0
3552    );
3553
3554   ShellPrintHiiEx(-1, -1, NULL,
3555     STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),
3556     gShellDebug1HiiHandle,
3557     (*Command & PCI_BIT_7) != 0
3558    );
3559
3560   ShellPrintHiiEx(-1, -1, NULL,
3561     STRING_TOKEN (STR_PCI2_SERR_DRIVER),
3562     gShellDebug1HiiHandle,
3563     (*Command & PCI_BIT_8) != 0
3564    );
3565
3566   ShellPrintHiiEx(-1, -1, NULL,
3567     STRING_TOKEN (STR_PCI2_FAST_BACK_2),
3568     gShellDebug1HiiHandle,
3569     (*Command & PCI_BIT_9) != 0
3570    );
3571
3572   return EFI_SUCCESS;
3573 }
3574
3575 EFI_STATUS
3576 PciExplainBridgeControl (
3577   IN UINT16                                 *BridgeControl,
3578   IN PCI_HEADER_TYPE                        HeaderType
3579   )
3580 /*++
3581
3582 Routine Description:
3583
3584   Explain each meaningful bit of register Bridge Control.
3585
3586 Arguments:
3587
3588   BridgeControl   Points to the content of register Bridge Control
3589   HeaderType      The headertype
3590
3591 Returns:
3592
3593   EFI_SUCCESS     The command completed successfully
3594
3595 **/
3596 {
3597   ShellPrintHiiEx(-1, -1, NULL,
3598     STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),
3599     gShellDebug1HiiHandle,
3600     INDEX_OF (BridgeControl),
3601     *BridgeControl
3602    );
3603
3604   ShellPrintHiiEx(-1, -1, NULL,
3605     STRING_TOKEN (STR_PCI2_PARITY_ERROR),
3606     gShellDebug1HiiHandle,
3607     (*BridgeControl & PCI_BIT_0) != 0
3608    );
3609   ShellPrintHiiEx(-1, -1, NULL,
3610     STRING_TOKEN (STR_PCI2_SERR_ENABLE),
3611     gShellDebug1HiiHandle,
3612     (*BridgeControl & PCI_BIT_1) != 0
3613    );
3614   ShellPrintHiiEx(-1, -1, NULL,
3615     STRING_TOKEN (STR_PCI2_ISA_ENABLE),
3616     gShellDebug1HiiHandle,
3617     (*BridgeControl & PCI_BIT_2) != 0
3618    );
3619   ShellPrintHiiEx(-1, -1, NULL,
3620     STRING_TOKEN (STR_PCI2_VGA_ENABLE),
3621     gShellDebug1HiiHandle,
3622     (*BridgeControl & PCI_BIT_3) != 0
3623    );
3624   ShellPrintHiiEx(-1, -1, NULL,
3625     STRING_TOKEN (STR_PCI2_MASTER_ABORT),
3626     gShellDebug1HiiHandle,
3627     (*BridgeControl & PCI_BIT_5) != 0
3628    );
3629
3630   //
3631   // Register Bridge Control has some slight differences between P2P bridge
3632   // and Cardbus bridge from bit 6 to bit 11.
3633   //
3634   if (HeaderType == PciP2pBridge) {
3635     ShellPrintHiiEx(-1, -1, NULL,
3636       STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),
3637       gShellDebug1HiiHandle,
3638       (*BridgeControl & PCI_BIT_6) != 0
3639      );
3640     ShellPrintHiiEx(-1, -1, NULL,
3641       STRING_TOKEN (STR_PCI2_FAST_ENABLE),
3642       gShellDebug1HiiHandle,
3643       (*BridgeControl & PCI_BIT_7) != 0
3644      );
3645     ShellPrintHiiEx(-1, -1, NULL,
3646       STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),
3647       gShellDebug1HiiHandle,
3648       (*BridgeControl & PCI_BIT_8)!=0 ? L"2^10" : L"2^15"
3649      );
3650     ShellPrintHiiEx(-1, -1, NULL,
3651       STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),
3652       gShellDebug1HiiHandle,
3653       (*BridgeControl & PCI_BIT_9)!=0 ? L"2^10" : L"2^15"
3654      );
3655     ShellPrintHiiEx(-1, -1, NULL,
3656       STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),
3657       gShellDebug1HiiHandle,
3658       (*BridgeControl & PCI_BIT_10) != 0
3659      );
3660     ShellPrintHiiEx(-1, -1, NULL,
3661       STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),
3662       gShellDebug1HiiHandle,
3663       (*BridgeControl & PCI_BIT_11) != 0
3664      );
3665
3666   } else {
3667     ShellPrintHiiEx(-1, -1, NULL,
3668       STRING_TOKEN (STR_PCI2_CARDBUS_RESET),
3669       gShellDebug1HiiHandle,
3670       (*BridgeControl & PCI_BIT_6) != 0
3671      );
3672     ShellPrintHiiEx(-1, -1, NULL,
3673       STRING_TOKEN (STR_PCI2_IREQ_ENABLE),
3674       gShellDebug1HiiHandle,
3675       (*BridgeControl & PCI_BIT_7) != 0
3676      );
3677     ShellPrintHiiEx(-1, -1, NULL,
3678       STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),
3679       gShellDebug1HiiHandle,
3680       (*BridgeControl & PCI_BIT_10) != 0
3681      );
3682   }
3683
3684   return EFI_SUCCESS;
3685 }
3686
3687 EFI_STATUS
3688 PciExplainCapabilityStruct (
3689   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         *IoDev,
3690   IN UINT64                                   Address,
3691   IN  UINT8                                   CapPtr
3692   )
3693 {
3694   UINT8   CapabilityPtr;
3695   UINT16  CapabilityEntry;
3696   UINT8   CapabilityID;
3697   UINT64  RegAddress;
3698
3699   CapabilityPtr = CapPtr;
3700
3701   //
3702   // Go through the Capability list
3703   //
3704   while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {
3705     RegAddress = Address + CapabilityPtr;
3706     IoDev->Pci.Read (IoDev, EfiPciWidthUint16, RegAddress, 1, &CapabilityEntry);
3707
3708     CapabilityID = (UINT8) CapabilityEntry;
3709
3710     //
3711     // Explain PciExpress data
3712     //
3713     if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {
3714       PciExplainPciExpress (IoDev, Address, CapabilityPtr);
3715       return EFI_SUCCESS;
3716     }
3717     //
3718     // Explain other capabilities here
3719     //
3720     CapabilityPtr = (UINT8) (CapabilityEntry >> 8);
3721   }
3722
3723   return EFI_SUCCESS;
3724 }
3725
3726 EFI_STATUS
3727 ExplainPcieCapReg (
3728   IN PCIE_CAP_STURCTURE *PciExpressCap
3729 )
3730 {
3731   UINT16 PcieCapReg;
3732   CHAR16 *DevicePortType;
3733
3734   PcieCapReg = PciExpressCap->PcieCapReg;
3735   Print (
3736     L"  Capability Version(3:0):          %E0x%04x%N\n",
3737     PCIE_CAP_VERSION (PcieCapReg)
3738    );
3739   if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {
3740     DevicePortType = DevicePortTypeTable[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg)];
3741   } else {
3742     DevicePortType = L"Unknown Type";
3743   }
3744   Print (
3745     L"  Device/PortType(7:4):             %E%s%N\n",
3746     DevicePortType
3747    );
3748   //
3749   // 'Slot Implemented' is only valid for:
3750   // a) Root Port of PCI Express Root Complex, or
3751   // b) Downstream Port of PCI Express Switch
3752   //
3753   if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||
3754       PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {
3755     Print (
3756       L"  Slot Implemented(8):              %E%d%N\n",
3757       PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg)
3758      );
3759   }
3760   Print (
3761     L"  Interrupt Message Number(13:9):   %E0x%05x%N\n",
3762     PCIE_CAP_INT_MSG_NUM (PcieCapReg)
3763    );
3764   return EFI_SUCCESS;
3765 }
3766
3767 EFI_STATUS
3768 ExplainPcieDeviceCap (
3769   IN PCIE_CAP_STURCTURE *PciExpressCap
3770 )
3771 {
3772   UINT16 PcieCapReg;
3773   UINT32 PcieDeviceCap;
3774   UINT8  DevicePortType;
3775   UINT8  L0sLatency;
3776   UINT8  L1Latency;
3777
3778   PcieCapReg     = PciExpressCap->PcieCapReg;
3779   PcieDeviceCap  = PciExpressCap->PcieDeviceCap;
3780   DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);
3781   Print (L"  Max_Payload_Size Supported(2:0):          ");
3782   if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) < 6) {
3783     Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));
3784   } else {
3785     Print (L"%EUnknown%N\n");
3786   }
3787   Print (
3788     L"  Phantom Functions Supported(4:3):         %E%d%N\n",
3789     PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap)
3790    );
3791   Print (
3792     L"  Extended Tag Field Supported(5):          %E%d-bit Tag field supported%N\n",
3793     PCIE_CAP_EXTENDED_TAG (PcieDeviceCap) ? 8 : 5
3794    );
3795   //
3796   // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint
3797   //
3798   if (IS_PCIE_ENDPOINT (DevicePortType)) {
3799     L0sLatency = (UINT8) PCIE_CAP_L0sLatency (PcieDeviceCap);
3800     L1Latency  = (UINT8) PCIE_CAP_L1Latency (PcieDeviceCap);
3801     Print (L"  Endpoint L0s Acceptable Latency(8:6):     ");
3802     if (L0sLatency < 4) {
3803       Print (L"%EMaximum of %d ns%N\n", 1 << (L0sLatency + 6));
3804     } else {
3805       if (L0sLatency < 7) {
3806         Print (L"%EMaximum of %d us%N\n", 1 << (L0sLatency - 3));
3807       } else {
3808         Print (L"%ENo limit%N\n");
3809       }
3810     }
3811     Print (L"  Endpoint L1 Acceptable Latency(11:9):     ");
3812     if (L1Latency < 7) {
3813       Print (L"%EMaximum of %d us%N\n", 1 << (L1Latency + 1));
3814     } else {
3815       Print (L"%ENo limit%N\n");
3816     }
3817   }
3818   Print (
3819     L"  Role-based Error Reporting(15):           %E%d%N\n",
3820     PCIE_CAP_ERR_REPORTING (PcieDeviceCap)
3821    );
3822   //
3823   // Only valid for Upstream Port:
3824   // a) Captured Slot Power Limit Value
3825   // b) Captured Slot Power Scale
3826   //
3827   if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {
3828     Print (
3829       L"  Captured Slot Power Limit Value(25:18):   %E0x%02x%N\n",
3830       PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap)
3831      );
3832     Print (
3833       L"  Captured Slot Power Limit Scale(27:26):   %E%s%N\n",
3834       SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]
3835      );
3836   }
3837   //
3838   // Function Level Reset Capability is only valid for Endpoint
3839   //
3840   if (IS_PCIE_ENDPOINT (DevicePortType)) {
3841     Print (
3842       L"  Function Level Reset Capability(28):      %E%d%N\n",
3843       PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap)
3844      );
3845   }
3846   return EFI_SUCCESS;
3847 }
3848
3849 EFI_STATUS
3850 ExplainPcieDeviceControl (
3851   IN PCIE_CAP_STURCTURE *PciExpressCap
3852 )
3853 {
3854   UINT16 PcieCapReg;
3855   UINT16 PcieDeviceControl;
3856
3857   PcieCapReg        = PciExpressCap->PcieCapReg;
3858   PcieDeviceControl = PciExpressCap->DeviceControl;
3859   Print (
3860     L"  Correctable Error Reporting Enable(0):    %E%d%N\n",
3861     PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)
3862    );
3863   Print (
3864     L"  Non-Fatal Error Reporting Enable(1):      %E%d%N\n",
3865     PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)
3866    );
3867   Print (
3868     L"  Fatal Error Reporting Enable(2):          %E%d%N\n",
3869     PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)
3870    );
3871   Print (
3872     L"  Unsupported Request Reporting Enable(3):  %E%d%N\n",
3873     PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)
3874    );
3875   Print (
3876     L"  Enable Relaxed Ordering(4):               %E%d%N\n",
3877     PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)
3878    );
3879   Print (L"  Max_Payload_Size(7:5):                    ");
3880   if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {
3881     Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));
3882   } else {
3883     Print (L"%EUnknown%N\n");
3884   }
3885   Print (
3886     L"  Extended Tag Field Enable(8):             %E%d%N\n",
3887     PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl)
3888    );
3889   Print (
3890     L"  Phantom Functions Enable(9):              %E%d%N\n",
3891     PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl)
3892    );
3893   Print (
3894     L"  Auxiliary (AUX) Power PM Enable(10):      %E%d%N\n",
3895     PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl)
3896    );
3897   Print (
3898     L"  Enable No Snoop(11):                      %E%d%N\n",
3899     PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl)
3900    );
3901   Print (L"  Max_Read_Request_Size(14:12):             ");
3902   if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {
3903     Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));
3904   } else {
3905     Print (L"%EUnknown%N\n");
3906   }
3907   //
3908   // Read operation is only valid for PCI Express to PCI/PCI-X Bridges
3909   //
3910   if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {
3911     Print (
3912       L"  Bridge Configuration Retry Enable(15):  %E%d%N\n",
3913       PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl)
3914      );
3915   }
3916   return EFI_SUCCESS;
3917 }
3918
3919 EFI_STATUS
3920 ExplainPcieDeviceStatus (
3921   IN PCIE_CAP_STURCTURE *PciExpressCap
3922 )
3923 {
3924   UINT16 PcieDeviceStatus;
3925
3926   PcieDeviceStatus = PciExpressCap->DeviceStatus;
3927   Print (
3928     L"  Correctable Error Detected(0):            %E%d%N\n",
3929     PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus)
3930    );
3931   Print (
3932     L"  Non-Fatal Error Detected(1):              %E%d%N\n",
3933     PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus)
3934    );
3935   Print (
3936     L"  Fatal Error Detected(2):                  %E%d%N\n",
3937     PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus)
3938    );
3939   Print (
3940     L"  Unsupported Request Detected(3):          %E%d%N\n",
3941     PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus)
3942    );
3943   Print (
3944     L"  AUX Power Detected(4):                    %E%d%N\n",
3945     PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus)
3946    );
3947   Print (
3948     L"  Transactions Pending(5):                  %E%d%N\n",
3949     PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus)
3950    );
3951   return EFI_SUCCESS;
3952 }
3953
3954 EFI_STATUS
3955 ExplainPcieLinkCap (
3956   IN PCIE_CAP_STURCTURE *PciExpressCap
3957 )
3958 {
3959   UINT32 PcieLinkCap;
3960   CHAR16 *SupLinkSpeeds;
3961   CHAR16 *ASPM;
3962
3963   PcieLinkCap = PciExpressCap->LinkCap;
3964   switch (PCIE_CAP_SUP_LINK_SPEEDS (PcieLinkCap)) {
3965     case 1:
3966       SupLinkSpeeds = L"2.5 GT/s";
3967       break;
3968     case 2:
3969       SupLinkSpeeds = L"5.0 GT/s and 2.5 GT/s";
3970       break;
3971     default:
3972       SupLinkSpeeds = L"Unknown";
3973       break;
3974   }
3975   Print (
3976     L"  Supported Link Speeds(3:0):                         %E%s supported%N\n",
3977     SupLinkSpeeds
3978    );
3979   Print (
3980     L"  Maximum Link Width(9:4):                            %Ex%d%N\n",
3981     PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)
3982    );
3983   switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {
3984     case 1:
3985       ASPM = L"L0s Entry";
3986       break;
3987     case 3:
3988       ASPM = L"L0s and L1";
3989       break;
3990     default:
3991       ASPM = L"Reserved";
3992       break;
3993   }
3994   Print (
3995     L"  Active State Power Management Support(11:10):       %E%s Supported%N\n",
3996     ASPM
3997    );
3998   Print (
3999     L"  L0s Exit Latency(14:12):                            %E%s%N\n",
4000     L0sLatencyStrTable[PCIE_CAP_L0s_LATENCY (PcieLinkCap)]
4001    );
4002   Print (
4003     L"  L1 Exit Latency(17:15):                             %E%s%N\n",
4004     L1LatencyStrTable[PCIE_CAP_L0s_LATENCY (PcieLinkCap)]
4005    );
4006   Print (
4007     L"  Clock Power Management(18):                         %E%d%N\n",
4008     PCIE_CAP_CLOCK_PM (PcieLinkCap)
4009    );
4010   Print (
4011     L"  Surprise Down Error Reporting Capable(19):          %E%d%N\n",
4012     PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap)
4013    );
4014   Print (
4015     L"  Data Link Layer Link Active Reporting Capable(20):  %E%d%N\n",
4016     PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap)
4017    );
4018   Print (
4019     L"  Link Bandwidth Notification Capability(21):         %E%d%N\n",
4020     PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap)
4021    );
4022   Print (
4023     L"  Port Number(31:24):                                 %E0x%02x%N\n",
4024     PCIE_CAP_PORT_NUMBER (PcieLinkCap)
4025    );
4026   return EFI_SUCCESS;
4027 }
4028
4029 EFI_STATUS
4030 ExplainPcieLinkControl (
4031   IN PCIE_CAP_STURCTURE *PciExpressCap
4032 )
4033 {
4034   UINT16 PcieLinkControl;
4035   UINT8  DevicePortType;
4036
4037   PcieLinkControl = PciExpressCap->LinkControl;
4038   DevicePortType  = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);
4039   Print (
4040     L"  Active State Power Management Control(1:0):         %E%s%N\n",
4041     ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]
4042    );
4043   //
4044   // RCB is not applicable to switches
4045   //
4046   if (!IS_PCIE_SWITCH(DevicePortType)) {
4047     Print (
4048       L"  Read Completion Boundary (RCB)(3):                  %E%d byte%N\n",
4049       1 << (PCIE_CAP_RCB (PcieLinkControl) + 6)
4050      );
4051   }
4052   //
4053   // Link Disable is reserved on
4054   // a) Endpoints
4055   // b) PCI Express to PCI/PCI-X bridges
4056   // c) Upstream Ports of Switches
4057   //
4058   if (!IS_PCIE_ENDPOINT (DevicePortType) &&
4059       DevicePortType != PCIE_SWITCH_UPSTREAM_PORT &&
4060       DevicePortType != PCIE_PCIE_TO_PCIX_BRIDGE) {
4061     Print (
4062       L"  Link Disable(4):                                    %E%d%N\n",
4063       PCIE_CAP_LINK_DISABLE (PcieLinkControl)
4064      );
4065   }
4066   Print (
4067     L"  Common Clock Configuration(6):                      %E%d%N\n",
4068     PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl)
4069    );
4070   Print (
4071     L"  Extended Synch(7):                                  %E%d%N\n",
4072     PCIE_CAP_EXT_SYNC (PcieLinkControl)
4073    );
4074   Print (
4075     L"  Enable Clock Power Management(8):                   %E%d%N\n",
4076     PCIE_CAP_CLK_PWR_MNG (PcieLinkControl)
4077    );
4078   Print (
4079     L"  Hardware Autonomous Width Disable(9):               %E%d%N\n",
4080     PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl)
4081    );
4082   Print (
4083     L"  Link Bandwidth Management Interrupt Enable(10):     %E%d%N\n",
4084     PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl)
4085    );
4086   Print (
4087     L"  Link Autonomous Bandwidth Interrupt Enable(11):     %E%d%N\n",
4088     PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl)
4089    );
4090   return EFI_SUCCESS;
4091 }
4092
4093 EFI_STATUS
4094 ExplainPcieLinkStatus (
4095   IN PCIE_CAP_STURCTURE *PciExpressCap
4096 )
4097 {
4098   UINT16 PcieLinkStatus;
4099   CHAR16 *SupLinkSpeeds;
4100
4101   PcieLinkStatus = PciExpressCap->LinkStatus;
4102   switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {
4103     case 1:
4104       SupLinkSpeeds = L"2.5 GT/s";
4105       break;
4106     case 2:
4107       SupLinkSpeeds = L"5.0 GT/s";
4108       break;
4109     default:
4110       SupLinkSpeeds = L"Reserved";
4111       break;
4112   }
4113   Print (
4114     L"  Current Link Speed(3:0):                            %E%s%N\n",
4115     SupLinkSpeeds
4116    );
4117   Print (
4118     L"  Negotiated Link Width(9:4):                         %Ex%d%N\n",
4119     PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus)
4120    );
4121   Print (
4122     L"  Link Training(11):                                  %E%d%N\n",
4123     PCIE_CAP_LINK_TRAINING (PcieLinkStatus)
4124    );
4125   Print (
4126     L"  Slot Clock Configuration(12):                       %E%d%N\n",
4127     PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus)
4128    );
4129   Print (
4130     L"  Data Link Layer Link Active(13):                    %E%d%N\n",
4131     PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus)
4132    );
4133   Print (
4134     L"  Link Bandwidth Management Status(14):               %E%d%N\n",
4135     PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus)
4136    );
4137   Print (
4138     L"  Link Autonomous Bandwidth Status(15):               %E%d%N\n",
4139     PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus)
4140    );
4141   return EFI_SUCCESS;
4142 }
4143
4144 EFI_STATUS
4145 ExplainPcieSlotCap (
4146   IN PCIE_CAP_STURCTURE *PciExpressCap
4147 )
4148 {
4149   UINT32 PcieSlotCap;
4150
4151   PcieSlotCap = PciExpressCap->SlotCap;
4152
4153   Print (
4154     L"  Attention Button Present(0):                        %E%d%N\n",
4155     PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap)
4156    );
4157   Print (
4158     L"  Power Controller Present(1):                        %E%d%N\n",
4159     PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap)
4160    );
4161   Print (
4162     L"  MRL Sensor Present(2):                              %E%d%N\n",
4163     PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap)
4164    );
4165   Print (
4166     L"  Attention Indicator Present(3):                     %E%d%N\n",
4167     PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap)
4168    );
4169   Print (
4170     L"  Power Indicator Present(4):                         %E%d%N\n",
4171     PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap)
4172    );
4173   Print (
4174     L"  Hot-Plug Surprise(5):                               %E%d%N\n",
4175     PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap)
4176    );
4177   Print (
4178     L"  Hot-Plug Capable(6):                                %E%d%N\n",
4179     PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap)
4180    );
4181   Print (
4182     L"  Slot Power Limit Value(14:7):                       %E0x%02x%N\n",
4183     PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap)
4184    );
4185   Print (
4186     L"  Slot Power Limit Scale(16:15):                      %E%s%N\n",
4187     SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]
4188    );
4189   Print (
4190     L"  Electromechanical Interlock Present(17):            %E%d%N\n",
4191     PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap)
4192    );
4193   Print (
4194     L"  No Command Completed Support(18):                   %E%d%N\n",
4195     PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap)
4196    );
4197   Print (
4198     L"  Physical Slot Number(31:19):                        %E%d%N\n",
4199     PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap)
4200    );
4201
4202   return EFI_SUCCESS;
4203 }
4204
4205 EFI_STATUS
4206 ExplainPcieSlotControl (
4207   IN PCIE_CAP_STURCTURE *PciExpressCap
4208 )
4209 {
4210   UINT16 PcieSlotControl;
4211
4212   PcieSlotControl = PciExpressCap->SlotControl;
4213   Print (
4214     L"  Attention Button Pressed Enable(0):                 %E%d%N\n",
4215     PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl)
4216    );
4217   Print (
4218     L"  Power Fault Detected Enable(1):                     %E%d%N\n",
4219     PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl)
4220    );
4221   Print (
4222     L"  MRL Sensor Changed Enable(2):                       %E%d%N\n",
4223     PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)
4224    );
4225   Print (
4226     L"  Presence Detect Changed Enable(3):                  %E%d%N\n",
4227     PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)
4228    );
4229   Print (
4230     L"  Command Completed Interrupt Enable(4):              %E%d%N\n",
4231     PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl)
4232    );
4233   Print (
4234     L"  Hot-Plug Interrupt Enable(5):                       %E%d%N\n",
4235     PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl)
4236    );
4237   Print (
4238     L"  Attention Indicator Control(7:6):                   %E%s%N\n",
4239     IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]
4240    );
4241   Print (
4242     L"  Power Indicator Control(9:8):                       %E%s%N\n",
4243     IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]
4244    );
4245   Print (L"  Power Controller Control(10):                       %EPower ");
4246   if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {
4247     Print (L"Off%N\n");
4248   } else {
4249     Print (L"On%N\n");
4250   }
4251   Print (
4252     L"  Electromechanical Interlock Control(11):            %E%d%N\n",
4253     PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl)
4254    );
4255   Print (
4256     L"  Data Link Layer State Changed Enable(12):           %E%d%N\n",
4257     PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)
4258    );
4259   return EFI_SUCCESS;
4260 }
4261
4262 EFI_STATUS
4263 ExplainPcieSlotStatus (
4264   IN PCIE_CAP_STURCTURE *PciExpressCap
4265 )
4266 {
4267   UINT16 PcieSlotStatus;
4268
4269   PcieSlotStatus = PciExpressCap->SlotStatus;
4270
4271   Print (
4272     L"  Attention Button Pressed(0):           %E%d%N\n",
4273     PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus)
4274    );
4275   Print (
4276     L"  Power Fault Detected(1):               %E%d%N\n",
4277     PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus)
4278    );
4279   Print (
4280     L"  MRL Sensor Changed(2):                 %E%d%N\n",
4281     PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus)
4282    );
4283   Print (
4284     L"  Presence Detect Changed(3):            %E%d%N\n",
4285     PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus)
4286    );
4287   Print (
4288     L"  Command Completed(4):                  %E%d%N\n",
4289     PCIE_CAP_COMM_COMPLETED (PcieSlotStatus)
4290    );
4291   Print (L"  MRL Sensor State(5):                   %EMRL ");
4292   if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {
4293     Print (L" Opened%N\n");
4294   } else {
4295     Print (L" Closed%N\n");
4296   }
4297   Print (L"  Presence Detect State(6):              ");
4298   if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {
4299     Print (L"%ECard Present in slot%N\n");
4300   } else {
4301     Print (L"%ESlot Empty%N\n");
4302   }
4303   Print (L"  Electromechanical Interlock Status(7): %EElectromechanical Interlock ");
4304   if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {
4305     Print (L"Engaged%N\n");
4306   } else {
4307     Print (L"Disengaged%N\n");
4308   }
4309   Print (
4310     L"  Data Link Layer State Changed(8):      %E%d%N\n",
4311     PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus)
4312    );
4313   return EFI_SUCCESS;
4314 }
4315
4316 EFI_STATUS
4317 ExplainPcieRootControl (
4318   IN PCIE_CAP_STURCTURE *PciExpressCap
4319 )
4320 {
4321   UINT16 PcieRootControl;
4322
4323   PcieRootControl = PciExpressCap->RootControl;
4324
4325   Print (
4326     L"  System Error on Correctable Error Enable(0):  %E%d%N\n",
4327     PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl)
4328    );
4329   Print (
4330     L"  System Error on Non-Fatal Error Enable(1):    %E%d%N\n",
4331     PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl)
4332    );
4333   Print (
4334     L"  System Error on Fatal Error Enable(2):        %E%d%N\n",
4335     PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl)
4336    );
4337   Print (
4338     L"  PME Interrupt Enable(3):                      %E%d%N\n",
4339     PCIE_CAP_PME_INT_ENABLE (PcieRootControl)
4340    );
4341   Print (
4342     L"  CRS Software Visibility Enable(4):            %E%d%N\n",
4343     PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl)
4344    );
4345
4346   return EFI_SUCCESS;
4347 }
4348
4349 EFI_STATUS
4350 ExplainPcieRootCap (
4351   IN PCIE_CAP_STURCTURE *PciExpressCap
4352 )
4353 {
4354   UINT16 PcieRootCap;
4355
4356   PcieRootCap = PciExpressCap->RsvdP;
4357
4358   Print (
4359     L"  CRS Software Visibility(0):                   %E%d%N\n",
4360     PCIE_CAP_CRS_SW_VIS (PcieRootCap)
4361    );
4362
4363   return EFI_SUCCESS;
4364 }
4365
4366 EFI_STATUS
4367 ExplainPcieRootStatus (
4368   IN PCIE_CAP_STURCTURE *PciExpressCap
4369 )
4370 {
4371   UINT32 PcieRootStatus;
4372
4373   PcieRootStatus = PciExpressCap->RootStatus;
4374
4375   Print (
4376     L"  PME Requester ID(15:0):                       %E0x%04x%N\n",
4377     PCIE_CAP_PME_REQ_ID (PcieRootStatus)
4378    );
4379   Print (
4380     L"  PME Status(16):                               %E%d%N\n",
4381     PCIE_CAP_PME_STATUS (PcieRootStatus)
4382    );
4383   Print (
4384     L"  PME Pending(17):                              %E%d%N\n",
4385     PCIE_CAP_PME_PENDING (PcieRootStatus)
4386    );
4387   return EFI_SUCCESS;
4388 }
4389
4390 EFI_STATUS
4391 PciExplainPciExpress (
4392   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         *IoDev,
4393   IN  UINT64                                  Address,
4394   IN  UINT8                                   CapabilityPtr
4395   )
4396 {
4397
4398   PCIE_CAP_STURCTURE  PciExpressCap;
4399   EFI_STATUS          Status;
4400   UINT64              CapRegAddress;
4401   UINT8               Bus;
4402   UINT8               Dev;
4403   UINT8               Func;
4404   UINT8               *ExRegBuffer;
4405   UINTN               ExtendRegSize;
4406   UINT64              Pciex_Address;
4407   UINT8               DevicePortType;
4408   UINTN               Index;
4409   UINT8               *RegAddr;
4410   UINTN               RegValue;
4411
4412   CapRegAddress = Address + CapabilityPtr;
4413   IoDev->Pci.Read (
4414               IoDev,
4415               EfiPciWidthUint32,
4416               CapRegAddress,
4417               sizeof (PciExpressCap) / sizeof (UINT32),
4418               &PciExpressCap
4419              );
4420
4421   DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);
4422
4423   Print (L"\nPci Express device capability structure:\n");
4424
4425   for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {
4426     if (ShellGetExecutionBreakFlag()) {
4427       goto Done;
4428     }
4429     RegAddr = ((UINT8 *) &PciExpressCap) + PcieExplainList[Index].Offset;
4430     switch (PcieExplainList[Index].Width) {
4431       case FieldWidthUINT8:
4432         RegValue = *(UINT8 *) RegAddr;
4433         break;
4434       case FieldWidthUINT16:
4435         RegValue = *(UINT16 *) RegAddr;
4436         break;
4437       case FieldWidthUINT32:
4438         RegValue = *(UINT32 *) RegAddr;
4439         break;
4440       default:
4441         RegValue = 0;
4442         break;
4443     }
4444     ShellPrintHiiEx(-1, -1, NULL,
4445       PcieExplainList[Index].Token,
4446       gShellDebug1HiiHandle,
4447       PcieExplainList[Index].Offset,
4448       RegValue
4449      );
4450     if (PcieExplainList[Index].Func == NULL) {
4451       continue;
4452     }
4453     switch (PcieExplainList[Index].Type) {
4454       case PcieExplainTypeLink:
4455         //
4456         // Link registers should not be used by
4457         // a) Root Complex Integrated Endpoint
4458         // b) Root Complex Event Collector
4459         //
4460         if (DevicePortType == PCIE_ROOT_COMPLEX_INTEGRATED_PORT ||
4461             DevicePortType == PCIE_ROOT_COMPLEX_EVENT_COLLECTOR) {
4462           continue;
4463         }
4464         break;
4465       case PcieExplainTypeSlot:
4466         //
4467         // Slot registers are only valid for
4468         // a) Root Port of PCI Express Root Complex
4469         // b) Downstream Port of PCI Express Switch
4470         // and when SlotImplemented bit is set in PCIE cap register.
4471         //
4472         if ((DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT &&
4473              DevicePortType != PCIE_SWITCH_DOWNSTREAM_PORT) ||
4474             !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap.PcieCapReg)) {
4475           continue;
4476         }
4477         break;
4478       case PcieExplainTypeRoot:
4479         //
4480         // Root registers are only valid for
4481         // Root Port of PCI Express Root Complex
4482         //
4483         if (DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT) {
4484           continue;
4485         }
4486         break;
4487       default:
4488         break;
4489     }
4490     PcieExplainList[Index].Func (&PciExpressCap);
4491   }
4492
4493   Bus           = (UINT8) (RShiftU64 (Address, 24));
4494   Dev           = (UINT8) (RShiftU64 (Address, 16));
4495   Func          = (UINT8) (RShiftU64 (Address, 8));
4496
4497   Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, 0x100);
4498
4499   ExtendRegSize = 0x1000 - 0x100;
4500
4501   ExRegBuffer   = (UINT8 *) AllocateZeroPool (ExtendRegSize);
4502
4503   //
4504   // PciRootBridgeIo protocol should support pci express extend space IO
4505   // (Begins at offset 0x100)
4506   //
4507   Status = IoDev->Pci.Read (
4508                         IoDev,
4509                         EfiPciWidthUint32,
4510                         Pciex_Address,
4511                         (ExtendRegSize) / sizeof (UINT32),
4512                         (VOID *) (ExRegBuffer)
4513                        );
4514   if (EFI_ERROR (Status)) {
4515     FreePool ((VOID *) ExRegBuffer);
4516     return EFI_UNSUPPORTED;
4517   }
4518   //
4519   // Start outputing PciEx extend space( 0xFF-0xFFF)
4520   //
4521   Print (L"\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\n\n");
4522
4523   PrivateDumpHex (
4524     2,
4525     0x100,
4526     ExtendRegSize,
4527     (VOID *) (ExRegBuffer)
4528    );
4529
4530   FreePool ((VOID *) ExRegBuffer);
4531
4532 Done:
4533   return EFI_SUCCESS;
4534 }