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UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm
[mirror_edk2.git] / ShellPkg / Library / UefiShellDebug1CommandsLib / Pci.c
1 /** @file
2 Main file for Pci shell Debug1 function.
3
4 Copyright (c) 2005 - 2021, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.<BR>
6 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
8
9 **/
10
11 #include "UefiShellDebug1CommandsLib.h"
12 #include <Protocol/PciRootBridgeIo.h>
13 #include <Library/ShellLib.h>
14 #include <IndustryStandard/Pci.h>
15 #include <IndustryStandard/Acpi.h>
16 #include "Pci.h"
17
18 //
19 // Printable strings for Pci class code
20 //
21 typedef struct {
22 CHAR16 *BaseClass; // Pointer to the PCI base class string
23 CHAR16 *SubClass; // Pointer to the PCI sub class string
24 CHAR16 *PIFClass; // Pointer to the PCI programming interface string
25 } PCI_CLASS_STRINGS;
26
27 //
28 // a structure holding a single entry, which also points to its lower level
29 // class
30 //
31 typedef struct PCI_CLASS_ENTRY_TAG {
32 UINT8 Code; // Class, subclass or I/F code
33 CHAR16 *DescText; // Description string
34 struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any
35 } PCI_CLASS_ENTRY;
36
37 //
38 // Declarations of entries which contain printable strings for class codes
39 // in PCI configuration space
40 //
41 PCI_CLASS_ENTRY PCIBlankEntry[];
42 PCI_CLASS_ENTRY PCISubClass_00[];
43 PCI_CLASS_ENTRY PCISubClass_01[];
44 PCI_CLASS_ENTRY PCISubClass_02[];
45 PCI_CLASS_ENTRY PCISubClass_03[];
46 PCI_CLASS_ENTRY PCISubClass_04[];
47 PCI_CLASS_ENTRY PCISubClass_05[];
48 PCI_CLASS_ENTRY PCISubClass_06[];
49 PCI_CLASS_ENTRY PCISubClass_07[];
50 PCI_CLASS_ENTRY PCISubClass_08[];
51 PCI_CLASS_ENTRY PCISubClass_09[];
52 PCI_CLASS_ENTRY PCISubClass_0a[];
53 PCI_CLASS_ENTRY PCISubClass_0b[];
54 PCI_CLASS_ENTRY PCISubClass_0c[];
55 PCI_CLASS_ENTRY PCISubClass_0d[];
56 PCI_CLASS_ENTRY PCISubClass_0e[];
57 PCI_CLASS_ENTRY PCISubClass_0f[];
58 PCI_CLASS_ENTRY PCISubClass_10[];
59 PCI_CLASS_ENTRY PCISubClass_11[];
60 PCI_CLASS_ENTRY PCISubClass_12[];
61 PCI_CLASS_ENTRY PCISubClass_13[];
62 PCI_CLASS_ENTRY PCIPIFClass_0100[];
63 PCI_CLASS_ENTRY PCIPIFClass_0101[];
64 PCI_CLASS_ENTRY PCIPIFClass_0105[];
65 PCI_CLASS_ENTRY PCIPIFClass_0106[];
66 PCI_CLASS_ENTRY PCIPIFClass_0107[];
67 PCI_CLASS_ENTRY PCIPIFClass_0108[];
68 PCI_CLASS_ENTRY PCIPIFClass_0109[];
69 PCI_CLASS_ENTRY PCIPIFClass_0300[];
70 PCI_CLASS_ENTRY PCIPIFClass_0604[];
71 PCI_CLASS_ENTRY PCIPIFClass_0609[];
72 PCI_CLASS_ENTRY PCIPIFClass_060b[];
73 PCI_CLASS_ENTRY PCIPIFClass_0700[];
74 PCI_CLASS_ENTRY PCIPIFClass_0701[];
75 PCI_CLASS_ENTRY PCIPIFClass_0703[];
76 PCI_CLASS_ENTRY PCIPIFClass_0800[];
77 PCI_CLASS_ENTRY PCIPIFClass_0801[];
78 PCI_CLASS_ENTRY PCIPIFClass_0802[];
79 PCI_CLASS_ENTRY PCIPIFClass_0803[];
80 PCI_CLASS_ENTRY PCIPIFClass_0904[];
81 PCI_CLASS_ENTRY PCIPIFClass_0c00[];
82 PCI_CLASS_ENTRY PCIPIFClass_0c03[];
83 PCI_CLASS_ENTRY PCIPIFClass_0c07[];
84 PCI_CLASS_ENTRY PCIPIFClass_0d01[];
85 PCI_CLASS_ENTRY PCIPIFClass_0e00[];
86
87 //
88 // Base class strings entries
89 //
90 PCI_CLASS_ENTRY gClassStringList[] = {
91 {
92 0x00,
93 L"Pre 2.0 device",
94 PCISubClass_00
95 },
96 {
97 0x01,
98 L"Mass Storage Controller",
99 PCISubClass_01
100 },
101 {
102 0x02,
103 L"Network Controller",
104 PCISubClass_02
105 },
106 {
107 0x03,
108 L"Display Controller",
109 PCISubClass_03
110 },
111 {
112 0x04,
113 L"Multimedia Device",
114 PCISubClass_04
115 },
116 {
117 0x05,
118 L"Memory Controller",
119 PCISubClass_05
120 },
121 {
122 0x06,
123 L"Bridge Device",
124 PCISubClass_06
125 },
126 {
127 0x07,
128 L"Simple Communications Controllers",
129 PCISubClass_07
130 },
131 {
132 0x08,
133 L"Base System Peripherals",
134 PCISubClass_08
135 },
136 {
137 0x09,
138 L"Input Devices",
139 PCISubClass_09
140 },
141 {
142 0x0a,
143 L"Docking Stations",
144 PCISubClass_0a
145 },
146 {
147 0x0b,
148 L"Processors",
149 PCISubClass_0b
150 },
151 {
152 0x0c,
153 L"Serial Bus Controllers",
154 PCISubClass_0c
155 },
156 {
157 0x0d,
158 L"Wireless Controllers",
159 PCISubClass_0d
160 },
161 {
162 0x0e,
163 L"Intelligent IO Controllers",
164 PCISubClass_0e
165 },
166 {
167 0x0f,
168 L"Satellite Communications Controllers",
169 PCISubClass_0f
170 },
171 {
172 0x10,
173 L"Encryption/Decryption Controllers",
174 PCISubClass_10
175 },
176 {
177 0x11,
178 L"Data Acquisition & Signal Processing Controllers",
179 PCISubClass_11
180 },
181 {
182 0x12,
183 L"Processing Accelerators",
184 PCISubClass_12
185 },
186 {
187 0x13,
188 L"Non-Essential Instrumentation",
189 PCISubClass_13
190 },
191 {
192 0xff,
193 L"Device does not fit in any defined classes",
194 PCIBlankEntry
195 },
196 {
197 0x00,
198 NULL,
199 /* null string ends the list */ NULL
200 }
201 };
202
203 //
204 // Subclass strings entries
205 //
206 PCI_CLASS_ENTRY PCIBlankEntry[] = {
207 {
208 0x00,
209 L"",
210 PCIBlankEntry
211 },
212 {
213 0x00,
214 NULL,
215 /* null string ends the list */ NULL
216 }
217 };
218
219 PCI_CLASS_ENTRY PCISubClass_00[] = {
220 {
221 0x00,
222 L"All devices other than VGA",
223 PCIBlankEntry
224 },
225 {
226 0x01,
227 L"VGA-compatible devices",
228 PCIBlankEntry
229 },
230 {
231 0x00,
232 NULL,
233 /* null string ends the list */ NULL
234 }
235 };
236
237 PCI_CLASS_ENTRY PCISubClass_01[] = {
238 {
239 0x00,
240 L"SCSI",
241 PCIPIFClass_0100
242 },
243 {
244 0x01,
245 L"IDE controller",
246 PCIPIFClass_0101
247 },
248 {
249 0x02,
250 L"Floppy disk controller",
251 PCIBlankEntry
252 },
253 {
254 0x03,
255 L"IPI controller",
256 PCIBlankEntry
257 },
258 {
259 0x04,
260 L"RAID controller",
261 PCIBlankEntry
262 },
263 {
264 0x05,
265 L"ATA controller with ADMA interface",
266 PCIPIFClass_0105
267 },
268 {
269 0x06,
270 L"Serial ATA controller",
271 PCIPIFClass_0106
272 },
273 {
274 0x07,
275 L"Serial Attached SCSI (SAS) controller ",
276 PCIPIFClass_0107
277 },
278 {
279 0x08,
280 L"Non-volatile memory subsystem",
281 PCIPIFClass_0108
282 },
283 {
284 0x09,
285 L"Universal Flash Storage (UFS) controller ",
286 PCIPIFClass_0109
287 },
288 {
289 0x80,
290 L"Other mass storage controller",
291 PCIBlankEntry
292 },
293 {
294 0x00,
295 NULL,
296 /* null string ends the list */ NULL
297 }
298 };
299
300 PCI_CLASS_ENTRY PCISubClass_02[] = {
301 {
302 0x00,
303 L"Ethernet controller",
304 PCIBlankEntry
305 },
306 {
307 0x01,
308 L"Token ring controller",
309 PCIBlankEntry
310 },
311 {
312 0x02,
313 L"FDDI controller",
314 PCIBlankEntry
315 },
316 {
317 0x03,
318 L"ATM controller",
319 PCIBlankEntry
320 },
321 {
322 0x04,
323 L"ISDN controller",
324 PCIBlankEntry
325 },
326 {
327 0x05,
328 L"WorldFip controller",
329 PCIBlankEntry
330 },
331 {
332 0x06,
333 L"PICMG 2.14 Multi Computing",
334 PCIBlankEntry
335 },
336 {
337 0x07,
338 L"InfiniBand controller",
339 PCIBlankEntry
340 },
341 {
342 0x80,
343 L"Other network controller",
344 PCIBlankEntry
345 },
346 {
347 0x00,
348 NULL,
349 /* null string ends the list */ NULL
350 }
351 };
352
353 PCI_CLASS_ENTRY PCISubClass_03[] = {
354 {
355 0x00,
356 L"VGA/8514 controller",
357 PCIPIFClass_0300
358 },
359 {
360 0x01,
361 L"XGA controller",
362 PCIBlankEntry
363 },
364 {
365 0x02,
366 L"3D controller",
367 PCIBlankEntry
368 },
369 {
370 0x80,
371 L"Other display controller",
372 PCIBlankEntry
373 },
374 {
375 0x00,
376 NULL,
377 /* null string ends the list */ PCIBlankEntry
378 }
379 };
380
381 PCI_CLASS_ENTRY PCISubClass_04[] = {
382 {
383 0x00,
384 L"Video device",
385 PCIBlankEntry
386 },
387 {
388 0x01,
389 L"Audio device",
390 PCIBlankEntry
391 },
392 {
393 0x02,
394 L"Computer Telephony device",
395 PCIBlankEntry
396 },
397 {
398 0x03,
399 L"Mixed mode device",
400 PCIBlankEntry
401 },
402 {
403 0x80,
404 L"Other multimedia device",
405 PCIBlankEntry
406 },
407 {
408 0x00,
409 NULL,
410 /* null string ends the list */ NULL
411 }
412 };
413
414 PCI_CLASS_ENTRY PCISubClass_05[] = {
415 {
416 0x00,
417 L"RAM memory controller",
418 PCIBlankEntry
419 },
420 {
421 0x01,
422 L"Flash memory controller",
423 PCIBlankEntry
424 },
425 {
426 0x80,
427 L"Other memory controller",
428 PCIBlankEntry
429 },
430 {
431 0x00,
432 NULL,
433 /* null string ends the list */ NULL
434 }
435 };
436
437 PCI_CLASS_ENTRY PCISubClass_06[] = {
438 {
439 0x00,
440 L"Host/PCI bridge",
441 PCIBlankEntry
442 },
443 {
444 0x01,
445 L"PCI/ISA bridge",
446 PCIBlankEntry
447 },
448 {
449 0x02,
450 L"PCI/EISA bridge",
451 PCIBlankEntry
452 },
453 {
454 0x03,
455 L"PCI/Micro Channel bridge",
456 PCIBlankEntry
457 },
458 {
459 0x04,
460 L"PCI/PCI bridge",
461 PCIPIFClass_0604
462 },
463 {
464 0x05,
465 L"PCI/PCMCIA bridge",
466 PCIBlankEntry
467 },
468 {
469 0x06,
470 L"NuBus bridge",
471 PCIBlankEntry
472 },
473 {
474 0x07,
475 L"CardBus bridge",
476 PCIBlankEntry
477 },
478 {
479 0x08,
480 L"RACEway bridge",
481 PCIBlankEntry
482 },
483 {
484 0x09,
485 L"Semi-transparent PCI-to-PCI bridge",
486 PCIPIFClass_0609
487 },
488 {
489 0x0A,
490 L"InfiniBand-to-PCI host bridge",
491 PCIBlankEntry
492 },
493 {
494 0x0B,
495 L"Advanced Switching to PCI host bridge",
496 PCIPIFClass_060b
497 },
498 {
499 0x80,
500 L"Other bridge type",
501 PCIBlankEntry
502 },
503 {
504 0x00,
505 NULL,
506 /* null string ends the list */ NULL
507 }
508 };
509
510 PCI_CLASS_ENTRY PCISubClass_07[] = {
511 {
512 0x00,
513 L"Serial controller",
514 PCIPIFClass_0700
515 },
516 {
517 0x01,
518 L"Parallel port",
519 PCIPIFClass_0701
520 },
521 {
522 0x02,
523 L"Multiport serial controller",
524 PCIBlankEntry
525 },
526 {
527 0x03,
528 L"Modem",
529 PCIPIFClass_0703
530 },
531 {
532 0x04,
533 L"GPIB (IEEE 488.1/2) controller",
534 PCIBlankEntry
535 },
536 {
537 0x05,
538 L"Smart Card",
539 PCIBlankEntry
540 },
541 {
542 0x80,
543 L"Other communication device",
544 PCIBlankEntry
545 },
546 {
547 0x00,
548 NULL,
549 /* null string ends the list */ NULL
550 }
551 };
552
553 PCI_CLASS_ENTRY PCISubClass_08[] = {
554 {
555 0x00,
556 L"PIC",
557 PCIPIFClass_0800
558 },
559 {
560 0x01,
561 L"DMA controller",
562 PCIPIFClass_0801
563 },
564 {
565 0x02,
566 L"System timer",
567 PCIPIFClass_0802
568 },
569 {
570 0x03,
571 L"RTC controller",
572 PCIPIFClass_0803
573 },
574 {
575 0x04,
576 L"Generic PCI Hot-Plug controller",
577 PCIBlankEntry
578 },
579 {
580 0x05,
581 L"SD Host controller",
582 PCIBlankEntry
583 },
584 {
585 0x06,
586 L"IOMMU",
587 PCIBlankEntry
588 },
589 {
590 0x07,
591 L"Root Complex Event Collector",
592 PCIBlankEntry
593 },
594 {
595 0x80,
596 L"Other system peripheral",
597 PCIBlankEntry
598 },
599 {
600 0x00,
601 NULL,
602 /* null string ends the list */ NULL
603 }
604 };
605
606 PCI_CLASS_ENTRY PCISubClass_09[] = {
607 {
608 0x00,
609 L"Keyboard controller",
610 PCIBlankEntry
611 },
612 {
613 0x01,
614 L"Digitizer (pen)",
615 PCIBlankEntry
616 },
617 {
618 0x02,
619 L"Mouse controller",
620 PCIBlankEntry
621 },
622 {
623 0x03,
624 L"Scanner controller",
625 PCIBlankEntry
626 },
627 {
628 0x04,
629 L"Gameport controller",
630 PCIPIFClass_0904
631 },
632 {
633 0x80,
634 L"Other input controller",
635 PCIBlankEntry
636 },
637 {
638 0x00,
639 NULL,
640 /* null string ends the list */ NULL
641 }
642 };
643
644 PCI_CLASS_ENTRY PCISubClass_0a[] = {
645 {
646 0x00,
647 L"Generic docking station",
648 PCIBlankEntry
649 },
650 {
651 0x80,
652 L"Other type of docking station",
653 PCIBlankEntry
654 },
655 {
656 0x00,
657 NULL,
658 /* null string ends the list */ NULL
659 }
660 };
661
662 PCI_CLASS_ENTRY PCISubClass_0b[] = {
663 {
664 0x00,
665 L"386",
666 PCIBlankEntry
667 },
668 {
669 0x01,
670 L"486",
671 PCIBlankEntry
672 },
673 {
674 0x02,
675 L"Pentium",
676 PCIBlankEntry
677 },
678 {
679 0x10,
680 L"Alpha",
681 PCIBlankEntry
682 },
683 {
684 0x20,
685 L"PowerPC",
686 PCIBlankEntry
687 },
688 {
689 0x30,
690 L"MIPS",
691 PCIBlankEntry
692 },
693 {
694 0x40,
695 L"Co-processor",
696 PCIBlankEntry
697 },
698 {
699 0x80,
700 L"Other processor",
701 PCIBlankEntry
702 },
703 {
704 0x00,
705 NULL,
706 /* null string ends the list */ NULL
707 }
708 };
709
710 PCI_CLASS_ENTRY PCISubClass_0c[] = {
711 {
712 0x00,
713 L"IEEE 1394",
714 PCIPIFClass_0c00
715 },
716 {
717 0x01,
718 L"ACCESS.bus",
719 PCIBlankEntry
720 },
721 {
722 0x02,
723 L"SSA",
724 PCIBlankEntry
725 },
726 {
727 0x03,
728 L"USB",
729 PCIPIFClass_0c03
730 },
731 {
732 0x04,
733 L"Fibre Channel",
734 PCIBlankEntry
735 },
736 {
737 0x05,
738 L"System Management Bus",
739 PCIBlankEntry
740 },
741 {
742 0x06,
743 L"InfiniBand",
744 PCIBlankEntry
745 },
746 {
747 0x07,
748 L"IPMI",
749 PCIPIFClass_0c07
750 },
751 {
752 0x08,
753 L"SERCOS Interface Standard (IEC 61491)",
754 PCIBlankEntry
755 },
756 {
757 0x09,
758 L"CANbus",
759 PCIBlankEntry
760 },
761 {
762 0x80,
763 L"Other bus type",
764 PCIBlankEntry
765 },
766 {
767 0x00,
768 NULL,
769 /* null string ends the list */ NULL
770 }
771 };
772
773 PCI_CLASS_ENTRY PCISubClass_0d[] = {
774 {
775 0x00,
776 L"iRDA compatible controller",
777 PCIBlankEntry
778 },
779 {
780 0x01,
781 L"",
782 PCIPIFClass_0d01
783 },
784 {
785 0x10,
786 L"RF controller",
787 PCIBlankEntry
788 },
789 {
790 0x11,
791 L"Bluetooth",
792 PCIBlankEntry
793 },
794 {
795 0x12,
796 L"Broadband",
797 PCIBlankEntry
798 },
799 {
800 0x20,
801 L"Ethernet (802.11a - 5 GHz)",
802 PCIBlankEntry
803 },
804 {
805 0x21,
806 L"Ethernet (802.11b - 2.4 GHz)",
807 PCIBlankEntry
808 },
809 {
810 0x80,
811 L"Other type of wireless controller",
812 PCIBlankEntry
813 },
814 {
815 0x00,
816 NULL,
817 /* null string ends the list */ NULL
818 }
819 };
820
821 PCI_CLASS_ENTRY PCISubClass_0e[] = {
822 {
823 0x00,
824 L"I2O Architecture",
825 PCIPIFClass_0e00
826 },
827 {
828 0x00,
829 NULL,
830 /* null string ends the list */ NULL
831 }
832 };
833
834 PCI_CLASS_ENTRY PCISubClass_0f[] = {
835 {
836 0x01,
837 L"TV",
838 PCIBlankEntry
839 },
840 {
841 0x02,
842 L"Audio",
843 PCIBlankEntry
844 },
845 {
846 0x03,
847 L"Voice",
848 PCIBlankEntry
849 },
850 {
851 0x04,
852 L"Data",
853 PCIBlankEntry
854 },
855 {
856 0x80,
857 L"Other satellite communication controller",
858 PCIBlankEntry
859 },
860 {
861 0x00,
862 NULL,
863 /* null string ends the list */ NULL
864 }
865 };
866
867 PCI_CLASS_ENTRY PCISubClass_10[] = {
868 {
869 0x00,
870 L"Network & computing Encrypt/Decrypt",
871 PCIBlankEntry
872 },
873 {
874 0x01,
875 L"Entertainment Encrypt/Decrypt",
876 PCIBlankEntry
877 },
878 {
879 0x80,
880 L"Other Encrypt/Decrypt",
881 PCIBlankEntry
882 },
883 {
884 0x00,
885 NULL,
886 /* null string ends the list */ NULL
887 }
888 };
889
890 PCI_CLASS_ENTRY PCISubClass_11[] = {
891 {
892 0x00,
893 L"DPIO modules",
894 PCIBlankEntry
895 },
896 {
897 0x01,
898 L"Performance Counters",
899 PCIBlankEntry
900 },
901 {
902 0x10,
903 L"Communications synchronization plus time and frequency test/measurement ",
904 PCIBlankEntry
905 },
906 {
907 0x20,
908 L"Management card",
909 PCIBlankEntry
910 },
911 {
912 0x80,
913 L"Other DAQ & SP controllers",
914 PCIBlankEntry
915 },
916 {
917 0x00,
918 NULL,
919 /* null string ends the list */ NULL
920 }
921 };
922
923 PCI_CLASS_ENTRY PCISubClass_12[] = {
924 {
925 0x00,
926 L"Processing Accelerator",
927 PCIBlankEntry
928 },
929 {
930 0x00,
931 NULL,
932 /* null string ends the list */ NULL
933 }
934 };
935
936 PCI_CLASS_ENTRY PCISubClass_13[] = {
937 {
938 0x00,
939 L"Non-Essential Instrumentation Function",
940 PCIBlankEntry
941 },
942 {
943 0x00,
944 NULL,
945 /* null string ends the list */ NULL
946 }
947 };
948
949 //
950 // Programming Interface entries
951 //
952 PCI_CLASS_ENTRY PCIPIFClass_0100[] = {
953 {
954 0x00,
955 L"SCSI controller",
956 PCIBlankEntry
957 },
958 {
959 0x11,
960 L"SCSI storage device SOP using PQI",
961 PCIBlankEntry
962 },
963 {
964 0x12,
965 L"SCSI controller SOP using PQI",
966 PCIBlankEntry
967 },
968 {
969 0x13,
970 L"SCSI storage device and controller SOP using PQI",
971 PCIBlankEntry
972 },
973 {
974 0x21,
975 L"SCSI storage device SOP using NVMe",
976 PCIBlankEntry
977 },
978 {
979 0x00,
980 NULL,
981 /* null string ends the list */ NULL
982 }
983 };
984
985 PCI_CLASS_ENTRY PCIPIFClass_0101[] = {
986 {
987 0x00,
988 L"",
989 PCIBlankEntry
990 },
991 {
992 0x01,
993 L"OM-primary",
994 PCIBlankEntry
995 },
996 {
997 0x02,
998 L"PI-primary",
999 PCIBlankEntry
1000 },
1001 {
1002 0x03,
1003 L"OM/PI-primary",
1004 PCIBlankEntry
1005 },
1006 {
1007 0x04,
1008 L"OM-secondary",
1009 PCIBlankEntry
1010 },
1011 {
1012 0x05,
1013 L"OM-primary, OM-secondary",
1014 PCIBlankEntry
1015 },
1016 {
1017 0x06,
1018 L"PI-primary, OM-secondary",
1019 PCIBlankEntry
1020 },
1021 {
1022 0x07,
1023 L"OM/PI-primary, OM-secondary",
1024 PCIBlankEntry
1025 },
1026 {
1027 0x08,
1028 L"OM-secondary",
1029 PCIBlankEntry
1030 },
1031 {
1032 0x09,
1033 L"OM-primary, PI-secondary",
1034 PCIBlankEntry
1035 },
1036 {
1037 0x0a,
1038 L"PI-primary, PI-secondary",
1039 PCIBlankEntry
1040 },
1041 {
1042 0x0b,
1043 L"OM/PI-primary, PI-secondary",
1044 PCIBlankEntry
1045 },
1046 {
1047 0x0c,
1048 L"OM-secondary",
1049 PCIBlankEntry
1050 },
1051 {
1052 0x0d,
1053 L"OM-primary, OM/PI-secondary",
1054 PCIBlankEntry
1055 },
1056 {
1057 0x0e,
1058 L"PI-primary, OM/PI-secondary",
1059 PCIBlankEntry
1060 },
1061 {
1062 0x0f,
1063 L"OM/PI-primary, OM/PI-secondary",
1064 PCIBlankEntry
1065 },
1066 {
1067 0x80,
1068 L"Master",
1069 PCIBlankEntry
1070 },
1071 {
1072 0x81,
1073 L"Master, OM-primary",
1074 PCIBlankEntry
1075 },
1076 {
1077 0x82,
1078 L"Master, PI-primary",
1079 PCIBlankEntry
1080 },
1081 {
1082 0x83,
1083 L"Master, OM/PI-primary",
1084 PCIBlankEntry
1085 },
1086 {
1087 0x84,
1088 L"Master, OM-secondary",
1089 PCIBlankEntry
1090 },
1091 {
1092 0x85,
1093 L"Master, OM-primary, OM-secondary",
1094 PCIBlankEntry
1095 },
1096 {
1097 0x86,
1098 L"Master, PI-primary, OM-secondary",
1099 PCIBlankEntry
1100 },
1101 {
1102 0x87,
1103 L"Master, OM/PI-primary, OM-secondary",
1104 PCIBlankEntry
1105 },
1106 {
1107 0x88,
1108 L"Master, OM-secondary",
1109 PCIBlankEntry
1110 },
1111 {
1112 0x89,
1113 L"Master, OM-primary, PI-secondary",
1114 PCIBlankEntry
1115 },
1116 {
1117 0x8a,
1118 L"Master, PI-primary, PI-secondary",
1119 PCIBlankEntry
1120 },
1121 {
1122 0x8b,
1123 L"Master, OM/PI-primary, PI-secondary",
1124 PCIBlankEntry
1125 },
1126 {
1127 0x8c,
1128 L"Master, OM-secondary",
1129 PCIBlankEntry
1130 },
1131 {
1132 0x8d,
1133 L"Master, OM-primary, OM/PI-secondary",
1134 PCIBlankEntry
1135 },
1136 {
1137 0x8e,
1138 L"Master, PI-primary, OM/PI-secondary",
1139 PCIBlankEntry
1140 },
1141 {
1142 0x8f,
1143 L"Master, OM/PI-primary, OM/PI-secondary",
1144 PCIBlankEntry
1145 },
1146 {
1147 0x00,
1148 NULL,
1149 /* null string ends the list */ NULL
1150 }
1151 };
1152
1153 PCI_CLASS_ENTRY PCIPIFClass_0105[] = {
1154 {
1155 0x20,
1156 L"Single stepping",
1157 PCIBlankEntry
1158 },
1159 {
1160 0x30,
1161 L"Continuous operation",
1162 PCIBlankEntry
1163 },
1164 {
1165 0x00,
1166 NULL,
1167 /* null string ends the list */ NULL
1168 }
1169 };
1170
1171 PCI_CLASS_ENTRY PCIPIFClass_0106[] = {
1172 {
1173 0x00,
1174 L"",
1175 PCIBlankEntry
1176 },
1177 {
1178 0x01,
1179 L"AHCI",
1180 PCIBlankEntry
1181 },
1182 {
1183 0x02,
1184 L"Serial Storage Bus",
1185 PCIBlankEntry
1186 },
1187 {
1188 0x00,
1189 NULL,
1190 /* null string ends the list */ NULL
1191 }
1192 };
1193
1194 PCI_CLASS_ENTRY PCIPIFClass_0107[] = {
1195 {
1196 0x00,
1197 L"",
1198 PCIBlankEntry
1199 },
1200 {
1201 0x01,
1202 L"Obsolete",
1203 PCIBlankEntry
1204 },
1205 {
1206 0x00,
1207 NULL,
1208 /* null string ends the list */ NULL
1209 }
1210 };
1211
1212 PCI_CLASS_ENTRY PCIPIFClass_0108[] = {
1213 {
1214 0x00,
1215 L"",
1216 PCIBlankEntry
1217 },
1218 {
1219 0x01,
1220 L"NVMHCI",
1221 PCIBlankEntry
1222 },
1223 {
1224 0x02,
1225 L"NVM Express",
1226 PCIBlankEntry
1227 },
1228 {
1229 0x00,
1230 NULL,
1231 /* null string ends the list */ NULL
1232 }
1233 };
1234
1235 PCI_CLASS_ENTRY PCIPIFClass_0109[] = {
1236 {
1237 0x00,
1238 L"",
1239 PCIBlankEntry
1240 },
1241 {
1242 0x01,
1243 L"UFSHCI",
1244 PCIBlankEntry
1245 },
1246 {
1247 0x00,
1248 NULL,
1249 /* null string ends the list */ NULL
1250 }
1251 };
1252
1253 PCI_CLASS_ENTRY PCIPIFClass_0300[] = {
1254 {
1255 0x00,
1256 L"VGA compatible",
1257 PCIBlankEntry
1258 },
1259 {
1260 0x01,
1261 L"8514 compatible",
1262 PCIBlankEntry
1263 },
1264 {
1265 0x00,
1266 NULL,
1267 /* null string ends the list */ NULL
1268 }
1269 };
1270
1271 PCI_CLASS_ENTRY PCIPIFClass_0604[] = {
1272 {
1273 0x00,
1274 L"",
1275 PCIBlankEntry
1276 },
1277 {
1278 0x01,
1279 L"Subtractive decode",
1280 PCIBlankEntry
1281 },
1282 {
1283 0x00,
1284 NULL,
1285 /* null string ends the list */ NULL
1286 }
1287 };
1288
1289 PCI_CLASS_ENTRY PCIPIFClass_0609[] = {
1290 {
1291 0x40,
1292 L"Primary PCI bus side facing the system host processor",
1293 PCIBlankEntry
1294 },
1295 {
1296 0x80,
1297 L"Secondary PCI bus side facing the system host processor",
1298 PCIBlankEntry
1299 },
1300 {
1301 0x00,
1302 NULL,
1303 /* null string ends the list */ NULL
1304 }
1305 };
1306
1307 PCI_CLASS_ENTRY PCIPIFClass_060b[] = {
1308 {
1309 0x00,
1310 L"Custom",
1311 PCIBlankEntry
1312 },
1313 {
1314 0x01,
1315 L"ASI-SIG Defined Portal",
1316 PCIBlankEntry
1317 },
1318 {
1319 0x00,
1320 NULL,
1321 /* null string ends the list */ NULL
1322 }
1323 };
1324
1325 PCI_CLASS_ENTRY PCIPIFClass_0700[] = {
1326 {
1327 0x00,
1328 L"Generic XT-compatible",
1329 PCIBlankEntry
1330 },
1331 {
1332 0x01,
1333 L"16450-compatible",
1334 PCIBlankEntry
1335 },
1336 {
1337 0x02,
1338 L"16550-compatible",
1339 PCIBlankEntry
1340 },
1341 {
1342 0x03,
1343 L"16650-compatible",
1344 PCIBlankEntry
1345 },
1346 {
1347 0x04,
1348 L"16750-compatible",
1349 PCIBlankEntry
1350 },
1351 {
1352 0x05,
1353 L"16850-compatible",
1354 PCIBlankEntry
1355 },
1356 {
1357 0x06,
1358 L"16950-compatible",
1359 PCIBlankEntry
1360 },
1361 {
1362 0x00,
1363 NULL,
1364 /* null string ends the list */ NULL
1365 }
1366 };
1367
1368 PCI_CLASS_ENTRY PCIPIFClass_0701[] = {
1369 {
1370 0x00,
1371 L"",
1372 PCIBlankEntry
1373 },
1374 {
1375 0x01,
1376 L"Bi-directional",
1377 PCIBlankEntry
1378 },
1379 {
1380 0x02,
1381 L"ECP 1.X-compliant",
1382 PCIBlankEntry
1383 },
1384 {
1385 0x03,
1386 L"IEEE 1284",
1387 PCIBlankEntry
1388 },
1389 {
1390 0xfe,
1391 L"IEEE 1284 target (not a controller)",
1392 PCIBlankEntry
1393 },
1394 {
1395 0x00,
1396 NULL,
1397 /* null string ends the list */ NULL
1398 }
1399 };
1400
1401 PCI_CLASS_ENTRY PCIPIFClass_0703[] = {
1402 {
1403 0x00,
1404 L"Generic",
1405 PCIBlankEntry
1406 },
1407 {
1408 0x01,
1409 L"Hayes-compatible 16450",
1410 PCIBlankEntry
1411 },
1412 {
1413 0x02,
1414 L"Hayes-compatible 16550",
1415 PCIBlankEntry
1416 },
1417 {
1418 0x03,
1419 L"Hayes-compatible 16650",
1420 PCIBlankEntry
1421 },
1422 {
1423 0x04,
1424 L"Hayes-compatible 16750",
1425 PCIBlankEntry
1426 },
1427 {
1428 0x00,
1429 NULL,
1430 /* null string ends the list */ NULL
1431 }
1432 };
1433
1434 PCI_CLASS_ENTRY PCIPIFClass_0800[] = {
1435 {
1436 0x00,
1437 L"Generic 8259",
1438 PCIBlankEntry
1439 },
1440 {
1441 0x01,
1442 L"ISA",
1443 PCIBlankEntry
1444 },
1445 {
1446 0x02,
1447 L"EISA",
1448 PCIBlankEntry
1449 },
1450 {
1451 0x10,
1452 L"IO APIC",
1453 PCIBlankEntry
1454 },
1455 {
1456 0x20,
1457 L"IO(x) APIC interrupt controller",
1458 PCIBlankEntry
1459 },
1460 {
1461 0x00,
1462 NULL,
1463 /* null string ends the list */ NULL
1464 }
1465 };
1466
1467 PCI_CLASS_ENTRY PCIPIFClass_0801[] = {
1468 {
1469 0x00,
1470 L"Generic 8237",
1471 PCIBlankEntry
1472 },
1473 {
1474 0x01,
1475 L"ISA",
1476 PCIBlankEntry
1477 },
1478 {
1479 0x02,
1480 L"EISA",
1481 PCIBlankEntry
1482 },
1483 {
1484 0x00,
1485 NULL,
1486 /* null string ends the list */ NULL
1487 }
1488 };
1489
1490 PCI_CLASS_ENTRY PCIPIFClass_0802[] = {
1491 {
1492 0x00,
1493 L"Generic 8254",
1494 PCIBlankEntry
1495 },
1496 {
1497 0x01,
1498 L"ISA",
1499 PCIBlankEntry
1500 },
1501 {
1502 0x02,
1503 L"EISA",
1504 PCIBlankEntry
1505 },
1506 {
1507 0x00,
1508 NULL,
1509 /* null string ends the list */ NULL
1510 }
1511 };
1512
1513 PCI_CLASS_ENTRY PCIPIFClass_0803[] = {
1514 {
1515 0x00,
1516 L"Generic",
1517 PCIBlankEntry
1518 },
1519 {
1520 0x01,
1521 L"ISA",
1522 PCIBlankEntry
1523 },
1524 {
1525 0x02,
1526 L"EISA",
1527 PCIBlankEntry
1528 },
1529 {
1530 0x00,
1531 NULL,
1532 /* null string ends the list */ NULL
1533 }
1534 };
1535
1536 PCI_CLASS_ENTRY PCIPIFClass_0904[] = {
1537 {
1538 0x00,
1539 L"Generic",
1540 PCIBlankEntry
1541 },
1542 {
1543 0x10,
1544 L"",
1545 PCIBlankEntry
1546 },
1547 {
1548 0x00,
1549 NULL,
1550 /* null string ends the list */ NULL
1551 }
1552 };
1553
1554 PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {
1555 {
1556 0x00,
1557 L"",
1558 PCIBlankEntry
1559 },
1560 {
1561 0x10,
1562 L"Using 1394 OpenHCI spec",
1563 PCIBlankEntry
1564 },
1565 {
1566 0x00,
1567 NULL,
1568 /* null string ends the list */ NULL
1569 }
1570 };
1571
1572 PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {
1573 {
1574 0x00,
1575 L"UHCI",
1576 PCIBlankEntry
1577 },
1578 {
1579 0x10,
1580 L"OHCI",
1581 PCIBlankEntry
1582 },
1583 {
1584 0x20,
1585 L"EHCI",
1586 PCIBlankEntry
1587 },
1588 {
1589 0x30,
1590 L"xHCI",
1591 PCIBlankEntry
1592 },
1593 {
1594 0x80,
1595 L"No specific programming interface",
1596 PCIBlankEntry
1597 },
1598 {
1599 0xfe,
1600 L"(Not Host Controller)",
1601 PCIBlankEntry
1602 },
1603 {
1604 0x00,
1605 NULL,
1606 /* null string ends the list */ NULL
1607 }
1608 };
1609
1610 PCI_CLASS_ENTRY PCIPIFClass_0c07[] = {
1611 {
1612 0x00,
1613 L"SMIC",
1614 PCIBlankEntry
1615 },
1616 {
1617 0x01,
1618 L"Keyboard Controller Style",
1619 PCIBlankEntry
1620 },
1621 {
1622 0x02,
1623 L"Block Transfer",
1624 PCIBlankEntry
1625 },
1626 {
1627 0x00,
1628 NULL,
1629 /* null string ends the list */ NULL
1630 }
1631 };
1632
1633 PCI_CLASS_ENTRY PCIPIFClass_0d01[] = {
1634 {
1635 0x00,
1636 L"Consumer IR controller",
1637 PCIBlankEntry
1638 },
1639 {
1640 0x10,
1641 L"UWB Radio controller",
1642 PCIBlankEntry
1643 },
1644 {
1645 0x00,
1646 NULL,
1647 /* null string ends the list */ NULL
1648 }
1649 };
1650
1651 PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {
1652 {
1653 0x00,
1654 L"Message FIFO at offset 40h",
1655 PCIBlankEntry
1656 },
1657 {
1658 0x01,
1659 L"",
1660 PCIBlankEntry
1661 },
1662 {
1663 0x00,
1664 NULL,
1665 /* null string ends the list */ NULL
1666 }
1667 };
1668
1669 /**
1670 Generates printable Unicode strings that represent PCI device class,
1671 subclass and programmed I/F based on a value passed to the function.
1672
1673 @param[in] ClassCode Value representing the PCI "Class Code" register read from a
1674 PCI device. The encodings are:
1675 bits 23:16 - Base Class Code
1676 bits 15:8 - Sub-Class Code
1677 bits 7:0 - Programming Interface
1678 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains
1679 printable class strings corresponding to ClassCode. The
1680 caller must not modify the strings that are pointed by
1681 the fields in ClassStrings.
1682 **/
1683 VOID
1684 PciGetClassStrings (
1685 IN UINT32 ClassCode,
1686 IN OUT PCI_CLASS_STRINGS *ClassStrings
1687 )
1688 {
1689 INTN Index;
1690 UINT8 Code;
1691 PCI_CLASS_ENTRY *CurrentClass;
1692
1693 //
1694 // Assume no strings found
1695 //
1696 ClassStrings->BaseClass = L"UNDEFINED";
1697 ClassStrings->SubClass = L"UNDEFINED";
1698 ClassStrings->PIFClass = L"UNDEFINED";
1699
1700 CurrentClass = gClassStringList;
1701 Code = (UINT8)(ClassCode >> 16);
1702 Index = 0;
1703
1704 //
1705 // Go through all entries of the base class, until the entry with a matching
1706 // base class code is found. If reaches an entry with a null description
1707 // text, the last entry is met, which means no text for the base class was
1708 // found, so no more action is needed.
1709 //
1710 while (Code != CurrentClass[Index].Code) {
1711 if (NULL == CurrentClass[Index].DescText) {
1712 return;
1713 }
1714
1715 Index++;
1716 }
1717
1718 //
1719 // A base class was found. Assign description, and check if this class has
1720 // sub-class defined. If sub-class defined, no more action is needed,
1721 // otherwise, continue to find description for the sub-class code.
1722 //
1723 ClassStrings->BaseClass = CurrentClass[Index].DescText;
1724 if (NULL == CurrentClass[Index].LowerLevelClass) {
1725 return;
1726 }
1727
1728 //
1729 // find Subclass entry
1730 //
1731 CurrentClass = CurrentClass[Index].LowerLevelClass;
1732 Code = (UINT8)(ClassCode >> 8);
1733 Index = 0;
1734
1735 //
1736 // Go through all entries of the sub-class, until the entry with a matching
1737 // sub-class code is found. If reaches an entry with a null description
1738 // text, the last entry is met, which means no text for the sub-class was
1739 // found, so no more action is needed.
1740 //
1741 while (Code != CurrentClass[Index].Code) {
1742 if (NULL == CurrentClass[Index].DescText) {
1743 return;
1744 }
1745
1746 Index++;
1747 }
1748
1749 //
1750 // A class was found for the sub-class code. Assign description, and check if
1751 // this sub-class has programming interface defined. If no, no more action is
1752 // needed, otherwise, continue to find description for the programming
1753 // interface.
1754 //
1755 ClassStrings->SubClass = CurrentClass[Index].DescText;
1756 if (NULL == CurrentClass[Index].LowerLevelClass) {
1757 return;
1758 }
1759
1760 //
1761 // Find programming interface entry
1762 //
1763 CurrentClass = CurrentClass[Index].LowerLevelClass;
1764 Code = (UINT8)ClassCode;
1765 Index = 0;
1766
1767 //
1768 // Go through all entries of the I/F entries, until the entry with a
1769 // matching I/F code is found. If reaches an entry with a null description
1770 // text, the last entry is met, which means no text was found, so no more
1771 // action is needed.
1772 //
1773 while (Code != CurrentClass[Index].Code) {
1774 if (NULL == CurrentClass[Index].DescText) {
1775 return;
1776 }
1777
1778 Index++;
1779 }
1780
1781 //
1782 // A class was found for the I/F code. Assign description, done!
1783 //
1784 ClassStrings->PIFClass = CurrentClass[Index].DescText;
1785 return;
1786 }
1787
1788 /**
1789 Print strings that represent PCI device class, subclass and programmed I/F.
1790
1791 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI
1792 configuration space.
1793 @param[in] IncludePIF If the printed string should include the programming I/F part
1794 **/
1795 VOID
1796 PciPrintClassCode (
1797 IN UINT8 *ClassCodePtr,
1798 IN BOOLEAN IncludePIF
1799 )
1800 {
1801 UINT32 ClassCode;
1802 PCI_CLASS_STRINGS ClassStrings;
1803
1804 ClassCode = 0;
1805 ClassCode |= (UINT32)ClassCodePtr[0];
1806 ClassCode |= (UINT32)(ClassCodePtr[1] << 8);
1807 ClassCode |= (UINT32)(ClassCodePtr[2] << 16);
1808
1809 //
1810 // Get name from class code
1811 //
1812 PciGetClassStrings (ClassCode, &ClassStrings);
1813
1814 if (IncludePIF) {
1815 //
1816 // Print base class, sub class, and programming inferface name
1817 //
1818 ShellPrintEx (
1819 -1,
1820 -1,
1821 L"%s - %s - %s",
1822 ClassStrings.BaseClass,
1823 ClassStrings.SubClass,
1824 ClassStrings.PIFClass
1825 );
1826 } else {
1827 //
1828 // Only print base class and sub class name
1829 //
1830 ShellPrintEx (
1831 -1,
1832 -1,
1833 L"%s - %s",
1834 ClassStrings.BaseClass,
1835 ClassStrings.SubClass
1836 );
1837 }
1838 }
1839
1840 /**
1841 This function finds out the protocol which is in charge of the given
1842 segment, and its bus range covers the current bus number. It lookes
1843 each instances of RootBridgeIoProtocol handle, until the one meets the
1844 criteria is found.
1845
1846 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1847 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1848 @param[in] Segment Segment number of device we are dealing with.
1849 @param[in] Bus Bus number of device we are dealing with.
1850 @param[out] IoDev Handle used to access configuration space of PCI device.
1851
1852 @retval EFI_SUCCESS The command completed successfully.
1853 @retval EFI_INVALID_PARAMETER Invalid parameter.
1854
1855 **/
1856 EFI_STATUS
1857 PciFindProtocolInterface (
1858 IN EFI_HANDLE *HandleBuf,
1859 IN UINTN HandleCount,
1860 IN UINT16 Segment,
1861 IN UINT16 Bus,
1862 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev
1863 );
1864
1865 /**
1866 This function gets the protocol interface from the given handle, and
1867 obtains its address space descriptors.
1868
1869 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
1870 @param[out] IoDev Handle used to access configuration space of PCI device.
1871 @param[out] Descriptors Points to the address space descriptors.
1872
1873 @retval EFI_SUCCESS The command completed successfully
1874 **/
1875 EFI_STATUS
1876 PciGetProtocolAndResource (
1877 IN EFI_HANDLE Handle,
1878 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,
1879 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors
1880 );
1881
1882 /**
1883 This function get the next bus range of given address space descriptors.
1884 It also moves the pointer backward a node, to get prepared to be called
1885 again.
1886
1887 @param[in, out] Descriptors Points to current position of a serial of address space
1888 descriptors.
1889 @param[out] MinBus The lower range of bus number.
1890 @param[out] MaxBus The upper range of bus number.
1891 @param[out] IsEnd Meet end of the serial of descriptors.
1892
1893 @retval EFI_SUCCESS The command completed successfully.
1894 **/
1895 EFI_STATUS
1896 PciGetNextBusRange (
1897 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,
1898 OUT UINT16 *MinBus,
1899 OUT UINT16 *MaxBus,
1900 OUT BOOLEAN *IsEnd
1901 );
1902
1903 /**
1904 Explain the data in PCI configuration space. The part which is common for
1905 PCI device and bridge is interpreted in this function. It calls other
1906 functions to interpret data unique for device or bridge.
1907
1908 @param[in] ConfigSpace Data in PCI configuration space.
1909 @param[in] Address Address used to access configuration space of this PCI device.
1910 @param[in] IoDev Handle used to access configuration space of PCI device.
1911 **/
1912 VOID
1913 PciExplainPci (
1914 IN PCI_CONFIG_SPACE *ConfigSpace,
1915 IN UINT64 Address,
1916 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
1917 );
1918
1919 /**
1920 Explain the device specific part of data in PCI configuration space.
1921
1922 @param[in] Device Data in PCI configuration space.
1923 @param[in] Address Address used to access configuration space of this PCI device.
1924 @param[in] IoDev Handle used to access configuration space of PCI device.
1925
1926 @retval EFI_SUCCESS The command completed successfully.
1927 **/
1928 EFI_STATUS
1929 PciExplainDeviceData (
1930 IN PCI_DEVICE_HEADER_TYPE_REGION *Device,
1931 IN UINT64 Address,
1932 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
1933 );
1934
1935 /**
1936 Explain the bridge specific part of data in PCI configuration space.
1937
1938 @param[in] Bridge Bridge specific data region in PCI configuration space.
1939 @param[in] Address Address used to access configuration space of this PCI device.
1940 @param[in] IoDev Handle used to access configuration space of PCI device.
1941
1942 @retval EFI_SUCCESS The command completed successfully.
1943 **/
1944 EFI_STATUS
1945 PciExplainBridgeData (
1946 IN PCI_BRIDGE_CONTROL_REGISTER *Bridge,
1947 IN UINT64 Address,
1948 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
1949 );
1950
1951 /**
1952 Explain the Base Address Register(Bar) in PCI configuration space.
1953
1954 @param[in] Bar Points to the Base Address Register intended to interpret.
1955 @param[in] Command Points to the register Command.
1956 @param[in] Address Address used to access configuration space of this PCI device.
1957 @param[in] IoDev Handle used to access configuration space of PCI device.
1958 @param[in, out] Index The Index.
1959
1960 @retval EFI_SUCCESS The command completed successfully.
1961 **/
1962 EFI_STATUS
1963 PciExplainBar (
1964 IN UINT32 *Bar,
1965 IN UINT16 *Command,
1966 IN UINT64 Address,
1967 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,
1968 IN OUT UINTN *Index
1969 );
1970
1971 /**
1972 Explain the cardbus specific part of data in PCI configuration space.
1973
1974 @param[in] CardBus CardBus specific region of PCI configuration space.
1975 @param[in] Address Address used to access configuration space of this PCI device.
1976 @param[in] IoDev Handle used to access configuration space of PCI device.
1977
1978 @retval EFI_SUCCESS The command completed successfully.
1979 **/
1980 EFI_STATUS
1981 PciExplainCardBusData (
1982 IN PCI_CARDBUS_CONTROL_REGISTER *CardBus,
1983 IN UINT64 Address,
1984 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
1985 );
1986
1987 /**
1988 Explain each meaningful bit of register Status. The definition of Status is
1989 slightly different depending on the PCI header type.
1990
1991 @param[in] Status Points to the content of register Status.
1992 @param[in] MainStatus Indicates if this register is main status(not secondary
1993 status).
1994 @param[in] HeaderType Header type of this PCI device.
1995
1996 @retval EFI_SUCCESS The command completed successfully.
1997 **/
1998 EFI_STATUS
1999 PciExplainStatus (
2000 IN UINT16 *Status,
2001 IN BOOLEAN MainStatus,
2002 IN PCI_HEADER_TYPE HeaderType
2003 );
2004
2005 /**
2006 Explain each meaningful bit of register Command.
2007
2008 @param[in] Command Points to the content of register Command.
2009
2010 @retval EFI_SUCCESS The command completed successfully.
2011 **/
2012 EFI_STATUS
2013 PciExplainCommand (
2014 IN UINT16 *Command
2015 );
2016
2017 /**
2018 Explain each meaningful bit of register Bridge Control.
2019
2020 @param[in] BridgeControl Points to the content of register Bridge Control.
2021 @param[in] HeaderType The headertype.
2022
2023 @retval EFI_SUCCESS The command completed successfully.
2024 **/
2025 EFI_STATUS
2026 PciExplainBridgeControl (
2027 IN UINT16 *BridgeControl,
2028 IN PCI_HEADER_TYPE HeaderType
2029 );
2030
2031 /**
2032 Locate capability register block per capability ID.
2033
2034 @param[in] ConfigSpace Data in PCI configuration space.
2035 @param[in] CapabilityId The capability ID.
2036
2037 @return The offset of the register block per capability ID.
2038 **/
2039 UINT8
2040 LocatePciCapability (
2041 IN PCI_CONFIG_SPACE *ConfigSpace,
2042 IN UINT8 CapabilityId
2043 );
2044
2045 /**
2046 Display Pcie device structure.
2047
2048 @param[in] PciExpressCap PCI Express capability buffer.
2049 @param[in] ExtendedConfigSpace PCI Express extended configuration space.
2050 @param[in] ExtendedConfigSize PCI Express extended configuration size.
2051 @param[in] ExtendedCapability PCI Express extended capability ID to explain.
2052 **/
2053 VOID
2054 PciExplainPciExpress (
2055 IN PCI_CAPABILITY_PCIEXP *PciExpressCap,
2056 IN UINT8 *ExtendedConfigSpace,
2057 IN UINTN ExtendedConfigSize,
2058 IN CONST UINT16 ExtendedCapability
2059 );
2060
2061 /**
2062 Print out information of the capability information.
2063
2064 @param[in] PciExpressCap The pointer to the structure about the device.
2065
2066 @retval EFI_SUCCESS The operation was successful.
2067 **/
2068 EFI_STATUS
2069 ExplainPcieCapReg (
2070 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
2071 );
2072
2073 /**
2074 Print out information of the device capability information.
2075
2076 @param[in] PciExpressCap The pointer to the structure about the device.
2077
2078 @retval EFI_SUCCESS The operation was successful.
2079 **/
2080 EFI_STATUS
2081 ExplainPcieDeviceCap (
2082 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
2083 );
2084
2085 /**
2086 Print out information of the device control information.
2087
2088 @param[in] PciExpressCap The pointer to the structure about the device.
2089
2090 @retval EFI_SUCCESS The operation was successful.
2091 **/
2092 EFI_STATUS
2093 ExplainPcieDeviceControl (
2094 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
2095 );
2096
2097 /**
2098 Print out information of the device status information.
2099
2100 @param[in] PciExpressCap The pointer to the structure about the device.
2101
2102 @retval EFI_SUCCESS The operation was successful.
2103 **/
2104 EFI_STATUS
2105 ExplainPcieDeviceStatus (
2106 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
2107 );
2108
2109 /**
2110 Print out information of the device link information.
2111
2112 @param[in] PciExpressCap The pointer to the structure about the device.
2113
2114 @retval EFI_SUCCESS The operation was successful.
2115 **/
2116 EFI_STATUS
2117 ExplainPcieLinkCap (
2118 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
2119 );
2120
2121 /**
2122 Print out information of the device link control information.
2123
2124 @param[in] PciExpressCap The pointer to the structure about the device.
2125
2126 @retval EFI_SUCCESS The operation was successful.
2127 **/
2128 EFI_STATUS
2129 ExplainPcieLinkControl (
2130 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
2131 );
2132
2133 /**
2134 Print out information of the device link status information.
2135
2136 @param[in] PciExpressCap The pointer to the structure about the device.
2137
2138 @retval EFI_SUCCESS The operation was successful.
2139 **/
2140 EFI_STATUS
2141 ExplainPcieLinkStatus (
2142 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
2143 );
2144
2145 /**
2146 Print out information of the device slot information.
2147
2148 @param[in] PciExpressCap The pointer to the structure about the device.
2149
2150 @retval EFI_SUCCESS The operation was successful.
2151 **/
2152 EFI_STATUS
2153 ExplainPcieSlotCap (
2154 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
2155 );
2156
2157 /**
2158 Print out information of the device slot control information.
2159
2160 @param[in] PciExpressCap The pointer to the structure about the device.
2161
2162 @retval EFI_SUCCESS The operation was successful.
2163 **/
2164 EFI_STATUS
2165 ExplainPcieSlotControl (
2166 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
2167 );
2168
2169 /**
2170 Print out information of the device slot status information.
2171
2172 @param[in] PciExpressCap The pointer to the structure about the device.
2173
2174 @retval EFI_SUCCESS The operation was successful.
2175 **/
2176 EFI_STATUS
2177 ExplainPcieSlotStatus (
2178 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
2179 );
2180
2181 /**
2182 Print out information of the device root information.
2183
2184 @param[in] PciExpressCap The pointer to the structure about the device.
2185
2186 @retval EFI_SUCCESS The operation was successful.
2187 **/
2188 EFI_STATUS
2189 ExplainPcieRootControl (
2190 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
2191 );
2192
2193 /**
2194 Print out information of the device root capability information.
2195
2196 @param[in] PciExpressCap The pointer to the structure about the device.
2197
2198 @retval EFI_SUCCESS The operation was successful.
2199 **/
2200 EFI_STATUS
2201 ExplainPcieRootCap (
2202 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
2203 );
2204
2205 /**
2206 Print out information of the device root status information.
2207
2208 @param[in] PciExpressCap The pointer to the structure about the device.
2209
2210 @retval EFI_SUCCESS The operation was successful.
2211 **/
2212 EFI_STATUS
2213 ExplainPcieRootStatus (
2214 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
2215 );
2216
2217 typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (
2218 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
2219 );
2220
2221 typedef enum {
2222 FieldWidthUINT8,
2223 FieldWidthUINT16,
2224 FieldWidthUINT32
2225 } PCIE_CAPREG_FIELD_WIDTH;
2226
2227 typedef enum {
2228 PcieExplainTypeCommon,
2229 PcieExplainTypeDevice,
2230 PcieExplainTypeLink,
2231 PcieExplainTypeSlot,
2232 PcieExplainTypeRoot,
2233 PcieExplainTypeMax
2234 } PCIE_EXPLAIN_TYPE;
2235
2236 typedef struct {
2237 UINT16 Token;
2238 UINTN Offset;
2239 PCIE_CAPREG_FIELD_WIDTH Width;
2240 PCIE_EXPLAIN_FUNCTION Func;
2241 PCIE_EXPLAIN_TYPE Type;
2242 } PCIE_EXPLAIN_STRUCT;
2243
2244 PCIE_EXPLAIN_STRUCT PcieExplainList[] = {
2245 {
2246 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),
2247 0x00,
2248 FieldWidthUINT8,
2249 NULL,
2250 PcieExplainTypeCommon
2251 },
2252 {
2253 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR),
2254 0x01,
2255 FieldWidthUINT8,
2256 NULL,
2257 PcieExplainTypeCommon
2258 },
2259 {
2260 STRING_TOKEN (STR_PCIEX_CAP_REGISTER),
2261 0x02,
2262 FieldWidthUINT16,
2263 ExplainPcieCapReg,
2264 PcieExplainTypeCommon
2265 },
2266 {
2267 STRING_TOKEN (STR_PCIEX_DEVICE_CAP),
2268 0x04,
2269 FieldWidthUINT32,
2270 ExplainPcieDeviceCap,
2271 PcieExplainTypeDevice
2272 },
2273 {
2274 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL),
2275 0x08,
2276 FieldWidthUINT16,
2277 ExplainPcieDeviceControl,
2278 PcieExplainTypeDevice
2279 },
2280 {
2281 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS),
2282 0x0a,
2283 FieldWidthUINT16,
2284 ExplainPcieDeviceStatus,
2285 PcieExplainTypeDevice
2286 },
2287 {
2288 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES),
2289 0x0c,
2290 FieldWidthUINT32,
2291 ExplainPcieLinkCap,
2292 PcieExplainTypeLink
2293 },
2294 {
2295 STRING_TOKEN (STR_PCIEX_LINK_CONTROL),
2296 0x10,
2297 FieldWidthUINT16,
2298 ExplainPcieLinkControl,
2299 PcieExplainTypeLink
2300 },
2301 {
2302 STRING_TOKEN (STR_PCIEX_LINK_STATUS),
2303 0x12,
2304 FieldWidthUINT16,
2305 ExplainPcieLinkStatus,
2306 PcieExplainTypeLink
2307 },
2308 {
2309 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES),
2310 0x14,
2311 FieldWidthUINT32,
2312 ExplainPcieSlotCap,
2313 PcieExplainTypeSlot
2314 },
2315 {
2316 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL),
2317 0x18,
2318 FieldWidthUINT16,
2319 ExplainPcieSlotControl,
2320 PcieExplainTypeSlot
2321 },
2322 {
2323 STRING_TOKEN (STR_PCIEX_SLOT_STATUS),
2324 0x1a,
2325 FieldWidthUINT16,
2326 ExplainPcieSlotStatus,
2327 PcieExplainTypeSlot
2328 },
2329 {
2330 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL),
2331 0x1c,
2332 FieldWidthUINT16,
2333 ExplainPcieRootControl,
2334 PcieExplainTypeRoot
2335 },
2336 {
2337 STRING_TOKEN (STR_PCIEX_RSVDP),
2338 0x1e,
2339 FieldWidthUINT16,
2340 ExplainPcieRootCap,
2341 PcieExplainTypeRoot
2342 },
2343 {
2344 STRING_TOKEN (STR_PCIEX_ROOT_STATUS),
2345 0x20,
2346 FieldWidthUINT32,
2347 ExplainPcieRootStatus,
2348 PcieExplainTypeRoot
2349 },
2350 {
2351 0,
2352 0,
2353 (PCIE_CAPREG_FIELD_WIDTH)0,
2354 NULL,
2355 PcieExplainTypeMax
2356 }
2357 };
2358
2359 //
2360 // Global Variables
2361 //
2362 PCI_CONFIG_SPACE *mConfigSpace = NULL;
2363 STATIC CONST SHELL_PARAM_ITEM ParamList[] = {
2364 { L"-s", TypeValue },
2365 { L"-i", TypeFlag },
2366 { L"-ec", TypeValue },
2367 { NULL, TypeMax }
2368 };
2369
2370 CHAR16 *DevicePortTypeTable[] = {
2371 L"PCI Express Endpoint",
2372 L"Legacy PCI Express Endpoint",
2373 L"Unknown Type",
2374 L"Unknonw Type",
2375 L"Root Port of PCI Express Root Complex",
2376 L"Upstream Port of PCI Express Switch",
2377 L"Downstream Port of PCI Express Switch",
2378 L"PCI Express to PCI/PCI-X Bridge",
2379 L"PCI/PCI-X to PCI Express Bridge",
2380 L"Root Complex Integrated Endpoint",
2381 L"Root Complex Event Collector"
2382 };
2383
2384 CHAR16 *L0sLatencyStrTable[] = {
2385 L"Less than 64ns",
2386 L"64ns to less than 128ns",
2387 L"128ns to less than 256ns",
2388 L"256ns to less than 512ns",
2389 L"512ns to less than 1us",
2390 L"1us to less than 2us",
2391 L"2us-4us",
2392 L"More than 4us"
2393 };
2394
2395 CHAR16 *L1LatencyStrTable[] = {
2396 L"Less than 1us",
2397 L"1us to less than 2us",
2398 L"2us to less than 4us",
2399 L"4us to less than 8us",
2400 L"8us to less than 16us",
2401 L"16us to less than 32us",
2402 L"32us-64us",
2403 L"More than 64us"
2404 };
2405
2406 CHAR16 *ASPMCtrlStrTable[] = {
2407 L"Disabled",
2408 L"L0s Entry Enabled",
2409 L"L1 Entry Enabled",
2410 L"L0s and L1 Entry Enabled"
2411 };
2412
2413 CHAR16 *SlotPwrLmtScaleTable[] = {
2414 L"1.0x",
2415 L"0.1x",
2416 L"0.01x",
2417 L"0.001x"
2418 };
2419
2420 CHAR16 *IndicatorTable[] = {
2421 L"Reserved",
2422 L"On",
2423 L"Blink",
2424 L"Off"
2425 };
2426
2427 /**
2428 Function for 'pci' command.
2429
2430 @param[in] ImageHandle Handle to the Image (NULL if Internal).
2431 @param[in] SystemTable Pointer to the System Table (NULL if Internal).
2432 **/
2433 SHELL_STATUS
2434 EFIAPI
2435 ShellCommandRunPci (
2436 IN EFI_HANDLE ImageHandle,
2437 IN EFI_SYSTEM_TABLE *SystemTable
2438 )
2439 {
2440 UINT16 Segment;
2441 UINT16 Bus;
2442 UINT16 Device;
2443 UINT16 Func;
2444 UINT64 Address;
2445 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;
2446 EFI_STATUS Status;
2447 PCI_DEVICE_INDEPENDENT_REGION PciHeader;
2448 PCI_CONFIG_SPACE ConfigSpace;
2449 UINTN ScreenCount;
2450 UINTN TempColumn;
2451 UINTN ScreenSize;
2452 BOOLEAN ExplainData;
2453 UINTN Index;
2454 UINTN SizeOfHeader;
2455 BOOLEAN PrintTitle;
2456 UINTN HandleBufSize;
2457 EFI_HANDLE *HandleBuf;
2458 UINTN HandleCount;
2459 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
2460 UINT16 MinBus;
2461 UINT16 MaxBus;
2462 BOOLEAN IsEnd;
2463 LIST_ENTRY *Package;
2464 CHAR16 *ProblemParam;
2465 SHELL_STATUS ShellStatus;
2466 CONST CHAR16 *Temp;
2467 UINT64 RetVal;
2468 UINT16 ExtendedCapability;
2469 UINT8 PcieCapabilityPtr;
2470 UINT8 *ExtendedConfigSpace;
2471 UINTN ExtendedConfigSize;
2472
2473 ShellStatus = SHELL_SUCCESS;
2474 Status = EFI_SUCCESS;
2475 Address = 0;
2476 IoDev = NULL;
2477 HandleBuf = NULL;
2478 Package = NULL;
2479
2480 //
2481 // initialize the shell lib (we must be in non-auto-init...)
2482 //
2483 Status = ShellInitialize ();
2484 ASSERT_EFI_ERROR (Status);
2485
2486 Status = CommandInit ();
2487 ASSERT_EFI_ERROR (Status);
2488
2489 //
2490 // parse the command line
2491 //
2492 Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);
2493 if (EFI_ERROR (Status)) {
2494 if ((Status == EFI_VOLUME_CORRUPTED) && (ProblemParam != NULL)) {
2495 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, L"pci", ProblemParam);
2496 FreePool (ProblemParam);
2497 ShellStatus = SHELL_INVALID_PARAMETER;
2498 } else {
2499 ASSERT (FALSE);
2500 }
2501 } else {
2502 if (ShellCommandLineGetCount (Package) == 2) {
2503 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle, L"pci");
2504 ShellStatus = SHELL_INVALID_PARAMETER;
2505 goto Done;
2506 }
2507
2508 if (ShellCommandLineGetCount (Package) > 4) {
2509 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"pci");
2510 ShellStatus = SHELL_INVALID_PARAMETER;
2511 goto Done;
2512 }
2513
2514 if (ShellCommandLineGetFlag (Package, L"-ec") && (ShellCommandLineGetValue (Package, L"-ec") == NULL)) {
2515 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-ec");
2516 ShellStatus = SHELL_INVALID_PARAMETER;
2517 goto Done;
2518 }
2519
2520 if (ShellCommandLineGetFlag (Package, L"-s") && (ShellCommandLineGetValue (Package, L"-s") == NULL)) {
2521 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-s");
2522 ShellStatus = SHELL_INVALID_PARAMETER;
2523 goto Done;
2524 }
2525
2526 //
2527 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and
2528 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough
2529 // space for handles and call it again.
2530 //
2531 HandleBufSize = sizeof (EFI_HANDLE);
2532 HandleBuf = (EFI_HANDLE *)AllocateZeroPool (HandleBufSize);
2533 if (HandleBuf == NULL) {
2534 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci");
2535 ShellStatus = SHELL_OUT_OF_RESOURCES;
2536 goto Done;
2537 }
2538
2539 Status = gBS->LocateHandle (
2540 ByProtocol,
2541 &gEfiPciRootBridgeIoProtocolGuid,
2542 NULL,
2543 &HandleBufSize,
2544 HandleBuf
2545 );
2546
2547 if (Status == EFI_BUFFER_TOO_SMALL) {
2548 HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);
2549 if (HandleBuf == NULL) {
2550 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci");
2551 ShellStatus = SHELL_OUT_OF_RESOURCES;
2552 goto Done;
2553 }
2554
2555 Status = gBS->LocateHandle (
2556 ByProtocol,
2557 &gEfiPciRootBridgeIoProtocolGuid,
2558 NULL,
2559 &HandleBufSize,
2560 HandleBuf
2561 );
2562 }
2563
2564 if (EFI_ERROR (Status)) {
2565 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle, L"pci");
2566 ShellStatus = SHELL_NOT_FOUND;
2567 goto Done;
2568 }
2569
2570 HandleCount = HandleBufSize / sizeof (EFI_HANDLE);
2571 //
2572 // Argument Count == 1(no other argument): enumerate all pci functions
2573 //
2574 if (ShellCommandLineGetCount (Package) == 1) {
2575 gST->ConOut->QueryMode (
2576 gST->ConOut,
2577 gST->ConOut->Mode->Mode,
2578 &TempColumn,
2579 &ScreenSize
2580 );
2581
2582 ScreenCount = 0;
2583 ScreenSize -= 4;
2584 if ((ScreenSize & 1) == 1) {
2585 ScreenSize -= 1;
2586 }
2587
2588 PrintTitle = TRUE;
2589
2590 //
2591 // For each handle, which decides a segment and a bus number range,
2592 // enumerate all devices on it.
2593 //
2594 for (Index = 0; Index < HandleCount; Index++) {
2595 Status = PciGetProtocolAndResource (
2596 HandleBuf[Index],
2597 &IoDev,
2598 &Descriptors
2599 );
2600 if (EFI_ERROR (Status)) {
2601 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, L"pci");
2602 ShellStatus = SHELL_NOT_FOUND;
2603 goto Done;
2604 }
2605
2606 //
2607 // No document say it's impossible for a RootBridgeIo protocol handle
2608 // to have more than one address space descriptors, so find out every
2609 // bus range and for each of them do device enumeration.
2610 //
2611 while (TRUE) {
2612 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);
2613
2614 if (EFI_ERROR (Status)) {
2615 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, L"pci");
2616 ShellStatus = SHELL_NOT_FOUND;
2617 goto Done;
2618 }
2619
2620 if (IsEnd) {
2621 break;
2622 }
2623
2624 for (Bus = MinBus; Bus <= MaxBus; Bus++) {
2625 //
2626 // For each devices, enumerate all functions it contains
2627 //
2628 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
2629 //
2630 // For each function, read its configuration space and print summary
2631 //
2632 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
2633 if (ShellGetExecutionBreakFlag ()) {
2634 ShellStatus = SHELL_ABORTED;
2635 goto Done;
2636 }
2637
2638 Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);
2639 IoDev->Pci.Read (
2640 IoDev,
2641 EfiPciWidthUint16,
2642 Address,
2643 1,
2644 &PciHeader.VendorId
2645 );
2646
2647 //
2648 // If VendorId = 0xffff, there does not exist a device at this
2649 // location. For each device, if there is any function on it,
2650 // there must be 1 function at Function 0. So if Func = 0, there
2651 // will be no more functions in the same device, so we can break
2652 // loop to deal with the next device.
2653 //
2654 if ((PciHeader.VendorId == 0xffff) && (Func == 0)) {
2655 break;
2656 }
2657
2658 if (PciHeader.VendorId != 0xffff) {
2659 if (PrintTitle) {
2660 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);
2661 PrintTitle = FALSE;
2662 }
2663
2664 IoDev->Pci.Read (
2665 IoDev,
2666 EfiPciWidthUint32,
2667 Address,
2668 sizeof (PciHeader) / sizeof (UINT32),
2669 &PciHeader
2670 );
2671
2672 ShellPrintHiiEx (
2673 -1,
2674 -1,
2675 NULL,
2676 STRING_TOKEN (STR_PCI_LINE_P1),
2677 gShellDebug1HiiHandle,
2678 IoDev->SegmentNumber,
2679 Bus,
2680 Device,
2681 Func
2682 );
2683
2684 PciPrintClassCode (PciHeader.ClassCode, FALSE);
2685 ShellPrintHiiEx (
2686 -1,
2687 -1,
2688 NULL,
2689 STRING_TOKEN (STR_PCI_LINE_P2),
2690 gShellDebug1HiiHandle,
2691 PciHeader.VendorId,
2692 PciHeader.DeviceId,
2693 PciHeader.ClassCode[0]
2694 );
2695
2696 ScreenCount += 2;
2697 if ((ScreenCount >= ScreenSize) && (ScreenSize != 0)) {
2698 //
2699 // If ScreenSize == 0 we have the console redirected so don't
2700 // block updates
2701 //
2702 ScreenCount = 0;
2703 }
2704
2705 //
2706 // If this is not a multi-function device, we can leave the loop
2707 // to deal with the next device.
2708 //
2709 if ((Func == 0) && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {
2710 break;
2711 }
2712 }
2713 }
2714 }
2715 }
2716
2717 //
2718 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,
2719 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all
2720 // devices on all bus, we can leave loop.
2721 //
2722 if (Descriptors == NULL) {
2723 break;
2724 }
2725 }
2726 }
2727
2728 Status = EFI_SUCCESS;
2729 goto Done;
2730 }
2731
2732 ExplainData = FALSE;
2733 Segment = 0;
2734 Bus = 0;
2735 Device = 0;
2736 Func = 0;
2737 ExtendedCapability = 0xFFFF;
2738 if (ShellCommandLineGetFlag (Package, L"-i")) {
2739 ExplainData = TRUE;
2740 }
2741
2742 Temp = ShellCommandLineGetValue (Package, L"-s");
2743 if (Temp != NULL) {
2744 //
2745 // Input converted to hexadecimal number.
2746 //
2747 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {
2748 Segment = (UINT16)RetVal;
2749 } else {
2750 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);
2751 ShellStatus = SHELL_INVALID_PARAMETER;
2752 goto Done;
2753 }
2754 }
2755
2756 //
2757 // The first Argument(except "-i") is assumed to be Bus number, second
2758 // to be Device number, and third to be Func number.
2759 //
2760 Temp = ShellCommandLineGetRawValue (Package, 1);
2761 if (Temp != NULL) {
2762 //
2763 // Input converted to hexadecimal number.
2764 //
2765 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {
2766 Bus = (UINT16)RetVal;
2767 } else {
2768 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);
2769 ShellStatus = SHELL_INVALID_PARAMETER;
2770 goto Done;
2771 }
2772
2773 if (Bus > PCI_MAX_BUS) {
2774 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);
2775 ShellStatus = SHELL_INVALID_PARAMETER;
2776 goto Done;
2777 }
2778 }
2779
2780 Temp = ShellCommandLineGetRawValue (Package, 2);
2781 if (Temp != NULL) {
2782 //
2783 // Input converted to hexadecimal number.
2784 //
2785 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {
2786 Device = (UINT16)RetVal;
2787 } else {
2788 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);
2789 ShellStatus = SHELL_INVALID_PARAMETER;
2790 goto Done;
2791 }
2792
2793 if (Device > PCI_MAX_DEVICE) {
2794 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);
2795 ShellStatus = SHELL_INVALID_PARAMETER;
2796 goto Done;
2797 }
2798 }
2799
2800 Temp = ShellCommandLineGetRawValue (Package, 3);
2801 if (Temp != NULL) {
2802 //
2803 // Input converted to hexadecimal number.
2804 //
2805 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {
2806 Func = (UINT16)RetVal;
2807 } else {
2808 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);
2809 ShellStatus = SHELL_INVALID_PARAMETER;
2810 goto Done;
2811 }
2812
2813 if (Func > PCI_MAX_FUNC) {
2814 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);
2815 ShellStatus = SHELL_INVALID_PARAMETER;
2816 goto Done;
2817 }
2818 }
2819
2820 Temp = ShellCommandLineGetValue (Package, L"-ec");
2821 if (Temp != NULL) {
2822 //
2823 // Input converted to hexadecimal number.
2824 //
2825 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {
2826 ExtendedCapability = (UINT16)RetVal;
2827 } else {
2828 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);
2829 ShellStatus = SHELL_INVALID_PARAMETER;
2830 goto Done;
2831 }
2832 }
2833
2834 //
2835 // Find the protocol interface who's in charge of current segment, and its
2836 // bus range covers the current bus
2837 //
2838 Status = PciFindProtocolInterface (
2839 HandleBuf,
2840 HandleCount,
2841 Segment,
2842 Bus,
2843 &IoDev
2844 );
2845
2846 if (EFI_ERROR (Status)) {
2847 ShellPrintHiiEx (
2848 -1,
2849 -1,
2850 NULL,
2851 STRING_TOKEN (STR_PCI_NO_FIND),
2852 gShellDebug1HiiHandle,
2853 L"pci",
2854 Segment,
2855 Bus
2856 );
2857 ShellStatus = SHELL_NOT_FOUND;
2858 goto Done;
2859 }
2860
2861 Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);
2862 Status = IoDev->Pci.Read (
2863 IoDev,
2864 EfiPciWidthUint8,
2865 Address,
2866 sizeof (ConfigSpace),
2867 &ConfigSpace
2868 );
2869
2870 if (EFI_ERROR (Status)) {
2871 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, L"pci");
2872 ShellStatus = SHELL_ACCESS_DENIED;
2873 goto Done;
2874 }
2875
2876 mConfigSpace = &ConfigSpace;
2877 ShellPrintHiiEx (
2878 -1,
2879 -1,
2880 NULL,
2881 STRING_TOKEN (STR_PCI_INFO),
2882 gShellDebug1HiiHandle,
2883 Segment,
2884 Bus,
2885 Device,
2886 Func,
2887 Segment,
2888 Bus,
2889 Device,
2890 Func
2891 );
2892
2893 //
2894 // Dump standard header of configuration space
2895 //
2896 SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);
2897
2898 DumpHex (2, 0, SizeOfHeader, &ConfigSpace);
2899 ShellPrintEx (-1, -1, L"\r\n");
2900
2901 //
2902 // Dump device dependent Part of configuration space
2903 //
2904 DumpHex (
2905 2,
2906 SizeOfHeader,
2907 sizeof (ConfigSpace) - SizeOfHeader,
2908 ConfigSpace.Data
2909 );
2910
2911 ExtendedConfigSpace = NULL;
2912 ExtendedConfigSize = 0;
2913 PcieCapabilityPtr = LocatePciCapability (&ConfigSpace, EFI_PCI_CAPABILITY_ID_PCIEXP);
2914 if (PcieCapabilityPtr != 0) {
2915 ExtendedConfigSize = 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET;
2916 ExtendedConfigSpace = AllocatePool (ExtendedConfigSize);
2917 if (ExtendedConfigSpace != NULL) {
2918 Status = IoDev->Pci.Read (
2919 IoDev,
2920 EfiPciWidthUint32,
2921 EFI_PCI_ADDRESS (Bus, Device, Func, EFI_PCIE_CAPABILITY_BASE_OFFSET),
2922 ExtendedConfigSize / sizeof (UINT32),
2923 ExtendedConfigSpace
2924 );
2925 if (EFI_ERROR (Status)) {
2926 SHELL_FREE_NON_NULL (ExtendedConfigSpace);
2927 }
2928 }
2929 }
2930
2931 if ((ExtendedConfigSpace != NULL) && !ShellGetExecutionBreakFlag ()) {
2932 //
2933 // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)
2934 //
2935 ShellPrintEx (-1, -1, L"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");
2936
2937 DumpHex (
2938 2,
2939 EFI_PCIE_CAPABILITY_BASE_OFFSET,
2940 ExtendedConfigSize,
2941 ExtendedConfigSpace
2942 );
2943 }
2944
2945 //
2946 // If "-i" appears in command line, interpret data in configuration space
2947 //
2948 if (ExplainData) {
2949 PciExplainPci (&ConfigSpace, Address, IoDev);
2950 if ((ExtendedConfigSpace != NULL) && !ShellGetExecutionBreakFlag ()) {
2951 PciExplainPciExpress (
2952 (PCI_CAPABILITY_PCIEXP *)((UINT8 *)&ConfigSpace + PcieCapabilityPtr),
2953 ExtendedConfigSpace,
2954 ExtendedConfigSize,
2955 ExtendedCapability
2956 );
2957 }
2958 }
2959 }
2960
2961 Done:
2962 if (HandleBuf != NULL) {
2963 FreePool (HandleBuf);
2964 }
2965
2966 if (Package != NULL) {
2967 ShellCommandLineFreeVarList (Package);
2968 }
2969
2970 mConfigSpace = NULL;
2971 return ShellStatus;
2972 }
2973
2974 /**
2975 This function finds out the protocol which is in charge of the given
2976 segment, and its bus range covers the current bus number. It lookes
2977 each instances of RootBridgeIoProtocol handle, until the one meets the
2978 criteria is found.
2979
2980 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2981 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2982 @param[in] Segment Segment number of device we are dealing with.
2983 @param[in] Bus Bus number of device we are dealing with.
2984 @param[out] IoDev Handle used to access configuration space of PCI device.
2985
2986 @retval EFI_SUCCESS The command completed successfully.
2987 @retval EFI_INVALID_PARAMETER Invalid parameter.
2988
2989 **/
2990 EFI_STATUS
2991 PciFindProtocolInterface (
2992 IN EFI_HANDLE *HandleBuf,
2993 IN UINTN HandleCount,
2994 IN UINT16 Segment,
2995 IN UINT16 Bus,
2996 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev
2997 )
2998 {
2999 UINTN Index;
3000 EFI_STATUS Status;
3001 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
3002 UINT16 MinBus;
3003 UINT16 MaxBus;
3004 BOOLEAN IsEnd;
3005
3006 //
3007 // Go through all handles, until the one meets the criteria is found
3008 //
3009 for (Index = 0; Index < HandleCount; Index++) {
3010 Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);
3011 if (EFI_ERROR (Status)) {
3012 return Status;
3013 }
3014
3015 //
3016 // When Descriptors == NULL, the Configuration() is not implemented,
3017 // so we only check the Segment number
3018 //
3019 if ((Descriptors == NULL) && (Segment == (*IoDev)->SegmentNumber)) {
3020 return EFI_SUCCESS;
3021 }
3022
3023 if ((*IoDev)->SegmentNumber != Segment) {
3024 continue;
3025 }
3026
3027 while (TRUE) {
3028 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);
3029 if (EFI_ERROR (Status)) {
3030 return Status;
3031 }
3032
3033 if (IsEnd) {
3034 break;
3035 }
3036
3037 if ((MinBus <= Bus) && (MaxBus >= Bus)) {
3038 return EFI_SUCCESS;
3039 }
3040 }
3041 }
3042
3043 return EFI_NOT_FOUND;
3044 }
3045
3046 /**
3047 This function gets the protocol interface from the given handle, and
3048 obtains its address space descriptors.
3049
3050 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
3051 @param[out] IoDev Handle used to access configuration space of PCI device.
3052 @param[out] Descriptors Points to the address space descriptors.
3053
3054 @retval EFI_SUCCESS The command completed successfully
3055 **/
3056 EFI_STATUS
3057 PciGetProtocolAndResource (
3058 IN EFI_HANDLE Handle,
3059 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,
3060 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors
3061 )
3062 {
3063 EFI_STATUS Status;
3064
3065 //
3066 // Get inferface from protocol
3067 //
3068 Status = gBS->HandleProtocol (
3069 Handle,
3070 &gEfiPciRootBridgeIoProtocolGuid,
3071 (VOID **)IoDev
3072 );
3073
3074 if (EFI_ERROR (Status)) {
3075 return Status;
3076 }
3077
3078 //
3079 // Call Configuration() to get address space descriptors
3080 //
3081 Status = (*IoDev)->Configuration (*IoDev, (VOID **)Descriptors);
3082 if (Status == EFI_UNSUPPORTED) {
3083 *Descriptors = NULL;
3084 return EFI_SUCCESS;
3085 } else {
3086 return Status;
3087 }
3088 }
3089
3090 /**
3091 This function get the next bus range of given address space descriptors.
3092 It also moves the pointer backward a node, to get prepared to be called
3093 again.
3094
3095 @param[in, out] Descriptors Points to current position of a serial of address space
3096 descriptors.
3097 @param[out] MinBus The lower range of bus number.
3098 @param[out] MaxBus The upper range of bus number.
3099 @param[out] IsEnd Meet end of the serial of descriptors.
3100
3101 @retval EFI_SUCCESS The command completed successfully.
3102 **/
3103 EFI_STATUS
3104 PciGetNextBusRange (
3105 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,
3106 OUT UINT16 *MinBus,
3107 OUT UINT16 *MaxBus,
3108 OUT BOOLEAN *IsEnd
3109 )
3110 {
3111 *IsEnd = FALSE;
3112
3113 //
3114 // When *Descriptors is NULL, Configuration() is not implemented, so assume
3115 // range is 0~PCI_MAX_BUS
3116 //
3117 if ((*Descriptors) == NULL) {
3118 *MinBus = 0;
3119 *MaxBus = PCI_MAX_BUS;
3120 return EFI_SUCCESS;
3121 }
3122
3123 //
3124 // *Descriptors points to one or more address space descriptors, which
3125 // ends with a end tagged descriptor. Examine each of the descriptors,
3126 // if a bus typed one is found and its bus range covers bus, this handle
3127 // is the handle we are looking for.
3128 //
3129
3130 while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {
3131 if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {
3132 *MinBus = (UINT16)(*Descriptors)->AddrRangeMin;
3133 *MaxBus = (UINT16)(*Descriptors)->AddrRangeMax;
3134 (*Descriptors)++;
3135 return (EFI_SUCCESS);
3136 }
3137
3138 (*Descriptors)++;
3139 }
3140
3141 if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {
3142 *IsEnd = TRUE;
3143 }
3144
3145 return EFI_SUCCESS;
3146 }
3147
3148 /**
3149 Explain the data in PCI configuration space. The part which is common for
3150 PCI device and bridge is interpreted in this function. It calls other
3151 functions to interpret data unique for device or bridge.
3152
3153 @param[in] ConfigSpace Data in PCI configuration space.
3154 @param[in] Address Address used to access configuration space of this PCI device.
3155 @param[in] IoDev Handle used to access configuration space of PCI device.
3156 **/
3157 VOID
3158 PciExplainPci (
3159 IN PCI_CONFIG_SPACE *ConfigSpace,
3160 IN UINT64 Address,
3161 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
3162 )
3163 {
3164 PCI_DEVICE_INDEPENDENT_REGION *Common;
3165 PCI_HEADER_TYPE HeaderType;
3166
3167 Common = &(ConfigSpace->Common);
3168
3169 ShellPrintEx (-1, -1, L"\r\n");
3170
3171 //
3172 // Print Vendor Id and Device Id
3173 //
3174 ShellPrintHiiEx (
3175 -1,
3176 -1,
3177 NULL,
3178 STRING_TOKEN (STR_PCI_LINE_VID_DID),
3179 gShellDebug1HiiHandle,
3180 INDEX_OF (&(Common->VendorId)),
3181 Common->VendorId,
3182 INDEX_OF (&(Common->DeviceId)),
3183 Common->DeviceId
3184 );
3185
3186 //
3187 // Print register Command
3188 //
3189 PciExplainCommand (&(Common->Command));
3190
3191 //
3192 // Print register Status
3193 //
3194 PciExplainStatus (&(Common->Status), TRUE, PciUndefined);
3195
3196 //
3197 // Print register Revision ID
3198 //
3199 ShellPrintEx (-1, -1, L"\r\n");
3200 ShellPrintHiiEx (
3201 -1,
3202 -1,
3203 NULL,
3204 STRING_TOKEN (STR_PCI_LINE_RID),
3205 gShellDebug1HiiHandle,
3206 INDEX_OF (&(Common->RevisionID)),
3207 Common->RevisionID
3208 );
3209
3210 //
3211 // Print register BIST
3212 //
3213 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->BIST)));
3214 if ((Common->BIST & BIT7) != 0) {
3215 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->BIST);
3216 } else {
3217 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);
3218 }
3219
3220 //
3221 // Print register Cache Line Size
3222 //
3223 ShellPrintHiiEx (
3224 -1,
3225 -1,
3226 NULL,
3227 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),
3228 gShellDebug1HiiHandle,
3229 INDEX_OF (&(Common->CacheLineSize)),
3230 Common->CacheLineSize
3231 );
3232
3233 //
3234 // Print register Latency Timer
3235 //
3236 ShellPrintHiiEx (
3237 -1,
3238 -1,
3239 NULL,
3240 STRING_TOKEN (STR_PCI2_LATENCY_TIMER),
3241 gShellDebug1HiiHandle,
3242 INDEX_OF (&(Common->LatencyTimer)),
3243 Common->LatencyTimer
3244 );
3245
3246 //
3247 // Print register Header Type
3248 //
3249 ShellPrintHiiEx (
3250 -1,
3251 -1,
3252 NULL,
3253 STRING_TOKEN (STR_PCI2_HEADER_TYPE),
3254 gShellDebug1HiiHandle,
3255 INDEX_OF (&(Common->HeaderType)),
3256 Common->HeaderType
3257 );
3258
3259 if ((Common->HeaderType & BIT7) != 0) {
3260 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);
3261 } else {
3262 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);
3263 }
3264
3265 HeaderType = (PCI_HEADER_TYPE)(UINT8)(Common->HeaderType & 0x7f);
3266 switch (HeaderType) {
3267 case PciDevice:
3268 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);
3269 break;
3270
3271 case PciP2pBridge:
3272 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);
3273 break;
3274
3275 case PciCardBusBridge:
3276 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);
3277 break;
3278
3279 default:
3280 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);
3281 HeaderType = PciUndefined;
3282 }
3283
3284 //
3285 // Print register Class Code
3286 //
3287 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);
3288 PciPrintClassCode ((UINT8 *)Common->ClassCode, TRUE);
3289 ShellPrintEx (-1, -1, L"\r\n");
3290 }
3291
3292 /**
3293 Explain the device specific part of data in PCI configuration space.
3294
3295 @param[in] Device Data in PCI configuration space.
3296 @param[in] Address Address used to access configuration space of this PCI device.
3297 @param[in] IoDev Handle used to access configuration space of PCI device.
3298
3299 @retval EFI_SUCCESS The command completed successfully.
3300 **/
3301 EFI_STATUS
3302 PciExplainDeviceData (
3303 IN PCI_DEVICE_HEADER_TYPE_REGION *Device,
3304 IN UINT64 Address,
3305 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
3306 )
3307 {
3308 UINTN Index;
3309 BOOLEAN BarExist;
3310 EFI_STATUS Status;
3311 UINTN BarCount;
3312
3313 //
3314 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not
3315 // exist. If these no Bar for this function, print "none", otherwise
3316 // list detail information about this Bar.
3317 //
3318 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));
3319
3320 BarExist = FALSE;
3321 BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);
3322 for (Index = 0; Index < BarCount; Index++) {
3323 if (Device->Bar[Index] == 0) {
3324 continue;
3325 }
3326
3327 if (!BarExist) {
3328 BarExist = TRUE;
3329 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);
3330 ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");
3331 }
3332
3333 Status = PciExplainBar (
3334 &(Device->Bar[Index]),
3335 &(mConfigSpace->Common.Command),
3336 Address,
3337 IoDev,
3338 &Index
3339 );
3340
3341 if (EFI_ERROR (Status)) {
3342 break;
3343 }
3344 }
3345
3346 if (!BarExist) {
3347 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);
3348 } else {
3349 ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");
3350 }
3351
3352 //
3353 // Print register Expansion ROM Base Address
3354 //
3355 if ((Device->ExpansionRomBar & BIT0) == 0) {
3356 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ExpansionRomBar)));
3357 } else {
3358 ShellPrintHiiEx (
3359 -1,
3360 -1,
3361 NULL,
3362 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),
3363 gShellDebug1HiiHandle,
3364 INDEX_OF (&(Device->ExpansionRomBar)),
3365 Device->ExpansionRomBar
3366 );
3367 }
3368
3369 //
3370 // Print register Cardbus CIS ptr
3371 //
3372 ShellPrintHiiEx (
3373 -1,
3374 -1,
3375 NULL,
3376 STRING_TOKEN (STR_PCI2_CARDBUS_CIS),
3377 gShellDebug1HiiHandle,
3378 INDEX_OF (&(Device->CISPtr)),
3379 Device->CISPtr
3380 );
3381
3382 //
3383 // Print register Sub-vendor ID and subsystem ID
3384 //
3385 ShellPrintHiiEx (
3386 -1,
3387 -1,
3388 NULL,
3389 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),
3390 gShellDebug1HiiHandle,
3391 INDEX_OF (&(Device->SubsystemVendorID)),
3392 Device->SubsystemVendorID
3393 );
3394
3395 ShellPrintHiiEx (
3396 -1,
3397 -1,
3398 NULL,
3399 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),
3400 gShellDebug1HiiHandle,
3401 INDEX_OF (&(Device->SubsystemID)),
3402 Device->SubsystemID
3403 );
3404
3405 //
3406 // Print register Capabilities Ptr
3407 //
3408 ShellPrintHiiEx (
3409 -1,
3410 -1,
3411 NULL,
3412 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),
3413 gShellDebug1HiiHandle,
3414 INDEX_OF (&(Device->CapabilityPtr)),
3415 Device->CapabilityPtr
3416 );
3417
3418 //
3419 // Print register Interrupt Line and interrupt pin
3420 //
3421 ShellPrintHiiEx (
3422 -1,
3423 -1,
3424 NULL,
3425 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),
3426 gShellDebug1HiiHandle,
3427 INDEX_OF (&(Device->InterruptLine)),
3428 Device->InterruptLine
3429 );
3430
3431 ShellPrintHiiEx (
3432 -1,
3433 -1,
3434 NULL,
3435 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),
3436 gShellDebug1HiiHandle,
3437 INDEX_OF (&(Device->InterruptPin)),
3438 Device->InterruptPin
3439 );
3440
3441 //
3442 // Print register Min_Gnt and Max_Lat
3443 //
3444 ShellPrintHiiEx (
3445 -1,
3446 -1,
3447 NULL,
3448 STRING_TOKEN (STR_PCI2_MIN_GNT),
3449 gShellDebug1HiiHandle,
3450 INDEX_OF (&(Device->MinGnt)),
3451 Device->MinGnt
3452 );
3453
3454 ShellPrintHiiEx (
3455 -1,
3456 -1,
3457 NULL,
3458 STRING_TOKEN (STR_PCI2_MAX_LAT),
3459 gShellDebug1HiiHandle,
3460 INDEX_OF (&(Device->MaxLat)),
3461 Device->MaxLat
3462 );
3463
3464 return EFI_SUCCESS;
3465 }
3466
3467 /**
3468 Explain the bridge specific part of data in PCI configuration space.
3469
3470 @param[in] Bridge Bridge specific data region in PCI configuration space.
3471 @param[in] Address Address used to access configuration space of this PCI device.
3472 @param[in] IoDev Handle used to access configuration space of PCI device.
3473
3474 @retval EFI_SUCCESS The command completed successfully.
3475 **/
3476 EFI_STATUS
3477 PciExplainBridgeData (
3478 IN PCI_BRIDGE_CONTROL_REGISTER *Bridge,
3479 IN UINT64 Address,
3480 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
3481 )
3482 {
3483 UINTN Index;
3484 BOOLEAN BarExist;
3485 UINTN BarCount;
3486 UINT32 IoAddress32;
3487 EFI_STATUS Status;
3488
3489 //
3490 // Print Base Address Registers. When Bar = 0, this Bar does not
3491 // exist. If these no Bar for this function, print "none", otherwise
3492 // list detail information about this Bar.
3493 //
3494 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));
3495
3496 BarExist = FALSE;
3497 BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);
3498
3499 for (Index = 0; Index < BarCount; Index++) {
3500 if (Bridge->Bar[Index] == 0) {
3501 continue;
3502 }
3503
3504 if (!BarExist) {
3505 BarExist = TRUE;
3506 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);
3507 ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");
3508 }
3509
3510 Status = PciExplainBar (
3511 &(Bridge->Bar[Index]),
3512 &(mConfigSpace->Common.Command),
3513 Address,
3514 IoDev,
3515 &Index
3516 );
3517
3518 if (EFI_ERROR (Status)) {
3519 break;
3520 }
3521 }
3522
3523 if (!BarExist) {
3524 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);
3525 } else {
3526 ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");
3527 }
3528
3529 //
3530 // Expansion register ROM Base Address
3531 //
3532 if ((Bridge->ExpansionRomBAR & BIT0) == 0) {
3533 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ExpansionRomBAR)));
3534 } else {
3535 ShellPrintHiiEx (
3536 -1,
3537 -1,
3538 NULL,
3539 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),
3540 gShellDebug1HiiHandle,
3541 INDEX_OF (&(Bridge->ExpansionRomBAR)),
3542 Bridge->ExpansionRomBAR
3543 );
3544 }
3545
3546 //
3547 // Print Bus Numbers(Primary, Secondary, and Subordinate
3548 //
3549 ShellPrintHiiEx (
3550 -1,
3551 -1,
3552 NULL,
3553 STRING_TOKEN (STR_PCI2_BUS_NUMBERS),
3554 gShellDebug1HiiHandle,
3555 INDEX_OF (&(Bridge->PrimaryBus)),
3556 INDEX_OF (&(Bridge->SecondaryBus)),
3557 INDEX_OF (&(Bridge->SubordinateBus))
3558 );
3559
3560 ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");
3561
3562 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);
3563 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);
3564 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);
3565
3566 //
3567 // Print register Secondary Latency Timer
3568 //
3569 ShellPrintHiiEx (
3570 -1,
3571 -1,
3572 NULL,
3573 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),
3574 gShellDebug1HiiHandle,
3575 INDEX_OF (&(Bridge->SecondaryLatencyTimer)),
3576 Bridge->SecondaryLatencyTimer
3577 );
3578
3579 //
3580 // Print register Secondary Status
3581 //
3582 PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);
3583
3584 //
3585 // Print I/O and memory ranges this bridge forwards. There are 3 resource
3586 // types: I/O, memory, and pre-fetchable memory. For each resource type,
3587 // base and limit address are listed.
3588 //
3589 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);
3590 ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");
3591
3592 //
3593 // IO Base & Limit
3594 //
3595 IoAddress32 = (Bridge->IoBaseUpper16 << 16 | Bridge->IoBase << 8);
3596 IoAddress32 &= 0xfffff000;
3597 ShellPrintHiiEx (
3598 -1,
3599 -1,
3600 NULL,
3601 STRING_TOKEN (STR_PCI2_TWO_VARS),
3602 gShellDebug1HiiHandle,
3603 INDEX_OF (&(Bridge->IoBase)),
3604 IoAddress32
3605 );
3606
3607 IoAddress32 = (Bridge->IoLimitUpper16 << 16 | Bridge->IoLimit << 8);
3608 IoAddress32 |= 0x00000fff;
3609 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);
3610
3611 //
3612 // Memory Base & Limit
3613 //
3614 ShellPrintHiiEx (
3615 -1,
3616 -1,
3617 NULL,
3618 STRING_TOKEN (STR_PCI2_MEMORY),
3619 gShellDebug1HiiHandle,
3620 INDEX_OF (&(Bridge->MemoryBase)),
3621 (Bridge->MemoryBase << 16) & 0xfff00000
3622 );
3623
3624 ShellPrintHiiEx (
3625 -1,
3626 -1,
3627 NULL,
3628 STRING_TOKEN (STR_PCI2_ONE_VAR),
3629 gShellDebug1HiiHandle,
3630 (Bridge->MemoryLimit << 16) | 0x000fffff
3631 );
3632
3633 //
3634 // Pre-fetch-able Memory Base & Limit
3635 //
3636 ShellPrintHiiEx (
3637 -1,
3638 -1,
3639 NULL,
3640 STRING_TOKEN (STR_PCI2_PREFETCHABLE),
3641 gShellDebug1HiiHandle,
3642 INDEX_OF (&(Bridge->PrefetchableMemoryBase)),
3643 Bridge->PrefetchableBaseUpper32,
3644 (Bridge->PrefetchableMemoryBase << 16) & 0xfff00000
3645 );
3646
3647 ShellPrintHiiEx (
3648 -1,
3649 -1,
3650 NULL,
3651 STRING_TOKEN (STR_PCI2_TWO_VARS_2),
3652 gShellDebug1HiiHandle,
3653 Bridge->PrefetchableLimitUpper32,
3654 (Bridge->PrefetchableMemoryLimit << 16) | 0x000fffff
3655 );
3656
3657 //
3658 // Print register Capabilities Pointer
3659 //
3660 ShellPrintHiiEx (
3661 -1,
3662 -1,
3663 NULL,
3664 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),
3665 gShellDebug1HiiHandle,
3666 INDEX_OF (&(Bridge->CapabilityPtr)),
3667 Bridge->CapabilityPtr
3668 );
3669
3670 //
3671 // Print register Bridge Control
3672 //
3673 PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);
3674
3675 //
3676 // Print register Interrupt Line & PIN
3677 //
3678 ShellPrintHiiEx (
3679 -1,
3680 -1,
3681 NULL,
3682 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),
3683 gShellDebug1HiiHandle,
3684 INDEX_OF (&(Bridge->InterruptLine)),
3685 Bridge->InterruptLine
3686 );
3687
3688 ShellPrintHiiEx (
3689 -1,
3690 -1,
3691 NULL,
3692 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),
3693 gShellDebug1HiiHandle,
3694 INDEX_OF (&(Bridge->InterruptPin)),
3695 Bridge->InterruptPin
3696 );
3697
3698 return EFI_SUCCESS;
3699 }
3700
3701 /**
3702 Explain the Base Address Register(Bar) in PCI configuration space.
3703
3704 @param[in] Bar Points to the Base Address Register intended to interpret.
3705 @param[in] Command Points to the register Command.
3706 @param[in] Address Address used to access configuration space of this PCI device.
3707 @param[in] IoDev Handle used to access configuration space of PCI device.
3708 @param[in, out] Index The Index.
3709
3710 @retval EFI_SUCCESS The command completed successfully.
3711 **/
3712 EFI_STATUS
3713 PciExplainBar (
3714 IN UINT32 *Bar,
3715 IN UINT16 *Command,
3716 IN UINT64 Address,
3717 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,
3718 IN OUT UINTN *Index
3719 )
3720 {
3721 UINT16 OldCommand;
3722 UINT16 NewCommand;
3723 UINT64 Bar64;
3724 UINT32 OldBar32;
3725 UINT32 NewBar32;
3726 UINT64 OldBar64;
3727 UINT64 NewBar64;
3728 BOOLEAN IsMem;
3729 BOOLEAN IsBar32;
3730 UINT64 RegAddress;
3731
3732 IsBar32 = TRUE;
3733 Bar64 = 0;
3734 NewBar32 = 0;
3735 NewBar64 = 0;
3736
3737 //
3738 // According the bar type, list detail about this bar, for example: 32 or
3739 // 64 bits; pre-fetchable or not.
3740 //
3741 if ((*Bar & BIT0) == 0) {
3742 //
3743 // This bar is of memory type
3744 //
3745 IsMem = TRUE;
3746
3747 if (((*Bar & BIT1) == 0) && ((*Bar & BIT2) == 0)) {
3748 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);
3749 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);
3750 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);
3751 } else if (((*Bar & BIT1) == 0) && ((*Bar & BIT2) != 0)) {
3752 Bar64 = 0x0;
3753 CopyMem (&Bar64, Bar, sizeof (UINT64));
3754 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32)RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));
3755 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32)(Bar64 & 0xfffffffffffffff0ULL));
3756 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);
3757 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);
3758 IsBar32 = FALSE;
3759 *Index += 1;
3760 } else {
3761 //
3762 // Reserved
3763 //
3764 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);
3765 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);
3766 }
3767
3768 if ((*Bar & BIT3) == 0) {
3769 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);
3770 } else {
3771 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);
3772 }
3773 } else {
3774 //
3775 // This bar is of io type
3776 //
3777 IsMem = FALSE;
3778 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);
3779 ShellPrintEx (-1, -1, L"I/O ");
3780 }
3781
3782 //
3783 // Get BAR length(or the amount of resource this bar demands for). To get
3784 // Bar length, first we should temporarily disable I/O and memory access
3785 // of this function(by set bits in the register Command), then write all
3786 // "1"s to this bar. The bar value read back is the amount of resource
3787 // this bar demands for.
3788 //
3789 //
3790 // Disable io & mem access
3791 //
3792 OldCommand = *Command;
3793 NewCommand = (UINT16)(OldCommand & 0xfffc);
3794 RegAddress = Address | INDEX_OF (Command);
3795 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);
3796
3797 RegAddress = Address | INDEX_OF (Bar);
3798
3799 //
3800 // Read after write the BAR to get the size
3801 //
3802 if (IsBar32) {
3803 OldBar32 = *Bar;
3804 NewBar32 = 0xffffffff;
3805
3806 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);
3807 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);
3808 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);
3809
3810 if (IsMem) {
3811 NewBar32 = NewBar32 & 0xfffffff0;
3812 NewBar32 = (~NewBar32) + 1;
3813 } else {
3814 NewBar32 = NewBar32 & 0xfffffffc;
3815 NewBar32 = (~NewBar32) + 1;
3816 NewBar32 = NewBar32 & 0x0000ffff;
3817 }
3818 } else {
3819 OldBar64 = 0x0;
3820 CopyMem (&OldBar64, Bar, sizeof (UINT64));
3821 NewBar64 = 0xffffffffffffffffULL;
3822
3823 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);
3824 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);
3825 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);
3826
3827 if (IsMem) {
3828 NewBar64 = NewBar64 & 0xfffffffffffffff0ULL;
3829 NewBar64 = (~NewBar64) + 1;
3830 } else {
3831 NewBar64 = NewBar64 & 0xfffffffffffffffcULL;
3832 NewBar64 = (~NewBar64) + 1;
3833 NewBar64 = NewBar64 & 0x000000000000ffff;
3834 }
3835 }
3836
3837 //
3838 // Enable io & mem access
3839 //
3840 RegAddress = Address | INDEX_OF (Command);
3841 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);
3842
3843 if (IsMem) {
3844 if (IsBar32) {
3845 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);
3846 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);
3847 } else {
3848 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32)RShiftU64 (NewBar64, 32));
3849 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32)NewBar64);
3850 ShellPrintEx (-1, -1, L" ");
3851 ShellPrintHiiEx (
3852 -1,
3853 -1,
3854 NULL,
3855 STRING_TOKEN (STR_PCI2_RSHIFT),
3856 gShellDebug1HiiHandle,
3857 (UINT32)RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)
3858 );
3859 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32)(NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));
3860 }
3861 } else {
3862 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);
3863 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);
3864 }
3865
3866 return EFI_SUCCESS;
3867 }
3868
3869 /**
3870 Explain the cardbus specific part of data in PCI configuration space.
3871
3872 @param[in] CardBus CardBus specific region of PCI configuration space.
3873 @param[in] Address Address used to access configuration space of this PCI device.
3874 @param[in] IoDev Handle used to access configuration space of PCI device.
3875
3876 @retval EFI_SUCCESS The command completed successfully.
3877 **/
3878 EFI_STATUS
3879 PciExplainCardBusData (
3880 IN PCI_CARDBUS_CONTROL_REGISTER *CardBus,
3881 IN UINT64 Address,
3882 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
3883 )
3884 {
3885 BOOLEAN Io32Bit;
3886 PCI_CARDBUS_DATA *CardBusData;
3887
3888 ShellPrintHiiEx (
3889 -1,
3890 -1,
3891 NULL,
3892 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),
3893 gShellDebug1HiiHandle,
3894 INDEX_OF (&(CardBus->CardBusSocketReg)),
3895 CardBus->CardBusSocketReg
3896 );
3897
3898 //
3899 // Print Secondary Status
3900 //
3901 PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);
3902
3903 //
3904 // Print Bus Numbers(Primary bus number, CardBus bus number, and
3905 // Subordinate bus number
3906 //
3907 ShellPrintHiiEx (
3908 -1,
3909 -1,
3910 NULL,
3911 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),
3912 gShellDebug1HiiHandle,
3913 INDEX_OF (&(CardBus->PciBusNumber)),
3914 INDEX_OF (&(CardBus->CardBusBusNumber)),
3915 INDEX_OF (&(CardBus->SubordinateBusNumber))
3916 );
3917
3918 ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");
3919
3920 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);
3921 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);
3922 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);
3923
3924 //
3925 // Print CardBus Latency Timer
3926 //
3927 ShellPrintHiiEx (
3928 -1,
3929 -1,
3930 NULL,
3931 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),
3932 gShellDebug1HiiHandle,
3933 INDEX_OF (&(CardBus->CardBusLatencyTimer)),
3934 CardBus->CardBusLatencyTimer
3935 );
3936
3937 //
3938 // Print Memory/Io ranges this cardbus bridge forwards
3939 //
3940 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);
3941 ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");
3942
3943 ShellPrintHiiEx (
3944 -1,
3945 -1,
3946 NULL,
3947 STRING_TOKEN (STR_PCI2_MEM_3),
3948 gShellDebug1HiiHandle,
3949 INDEX_OF (&(CardBus->MemoryBase0)),
3950 CardBus->BridgeControl & BIT8 ? L" Prefetchable" : L"Non-Prefetchable",
3951 CardBus->MemoryBase0 & 0xfffff000,
3952 CardBus->MemoryLimit0 | 0x00000fff
3953 );
3954
3955 ShellPrintHiiEx (
3956 -1,
3957 -1,
3958 NULL,
3959 STRING_TOKEN (STR_PCI2_MEM_3),
3960 gShellDebug1HiiHandle,
3961 INDEX_OF (&(CardBus->MemoryBase1)),
3962 CardBus->BridgeControl & BIT9 ? L" Prefetchable" : L"Non-Prefetchable",
3963 CardBus->MemoryBase1 & 0xfffff000,
3964 CardBus->MemoryLimit1 | 0x00000fff
3965 );
3966
3967 Io32Bit = (BOOLEAN)(CardBus->IoBase0 & BIT0);
3968 ShellPrintHiiEx (
3969 -1,
3970 -1,
3971 NULL,
3972 STRING_TOKEN (STR_PCI2_IO_2),
3973 gShellDebug1HiiHandle,
3974 INDEX_OF (&(CardBus->IoBase0)),
3975 Io32Bit ? L" 32 bit" : L" 16 bit",
3976 CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),
3977 (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003
3978 );
3979
3980 Io32Bit = (BOOLEAN)(CardBus->IoBase1 & BIT0);
3981 ShellPrintHiiEx (
3982 -1,
3983 -1,
3984 NULL,
3985 STRING_TOKEN (STR_PCI2_IO_2),
3986 gShellDebug1HiiHandle,
3987 INDEX_OF (&(CardBus->IoBase1)),
3988 Io32Bit ? L" 32 bit" : L" 16 bit",
3989 CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),
3990 (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003
3991 );
3992
3993 //
3994 // Print register Interrupt Line & PIN
3995 //
3996 ShellPrintHiiEx (
3997 -1,
3998 -1,
3999 NULL,
4000 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),
4001 gShellDebug1HiiHandle,
4002 INDEX_OF (&(CardBus->InterruptLine)),
4003 CardBus->InterruptLine,
4004 INDEX_OF (&(CardBus->InterruptPin)),
4005 CardBus->InterruptPin
4006 );
4007
4008 //
4009 // Print register Bridge Control
4010 //
4011 PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);
4012
4013 //
4014 // Print some registers in data region of PCI configuration space for cardbus
4015 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base
4016 // Address.
4017 //
4018 CardBusData = (PCI_CARDBUS_DATA *)((UINT8 *)CardBus + sizeof (PCI_CARDBUS_CONTROL_REGISTER));
4019
4020 ShellPrintHiiEx (
4021 -1,
4022 -1,
4023 NULL,
4024 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),
4025 gShellDebug1HiiHandle,
4026 INDEX_OF (&(CardBusData->SubVendorId)),
4027 CardBusData->SubVendorId,
4028 INDEX_OF (&(CardBusData->SubSystemId)),
4029 CardBusData->SubSystemId
4030 );
4031
4032 ShellPrintHiiEx (
4033 -1,
4034 -1,
4035 NULL,
4036 STRING_TOKEN (STR_PCI2_OPTIONAL),
4037 gShellDebug1HiiHandle,
4038 INDEX_OF (&(CardBusData->LegacyBase)),
4039 CardBusData->LegacyBase
4040 );
4041
4042 return EFI_SUCCESS;
4043 }
4044
4045 /**
4046 Explain each meaningful bit of register Status. The definition of Status is
4047 slightly different depending on the PCI header type.
4048
4049 @param[in] Status Points to the content of register Status.
4050 @param[in] MainStatus Indicates if this register is main status(not secondary
4051 status).
4052 @param[in] HeaderType Header type of this PCI device.
4053
4054 @retval EFI_SUCCESS The command completed successfully.
4055 **/
4056 EFI_STATUS
4057 PciExplainStatus (
4058 IN UINT16 *Status,
4059 IN BOOLEAN MainStatus,
4060 IN PCI_HEADER_TYPE HeaderType
4061 )
4062 {
4063 if (MainStatus) {
4064 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);
4065 } else {
4066 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);
4067 }
4068
4069 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & BIT4) != 0);
4070
4071 //
4072 // Bit 5 is meaningless for CardBus Bridge
4073 //
4074 if (HeaderType == PciCardBusBridge) {
4075 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & BIT5) != 0);
4076 } else {
4077 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & BIT5) != 0);
4078 }
4079
4080 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & BIT7) != 0);
4081
4082 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & BIT8) != 0);
4083 //
4084 // Bit 9 and bit 10 together decides the DEVSEL timing
4085 //
4086 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);
4087 if (((*Status & BIT9) == 0) && ((*Status & BIT10) == 0)) {
4088 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);
4089 } else if (((*Status & BIT9) != 0) && ((*Status & BIT10) == 0)) {
4090 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);
4091 } else if (((*Status & BIT9) == 0) && ((*Status & BIT10) != 0)) {
4092 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);
4093 } else {
4094 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);
4095 }
4096
4097 ShellPrintHiiEx (
4098 -1,
4099 -1,
4100 NULL,
4101 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),
4102 gShellDebug1HiiHandle,
4103 (*Status & BIT11) != 0
4104 );
4105
4106 ShellPrintHiiEx (
4107 -1,
4108 -1,
4109 NULL,
4110 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),
4111 gShellDebug1HiiHandle,
4112 (*Status & BIT12) != 0
4113 );
4114
4115 ShellPrintHiiEx (
4116 -1,
4117 -1,
4118 NULL,
4119 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),
4120 gShellDebug1HiiHandle,
4121 (*Status & BIT13) != 0
4122 );
4123
4124 if (MainStatus) {
4125 ShellPrintHiiEx (
4126 -1,
4127 -1,
4128 NULL,
4129 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),
4130 gShellDebug1HiiHandle,
4131 (*Status & BIT14) != 0
4132 );
4133 } else {
4134 ShellPrintHiiEx (
4135 -1,
4136 -1,
4137 NULL,
4138 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),
4139 gShellDebug1HiiHandle,
4140 (*Status & BIT14) != 0
4141 );
4142 }
4143
4144 ShellPrintHiiEx (
4145 -1,
4146 -1,
4147 NULL,
4148 STRING_TOKEN (STR_PCI2_DETECTED_ERROR),
4149 gShellDebug1HiiHandle,
4150 (*Status & BIT15) != 0
4151 );
4152
4153 return EFI_SUCCESS;
4154 }
4155
4156 /**
4157 Explain each meaningful bit of register Command.
4158
4159 @param[in] Command Points to the content of register Command.
4160
4161 @retval EFI_SUCCESS The command completed successfully.
4162 **/
4163 EFI_STATUS
4164 PciExplainCommand (
4165 IN UINT16 *Command
4166 )
4167 {
4168 //
4169 // Print the binary value of register Command
4170 //
4171 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);
4172
4173 //
4174 // Explain register Command bit by bit
4175 //
4176 ShellPrintHiiEx (
4177 -1,
4178 -1,
4179 NULL,
4180 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),
4181 gShellDebug1HiiHandle,
4182 (*Command & BIT0) != 0
4183 );
4184
4185 ShellPrintHiiEx (
4186 -1,
4187 -1,
4188 NULL,
4189 STRING_TOKEN (STR_PCI2_MEMORY_SPACE),
4190 gShellDebug1HiiHandle,
4191 (*Command & BIT1) != 0
4192 );
4193
4194 ShellPrintHiiEx (
4195 -1,
4196 -1,
4197 NULL,
4198 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),
4199 gShellDebug1HiiHandle,
4200 (*Command & BIT2) != 0
4201 );
4202
4203 ShellPrintHiiEx (
4204 -1,
4205 -1,
4206 NULL,
4207 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),
4208 gShellDebug1HiiHandle,
4209 (*Command & BIT3) != 0
4210 );
4211
4212 ShellPrintHiiEx (
4213 -1,
4214 -1,
4215 NULL,
4216 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),
4217 gShellDebug1HiiHandle,
4218 (*Command & BIT4) != 0
4219 );
4220
4221 ShellPrintHiiEx (
4222 -1,
4223 -1,
4224 NULL,
4225 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),
4226 gShellDebug1HiiHandle,
4227 (*Command & BIT5) != 0
4228 );
4229
4230 ShellPrintHiiEx (
4231 -1,
4232 -1,
4233 NULL,
4234 STRING_TOKEN (STR_PCI2_ASSERT_PERR),
4235 gShellDebug1HiiHandle,
4236 (*Command & BIT6) != 0
4237 );
4238
4239 ShellPrintHiiEx (
4240 -1,
4241 -1,
4242 NULL,
4243 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),
4244 gShellDebug1HiiHandle,
4245 (*Command & BIT7) != 0
4246 );
4247
4248 ShellPrintHiiEx (
4249 -1,
4250 -1,
4251 NULL,
4252 STRING_TOKEN (STR_PCI2_SERR_DRIVER),
4253 gShellDebug1HiiHandle,
4254 (*Command & BIT8) != 0
4255 );
4256
4257 ShellPrintHiiEx (
4258 -1,
4259 -1,
4260 NULL,
4261 STRING_TOKEN (STR_PCI2_FAST_BACK_2),
4262 gShellDebug1HiiHandle,
4263 (*Command & BIT9) != 0
4264 );
4265
4266 return EFI_SUCCESS;
4267 }
4268
4269 /**
4270 Explain each meaningful bit of register Bridge Control.
4271
4272 @param[in] BridgeControl Points to the content of register Bridge Control.
4273 @param[in] HeaderType The headertype.
4274
4275 @retval EFI_SUCCESS The command completed successfully.
4276 **/
4277 EFI_STATUS
4278 PciExplainBridgeControl (
4279 IN UINT16 *BridgeControl,
4280 IN PCI_HEADER_TYPE HeaderType
4281 )
4282 {
4283 ShellPrintHiiEx (
4284 -1,
4285 -1,
4286 NULL,
4287 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),
4288 gShellDebug1HiiHandle,
4289 INDEX_OF (BridgeControl),
4290 *BridgeControl
4291 );
4292
4293 ShellPrintHiiEx (
4294 -1,
4295 -1,
4296 NULL,
4297 STRING_TOKEN (STR_PCI2_PARITY_ERROR),
4298 gShellDebug1HiiHandle,
4299 (*BridgeControl & BIT0) != 0
4300 );
4301 ShellPrintHiiEx (
4302 -1,
4303 -1,
4304 NULL,
4305 STRING_TOKEN (STR_PCI2_SERR_ENABLE),
4306 gShellDebug1HiiHandle,
4307 (*BridgeControl & BIT1) != 0
4308 );
4309 ShellPrintHiiEx (
4310 -1,
4311 -1,
4312 NULL,
4313 STRING_TOKEN (STR_PCI2_ISA_ENABLE),
4314 gShellDebug1HiiHandle,
4315 (*BridgeControl & BIT2) != 0
4316 );
4317 ShellPrintHiiEx (
4318 -1,
4319 -1,
4320 NULL,
4321 STRING_TOKEN (STR_PCI2_VGA_ENABLE),
4322 gShellDebug1HiiHandle,
4323 (*BridgeControl & BIT3) != 0
4324 );
4325 ShellPrintHiiEx (
4326 -1,
4327 -1,
4328 NULL,
4329 STRING_TOKEN (STR_PCI2_MASTER_ABORT),
4330 gShellDebug1HiiHandle,
4331 (*BridgeControl & BIT5) != 0
4332 );
4333
4334 //
4335 // Register Bridge Control has some slight differences between P2P bridge
4336 // and Cardbus bridge from bit 6 to bit 11.
4337 //
4338 if (HeaderType == PciP2pBridge) {
4339 ShellPrintHiiEx (
4340 -1,
4341 -1,
4342 NULL,
4343 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),
4344 gShellDebug1HiiHandle,
4345 (*BridgeControl & BIT6) != 0
4346 );
4347 ShellPrintHiiEx (
4348 -1,
4349 -1,
4350 NULL,
4351 STRING_TOKEN (STR_PCI2_FAST_ENABLE),
4352 gShellDebug1HiiHandle,
4353 (*BridgeControl & BIT7) != 0
4354 );
4355 ShellPrintHiiEx (
4356 -1,
4357 -1,
4358 NULL,
4359 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),
4360 gShellDebug1HiiHandle,
4361 (*BridgeControl & BIT8) != 0 ? L"2^10" : L"2^15"
4362 );
4363 ShellPrintHiiEx (
4364 -1,
4365 -1,
4366 NULL,
4367 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),
4368 gShellDebug1HiiHandle,
4369 (*BridgeControl & BIT9) != 0 ? L"2^10" : L"2^15"
4370 );
4371 ShellPrintHiiEx (
4372 -1,
4373 -1,
4374 NULL,
4375 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),
4376 gShellDebug1HiiHandle,
4377 (*BridgeControl & BIT10) != 0
4378 );
4379 ShellPrintHiiEx (
4380 -1,
4381 -1,
4382 NULL,
4383 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),
4384 gShellDebug1HiiHandle,
4385 (*BridgeControl & BIT11) != 0
4386 );
4387 } else {
4388 ShellPrintHiiEx (
4389 -1,
4390 -1,
4391 NULL,
4392 STRING_TOKEN (STR_PCI2_CARDBUS_RESET),
4393 gShellDebug1HiiHandle,
4394 (*BridgeControl & BIT6) != 0
4395 );
4396 ShellPrintHiiEx (
4397 -1,
4398 -1,
4399 NULL,
4400 STRING_TOKEN (STR_PCI2_IREQ_ENABLE),
4401 gShellDebug1HiiHandle,
4402 (*BridgeControl & BIT7) != 0
4403 );
4404 ShellPrintHiiEx (
4405 -1,
4406 -1,
4407 NULL,
4408 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),
4409 gShellDebug1HiiHandle,
4410 (*BridgeControl & BIT10) != 0
4411 );
4412 }
4413
4414 return EFI_SUCCESS;
4415 }
4416
4417 /**
4418 Locate capability register block per capability ID.
4419
4420 @param[in] ConfigSpace Data in PCI configuration space.
4421 @param[in] CapabilityId The capability ID.
4422
4423 @return The offset of the register block per capability ID,
4424 or 0 if the register block cannot be found.
4425 **/
4426 UINT8
4427 LocatePciCapability (
4428 IN PCI_CONFIG_SPACE *ConfigSpace,
4429 IN UINT8 CapabilityId
4430 )
4431 {
4432 UINT8 CapabilityPtr;
4433 EFI_PCI_CAPABILITY_HDR *CapabilityEntry;
4434
4435 //
4436 // To check the cpability of this device supports
4437 //
4438 if ((ConfigSpace->Common.Status & EFI_PCI_STATUS_CAPABILITY) == 0) {
4439 return 0;
4440 }
4441
4442 switch ((PCI_HEADER_TYPE)(ConfigSpace->Common.HeaderType & 0x7f)) {
4443 case PciDevice:
4444 CapabilityPtr = ConfigSpace->NonCommon.Device.CapabilityPtr;
4445 break;
4446 case PciP2pBridge:
4447 CapabilityPtr = ConfigSpace->NonCommon.Bridge.CapabilityPtr;
4448 break;
4449 case PciCardBusBridge:
4450 CapabilityPtr = ConfigSpace->NonCommon.CardBus.Cap_Ptr;
4451 break;
4452 default:
4453 return 0;
4454 }
4455
4456 while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {
4457 CapabilityEntry = (EFI_PCI_CAPABILITY_HDR *)((UINT8 *)ConfigSpace + CapabilityPtr);
4458 if (CapabilityEntry->CapabilityID == CapabilityId) {
4459 return CapabilityPtr;
4460 }
4461
4462 //
4463 // Certain PCI device may incorrectly have capability pointing to itself,
4464 // break to avoid dead loop.
4465 //
4466 if (CapabilityPtr == CapabilityEntry->NextItemPtr) {
4467 break;
4468 }
4469
4470 CapabilityPtr = CapabilityEntry->NextItemPtr;
4471 }
4472
4473 return 0;
4474 }
4475
4476 /**
4477 Print out information of the capability information.
4478
4479 @param[in] PciExpressCap The pointer to the structure about the device.
4480
4481 @retval EFI_SUCCESS The operation was successful.
4482 **/
4483 EFI_STATUS
4484 ExplainPcieCapReg (
4485 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
4486 )
4487 {
4488 CHAR16 *DevicePortType;
4489
4490 ShellPrintEx (
4491 -1,
4492 -1,
4493 L" Capability Version(3:0): %E0x%04x%N\r\n",
4494 PciExpressCap->Capability.Bits.Version
4495 );
4496 if (PciExpressCap->Capability.Bits.DevicePortType < ARRAY_SIZE (DevicePortTypeTable)) {
4497 DevicePortType = DevicePortTypeTable[PciExpressCap->Capability.Bits.DevicePortType];
4498 } else {
4499 DevicePortType = L"Unknown Type";
4500 }
4501
4502 ShellPrintEx (
4503 -1,
4504 -1,
4505 L" Device/PortType(7:4): %E%s%N\r\n",
4506 DevicePortType
4507 );
4508 //
4509 // 'Slot Implemented' is only valid for:
4510 // a) Root Port of PCI Express Root Complex, or
4511 // b) Downstream Port of PCI Express Switch
4512 //
4513 if ((PciExpressCap->Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_ROOT_PORT) ||
4514 (PciExpressCap->Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT))
4515 {
4516 ShellPrintEx (
4517 -1,
4518 -1,
4519 L" Slot Implemented(8): %E%d%N\r\n",
4520 PciExpressCap->Capability.Bits.SlotImplemented
4521 );
4522 }
4523
4524 ShellPrintEx (
4525 -1,
4526 -1,
4527 L" Interrupt Message Number(13:9): %E0x%05x%N\r\n",
4528 PciExpressCap->Capability.Bits.InterruptMessageNumber
4529 );
4530 return EFI_SUCCESS;
4531 }
4532
4533 /**
4534 Print out information of the device capability information.
4535
4536 @param[in] PciExpressCap The pointer to the structure about the device.
4537
4538 @retval EFI_SUCCESS The operation was successful.
4539 **/
4540 EFI_STATUS
4541 ExplainPcieDeviceCap (
4542 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
4543 )
4544 {
4545 UINT8 DevicePortType;
4546 UINT8 L0sLatency;
4547 UINT8 L1Latency;
4548
4549 DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;
4550 ShellPrintEx (-1, -1, L" Max_Payload_Size Supported(2:0): ");
4551 if (PciExpressCap->DeviceCapability.Bits.MaxPayloadSize < 6) {
4552 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PciExpressCap->DeviceCapability.Bits.MaxPayloadSize + 7));
4553 } else {
4554 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");
4555 }
4556
4557 ShellPrintEx (
4558 -1,
4559 -1,
4560 L" Phantom Functions Supported(4:3): %E%d%N\r\n",
4561 PciExpressCap->DeviceCapability.Bits.PhantomFunctions
4562 );
4563 ShellPrintEx (
4564 -1,
4565 -1,
4566 L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",
4567 PciExpressCap->DeviceCapability.Bits.ExtendedTagField ? 8 : 5
4568 );
4569 //
4570 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint
4571 //
4572 if (IS_PCIE_ENDPOINT (DevicePortType)) {
4573 L0sLatency = (UINT8)PciExpressCap->DeviceCapability.Bits.EndpointL0sAcceptableLatency;
4574 L1Latency = (UINT8)PciExpressCap->DeviceCapability.Bits.EndpointL1AcceptableLatency;
4575 ShellPrintEx (-1, -1, L" Endpoint L0s Acceptable Latency(8:6): ");
4576 if (L0sLatency < 4) {
4577 ShellPrintEx (-1, -1, L"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency + 6));
4578 } else {
4579 if (L0sLatency < 7) {
4580 ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L0sLatency - 3));
4581 } else {
4582 ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");
4583 }
4584 }
4585
4586 ShellPrintEx (-1, -1, L" Endpoint L1 Acceptable Latency(11:9): ");
4587 if (L1Latency < 7) {
4588 ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L1Latency + 1));
4589 } else {
4590 ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");
4591 }
4592 }
4593
4594 ShellPrintEx (
4595 -1,
4596 -1,
4597 L" Role-based Error Reporting(15): %E%d%N\r\n",
4598 PciExpressCap->DeviceCapability.Bits.RoleBasedErrorReporting
4599 );
4600 //
4601 // Only valid for Upstream Port:
4602 // a) Captured Slot Power Limit Value
4603 // b) Captured Slot Power Scale
4604 //
4605 if (DevicePortType == PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT) {
4606 ShellPrintEx (
4607 -1,
4608 -1,
4609 L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",
4610 PciExpressCap->DeviceCapability.Bits.CapturedSlotPowerLimitValue
4611 );
4612 ShellPrintEx (
4613 -1,
4614 -1,
4615 L" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",
4616 SlotPwrLmtScaleTable[PciExpressCap->DeviceCapability.Bits.CapturedSlotPowerLimitScale]
4617 );
4618 }
4619
4620 //
4621 // Function Level Reset Capability is only valid for Endpoint
4622 //
4623 if (IS_PCIE_ENDPOINT (DevicePortType)) {
4624 ShellPrintEx (
4625 -1,
4626 -1,
4627 L" Function Level Reset Capability(28): %E%d%N\r\n",
4628 PciExpressCap->DeviceCapability.Bits.FunctionLevelReset
4629 );
4630 }
4631
4632 return EFI_SUCCESS;
4633 }
4634
4635 /**
4636 Print out information of the device control information.
4637
4638 @param[in] PciExpressCap The pointer to the structure about the device.
4639
4640 @retval EFI_SUCCESS The operation was successful.
4641 **/
4642 EFI_STATUS
4643 ExplainPcieDeviceControl (
4644 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
4645 )
4646 {
4647 ShellPrintEx (
4648 -1,
4649 -1,
4650 L" Correctable Error Reporting Enable(0): %E%d%N\r\n",
4651 PciExpressCap->DeviceControl.Bits.CorrectableError
4652 );
4653 ShellPrintEx (
4654 -1,
4655 -1,
4656 L" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",
4657 PciExpressCap->DeviceControl.Bits.NonFatalError
4658 );
4659 ShellPrintEx (
4660 -1,
4661 -1,
4662 L" Fatal Error Reporting Enable(2): %E%d%N\r\n",
4663 PciExpressCap->DeviceControl.Bits.FatalError
4664 );
4665 ShellPrintEx (
4666 -1,
4667 -1,
4668 L" Unsupported Request Reporting Enable(3): %E%d%N\r\n",
4669 PciExpressCap->DeviceControl.Bits.UnsupportedRequest
4670 );
4671 ShellPrintEx (
4672 -1,
4673 -1,
4674 L" Enable Relaxed Ordering(4): %E%d%N\r\n",
4675 PciExpressCap->DeviceControl.Bits.RelaxedOrdering
4676 );
4677 ShellPrintEx (-1, -1, L" Max_Payload_Size(7:5): ");
4678 if (PciExpressCap->DeviceControl.Bits.MaxPayloadSize < 6) {
4679 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PciExpressCap->DeviceControl.Bits.MaxPayloadSize + 7));
4680 } else {
4681 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");
4682 }
4683
4684 ShellPrintEx (
4685 -1,
4686 -1,
4687 L" Extended Tag Field Enable(8): %E%d%N\r\n",
4688 PciExpressCap->DeviceControl.Bits.ExtendedTagField
4689 );
4690 ShellPrintEx (
4691 -1,
4692 -1,
4693 L" Phantom Functions Enable(9): %E%d%N\r\n",
4694 PciExpressCap->DeviceControl.Bits.PhantomFunctions
4695 );
4696 ShellPrintEx (
4697 -1,
4698 -1,
4699 L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",
4700 PciExpressCap->DeviceControl.Bits.AuxPower
4701 );
4702 ShellPrintEx (
4703 -1,
4704 -1,
4705 L" Enable No Snoop(11): %E%d%N\r\n",
4706 PciExpressCap->DeviceControl.Bits.NoSnoop
4707 );
4708 ShellPrintEx (-1, -1, L" Max_Read_Request_Size(14:12): ");
4709 if (PciExpressCap->DeviceControl.Bits.MaxReadRequestSize < 6) {
4710 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PciExpressCap->DeviceControl.Bits.MaxReadRequestSize + 7));
4711 } else {
4712 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");
4713 }
4714
4715 //
4716 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges
4717 //
4718 if (PciExpressCap->Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE) {
4719 ShellPrintEx (
4720 -1,
4721 -1,
4722 L" Bridge Configuration Retry Enable(15): %E%d%N\r\n",
4723 PciExpressCap->DeviceControl.Bits.BridgeConfigurationRetryOrFunctionLevelReset
4724 );
4725 }
4726
4727 return EFI_SUCCESS;
4728 }
4729
4730 /**
4731 Print out information of the device status information.
4732
4733 @param[in] PciExpressCap The pointer to the structure about the device.
4734
4735 @retval EFI_SUCCESS The operation was successful.
4736 **/
4737 EFI_STATUS
4738 ExplainPcieDeviceStatus (
4739 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
4740 )
4741 {
4742 ShellPrintEx (
4743 -1,
4744 -1,
4745 L" Correctable Error Detected(0): %E%d%N\r\n",
4746 PciExpressCap->DeviceStatus.Bits.CorrectableError
4747 );
4748 ShellPrintEx (
4749 -1,
4750 -1,
4751 L" Non-Fatal Error Detected(1): %E%d%N\r\n",
4752 PciExpressCap->DeviceStatus.Bits.NonFatalError
4753 );
4754 ShellPrintEx (
4755 -1,
4756 -1,
4757 L" Fatal Error Detected(2): %E%d%N\r\n",
4758 PciExpressCap->DeviceStatus.Bits.FatalError
4759 );
4760 ShellPrintEx (
4761 -1,
4762 -1,
4763 L" Unsupported Request Detected(3): %E%d%N\r\n",
4764 PciExpressCap->DeviceStatus.Bits.UnsupportedRequest
4765 );
4766 ShellPrintEx (
4767 -1,
4768 -1,
4769 L" AUX Power Detected(4): %E%d%N\r\n",
4770 PciExpressCap->DeviceStatus.Bits.AuxPower
4771 );
4772 ShellPrintEx (
4773 -1,
4774 -1,
4775 L" Transactions Pending(5): %E%d%N\r\n",
4776 PciExpressCap->DeviceStatus.Bits.TransactionsPending
4777 );
4778 return EFI_SUCCESS;
4779 }
4780
4781 /**
4782 Print out information of the device link information.
4783
4784 @param[in] PciExpressCap The pointer to the structure about the device.
4785
4786 @retval EFI_SUCCESS The operation was successful.
4787 **/
4788 EFI_STATUS
4789 ExplainPcieLinkCap (
4790 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
4791 )
4792 {
4793 CHAR16 *MaxLinkSpeed;
4794 CHAR16 *AspmValue;
4795
4796 switch (PciExpressCap->LinkCapability.Bits.MaxLinkSpeed) {
4797 case 1:
4798 MaxLinkSpeed = L"2.5 GT/s";
4799 break;
4800 case 2:
4801 MaxLinkSpeed = L"5.0 GT/s";
4802 break;
4803 case 3:
4804 MaxLinkSpeed = L"8.0 GT/s";
4805 break;
4806 case 4:
4807 MaxLinkSpeed = L"16.0 GT/s";
4808 break;
4809 case 5:
4810 MaxLinkSpeed = L"32.0 GT/s";
4811 break;
4812 default:
4813 MaxLinkSpeed = L"Reserved";
4814 break;
4815 }
4816
4817 ShellPrintEx (
4818 -1,
4819 -1,
4820 L" Maximum Link Speed(3:0): %E%s%N\r\n",
4821 MaxLinkSpeed
4822 );
4823 ShellPrintEx (
4824 -1,
4825 -1,
4826 L" Maximum Link Width(9:4): %Ex%d%N\r\n",
4827 PciExpressCap->LinkCapability.Bits.MaxLinkWidth
4828 );
4829 switch (PciExpressCap->LinkCapability.Bits.Aspm) {
4830 case 0:
4831 AspmValue = L"Not";
4832 break;
4833 case 1:
4834 AspmValue = L"L0s";
4835 break;
4836 case 2:
4837 AspmValue = L"L1";
4838 break;
4839 case 3:
4840 AspmValue = L"L0s and L1";
4841 break;
4842 default:
4843 AspmValue = L"Reserved";
4844 break;
4845 }
4846
4847 ShellPrintEx (
4848 -1,
4849 -1,
4850 L" Active State Power Management Support(11:10): %E%s Supported%N\r\n",
4851 AspmValue
4852 );
4853 ShellPrintEx (
4854 -1,
4855 -1,
4856 L" L0s Exit Latency(14:12): %E%s%N\r\n",
4857 L0sLatencyStrTable[PciExpressCap->LinkCapability.Bits.L0sExitLatency]
4858 );
4859 ShellPrintEx (
4860 -1,
4861 -1,
4862 L" L1 Exit Latency(17:15): %E%s%N\r\n",
4863 L1LatencyStrTable[PciExpressCap->LinkCapability.Bits.L1ExitLatency]
4864 );
4865 ShellPrintEx (
4866 -1,
4867 -1,
4868 L" Clock Power Management(18): %E%d%N\r\n",
4869 PciExpressCap->LinkCapability.Bits.ClockPowerManagement
4870 );
4871 ShellPrintEx (
4872 -1,
4873 -1,
4874 L" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",
4875 PciExpressCap->LinkCapability.Bits.SurpriseDownError
4876 );
4877 ShellPrintEx (
4878 -1,
4879 -1,
4880 L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",
4881 PciExpressCap->LinkCapability.Bits.DataLinkLayerLinkActive
4882 );
4883 ShellPrintEx (
4884 -1,
4885 -1,
4886 L" Link Bandwidth Notification Capability(21): %E%d%N\r\n",
4887 PciExpressCap->LinkCapability.Bits.LinkBandwidthNotification
4888 );
4889 ShellPrintEx (
4890 -1,
4891 -1,
4892 L" Port Number(31:24): %E0x%02x%N\r\n",
4893 PciExpressCap->LinkCapability.Bits.PortNumber
4894 );
4895 return EFI_SUCCESS;
4896 }
4897
4898 /**
4899 Print out information of the device link control information.
4900
4901 @param[in] PciExpressCap The pointer to the structure about the device.
4902
4903 @retval EFI_SUCCESS The operation was successful.
4904 **/
4905 EFI_STATUS
4906 ExplainPcieLinkControl (
4907 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
4908 )
4909 {
4910 UINT8 DevicePortType;
4911
4912 DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;
4913 ShellPrintEx (
4914 -1,
4915 -1,
4916 L" Active State Power Management Control(1:0): %E%s%N\r\n",
4917 ASPMCtrlStrTable[PciExpressCap->LinkControl.Bits.AspmControl]
4918 );
4919 //
4920 // RCB is not applicable to switches
4921 //
4922 if (!IS_PCIE_SWITCH (DevicePortType)) {
4923 ShellPrintEx (
4924 -1,
4925 -1,
4926 L" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",
4927 1 << (PciExpressCap->LinkControl.Bits.ReadCompletionBoundary + 6)
4928 );
4929 }
4930
4931 //
4932 // Link Disable is reserved on
4933 // a) Endpoints
4934 // b) PCI Express to PCI/PCI-X bridges
4935 // c) Upstream Ports of Switches
4936 //
4937 if (!IS_PCIE_ENDPOINT (DevicePortType) &&
4938 (DevicePortType != PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT) &&
4939 (DevicePortType != PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE))
4940 {
4941 ShellPrintEx (
4942 -1,
4943 -1,
4944 L" Link Disable(4): %E%d%N\r\n",
4945 PciExpressCap->LinkControl.Bits.LinkDisable
4946 );
4947 }
4948
4949 ShellPrintEx (
4950 -1,
4951 -1,
4952 L" Common Clock Configuration(6): %E%d%N\r\n",
4953 PciExpressCap->LinkControl.Bits.CommonClockConfiguration
4954 );
4955 ShellPrintEx (
4956 -1,
4957 -1,
4958 L" Extended Synch(7): %E%d%N\r\n",
4959 PciExpressCap->LinkControl.Bits.ExtendedSynch
4960 );
4961 ShellPrintEx (
4962 -1,
4963 -1,
4964 L" Enable Clock Power Management(8): %E%d%N\r\n",
4965 PciExpressCap->LinkControl.Bits.ClockPowerManagement
4966 );
4967 ShellPrintEx (
4968 -1,
4969 -1,
4970 L" Hardware Autonomous Width Disable(9): %E%d%N\r\n",
4971 PciExpressCap->LinkControl.Bits.HardwareAutonomousWidthDisable
4972 );
4973 ShellPrintEx (
4974 -1,
4975 -1,
4976 L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",
4977 PciExpressCap->LinkControl.Bits.LinkBandwidthManagementInterrupt
4978 );
4979 ShellPrintEx (
4980 -1,
4981 -1,
4982 L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",
4983 PciExpressCap->LinkControl.Bits.LinkAutonomousBandwidthInterrupt
4984 );
4985 return EFI_SUCCESS;
4986 }
4987
4988 /**
4989 Print out information of the device link status information.
4990
4991 @param[in] PciExpressCap The pointer to the structure about the device.
4992
4993 @retval EFI_SUCCESS The operation was successful.
4994 **/
4995 EFI_STATUS
4996 ExplainPcieLinkStatus (
4997 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
4998 )
4999 {
5000 CHAR16 *CurLinkSpeed;
5001
5002 switch (PciExpressCap->LinkStatus.Bits.CurrentLinkSpeed) {
5003 case 1:
5004 CurLinkSpeed = L"2.5 GT/s";
5005 break;
5006 case 2:
5007 CurLinkSpeed = L"5.0 GT/s";
5008 break;
5009 case 3:
5010 CurLinkSpeed = L"8.0 GT/s";
5011 break;
5012 case 4:
5013 CurLinkSpeed = L"16.0 GT/s";
5014 break;
5015 case 5:
5016 CurLinkSpeed = L"32.0 GT/s";
5017 break;
5018 default:
5019 CurLinkSpeed = L"Reserved";
5020 break;
5021 }
5022
5023 ShellPrintEx (
5024 -1,
5025 -1,
5026 L" Current Link Speed(3:0): %E%s%N\r\n",
5027 CurLinkSpeed
5028 );
5029 ShellPrintEx (
5030 -1,
5031 -1,
5032 L" Negotiated Link Width(9:4): %Ex%d%N\r\n",
5033 PciExpressCap->LinkStatus.Bits.NegotiatedLinkWidth
5034 );
5035 ShellPrintEx (
5036 -1,
5037 -1,
5038 L" Link Training(11): %E%d%N\r\n",
5039 PciExpressCap->LinkStatus.Bits.LinkTraining
5040 );
5041 ShellPrintEx (
5042 -1,
5043 -1,
5044 L" Slot Clock Configuration(12): %E%d%N\r\n",
5045 PciExpressCap->LinkStatus.Bits.SlotClockConfiguration
5046 );
5047 ShellPrintEx (
5048 -1,
5049 -1,
5050 L" Data Link Layer Link Active(13): %E%d%N\r\n",
5051 PciExpressCap->LinkStatus.Bits.DataLinkLayerLinkActive
5052 );
5053 ShellPrintEx (
5054 -1,
5055 -1,
5056 L" Link Bandwidth Management Status(14): %E%d%N\r\n",
5057 PciExpressCap->LinkStatus.Bits.LinkBandwidthManagement
5058 );
5059 ShellPrintEx (
5060 -1,
5061 -1,
5062 L" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",
5063 PciExpressCap->LinkStatus.Bits.LinkAutonomousBandwidth
5064 );
5065 return EFI_SUCCESS;
5066 }
5067
5068 /**
5069 Print out information of the device slot information.
5070
5071 @param[in] PciExpressCap The pointer to the structure about the device.
5072
5073 @retval EFI_SUCCESS The operation was successful.
5074 **/
5075 EFI_STATUS
5076 ExplainPcieSlotCap (
5077 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
5078 )
5079 {
5080 ShellPrintEx (
5081 -1,
5082 -1,
5083 L" Attention Button Present(0): %E%d%N\r\n",
5084 PciExpressCap->SlotCapability.Bits.AttentionButton
5085 );
5086 ShellPrintEx (
5087 -1,
5088 -1,
5089 L" Power Controller Present(1): %E%d%N\r\n",
5090 PciExpressCap->SlotCapability.Bits.PowerController
5091 );
5092 ShellPrintEx (
5093 -1,
5094 -1,
5095 L" MRL Sensor Present(2): %E%d%N\r\n",
5096 PciExpressCap->SlotCapability.Bits.MrlSensor
5097 );
5098 ShellPrintEx (
5099 -1,
5100 -1,
5101 L" Attention Indicator Present(3): %E%d%N\r\n",
5102 PciExpressCap->SlotCapability.Bits.AttentionIndicator
5103 );
5104 ShellPrintEx (
5105 -1,
5106 -1,
5107 L" Power Indicator Present(4): %E%d%N\r\n",
5108 PciExpressCap->SlotCapability.Bits.PowerIndicator
5109 );
5110 ShellPrintEx (
5111 -1,
5112 -1,
5113 L" Hot-Plug Surprise(5): %E%d%N\r\n",
5114 PciExpressCap->SlotCapability.Bits.HotPlugSurprise
5115 );
5116 ShellPrintEx (
5117 -1,
5118 -1,
5119 L" Hot-Plug Capable(6): %E%d%N\r\n",
5120 PciExpressCap->SlotCapability.Bits.HotPlugCapable
5121 );
5122 ShellPrintEx (
5123 -1,
5124 -1,
5125 L" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",
5126 PciExpressCap->SlotCapability.Bits.SlotPowerLimitValue
5127 );
5128 ShellPrintEx (
5129 -1,
5130 -1,
5131 L" Slot Power Limit Scale(16:15): %E%s%N\r\n",
5132 SlotPwrLmtScaleTable[PciExpressCap->SlotCapability.Bits.SlotPowerLimitScale]
5133 );
5134 ShellPrintEx (
5135 -1,
5136 -1,
5137 L" Electromechanical Interlock Present(17): %E%d%N\r\n",
5138 PciExpressCap->SlotCapability.Bits.ElectromechanicalInterlock
5139 );
5140 ShellPrintEx (
5141 -1,
5142 -1,
5143 L" No Command Completed Support(18): %E%d%N\r\n",
5144 PciExpressCap->SlotCapability.Bits.NoCommandCompleted
5145 );
5146 ShellPrintEx (
5147 -1,
5148 -1,
5149 L" Physical Slot Number(31:19): %E%d%N\r\n",
5150 PciExpressCap->SlotCapability.Bits.PhysicalSlotNumber
5151 );
5152
5153 return EFI_SUCCESS;
5154 }
5155
5156 /**
5157 Print out information of the device slot control information.
5158
5159 @param[in] PciExpressCap The pointer to the structure about the device.
5160
5161 @retval EFI_SUCCESS The operation was successful.
5162 **/
5163 EFI_STATUS
5164 ExplainPcieSlotControl (
5165 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
5166 )
5167 {
5168 ShellPrintEx (
5169 -1,
5170 -1,
5171 L" Attention Button Pressed Enable(0): %E%d%N\r\n",
5172 PciExpressCap->SlotControl.Bits.AttentionButtonPressed
5173 );
5174 ShellPrintEx (
5175 -1,
5176 -1,
5177 L" Power Fault Detected Enable(1): %E%d%N\r\n",
5178 PciExpressCap->SlotControl.Bits.PowerFaultDetected
5179 );
5180 ShellPrintEx (
5181 -1,
5182 -1,
5183 L" MRL Sensor Changed Enable(2): %E%d%N\r\n",
5184 PciExpressCap->SlotControl.Bits.MrlSensorChanged
5185 );
5186 ShellPrintEx (
5187 -1,
5188 -1,
5189 L" Presence Detect Changed Enable(3): %E%d%N\r\n",
5190 PciExpressCap->SlotControl.Bits.PresenceDetectChanged
5191 );
5192 ShellPrintEx (
5193 -1,
5194 -1,
5195 L" Command Completed Interrupt Enable(4): %E%d%N\r\n",
5196 PciExpressCap->SlotControl.Bits.CommandCompletedInterrupt
5197 );
5198 ShellPrintEx (
5199 -1,
5200 -1,
5201 L" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",
5202 PciExpressCap->SlotControl.Bits.HotPlugInterrupt
5203 );
5204 ShellPrintEx (
5205 -1,
5206 -1,
5207 L" Attention Indicator Control(7:6): %E%s%N\r\n",
5208 IndicatorTable[
5209 PciExpressCap->SlotControl.Bits.AttentionIndicator]
5210 );
5211 ShellPrintEx (
5212 -1,
5213 -1,
5214 L" Power Indicator Control(9:8): %E%s%N\r\n",
5215 IndicatorTable[PciExpressCap->SlotControl.Bits.PowerIndicator]
5216 );
5217 ShellPrintEx (-1, -1, L" Power Controller Control(10): %EPower ");
5218 if (
5219 PciExpressCap->SlotControl.Bits.PowerController)
5220 {
5221 ShellPrintEx (-1, -1, L"Off%N\r\n");
5222 } else {
5223 ShellPrintEx (-1, -1, L"On%N\r\n");
5224 }
5225
5226 ShellPrintEx (
5227 -1,
5228 -1,
5229 L" Electromechanical Interlock Control(11): %E%d%N\r\n",
5230 PciExpressCap->SlotControl.Bits.ElectromechanicalInterlock
5231 );
5232 ShellPrintEx (
5233 -1,
5234 -1,
5235 L" Data Link Layer State Changed Enable(12): %E%d%N\r\n",
5236 PciExpressCap->SlotControl.Bits.DataLinkLayerStateChanged
5237 );
5238 return EFI_SUCCESS;
5239 }
5240
5241 /**
5242 Print out information of the device slot status information.
5243
5244 @param[in] PciExpressCap The pointer to the structure about the device.
5245
5246 @retval EFI_SUCCESS The operation was successful.
5247 **/
5248 EFI_STATUS
5249 ExplainPcieSlotStatus (
5250 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
5251 )
5252 {
5253 ShellPrintEx (
5254 -1,
5255 -1,
5256 L" Attention Button Pressed(0): %E%d%N\r\n",
5257 PciExpressCap->SlotStatus.Bits.AttentionButtonPressed
5258 );
5259 ShellPrintEx (
5260 -1,
5261 -1,
5262 L" Power Fault Detected(1): %E%d%N\r\n",
5263 PciExpressCap->SlotStatus.Bits.PowerFaultDetected
5264 );
5265 ShellPrintEx (
5266 -1,
5267 -1,
5268 L" MRL Sensor Changed(2): %E%d%N\r\n",
5269 PciExpressCap->SlotStatus.Bits.MrlSensorChanged
5270 );
5271 ShellPrintEx (
5272 -1,
5273 -1,
5274 L" Presence Detect Changed(3): %E%d%N\r\n",
5275 PciExpressCap->SlotStatus.Bits.PresenceDetectChanged
5276 );
5277 ShellPrintEx (
5278 -1,
5279 -1,
5280 L" Command Completed(4): %E%d%N\r\n",
5281 PciExpressCap->SlotStatus.Bits.CommandCompleted
5282 );
5283 ShellPrintEx (-1, -1, L" MRL Sensor State(5): %EMRL ");
5284 if (
5285 PciExpressCap->SlotStatus.Bits.MrlSensor)
5286 {
5287 ShellPrintEx (-1, -1, L" Opened%N\r\n");
5288 } else {
5289 ShellPrintEx (-1, -1, L" Closed%N\r\n");
5290 }
5291
5292 ShellPrintEx (-1, -1, L" Presence Detect State(6): ");
5293 if (
5294 PciExpressCap->SlotStatus.Bits.PresenceDetect)
5295 {
5296 ShellPrintEx (-1, -1, L"%ECard Present in slot%N\r\n");
5297 } else {
5298 ShellPrintEx (-1, -1, L"%ESlot Empty%N\r\n");
5299 }
5300
5301 ShellPrintEx (-1, -1, L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");
5302 if (
5303 PciExpressCap->SlotStatus.Bits.ElectromechanicalInterlock)
5304 {
5305 ShellPrintEx (-1, -1, L"Engaged%N\r\n");
5306 } else {
5307 ShellPrintEx (-1, -1, L"Disengaged%N\r\n");
5308 }
5309
5310 ShellPrintEx (
5311 -1,
5312 -1,
5313 L" Data Link Layer State Changed(8): %E%d%N\r\n",
5314 PciExpressCap->SlotStatus.Bits.DataLinkLayerStateChanged
5315 );
5316 return EFI_SUCCESS;
5317 }
5318
5319 /**
5320 Print out information of the device root information.
5321
5322 @param[in] PciExpressCap The pointer to the structure about the device.
5323
5324 @retval EFI_SUCCESS The operation was successful.
5325 **/
5326 EFI_STATUS
5327 ExplainPcieRootControl (
5328 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
5329 )
5330 {
5331 ShellPrintEx (
5332 -1,
5333 -1,
5334 L" System Error on Correctable Error Enable(0): %E%d%N\r\n",
5335 PciExpressCap->RootControl.Bits.SystemErrorOnCorrectableError
5336 );
5337 ShellPrintEx (
5338 -1,
5339 -1,
5340 L" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",
5341 PciExpressCap->RootControl.Bits.SystemErrorOnNonFatalError
5342 );
5343 ShellPrintEx (
5344 -1,
5345 -1,
5346 L" System Error on Fatal Error Enable(2): %E%d%N\r\n",
5347 PciExpressCap->RootControl.Bits.SystemErrorOnFatalError
5348 );
5349 ShellPrintEx (
5350 -1,
5351 -1,
5352 L" PME Interrupt Enable(3): %E%d%N\r\n",
5353 PciExpressCap->RootControl.Bits.PmeInterrupt
5354 );
5355 ShellPrintEx (
5356 -1,
5357 -1,
5358 L" CRS Software Visibility Enable(4): %E%d%N\r\n",
5359 PciExpressCap->RootControl.Bits.CrsSoftwareVisibility
5360 );
5361
5362 return EFI_SUCCESS;
5363 }
5364
5365 /**
5366 Print out information of the device root capability information.
5367
5368 @param[in] PciExpressCap The pointer to the structure about the device.
5369
5370 @retval EFI_SUCCESS The operation was successful.
5371 **/
5372 EFI_STATUS
5373 ExplainPcieRootCap (
5374 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
5375 )
5376 {
5377 ShellPrintEx (
5378 -1,
5379 -1,
5380 L" CRS Software Visibility(0): %E%d%N\r\n",
5381 PciExpressCap->RootCapability.Bits.CrsSoftwareVisibility
5382 );
5383
5384 return EFI_SUCCESS;
5385 }
5386
5387 /**
5388 Print out information of the device root status information.
5389
5390 @param[in] PciExpressCap The pointer to the structure about the device.
5391
5392 @retval EFI_SUCCESS The operation was successful.
5393 **/
5394 EFI_STATUS
5395 ExplainPcieRootStatus (
5396 IN PCI_CAPABILITY_PCIEXP *PciExpressCap
5397 )
5398 {
5399 ShellPrintEx (
5400 -1,
5401 -1,
5402 L" PME Requester ID(15:0): %E0x%04x%N\r\n",
5403 PciExpressCap->RootStatus.Bits.PmeRequesterId
5404 );
5405 ShellPrintEx (
5406 -1,
5407 -1,
5408 L" PME Status(16): %E%d%N\r\n",
5409 PciExpressCap->RootStatus.Bits.PmeStatus
5410 );
5411 ShellPrintEx (
5412 -1,
5413 -1,
5414 L" PME Pending(17): %E%d%N\r\n",
5415 PciExpressCap->RootStatus.Bits.PmePending
5416 );
5417 return EFI_SUCCESS;
5418 }
5419
5420 /**
5421 Function to interpret and print out the link control structure
5422
5423 @param[in] HeaderAddress The Address of this capability header.
5424 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5425 **/
5426 EFI_STATUS
5427 PrintInterpretedExtendedCompatibilityLinkControl (
5428 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
5429 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
5430 )
5431 {
5432 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL *Header;
5433
5434 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL *)HeaderAddress;
5435
5436 ShellPrintHiiEx (
5437 -1,
5438 -1,
5439 NULL,
5440 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL),
5441 gShellDebug1HiiHandle,
5442 Header->RootComplexLinkCapabilities,
5443 Header->RootComplexLinkControl,
5444 Header->RootComplexLinkStatus
5445 );
5446 DumpHex (
5447 4,
5448 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),
5449 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL),
5450 (VOID *)(HeaderAddress)
5451 );
5452 return (EFI_SUCCESS);
5453 }
5454
5455 /**
5456 Function to interpret and print out the power budgeting structure
5457
5458 @param[in] HeaderAddress The Address of this capability header.
5459 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5460 **/
5461 EFI_STATUS
5462 PrintInterpretedExtendedCompatibilityPowerBudgeting (
5463 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
5464 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
5465 )
5466 {
5467 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING *Header;
5468
5469 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING *)HeaderAddress;
5470
5471 ShellPrintHiiEx (
5472 -1,
5473 -1,
5474 NULL,
5475 STRING_TOKEN (STR_PCI_EXT_CAP_POWER),
5476 gShellDebug1HiiHandle,
5477 Header->DataSelect,
5478 Header->Data,
5479 Header->PowerBudgetCapability
5480 );
5481 DumpHex (
5482 4,
5483 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),
5484 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING),
5485 (VOID *)(HeaderAddress)
5486 );
5487 return (EFI_SUCCESS);
5488 }
5489
5490 /**
5491 Function to interpret and print out the ACS structure
5492
5493 @param[in] HeaderAddress The Address of this capability header.
5494 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5495 **/
5496 EFI_STATUS
5497 PrintInterpretedExtendedCompatibilityAcs (
5498 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
5499 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
5500 )
5501 {
5502 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED *Header;
5503 UINT16 VectorSize;
5504 UINT16 LoopCounter;
5505
5506 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED *)HeaderAddress;
5507 VectorSize = 0;
5508
5509 ShellPrintHiiEx (
5510 -1,
5511 -1,
5512 NULL,
5513 STRING_TOKEN (STR_PCI_EXT_CAP_ACS),
5514 gShellDebug1HiiHandle,
5515 Header->AcsCapability,
5516 Header->AcsControl
5517 );
5518 if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL (Header)) {
5519 VectorSize = PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE (Header);
5520 if (VectorSize == 0) {
5521 VectorSize = 256;
5522 }
5523
5524 for (LoopCounter = 0; LoopCounter * 8 < VectorSize; LoopCounter++) {
5525 ShellPrintHiiEx (
5526 -1,
5527 -1,
5528 NULL,
5529 STRING_TOKEN (STR_PCI_EXT_CAP_ACS2),
5530 gShellDebug1HiiHandle,
5531 LoopCounter + 1,
5532 Header->EgressControlVectorArray[LoopCounter]
5533 );
5534 }
5535 }
5536
5537 DumpHex (
5538 4,
5539 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),
5540 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED) + (VectorSize / 8) - 1,
5541 (VOID *)(HeaderAddress)
5542 );
5543 return (EFI_SUCCESS);
5544 }
5545
5546 /**
5547 Function to interpret and print out the latency tolerance reporting structure
5548
5549 @param[in] HeaderAddress The Address of this capability header.
5550 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5551 **/
5552 EFI_STATUS
5553 PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (
5554 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
5555 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
5556 )
5557 {
5558 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING *Header;
5559
5560 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING *)HeaderAddress;
5561
5562 ShellPrintHiiEx (
5563 -1,
5564 -1,
5565 NULL,
5566 STRING_TOKEN (STR_PCI_EXT_CAP_LAT),
5567 gShellDebug1HiiHandle,
5568 Header->MaxSnoopLatency,
5569 Header->MaxNoSnoopLatency
5570 );
5571 DumpHex (
5572 4,
5573 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),
5574 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING),
5575 (VOID *)(HeaderAddress)
5576 );
5577 return (EFI_SUCCESS);
5578 }
5579
5580 /**
5581 Function to interpret and print out the serial number structure
5582
5583 @param[in] HeaderAddress The Address of this capability header.
5584 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5585 **/
5586 EFI_STATUS
5587 PrintInterpretedExtendedCompatibilitySerialNumber (
5588 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
5589 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
5590 )
5591 {
5592 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER *Header;
5593
5594 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER *)HeaderAddress;
5595
5596 ShellPrintHiiEx (
5597 -1,
5598 -1,
5599 NULL,
5600 STRING_TOKEN (STR_PCI_EXT_CAP_SN),
5601 gShellDebug1HiiHandle,
5602 Header->SerialNumber
5603 );
5604 DumpHex (
5605 4,
5606 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),
5607 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER),
5608 (VOID *)(HeaderAddress)
5609 );
5610 return (EFI_SUCCESS);
5611 }
5612
5613 /**
5614 Function to interpret and print out the RCRB structure
5615
5616 @param[in] HeaderAddress The Address of this capability header.
5617 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5618 **/
5619 EFI_STATUS
5620 PrintInterpretedExtendedCompatibilityRcrb (
5621 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
5622 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
5623 )
5624 {
5625 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER *Header;
5626
5627 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER *)HeaderAddress;
5628
5629 ShellPrintHiiEx (
5630 -1,
5631 -1,
5632 NULL,
5633 STRING_TOKEN (STR_PCI_EXT_CAP_RCRB),
5634 gShellDebug1HiiHandle,
5635 Header->VendorId,
5636 Header->DeviceId,
5637 Header->RcrbCapabilities,
5638 Header->RcrbControl
5639 );
5640 DumpHex (
5641 4,
5642 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),
5643 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER),
5644 (VOID *)(HeaderAddress)
5645 );
5646 return (EFI_SUCCESS);
5647 }
5648
5649 /**
5650 Function to interpret and print out the vendor specific structure
5651
5652 @param[in] HeaderAddress The Address of this capability header.
5653 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5654 **/
5655 EFI_STATUS
5656 PrintInterpretedExtendedCompatibilityVendorSpecific (
5657 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
5658 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
5659 )
5660 {
5661 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC *Header;
5662
5663 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC *)HeaderAddress;
5664
5665 ShellPrintHiiEx (
5666 -1,
5667 -1,
5668 NULL,
5669 STRING_TOKEN (STR_PCI_EXT_CAP_VEN),
5670 gShellDebug1HiiHandle,
5671 Header->VendorSpecificHeader
5672 );
5673 DumpHex (
5674 4,
5675 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),
5676 PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE (Header),
5677 (VOID *)(HeaderAddress)
5678 );
5679 return (EFI_SUCCESS);
5680 }
5681
5682 /**
5683 Function to interpret and print out the Event Collector Endpoint Association structure
5684
5685 @param[in] HeaderAddress The Address of this capability header.
5686 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5687 **/
5688 EFI_STATUS
5689 PrintInterpretedExtendedCompatibilityECEA (
5690 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
5691 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
5692 )
5693 {
5694 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION *Header;
5695
5696 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION *)HeaderAddress;
5697
5698 ShellPrintHiiEx (
5699 -1,
5700 -1,
5701 NULL,
5702 STRING_TOKEN (STR_PCI_EXT_CAP_ECEA),
5703 gShellDebug1HiiHandle,
5704 Header->AssociationBitmap
5705 );
5706 DumpHex (
5707 4,
5708 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),
5709 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION),
5710 (VOID *)(HeaderAddress)
5711 );
5712 return (EFI_SUCCESS);
5713 }
5714
5715 /**
5716 Function to interpret and print out the ARI structure
5717
5718 @param[in] HeaderAddress The Address of this capability header.
5719 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5720 **/
5721 EFI_STATUS
5722 PrintInterpretedExtendedCompatibilityAri (
5723 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
5724 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
5725 )
5726 {
5727 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY *Header;
5728
5729 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY *)HeaderAddress;
5730
5731 ShellPrintHiiEx (
5732 -1,
5733 -1,
5734 NULL,
5735 STRING_TOKEN (STR_PCI_EXT_CAP_ARI),
5736 gShellDebug1HiiHandle,
5737 Header->AriCapability,
5738 Header->AriControl
5739 );
5740 DumpHex (
5741 4,
5742 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),
5743 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY),
5744 (VOID *)(HeaderAddress)
5745 );
5746 return (EFI_SUCCESS);
5747 }
5748
5749 /**
5750 Function to interpret and print out the DPA structure
5751
5752 @param[in] HeaderAddress The Address of this capability header.
5753 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5754 **/
5755 EFI_STATUS
5756 PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (
5757 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
5758 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
5759 )
5760 {
5761 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION *Header;
5762 UINT8 LinkCount;
5763
5764 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION *)HeaderAddress;
5765
5766 ShellPrintHiiEx (
5767 -1,
5768 -1,
5769 NULL,
5770 STRING_TOKEN (STR_PCI_EXT_CAP_DPA),
5771 gShellDebug1HiiHandle,
5772 Header->DpaCapability,
5773 Header->DpaLatencyIndicator,
5774 Header->DpaStatus,
5775 Header->DpaControl
5776 );
5777 for (LinkCount = 0; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX (Header) + 1; LinkCount++) {
5778 ShellPrintHiiEx (
5779 -1,
5780 -1,
5781 NULL,
5782 STRING_TOKEN (STR_PCI_EXT_CAP_DPA2),
5783 gShellDebug1HiiHandle,
5784 LinkCount+1,
5785 Header->DpaPowerAllocationArray[LinkCount]
5786 );
5787 }
5788
5789 DumpHex (
5790 4,
5791 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),
5792 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX (Header),
5793 (VOID *)(HeaderAddress)
5794 );
5795 return (EFI_SUCCESS);
5796 }
5797
5798 /**
5799 Function to interpret and print out the link declaration structure
5800
5801 @param[in] HeaderAddress The Address of this capability header.
5802 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5803 **/
5804 EFI_STATUS
5805 PrintInterpretedExtendedCompatibilityLinkDeclaration (
5806 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
5807 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
5808 )
5809 {
5810 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION *Header;
5811 UINT8 LinkCount;
5812
5813 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION *)HeaderAddress;
5814
5815 ShellPrintHiiEx (
5816 -1,
5817 -1,
5818 NULL,
5819 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR),
5820 gShellDebug1HiiHandle,
5821 Header->ElementSelfDescription
5822 );
5823
5824 for (LinkCount = 0; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT (Header); LinkCount++) {
5825 ShellPrintHiiEx (
5826 -1,
5827 -1,
5828 NULL,
5829 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2),
5830 gShellDebug1HiiHandle,
5831 LinkCount+1,
5832 Header->LinkEntry[LinkCount]
5833 );
5834 }
5835
5836 DumpHex (
5837 4,
5838 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),
5839 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT (Header)-1)*sizeof (UINT32),
5840 (VOID *)(HeaderAddress)
5841 );
5842 return (EFI_SUCCESS);
5843 }
5844
5845 /**
5846 Function to interpret and print out the Advanced Error Reporting structure
5847
5848 @param[in] HeaderAddress The Address of this capability header.
5849 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5850 **/
5851 EFI_STATUS
5852 PrintInterpretedExtendedCompatibilityAer (
5853 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
5854 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
5855 )
5856 {
5857 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING *Header;
5858
5859 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING *)HeaderAddress;
5860
5861 ShellPrintHiiEx (
5862 -1,
5863 -1,
5864 NULL,
5865 STRING_TOKEN (STR_PCI_EXT_CAP_AER),
5866 gShellDebug1HiiHandle,
5867 Header->UncorrectableErrorStatus,
5868 Header->UncorrectableErrorMask,
5869 Header->UncorrectableErrorSeverity,
5870 Header->CorrectableErrorStatus,
5871 Header->CorrectableErrorMask,
5872 Header->AdvancedErrorCapabilitiesAndControl,
5873 Header->HeaderLog[0],
5874 Header->HeaderLog[1],
5875 Header->HeaderLog[2],
5876 Header->HeaderLog[3],
5877 Header->RootErrorCommand,
5878 Header->RootErrorStatus,
5879 Header->ErrorSourceIdentification,
5880 Header->CorrectableErrorSourceIdentification,
5881 Header->TlpPrefixLog[0],
5882 Header->TlpPrefixLog[1],
5883 Header->TlpPrefixLog[2],
5884 Header->TlpPrefixLog[3]
5885 );
5886 DumpHex (
5887 4,
5888 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),
5889 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING),
5890 (VOID *)(HeaderAddress)
5891 );
5892 return (EFI_SUCCESS);
5893 }
5894
5895 /**
5896 Function to interpret and print out the multicast structure
5897
5898 @param[in] HeaderAddress The Address of this capability header.
5899 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5900 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5901 **/
5902 EFI_STATUS
5903 PrintInterpretedExtendedCompatibilityMulticast (
5904 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
5905 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,
5906 IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCapPtr
5907 )
5908 {
5909 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *Header;
5910
5911 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *)HeaderAddress;
5912
5913 ShellPrintHiiEx (
5914 -1,
5915 -1,
5916 NULL,
5917 STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST),
5918 gShellDebug1HiiHandle,
5919 Header->MultiCastCapability,
5920 Header->MulticastControl,
5921 Header->McBaseAddress,
5922 Header->McReceiveAddress,
5923 Header->McBlockAll,
5924 Header->McBlockUntranslated,
5925 Header->McOverlayBar
5926 );
5927
5928 DumpHex (
5929 4,
5930 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),
5931 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST),
5932 (VOID *)(HeaderAddress)
5933 );
5934
5935 return (EFI_SUCCESS);
5936 }
5937
5938 /**
5939 Function to interpret and print out the virtual channel and multi virtual channel structure
5940
5941 @param[in] HeaderAddress The Address of this capability header.
5942 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5943 **/
5944 EFI_STATUS
5945 PrintInterpretedExtendedCompatibilityVirtualChannel (
5946 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
5947 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
5948 )
5949 {
5950 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY *Header;
5951 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC *CapabilityItem;
5952 UINT32 ItemCount;
5953
5954 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY *)HeaderAddress;
5955
5956 ShellPrintHiiEx (
5957 -1,
5958 -1,
5959 NULL,
5960 STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE),
5961 gShellDebug1HiiHandle,
5962 Header->ExtendedVcCount,
5963 Header->PortVcCapability1,
5964 Header->PortVcCapability2,
5965 Header->VcArbTableOffset,
5966 Header->PortVcControl,
5967 Header->PortVcStatus
5968 );
5969 for (ItemCount = 0; ItemCount < Header->ExtendedVcCount; ItemCount++) {
5970 CapabilityItem = &Header->Capability[ItemCount];
5971 ShellPrintHiiEx (
5972 -1,
5973 -1,
5974 NULL,
5975 STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM),
5976 gShellDebug1HiiHandle,
5977 ItemCount+1,
5978 CapabilityItem->VcResourceCapability,
5979 CapabilityItem->PortArbTableOffset,
5980 CapabilityItem->VcResourceControl,
5981 CapabilityItem->VcResourceStatus
5982 );
5983 }
5984
5985 DumpHex (
5986 4,
5987 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),
5988 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY)
5989 + Header->ExtendedVcCount * sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC),
5990 (VOID *)(HeaderAddress)
5991 );
5992
5993 return (EFI_SUCCESS);
5994 }
5995
5996 /**
5997 Function to interpret and print out the resizeable bar structure
5998
5999 @param[in] HeaderAddress The Address of this capability header.
6000 @param[in] HeadersBaseAddress The address of all the extended capability headers.
6001 **/
6002 EFI_STATUS
6003 PrintInterpretedExtendedCompatibilityResizeableBar (
6004 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
6005 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
6006 )
6007 {
6008 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR *Header;
6009 UINT32 ItemCount;
6010
6011 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR *)HeaderAddress;
6012
6013 for (ItemCount = 0; ItemCount < (UINT32)GET_NUMBER_RESIZABLE_BARS (Header); ItemCount++) {
6014 ShellPrintHiiEx (
6015 -1,
6016 -1,
6017 NULL,
6018 STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR),
6019 gShellDebug1HiiHandle,
6020 ItemCount+1,
6021 Header->Capability[ItemCount].ResizableBarCapability.Uint32,
6022 Header->Capability[ItemCount].ResizableBarControl.Uint32
6023 );
6024 }
6025
6026 DumpHex (
6027 4,
6028 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),
6029 (UINT32)GET_NUMBER_RESIZABLE_BARS (Header) * sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY),
6030 (VOID *)(HeaderAddress)
6031 );
6032
6033 return (EFI_SUCCESS);
6034 }
6035
6036 /**
6037 Function to interpret and print out the TPH structure
6038
6039 @param[in] HeaderAddress The Address of this capability header.
6040 @param[in] HeadersBaseAddress The address of all the extended capability headers.
6041 **/
6042 EFI_STATUS
6043 PrintInterpretedExtendedCompatibilityTph (
6044 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
6045 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
6046 )
6047 {
6048 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *Header;
6049
6050 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *)HeaderAddress;
6051
6052 ShellPrintHiiEx (
6053 -1,
6054 -1,
6055 NULL,
6056 STRING_TOKEN (STR_PCI_EXT_CAP_TPH),
6057 gShellDebug1HiiHandle,
6058 Header->TphRequesterCapability,
6059 Header->TphRequesterControl
6060 );
6061 DumpHex (
6062 8,
6063 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)Header->TphStTable - (UINT8 *)HeadersBaseAddress),
6064 GET_TPH_TABLE_SIZE (Header),
6065 (VOID *)Header->TphStTable
6066 );
6067
6068 DumpHex (
6069 4,
6070 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),
6071 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) + GET_TPH_TABLE_SIZE (Header) - sizeof (UINT16),
6072 (VOID *)(HeaderAddress)
6073 );
6074
6075 return (EFI_SUCCESS);
6076 }
6077
6078 /**
6079 Function to interpret and print out the secondary PCIe capability structure
6080
6081 @param[in] HeaderAddress The Address of this capability header.
6082 @param[in] HeadersBaseAddress The address of all the extended capability headers.
6083 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
6084 **/
6085 EFI_STATUS
6086 PrintInterpretedExtendedCompatibilitySecondary (
6087 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
6088 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,
6089 IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCap
6090 )
6091 {
6092 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *Header;
6093
6094 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *)HeaderAddress;
6095
6096 ShellPrintHiiEx (
6097 -1,
6098 -1,
6099 NULL,
6100 STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY),
6101 gShellDebug1HiiHandle,
6102 Header->LinkControl3.Uint32,
6103 Header->LaneErrorStatus
6104 );
6105 DumpHex (
6106 8,
6107 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)Header->EqualizationControl - (UINT8 *)HeadersBaseAddress),
6108 PciExpressCap->LinkCapability.Bits.MaxLinkWidth * sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL),
6109 (VOID *)Header->EqualizationControl
6110 );
6111
6112 DumpHex (
6113 4,
6114 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),
6115 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE) - sizeof (Header->EqualizationControl)
6116 + PciExpressCap->LinkCapability.Bits.MaxLinkWidth * sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL),
6117 (VOID *)(HeaderAddress)
6118 );
6119
6120 return (EFI_SUCCESS);
6121 }
6122
6123 /**
6124 Display Pcie extended capability details
6125
6126 @param[in] HeadersBaseAddress The address of all the extended capability headers.
6127 @param[in] HeaderAddress The address of this capability header.
6128 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
6129 **/
6130 EFI_STATUS
6131 PrintPciExtendedCapabilityDetails (
6132 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,
6133 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
6134 IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCapPtr
6135 )
6136 {
6137 switch (HeaderAddress->CapabilityId) {
6138 case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID:
6139 return PrintInterpretedExtendedCompatibilityAer (HeaderAddress, HeadersBaseAddress);
6140 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID:
6141 return PrintInterpretedExtendedCompatibilityLinkControl (HeaderAddress, HeadersBaseAddress);
6142 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID:
6143 return PrintInterpretedExtendedCompatibilityLinkDeclaration (HeaderAddress, HeadersBaseAddress);
6144 case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID:
6145 return PrintInterpretedExtendedCompatibilitySerialNumber (HeaderAddress, HeadersBaseAddress);
6146 case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID:
6147 return PrintInterpretedExtendedCompatibilityPowerBudgeting (HeaderAddress, HeadersBaseAddress);
6148 case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID:
6149 return PrintInterpretedExtendedCompatibilityAcs (HeaderAddress, HeadersBaseAddress);
6150 case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID:
6151 return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (HeaderAddress, HeadersBaseAddress);
6152 case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID:
6153 return PrintInterpretedExtendedCompatibilityAri (HeaderAddress, HeadersBaseAddress);
6154 case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID:
6155 return PrintInterpretedExtendedCompatibilityRcrb (HeaderAddress, HeadersBaseAddress);
6156 case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID:
6157 return PrintInterpretedExtendedCompatibilityVendorSpecific (HeaderAddress, HeadersBaseAddress);
6158 case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID:
6159 return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (HeaderAddress, HeadersBaseAddress);
6160 case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID:
6161 return PrintInterpretedExtendedCompatibilityECEA (HeaderAddress, HeadersBaseAddress);
6162 case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:
6163 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:
6164 return PrintInterpretedExtendedCompatibilityVirtualChannel (HeaderAddress, HeadersBaseAddress);
6165 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID:
6166 //
6167 // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b
6168 //
6169 return PrintInterpretedExtendedCompatibilityMulticast (HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);
6170 case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID:
6171 return PrintInterpretedExtendedCompatibilityResizeableBar (HeaderAddress, HeadersBaseAddress);
6172 case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID:
6173 return PrintInterpretedExtendedCompatibilityTph (HeaderAddress, HeadersBaseAddress);
6174 case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID:
6175 return PrintInterpretedExtendedCompatibilitySecondary (HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);
6176 default:
6177 ShellPrintEx (
6178 -1,
6179 -1,
6180 L"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",
6181 HeaderAddress->CapabilityId
6182 );
6183 return EFI_SUCCESS;
6184 }
6185 }
6186
6187 /**
6188 Display Pcie device structure.
6189
6190 @param[in] PciExpressCap PCI Express capability buffer.
6191 @param[in] ExtendedConfigSpace PCI Express extended configuration space.
6192 @param[in] ExtendedConfigSize PCI Express extended configuration size.
6193 @param[in] ExtendedCapability PCI Express extended capability ID to explain.
6194 **/
6195 VOID
6196 PciExplainPciExpress (
6197 IN PCI_CAPABILITY_PCIEXP *PciExpressCap,
6198 IN UINT8 *ExtendedConfigSpace,
6199 IN UINTN ExtendedConfigSize,
6200 IN CONST UINT16 ExtendedCapability
6201 )
6202 {
6203 UINT8 DevicePortType;
6204 UINTN Index;
6205 UINT8 *RegAddr;
6206 UINTN RegValue;
6207 PCI_EXP_EXT_HDR *ExtHdr;
6208
6209 DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;
6210
6211 ShellPrintEx (-1, -1, L"\r\nPci Express device capability structure:\r\n");
6212
6213 for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {
6214 if (ShellGetExecutionBreakFlag ()) {
6215 return;
6216 }
6217
6218 RegAddr = (UINT8 *)PciExpressCap + PcieExplainList[Index].Offset;
6219 switch (PcieExplainList[Index].Width) {
6220 case FieldWidthUINT8:
6221 RegValue = *(UINT8 *)RegAddr;
6222 break;
6223 case FieldWidthUINT16:
6224 RegValue = *(UINT16 *)RegAddr;
6225 break;
6226 case FieldWidthUINT32:
6227 RegValue = *(UINT32 *)RegAddr;
6228 break;
6229 default:
6230 RegValue = 0;
6231 break;
6232 }
6233
6234 ShellPrintHiiEx (
6235 -1,
6236 -1,
6237 NULL,
6238 PcieExplainList[Index].Token,
6239 gShellDebug1HiiHandle,
6240 PcieExplainList[Index].Offset,
6241 RegValue
6242 );
6243 if (PcieExplainList[Index].Func == NULL) {
6244 continue;
6245 }
6246
6247 switch (PcieExplainList[Index].Type) {
6248 case PcieExplainTypeLink:
6249 //
6250 // Link registers should not be used by
6251 // a) Root Complex Integrated Endpoint
6252 // b) Root Complex Event Collector
6253 //
6254 if ((DevicePortType == PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT) ||
6255 (DevicePortType == PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR))
6256 {
6257 continue;
6258 }
6259
6260 break;
6261 case PcieExplainTypeSlot:
6262 //
6263 // Slot registers are only valid for
6264 // a) Root Port of PCI Express Root Complex
6265 // b) Downstream Port of PCI Express Switch
6266 // and when SlotImplemented bit is set in PCIE cap register.
6267 //
6268 if (((DevicePortType != PCIE_DEVICE_PORT_TYPE_ROOT_PORT) &&
6269 (DevicePortType != PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT)) ||
6270 !PciExpressCap->Capability.Bits.SlotImplemented)
6271 {
6272 continue;
6273 }
6274
6275 break;
6276 case PcieExplainTypeRoot:
6277 //
6278 // Root registers are only valid for
6279 // Root Port of PCI Express Root Complex
6280 //
6281 if (DevicePortType != PCIE_DEVICE_PORT_TYPE_ROOT_PORT) {
6282 continue;
6283 }
6284
6285 break;
6286 default:
6287 break;
6288 }
6289
6290 PcieExplainList[Index].Func (PciExpressCap);
6291 }
6292
6293 ExtHdr = (PCI_EXP_EXT_HDR *)ExtendedConfigSpace;
6294 while (ExtHdr->CapabilityId != 0 && ExtHdr->CapabilityVersion != 0 && ExtHdr->CapabilityId != 0xFFFF) {
6295 //
6296 // Process this item
6297 //
6298 if ((ExtendedCapability == 0xFFFF) || (ExtendedCapability == ExtHdr->CapabilityId)) {
6299 //
6300 // Print this item
6301 //
6302 PrintPciExtendedCapabilityDetails ((PCI_EXP_EXT_HDR *)ExtendedConfigSpace, ExtHdr, PciExpressCap);
6303 }
6304
6305 //
6306 // Advance to the next item if it exists
6307 //
6308 if ((ExtHdr->NextCapabilityOffset != 0) &&
6309 (ExtHdr->NextCapabilityOffset <= (UINT32)(ExtendedConfigSize + EFI_PCIE_CAPABILITY_BASE_OFFSET - sizeof (PCI_EXP_EXT_HDR))))
6310 {
6311 ExtHdr = (PCI_EXP_EXT_HDR *)(ExtendedConfigSpace + ExtHdr->NextCapabilityOffset - EFI_PCIE_CAPABILITY_BASE_OFFSET);
6312 } else {
6313 break;
6314 }
6315 }
6316 }
EFI Development Kit II mirror for PVE