2 IA32 register defintions needed by debug transfer protocol.
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15 #ifndef _ARCH_REGISTERS_H_
16 #define _ARCH_REGISTERS_H_
20 /// FP / MMX / XMM registers (see fxrstor instruction definition)
59 UINT8 Reserved11
[14 * 16];
60 } DEBUG_DATA_IA32_FX_SAVE_STATE
;
63 /// IA-32 processor context definition
66 DEBUG_DATA_IA32_FX_SAVE_STATE FxSaveState
;
86 UINT32 Cr1
; ///< Reserved
98 } DEBUG_DATA_IA32_SYSTEM_CONTEXT
;
101 /// IA32 GROUP register
126 } DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_IA32
;
129 /// IA32 Segment Limit GROUP register
140 } DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM_IA32
;
143 /// IA32 Segment Base GROUP register
154 } DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE_IA32
;