SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/ArchRegisters.h

   1 /** @file
   2   X64 register defintions needed by debug transfer protocol.
   3
   4   Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php.
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _ARCH_REGISTERS_H_
  16 #define _ARCH_REGISTERS_H_
  17
  18 ///
  19 /// FXSAVE_STATE (promoted operation)
  20 /// FP / MMX / XMM registers (see fxrstor instruction definition)
  21 ///
  22 typedef struct {
  23   UINT16  Fcw;
  24   UINT16  Fsw;
  25   UINT16  Ftw;
  26   UINT16  Opcode;
  27   UINT64  Rip;
  28   UINT64  DataOffset;
  29   UINT32  Mxcsr;
  30   UINT32  Mxcsr_Mask;
  31   UINT8   St0Mm0[10];
  32   UINT8   Reserved2[6];
  33   UINT8   St1Mm1[10];
  34   UINT8   Reserved3[6];
  35   UINT8   St2Mm2[10];
  36   UINT8   Reserved4[6];
  37   UINT8   St3Mm3[10];
  38   UINT8   Reserved5[6];
  39   UINT8   St4Mm4[10];
  40   UINT8   Reserved6[6];
  41   UINT8   St5Mm5[10];
  42   UINT8   Reserved7[6];
  43   UINT8   St6Mm6[10];
  44   UINT8   Reserved8[6];
  45   UINT8   St7Mm7[10];
  46   UINT8   Reserved9[6];
  47   UINT8   Xmm0[16];
  48   UINT8   Xmm1[16];
  49   UINT8   Xmm2[16];
  50   UINT8   Xmm3[16];
  51   UINT8   Xmm4[16];
  52   UINT8   Xmm5[16];
  53   UINT8   Xmm6[16];
  54   UINT8   Xmm7[16];
  55   UINT8   Xmm8[16];
  56   UINT8   Xmm9[16];
  57   UINT8   Xmm10[16];
  58   UINT8   Xmm11[16];
  59   UINT8   Xmm12[16];
  60   UINT8   Xmm13[16];
  61   UINT8   Xmm14[16];
  62   UINT8   Xmm15[16];
  63   UINT8   Reserved11[6 * 16];
  64 } DEBUG_DATA_X64_FX_SAVE_STATE;
  65
  66 ///
  67 ///  x64 processor context definition
  68 ///
  69 typedef struct {
  70   DEBUG_DATA_X64_FX_SAVE_STATE   FxSaveState;
  71   UINT64                         Dr0;
  72   UINT64                         Dr1;
  73   UINT64                         Dr2;
  74   UINT64                         Dr3;
  75   UINT64                         Dr6;
  76   UINT64                         Dr7;
  77   UINT64                         Eflags;
  78   UINT64                         Ldtr;
  79   UINT64                         Tr;
  80   UINT64                         Gdtr[2];
  81   UINT64                         Idtr[2];
  82   UINT64                         Eip;
  83   UINT64                         Gs;
  84   UINT64                         Fs;
  85   UINT64                         Es;
  86   UINT64                         Ds;
  87   UINT64                         Cs;
  88   UINT64                         Ss;
  89   UINT64                         Cr0;
  90   UINT64                         Cr1;  /* Reserved */
  91   UINT64                         Cr2;
  92   UINT64                         Cr3;
  93   UINT64                         Cr4;
  94   UINT64                         Rdi;
  95   UINT64                         Rsi;
  96   UINT64                         Rbp;
  97   UINT64                         Rsp;
  98   UINT64                         Rdx;
  99   UINT64                         Rcx;
 100   UINT64                         Rbx;
 101   UINT64                         Rax;
 102   UINT64                         Cr8;
 103   UINT64                         R8;
 104   UINT64                         R9;
 105   UINT64                         R10;
 106   UINT64                         R11;
 107   UINT64                         R12;
 108   UINT64                         R13;
 109   UINT64                         R14;
 110   UINT64                         R15;
 111 } DEBUG_DATA_X64_SYSTEM_CONTEXT;
 112
 113
 114 ///
 115 ///  x64 GROUP register
 116 ///
 117 typedef struct {
 118   UINT16         Cs;
 119   UINT16         Ds;
 120   UINT16         Es;
 121   UINT16         Fs;
 122   UINT16         Gs;
 123   UINT16         Ss;
 124   UINT32         Eflags;
 125   UINT64         Rbp;
 126   UINT64         Eip;
 127   UINT64         Rsp;
 128   UINT64         Eax;
 129   UINT64         Rbx;
 130   UINT64         Rcx;
 131   UINT64         Rdx;
 132   UINT64         Rsi;
 133   UINT64         Rdi;
 134   UINT64         R8;
 135   UINT64         R9;
 136   UINT64         R10;
 137   UINT64         R11;
 138   UINT64         R12;
 139   UINT64         R13;
 140   UINT64         R14;
 141   UINT64         R15;
 142   UINT64         Dr0;
 143   UINT64         Dr1;
 144   UINT64         Dr2;
 145   UINT64         Dr3;
 146   UINT64         Dr6;
 147   UINT64         Dr7;
 148   UINT64         Cr0;
 149   UINT64         Cr2;
 150   UINT64         Cr3;
 151   UINT64         Cr4;
 152   UINT64         Cr8;
 153   UINT8          Xmm0[16];
 154   UINT8          Xmm1[16];
 155   UINT8          Xmm2[16];
 156   UINT8          Xmm3[16];
 157   UINT8          Xmm4[16];
 158   UINT8          Xmm5[16];
 159   UINT8          Xmm6[16];
 160   UINT8          Xmm7[16];
 161   UINT8          Xmm8[16];
 162   UINT8          Xmm9[16];
 163   UINT8          Xmm10[16];
 164   UINT8          Xmm11[16];
 165   UINT8          Xmm12[16];
 166   UINT8          Xmm13[16];
 167   UINT8          Xmm14[16];
 168   UINT8          Xmm15[16];
 169 } DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_X64;
 170
 171 ///
 172 ///  x64 Segment Limit GROUP register
 173 ///
 174 typedef struct {
 175   UINT64         CsLim;
 176   UINT64         SsLim;
 177   UINT64         GsLim;
 178   UINT64         FsLim;
 179   UINT64         EsLim;
 180   UINT64         DsLim;
 181   UINT64         LdtLim;
 182   UINT64         TssLim;
 183 } DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM_X64;
 184
 185 ///
 186 ///  x64 Segment Base GROUP register
 187 ///
 188 typedef struct {
 189   UINT64         CsBas;
 190   UINT64         SsBas;
 191   UINT64         GsBas;
 192   UINT64         FsBas;
 193   UINT64         EsBas;
 194   UINT64         DsBas;
 195   UINT64         LdtBas;
 196   UINT64         TssBas;
 197 } DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE_X64;
 198
 199 ///
 200 ///  x64 Segment Base/Limit GROUP register
 201 ///
 202 typedef struct {
 203   UINT64         IdtBas;
 204   UINT64         IdtLim;
 205   UINT64         GdtBas;
 206   UINT64         GdtLim;
 207   UINT64         CsLim;
 208   UINT64         SsLim;
 209   UINT64         GsLim;
 210   UINT64         FsLim;
 211   UINT64         EsLim;
 212   UINT64         DsLim;
 213   UINT64         LdtLim;
 214   UINT64         TssLim;
 215   UINT64         CsBas;
 216   UINT64         SsBas;
 217   UINT64         GsBas;
 218   UINT64         FsBas;
 219   UINT64         EsBas;
 220   UINT64         DsBas;
 221   UINT64         LdtBas;
 222   UINT64         TssBas;
 223 } DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT_BAS_LIM;
 224
 225 ///
 226 ///  x64 register GROUP register
 227 ///
 228 typedef struct {
 229   UINT32         Eflags;
 230   UINT64         Rbp;
 231   UINT64         Eip;
 232   UINT64         Rsp;
 233 } DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_GP2;
 234
 235 ///
 236 ///  x64 general register GROUP register
 237 ///
 238 typedef struct {
 239   UINT64         Eax;
 240   UINT64         Rbx;
 241   UINT64         Rcx;
 242   UINT64         Rdx;
 243   UINT64         Rsi;
 244   UINT64         Rdi;
 245   UINT64         R8;
 246   UINT64         R9;
 247   UINT64         R10;
 248   UINT64         R11;
 249   UINT64         R12;
 250   UINT64         R13;
 251   UINT64         R14;
 252   UINT64         R15;
 253 } DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_GP;
 254
 255 ///
 256 ///  x64 Segment GROUP register
 257 ///
 258 typedef struct {
 259   UINT16         Cs;
 260   UINT16         Ds;
 261   UINT16         Es;
 262   UINT16         Fs;
 263   UINT16         Gs;
 264   UINT16         Ss;
 265 } DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT;
 266
 267 ///
 268 ///  x64 Debug Register GROUP register
 269 ///
 270 typedef struct {
 271   UINT64         Dr0;
 272   UINT64         Dr1;
 273   UINT64         Dr2;
 274   UINT64         Dr3;
 275   UINT64         Dr6;
 276   UINT64         Dr7;
 277 } DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_DR;
 278
 279 ///
 280 ///  x64 Control Register GROUP register
 281 ///
 282 typedef struct {
 283   UINT64         Cr0;
 284   UINT64         Cr2;
 285   UINT64         Cr3;
 286   UINT64         Cr4;
 287   UINT64         Cr8;
 288 } DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_CR;
 289
 290 ///
 291 ///  x64 XMM Register GROUP register
 292 ///
 293 typedef struct {
 294   UINT8          Xmm0[16];
 295   UINT8          Xmm1[16];
 296   UINT8          Xmm2[16];
 297   UINT8          Xmm3[16];
 298   UINT8          Xmm4[16];
 299   UINT8          Xmm5[16];
 300   UINT8          Xmm6[16];
 301   UINT8          Xmm7[16];
 302   UINT8          Xmm8[16];
 303   UINT8          Xmm9[16];
 304   UINT8          Xmm10[16];
 305   UINT8          Xmm11[16];
 306   UINT8          Xmm12[16];
 307   UINT8          Xmm13[16];
 308   UINT8          Xmm14[16];
 309   UINT8          Xmm15[16];
 310 } DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_XMM;
 311
 312 ///
 313 ///  x64 Segment Base GROUP register
 314 ///
 315 typedef struct {
 316   UINT16         Ldtr;
 317   UINT16         Tr;
 318   UINT64         Csas;
 319   UINT64         Ssas;
 320   UINT64         Gsas;
 321   UINT64         Fsas;
 322   UINT64         Esas;
 323   UINT64         Dsas;
 324   UINT64         Ldtas;
 325   UINT64         Tssas;
 326 } DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT_BASES_X64;
 327
 328
 329 #endif