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[mirror_edk2.git] / SourceLevelDebugPkg / Library / DebugCommunicationLibUsb3 / DebugCommunicationLibUsb3Common.c
1 /** @file
2 Debug Port Library implementation based on usb3 debug port.
3
4 Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "DebugCommunicationLibUsb3Internal.h"
16
17 UINT16 mString0Desc[] = {
18 // String Descriptor Type + Length
19 ( USB_DESC_TYPE_STRING << 8 ) + STRING0_DESC_LEN,
20 0x0409
21 };
22
23 UINT16 mManufacturerStrDesc[] = {
24 // String Descriptor Type + Length
25 ( USB_DESC_TYPE_STRING << 8 ) + MANU_DESC_LEN,
26 'I', 'n', 't', 'e', 'l'
27 };
28
29 UINT16 mProductStrDesc[] = {
30 // String Descriptor Type + Length
31 ( USB_DESC_TYPE_STRING << 8 ) + PRODUCT_DESC_LEN,
32 'U', 'S', 'B', ' ', '3', '.', '0', ' ', 'D', 'e', 'b', 'u', 'g', ' ', 'C', 'a', 'b', 'l', 'e'
33 };
34
35 UINT16 mSerialNumberStrDesc[] = {
36 // String Descriptor Type + Length
37 ( USB_DESC_TYPE_STRING << 8 ) + SERIAL_DESC_LEN,
38 '1'
39 };
40
41 /**
42 Sets bits as per the enabled bit positions in the mask.
43
44 @param[in, out] Register UINTN register
45 @param[in] BitMask 32-bit mask
46 **/
47 VOID
48 XhcSetR32Bit(
49 IN OUT UINTN Register,
50 IN UINT32 BitMask
51 )
52 {
53 UINT32 RegisterValue;
54
55 RegisterValue = MmioRead32 (Register);
56 RegisterValue |= (UINT32)(BitMask);
57 MmioWrite32 (Register, RegisterValue);
58 }
59
60 /**
61 Clears bits as per the enabled bit positions in the mask.
62
63 @param[in, out] Register UINTN register
64 @param[in] BitMask 32-bit mask
65 **/
66 VOID
67 XhcClearR32Bit(
68 IN OUT UINTN Register,
69 IN UINT32 BitMask
70 )
71 {
72 UINT32 RegisterValue;
73
74 RegisterValue = MmioRead32 (Register);
75 RegisterValue &= ~BitMask;
76 MmioWrite32 (Register, RegisterValue);
77 }
78
79 /**
80 Write the data to the XHCI debug register.
81
82 @param Handle Debug port handle.
83 @param Offset The offset of the debug register.
84 @param Data The data to write.
85
86 **/
87 VOID
88 XhcWriteDebugReg (
89 IN USB3_DEBUG_PORT_HANDLE *Handle,
90 IN UINT32 Offset,
91 IN UINT32 Data
92 )
93 {
94 EFI_PHYSICAL_ADDRESS DebugCapabilityBase;
95
96 DebugCapabilityBase = Handle->DebugCapabilityBase;
97 MmioWrite32 ((UINTN)(DebugCapabilityBase + Offset), Data);
98
99 return;
100 }
101
102 /**
103 Read XHCI debug register.
104
105 @param Handle Debug port handle.
106 @param Offset The offset of the runtime register.
107
108 @return The register content read
109
110 **/
111 UINT32
112 XhcReadDebugReg (
113 IN USB3_DEBUG_PORT_HANDLE *Handle,
114 IN UINT32 Offset
115 )
116 {
117 UINT32 Data;
118 EFI_PHYSICAL_ADDRESS DebugCapabilityBase;
119
120 DebugCapabilityBase = Handle->DebugCapabilityBase;
121 Data = MmioRead32 ((UINTN)(DebugCapabilityBase + Offset));
122
123 return Data;
124 }
125
126 /**
127 Set one bit of the debug register while keeping other bits.
128
129 @param Handle Debug port handle.
130 @param Offset The offset of the debug register.
131 @param Bit The bit mask of the register to set.
132
133 **/
134 VOID
135 XhcSetDebugRegBit (
136 IN USB3_DEBUG_PORT_HANDLE *Handle,
137 IN UINT32 Offset,
138 IN UINT32 Bit
139 )
140 {
141 UINT32 Data;
142
143 Data = XhcReadDebugReg (Handle, Offset);
144 Data |= Bit;
145 XhcWriteDebugReg (Handle, Offset, Data);
146 }
147
148 /**
149 Clear one bit of the debug register while keeping other bits.
150
151 @param Handle Debug port handle.
152 @param Offset The offset of the debug register.
153 @param Bit The bit mask of the register to clear.
154
155 **/
156 VOID
157 XhcClearDebugRegBit (
158 IN USB3_DEBUG_PORT_HANDLE *Handle,
159 IN UINT32 Offset,
160 IN UINT32 Bit
161 )
162 {
163 UINT32 Data;
164
165 Data = XhcReadDebugReg (Handle, Offset);
166 Data &= ~Bit;
167 XhcWriteDebugReg (Handle, Offset, Data);
168 }
169
170 /**
171 Program and eanble XHCI MMIO base address.
172
173 @return XHCI MMIO base address.
174
175 **/
176 EFI_PHYSICAL_ADDRESS
177 ProgramXhciBaseAddress (
178 VOID
179 )
180 {
181 UINT16 PciCmd;
182 UINT32 Low;
183 UINT32 High;
184 EFI_PHYSICAL_ADDRESS XhciMmioBase;
185
186 Low = PciRead32 (PcdGet32(PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET);
187 High = PciRead32 (PcdGet32(PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET + 4);
188 XhciMmioBase = (EFI_PHYSICAL_ADDRESS) (LShiftU64 ((UINT64) High, 32) | Low);
189 XhciMmioBase &= XHCI_BASE_ADDRESS_64_BIT_MASK;
190
191 if ((XhciMmioBase == 0) || (XhciMmioBase == XHCI_BASE_ADDRESS_64_BIT_MASK)) {
192 XhciMmioBase = PcdGet64(PcdUsbXhciMemorySpaceBase);
193 PciWrite32(PcdGet32(PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET, XhciMmioBase & 0xFFFFFFFF);
194 PciWrite32(PcdGet32(PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET + 4, (RShiftU64 (XhciMmioBase, 32) & 0xFFFFFFFF));
195 }
196
197 PciCmd = PciRead16 (PcdGet32(PcdUsbXhciPciAddress) + PCI_COMMAND_OFFSET);
198 if (((PciCmd & EFI_PCI_COMMAND_MEMORY_SPACE) == 0) || ((PciCmd & EFI_PCI_COMMAND_BUS_MASTER) == 0)) {
199 PciCmd |= EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_BUS_MASTER;
200 PciWrite16(PcdGet32(PcdUsbXhciPciAddress) + PCI_COMMAND_OFFSET, PciCmd);
201 }
202
203 return XhciMmioBase;
204 }
205
206 /**
207 Update XHC MMIO base address when MMIO base address is changed.
208
209 @param Handle Debug port handle.
210 @param XhciMmioBase XHCI MMIO base address.
211
212 **/
213 VOID
214 UpdateXhcResource (
215 IN OUT USB3_DEBUG_PORT_HANDLE *Handle,
216 IN EFI_PHYSICAL_ADDRESS XhciMmioBase
217 )
218 {
219 if (Handle == NULL) {
220 return;
221 }
222
223 //
224 // Need fix Handle data according to new XHCI MMIO base address.
225 //
226 Handle->XhciMmioBase = XhciMmioBase;
227 Handle->DebugCapabilityBase = XhciMmioBase + Handle->DebugCapabilityOffset;
228 Handle->XhciOpRegister = XhciMmioBase + MmioRead8 ((UINTN)XhciMmioBase);
229 }
230
231 /**
232 Calculate the usb debug port bar address.
233
234 @param Handle Debug port handle.
235
236 @retval RETURN_UNSUPPORTED The usb host controller does not support usb debug port capability.
237 @retval RETURN_SUCCESS Get bar and offset successfully.
238
239 **/
240 RETURN_STATUS
241 EFIAPI
242 CalculateUsbDebugPortMmioBase (
243 USB3_DEBUG_PORT_HANDLE *Handle
244 )
245 {
246 UINT16 VendorId;
247 UINT16 DeviceId;
248 UINT8 ProgInterface;
249 UINT8 SubClassCode;
250 UINT8 BaseCode;
251 BOOLEAN Flag;
252 UINT32 Capability;
253 EFI_PHYSICAL_ADDRESS CapabilityPointer;
254 UINT8 CapLength;
255
256 if (Handle->Initialized != USB3DBG_UNINITIALIZED) {
257 if (Handle->Initialized == USB3DBG_NO_DBG_CAB) {
258 return RETURN_UNSUPPORTED;
259 } else {
260 return RETURN_SUCCESS;
261 }
262 }
263
264 VendorId = PciRead16 (PcdGet32(PcdUsbXhciPciAddress) + PCI_VENDOR_ID_OFFSET);
265 DeviceId = PciRead16 (PcdGet32(PcdUsbXhciPciAddress) + PCI_DEVICE_ID_OFFSET);
266
267 if ((VendorId == 0xFFFF) || (DeviceId == 0xFFFF)) {
268 goto Done;
269 }
270
271 ProgInterface = PciRead8 (PcdGet32(PcdUsbXhciPciAddress) + PCI_CLASSCODE_OFFSET);
272 SubClassCode = PciRead8 (PcdGet32(PcdUsbXhciPciAddress) + PCI_CLASSCODE_OFFSET + 1);
273 BaseCode = PciRead8 (PcdGet32(PcdUsbXhciPciAddress) + PCI_CLASSCODE_OFFSET + 2);
274
275 if ((ProgInterface != PCI_IF_XHCI) || (SubClassCode != PCI_CLASS_SERIAL_USB) || (BaseCode != PCI_CLASS_SERIAL)) {
276 goto Done;
277 }
278
279 CapLength = MmioRead8 ((UINTN) Handle->XhciMmioBase);
280
281 //
282 // Get capability pointer from HCCPARAMS at offset 0x10
283 //
284 CapabilityPointer = Handle->XhciMmioBase + (MmioRead32 ((UINTN)(Handle->XhciMmioBase + XHC_HCCPARAMS_OFFSET)) >> 16) * 4;
285
286 //
287 // Search XHCI debug capability
288 //
289 Flag = FALSE;
290 Capability = MmioRead32 ((UINTN)CapabilityPointer);
291 while (TRUE) {
292 if ((Capability & XHC_CAPABILITY_ID_MASK) == PCI_CAPABILITY_ID_DEBUG_PORT) {
293 Flag = TRUE;
294 break;
295 }
296 if ((((Capability & XHC_NEXT_CAPABILITY_MASK) >> 8) & XHC_CAPABILITY_ID_MASK) == 0) {
297 //
298 // Reach the end of capability list, quit
299 //
300 break;
301 }
302 CapabilityPointer += ((Capability & XHC_NEXT_CAPABILITY_MASK) >> 8) * 4;
303 Capability = MmioRead32 ((UINTN)CapabilityPointer);
304 }
305
306 if (!Flag) {
307 goto Done;
308 }
309
310 //
311 // USB3 debug capability is supported.
312 //
313 Handle->DebugCapabilityBase = CapabilityPointer;
314 Handle->DebugCapabilityOffset = CapabilityPointer - Handle->XhciMmioBase;
315 Handle->XhciOpRegister = Handle->XhciMmioBase + CapLength;
316 Handle->DebugSupport = TRUE;
317 Handle->Initialized = USB3DBG_DBG_CAB;
318 return RETURN_SUCCESS;
319
320 Done:
321 Handle->Initialized = USB3DBG_NO_DBG_CAB;
322 return RETURN_UNSUPPORTED;
323 }
324
325 /**
326 Check if it needs to re-initialize usb debug port hardware.
327
328 During different phases switch, such as SEC to PEI or PEI to DXE or DXE to SMM, we should check
329 whether the usb debug port hardware configuration is changed. Such case can be triggered by
330 Pci bus resource allocation and so on.
331
332 @param Handle Debug port handle.
333
334 @retval TRUE The usb debug port hardware configuration is changed.
335 @retval FALSE The usb debug port hardware configuration is not changed.
336
337 **/
338 BOOLEAN
339 EFIAPI
340 NeedReinitializeHardware(
341 IN USB3_DEBUG_PORT_HANDLE *Handle
342 )
343 {
344 BOOLEAN Result;
345 volatile UINT32 Dcctrl;
346
347 Result = FALSE;
348
349 //
350 // If DCE bit, it means USB3 debug is not enabled.
351 //
352 Dcctrl = XhcReadDebugReg (Handle, XHC_DC_DCCTRL);
353 if ((Dcctrl & BIT0) == 0) {
354 Result = TRUE;
355 } else if (!Handle->Ready) {
356 Handle->Ready = TRUE;
357 Handle->Initialized = USB3DBG_ENABLED;
358 }
359
360 return Result;
361 }
362
363 /**
364 Create XHCI event ring.
365
366 @param Handle Debug port handle.
367 @param EventRing The created event ring.
368
369 **/
370 EFI_STATUS
371 CreateEventRing (
372 IN USB3_DEBUG_PORT_HANDLE *Handle,
373 OUT EVENT_RING *EventRing
374 )
375 {
376 VOID *Buf;
377 EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;
378
379 ASSERT (EventRing != NULL);
380
381 //
382 // Allocate Event Ring
383 //
384 Buf = AllocateAlignBuffer (sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER);
385 ASSERT (Buf != NULL);
386 ASSERT (((UINTN) Buf & 0x3F) == 0);
387 ZeroMem (Buf, sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER);
388
389 EventRing->EventRingSeg0 = (EFI_PHYSICAL_ADDRESS)(UINTN) Buf;
390 EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;
391 EventRing->EventRingDequeue = (EFI_PHYSICAL_ADDRESS)(UINTN) EventRing->EventRingSeg0;
392 EventRing->EventRingEnqueue = (EFI_PHYSICAL_ADDRESS)(UINTN) EventRing->EventRingSeg0;
393
394 //
395 // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
396 // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.
397 //
398 EventRing->EventRingCCS = 1;
399
400 //
401 // Allocate Event Ring Segment Table Entry 0 in Event Ring Segment Table
402 //
403 Buf = AllocateAlignBuffer (sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER);
404 ASSERT (Buf != NULL);
405 ASSERT (((UINTN) Buf & 0x3F) == 0);
406 ZeroMem (Buf, sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER);
407
408 ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;
409 EventRing->ERSTBase = (EFI_PHYSICAL_ADDRESS)(UINTN) ERSTBase;
410
411 //
412 // Fill Event Segment address
413 //
414 ERSTBase->PtrLo = XHC_LOW_32BIT (EventRing->EventRingSeg0);
415 ERSTBase->PtrHi = XHC_HIGH_32BIT (EventRing->EventRingSeg0);
416 ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER;
417
418 //
419 // Program the Interrupter Event Ring Dequeue Pointer (DCERDP) register (7.6.4.1)
420 //
421 XhcWriteDebugReg (
422 Handle,
423 XHC_DC_DCERDP,
424 XHC_LOW_32BIT((UINT64)(UINTN)EventRing->EventRingDequeue)
425 );
426
427 XhcWriteDebugReg (
428 Handle,
429 XHC_DC_DCERDP + 4,
430 XHC_HIGH_32BIT((UINT64)(UINTN)EventRing->EventRingDequeue)
431 );
432
433 //
434 // Program the Debug Capability Event Ring Segment Table Base Address (DCERSTBA) register(7.6.4.1)
435 //
436 XhcWriteDebugReg (
437 Handle,
438 XHC_DC_DCERSTBA,
439 XHC_LOW_32BIT((UINT64)(UINTN)ERSTBase)
440 );
441
442 XhcWriteDebugReg (
443 Handle,
444 XHC_DC_DCERSTBA + 4,
445 XHC_HIGH_32BIT((UINT64)(UINTN)ERSTBase)
446 );
447
448 //
449 // Program the Debug Capability Event Ring Segment Table Size (DCERSTSZ) register(7.6.4.1)
450 //
451 XhcWriteDebugReg (
452 Handle,
453 XHC_DC_DCERSTSZ,
454 ERST_NUMBER
455 );
456 return EFI_SUCCESS;
457 }
458
459 /**
460 Create XHCI transfer ring.
461
462 @param Handle Debug port handle.
463 @param TrbNum The number of TRB in the ring.
464 @param TransferRing The created transfer ring.
465
466 **/
467 VOID
468 CreateTransferRing (
469 IN USB3_DEBUG_PORT_HANDLE *Handle,
470 IN UINT32 TrbNum,
471 OUT TRANSFER_RING *TransferRing
472 )
473 {
474 VOID *Buf;
475 LINK_TRB *EndTrb;
476
477 Buf = AllocateAlignBuffer (sizeof (TRB_TEMPLATE) * TrbNum);
478 ASSERT (Buf != NULL);
479 ASSERT (((UINTN) Buf & 0xF) == 0);
480 ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);
481
482 TransferRing->RingSeg0 = (EFI_PHYSICAL_ADDRESS)(UINTN) Buf;
483 TransferRing->TrbNumber = TrbNum;
484 TransferRing->RingEnqueue = TransferRing->RingSeg0;
485 TransferRing->RingDequeue = TransferRing->RingSeg0;
486 TransferRing->RingPCS = 1;
487 //
488 // 4.9.2 Transfer Ring Management
489 // To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to
490 // point to the first TRB in the ring.
491 //
492 EndTrb = (LINK_TRB *) ((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
493 EndTrb->Type = TRB_TYPE_LINK;
494 EndTrb->PtrLo = XHC_LOW_32BIT (Buf);
495 EndTrb->PtrHi = XHC_HIGH_32BIT (Buf);
496 //
497 // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
498 //
499 EndTrb->TC = 1;
500 //
501 // Set Cycle bit as other TRB PCS init value
502 //
503 EndTrb->CycleBit = 0;
504 }
505
506 /**
507 Create debug capability context for XHC debug device.
508
509 @param Handle Debug port handle.
510
511 @retval EFI_SUCCESS The bit successfully changed by host controller.
512 @retval EFI_TIMEOUT The time out occurred.
513
514 **/
515 EFI_STATUS
516 CreateDebugCapabilityContext (
517 IN USB3_DEBUG_PORT_HANDLE *Handle
518 )
519 {
520 VOID *Buf;
521 XHC_DC_CONTEXT *DebugCapabilityContext;
522 UINT8 *String0Desc;
523 UINT8 *ManufacturerStrDesc;
524 UINT8 *ProductStrDesc;
525 UINT8 *SerialNumberStrDesc;
526
527 //
528 // Allocate debug device context
529 //
530 Buf = AllocateAlignBuffer (sizeof (XHC_DC_CONTEXT));
531 ASSERT (Buf != NULL);
532 ASSERT (((UINTN) Buf & 0xF) == 0);
533 ZeroMem (Buf, sizeof (XHC_DC_CONTEXT));
534
535 DebugCapabilityContext = (XHC_DC_CONTEXT *)(UINTN) Buf;
536 Handle->DebugCapabilityContext = (EFI_PHYSICAL_ADDRESS)(UINTN) DebugCapabilityContext;
537
538 //
539 // Initialize DbcInfoContext.
540 //
541 DebugCapabilityContext->DbcInfoContext.String0Length = STRING0_DESC_LEN;
542 DebugCapabilityContext->DbcInfoContext.ManufacturerStrLength = MANU_DESC_LEN;
543 DebugCapabilityContext->DbcInfoContext.ProductStrLength = PRODUCT_DESC_LEN;
544 DebugCapabilityContext->DbcInfoContext.SerialNumberStrLength = SERIAL_DESC_LEN;
545
546 //
547 // Initialize EpOutContext.
548 //
549 DebugCapabilityContext->EpOutContext.CErr = 0x3;
550 DebugCapabilityContext->EpOutContext.EPType = ED_BULK_OUT;
551 DebugCapabilityContext->EpOutContext.MaxPacketSize = XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE;
552 DebugCapabilityContext->EpOutContext.AverageTRBLength = 0x1000;
553
554 //
555 // Initialize EpInContext.
556 //
557 DebugCapabilityContext->EpInContext.CErr = 0x3;
558 DebugCapabilityContext->EpInContext.EPType = ED_BULK_IN;
559 DebugCapabilityContext->EpInContext.MaxPacketSize = XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE;
560 DebugCapabilityContext->EpInContext.AverageTRBLength = 0x1000;
561
562 //
563 // Update string descriptor address
564 //
565 String0Desc = (UINT8 *) AllocateAlignBuffer (STRING0_DESC_LEN + MANU_DESC_LEN + PRODUCT_DESC_LEN + SERIAL_DESC_LEN);
566 ASSERT (String0Desc != NULL);
567 ZeroMem (String0Desc, STRING0_DESC_LEN + MANU_DESC_LEN + PRODUCT_DESC_LEN + SERIAL_DESC_LEN);
568 CopyMem (String0Desc, mString0Desc, STRING0_DESC_LEN);
569 DebugCapabilityContext->DbcInfoContext.String0DescAddress = (UINT64)(UINTN)String0Desc;
570
571 ManufacturerStrDesc = String0Desc + STRING0_DESC_LEN;
572 CopyMem (ManufacturerStrDesc, mManufacturerStrDesc, MANU_DESC_LEN);
573 DebugCapabilityContext->DbcInfoContext.ManufacturerStrDescAddress = (UINT64)(UINTN)ManufacturerStrDesc;
574
575 ProductStrDesc = ManufacturerStrDesc + MANU_DESC_LEN;
576 CopyMem (ProductStrDesc, mProductStrDesc, PRODUCT_DESC_LEN);
577 DebugCapabilityContext->DbcInfoContext.ProductStrDescAddress = (UINT64)(UINTN)ProductStrDesc;
578
579 SerialNumberStrDesc = ProductStrDesc + PRODUCT_DESC_LEN;
580 CopyMem (SerialNumberStrDesc, mSerialNumberStrDesc, SERIAL_DESC_LEN);
581 DebugCapabilityContext->DbcInfoContext.SerialNumberStrDescAddress = (UINT64)(UINTN)SerialNumberStrDesc;
582
583 //
584 // Allocate and initialize the Transfer Ring for the Input Endpoint Context.
585 //
586 ZeroMem (&Handle->TransferRingIn, sizeof (TRANSFER_RING));
587 CreateTransferRing (Handle, TR_RING_TRB_NUMBER, &Handle->TransferRingIn);
588 DebugCapabilityContext->EpInContext.PtrLo = XHC_LOW_32BIT (Handle->TransferRingIn.RingSeg0) | BIT0;
589 DebugCapabilityContext->EpInContext.PtrHi = XHC_HIGH_32BIT (Handle->TransferRingIn.RingSeg0);
590
591 //
592 // Allocate and initialize the Transfer Ring for the Output Endpoint Context.
593 //
594 ZeroMem (&Handle->TransferRingOut, sizeof (TRANSFER_RING));
595 CreateTransferRing (Handle, TR_RING_TRB_NUMBER, &Handle->TransferRingOut);
596 DebugCapabilityContext->EpOutContext.PtrLo = XHC_LOW_32BIT (Handle->TransferRingOut.RingSeg0) | BIT0;
597 DebugCapabilityContext->EpOutContext.PtrHi = XHC_HIGH_32BIT (Handle->TransferRingOut.RingSeg0);
598
599 //
600 // Program the Debug Capability Context Pointer (DCCP) register(7.6.8.7)
601 //
602 XhcWriteDebugReg (
603 Handle,
604 XHC_DC_DCCP,
605 XHC_LOW_32BIT((UINT64)(UINTN)DebugCapabilityContext)
606 );
607 XhcWriteDebugReg (
608 Handle,
609 XHC_DC_DCCP + 4,
610 XHC_HIGH_32BIT((UINT64)(UINTN)DebugCapabilityContext)
611 );
612 return EFI_SUCCESS;
613 }
614
615 /**
616 Check if debug device is running.
617
618 @param Handle Debug port handle.
619
620 **/
621 VOID
622 XhcDetectDebugCapabilityReady (
623 IN USB3_DEBUG_PORT_HANDLE *Handle
624 )
625 {
626 UINT64 TimeOut;
627 volatile UINT32 Dcctrl;
628
629 TimeOut = 1;
630 if (Handle->Initialized == USB3DBG_DBG_CAB) {
631 //
632 // As detection is slow in seconds, wait for longer timeout for the first time.
633 // If first initialization is failed, we will try to enable debug device in the
634 // Poll function invoked by timer.
635 //
636 TimeOut = DivU64x32 (PcdGet64 (PcdUsbXhciDebugDetectTimeout), XHC_POLL_DELAY) + 1;
637 }
638
639 do {
640 //
641 // Check if debug device is in configured state
642 //
643 Dcctrl = XhcReadDebugReg (Handle, XHC_DC_DCCTRL);
644 if ((Dcctrl & BIT0) != 0) {
645 //
646 // Set the flag to indicate debug device is in configured state
647 //
648 Handle->Ready = TRUE;
649 break;
650 }
651 MicroSecondDelay (XHC_POLL_DELAY);
652 TimeOut--;
653 } while (TimeOut != 0);
654 }
655
656 /**
657 Initialize usb debug port hardware.
658
659 @param Handle Debug port handle.
660
661 @retval TRUE The usb debug port hardware configuration is changed.
662 @retval FALSE The usb debug port hardware configuration is not changed.
663
664 **/
665 RETURN_STATUS
666 EFIAPI
667 InitializeUsbDebugHardware (
668 IN USB3_DEBUG_PORT_HANDLE *Handle
669 )
670 {
671 RETURN_STATUS Status;
672 UINT8 *Buffer;
673 UINTN Index;
674 UINT8 TotalUsb3Port;
675 EFI_PHYSICAL_ADDRESS XhciOpRegister;
676
677 XhciOpRegister = Handle->XhciOpRegister;
678 TotalUsb3Port = MmioRead32 (((UINTN) Handle->XhciMmioBase + XHC_HCSPARAMS1_OFFSET)) >> 24;
679
680 if (Handle->Initialized == USB3DBG_NOT_ENABLED) {
681 //
682 // If XHCI supports debug capability, hardware resource has been allocated,
683 // but it has not been enabled, try to enable again.
684 //
685 goto Enable;
686 }
687
688 //
689 // Initialize for PEI phase when AllocatePages can work.
690 // Allocate data buffer with max packet size for data read and data poll.
691 // Allocate data buffer for data write.
692 //
693 Buffer = AllocateAlignBuffer (XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE * 2 + USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE);
694 if (Buffer == NULL) {
695 //
696 // AllocatePages can not still work now, return fail and do not initialize now.
697 //
698 return RETURN_NOT_READY;
699 }
700
701 //
702 // Reset port to get debug device discovered
703 //
704 for (Index = 0; Index < TotalUsb3Port; Index++) {
705 XhcSetR32Bit ((UINTN)XhciOpRegister + XHC_PORTSC_OFFSET + Index * 0x10, BIT4);
706 MicroSecondDelay (10 * 1000);
707 }
708
709 //
710 // Clear DCE bit and LSE bit in DCCTRL
711 //
712 if ((XhcReadDebugReg (Handle, XHC_DC_DCCTRL) & (BIT1|BIT31)) == (BIT1|BIT31)) {
713 XhcClearDebugRegBit (Handle, XHC_DC_DCCTRL, BIT1|BIT31);
714 }
715
716 //
717 // Construct the buffer for read, poll and write.
718 //
719 Handle->UrbIn.Data = (EFI_PHYSICAL_ADDRESS)(UINTN) Buffer;
720 Handle->Data = (EFI_PHYSICAL_ADDRESS)(UINTN) Buffer + XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE;
721 Handle->UrbOut.Data = Handle->UrbIn.Data + XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE * 2;
722
723 //
724 // Initialize event ring
725 //
726 ZeroMem (&Handle->EventRing, sizeof (EVENT_RING));
727 Status = CreateEventRing (Handle, &Handle->EventRing);
728 ASSERT_EFI_ERROR (Status);
729
730 //
731 // Init IN and OUT endpoint context
732 //
733 Status = CreateDebugCapabilityContext (Handle);
734 ASSERT_EFI_ERROR (Status);
735
736 //
737 // Init DCDDI1 and DCDDI2
738 //
739 XhcWriteDebugReg (
740 Handle,
741 XHC_DC_DCDDI1,
742 (UINT32)((XHCI_DEBUG_DEVICE_VENDOR_ID << 16) | XHCI_DEBUG_DEVICE_PROTOCOL)
743 );
744
745 XhcWriteDebugReg (
746 Handle,
747 XHC_DC_DCDDI2,
748 (UINT32)((XHCI_DEBUG_DEVICE_REVISION << 16) | XHCI_DEBUG_DEVICE_PRODUCT_ID)
749 );
750
751 Enable:
752 if ((Handle->Initialized == USB3DBG_NOT_ENABLED) && (!Handle->ChangePortPower)) {
753 //
754 // If the first time detection is failed, turn port power off and on in order to
755 // reset port status this time, then try to check if debug device is ready again.
756 //
757 for (Index = 0; Index < TotalUsb3Port; Index++) {
758 XhcClearR32Bit ((UINTN)XhciOpRegister + XHC_PORTSC_OFFSET + Index * 0x10, BIT9);
759 MicroSecondDelay (XHC_DEBUG_PORT_ON_OFF_DELAY);
760 XhcSetR32Bit ((UINTN)XhciOpRegister + XHC_PORTSC_OFFSET + Index * 0x10, BIT9);
761 MicroSecondDelay (XHC_DEBUG_PORT_ON_OFF_DELAY);
762 Handle->ChangePortPower = TRUE;
763 }
764 }
765
766 //
767 // Set DCE bit and LSE bit to "1" in DCCTRL in first initialization
768 //
769 XhcSetDebugRegBit (Handle, XHC_DC_DCCTRL, BIT1|BIT31);
770
771 XhcDetectDebugCapabilityReady (Handle);
772
773 Status = RETURN_SUCCESS;
774 if (!Handle->Ready) {
775 Handle->Initialized = USB3DBG_NOT_ENABLED;
776 Status = RETURN_NOT_READY;
777 } else {
778 Handle->Initialized = USB3DBG_ENABLED;
779 }
780
781 return Status;
782 }
783
784 /**
785 Discover and initialize usb debug port.
786
787 @param Handle Debug port handle.
788
789 **/
790 VOID
791 DiscoverInitializeUsbDebugPort (
792 IN USB3_DEBUG_PORT_HANDLE *Handle
793 )
794 {
795 EFI_STATUS Status;
796 EFI_PHYSICAL_ADDRESS XhciMmioBase;
797
798 //
799 // Read 64-bit MMIO base address
800 //
801 XhciMmioBase = ProgramXhciBaseAddress ();
802 Handle->XhciMmioBase = XhciMmioBase;
803
804 Status = CalculateUsbDebugPortMmioBase (Handle);
805 if (!RETURN_ERROR (Status)) {
806 UpdateXhcResource (Handle, XhciMmioBase);
807 if (NeedReinitializeHardware (Handle)) {
808 InitializeUsbDebugHardware (Handle);
809 }
810 }
811 }
812
813 /**
814 Read data from debug device and save the data in buffer.
815
816 Reads NumberOfBytes data bytes from a debug device into the buffer
817 specified by Buffer. The number of bytes actually read is returned.
818 If the return value is less than NumberOfBytes, then the rest operation failed.
819 If NumberOfBytes is zero, then return 0.
820
821 @param Handle Debug port handle.
822 @param Buffer Pointer to the data buffer to store the data read from the debug device.
823 @param NumberOfBytes Number of bytes which will be read.
824 @param Timeout Timeout value for reading from debug device. Its unit is Microsecond.
825
826 @retval 0 Read data failed, no data is to be read.
827 @retval >0 Actual number of bytes read from debug device.
828
829 **/
830 UINTN
831 EFIAPI
832 DebugPortReadBuffer (
833 IN DEBUG_PORT_HANDLE Handle,
834 IN UINT8 *Buffer,
835 IN UINTN NumberOfBytes,
836 IN UINTN Timeout
837 )
838 {
839 USB3_DEBUG_PORT_HANDLE *UsbDebugPortHandle;
840 UINT8 Index;
841 UINT8 *Data;
842
843 if (NumberOfBytes != 1 || Buffer == NULL || Timeout != 0) {
844 return 0;
845 }
846
847 UsbDebugPortHandle = GetUsb3DebugPortInstance ();
848 if (UsbDebugPortHandle == NULL) {
849 return 0;
850 }
851
852 if (UsbDebugPortHandle->Initialized != USB3DBG_ENABLED) {
853 return 0;
854 }
855
856 if (UsbDebugPortHandle->InNotify) {
857 return 0;
858 }
859
860 Data = (UINT8 *)(UINTN)UsbDebugPortHandle->Data;
861
862 //
863 // Read data from buffer
864 //
865 if (UsbDebugPortHandle->DataCount < 1) {
866 return 0;
867 } else {
868 *Buffer = Data[0];
869
870 for (Index = 0; Index < UsbDebugPortHandle->DataCount - 1; Index++) {
871 if ((Index + 1) >= XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE) {
872 return 0;
873 }
874 Data[Index] = Data[Index + 1];
875 }
876 UsbDebugPortHandle->DataCount = (UINT8)(UsbDebugPortHandle->DataCount - 1);
877 return 1;
878 }
879 }
880
881 /**
882 Write data from buffer to debug device.
883
884 Writes NumberOfBytes data bytes from Buffer to the debug device.
885 The number of bytes actually written to the debug device is returned.
886 If the return value is less than NumberOfBytes, then the write operation failed.
887 If NumberOfBytes is zero, then return 0.
888
889 @param Handle Debug port handle.
890 @param Buffer Pointer to the data buffer to be written.
891 @param NumberOfBytes Number of bytes to written to the debug device.
892
893 @retval 0 NumberOfBytes is 0.
894 @retval >0 The number of bytes written to the debug device.
895 If this value is less than NumberOfBytes, then the write operation failed.
896
897 **/
898 UINTN
899 EFIAPI
900 DebugPortWriteBuffer (
901 IN DEBUG_PORT_HANDLE Handle,
902 IN UINT8 *Buffer,
903 IN UINTN NumberOfBytes
904 )
905 {
906 USB3_DEBUG_PORT_HANDLE *UsbDebugPortHandle;
907 UINTN Sent;
908 UINTN Total;
909 UINTN Index;
910
911 if (NumberOfBytes == 0 || Buffer == NULL) {
912 return 0;
913 }
914
915 Sent = 0;
916 Total = 0;
917
918 UsbDebugPortHandle = GetUsb3DebugPortInstance ();
919 if (UsbDebugPortHandle == NULL) {
920 return 0;
921 }
922
923 if (UsbDebugPortHandle->Initialized != USB3DBG_ENABLED) {
924 return 0;
925 }
926
927 if (UsbDebugPortHandle->InNotify) {
928 return 0;
929 }
930
931 //
932 // When host is trying to send data, write will be blocked.
933 // Poll to see if there is any data sent by host at first.
934 //
935 DebugPortPollBuffer (UsbDebugPortHandle);
936
937 Index = 0;
938 while ((Total < NumberOfBytes)) {
939 if (NumberOfBytes - Total > USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE) {
940 Sent = USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE;
941 } else {
942 Sent = (UINT8)(NumberOfBytes - Total);
943 }
944 XhcDataTransfer (UsbDebugPortHandle, EfiUsbDataOut, Buffer + Total, &Sent, DATA_TRANSFER_WRITE_TIMEOUT);
945 Total += Sent;
946 }
947
948 return Total;
949 }
950
951 /**
952 Polls a debug device to see if there is any data waiting to be read.
953
954 Polls a debug device to see if there is any data waiting to be read.
955 If there is data waiting to be read from the debug device, then TRUE is returned.
956 If there is no data waiting to be read from the debug device, then FALSE is returned.
957
958 @param Handle Debug port handle.
959
960 @retval TRUE Data is waiting to be read from the debug device.
961 @retval FALSE There is no data waiting to be read from the debug device.
962
963 **/
964 BOOLEAN
965 EFIAPI
966 DebugPortPollBuffer (
967 IN DEBUG_PORT_HANDLE Handle
968 )
969 {
970 USB3_DEBUG_PORT_HANDLE *UsbDebugPortHandle;
971 UINTN Length;
972
973 UsbDebugPortHandle = GetUsb3DebugPortInstance ();
974 if (UsbDebugPortHandle == NULL) {
975 return FALSE;
976 }
977
978 if (UsbDebugPortHandle->Initialized != USB3DBG_ENABLED) {
979 return FALSE;
980 }
981
982 if (UsbDebugPortHandle->InNotify) {
983 return FALSE;
984 }
985
986 //
987 // If the data buffer is not empty, then return TRUE directly.
988 // Otherwise initialize a usb read transaction and read data to internal data buffer.
989 //
990 if (UsbDebugPortHandle->DataCount != 0) {
991 return TRUE;
992 }
993
994 //
995 // Read data as much as we can
996 //
997 Length = XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE;
998 XhcDataTransfer (UsbDebugPortHandle, EfiUsbDataIn, (VOID *)(UINTN)UsbDebugPortHandle->Data, &Length, DATA_TRANSFER_POLL_TIMEOUT);
999
1000 if (Length > XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE) {
1001 return FALSE;
1002 }
1003
1004 if (Length == 0) {
1005 return FALSE;
1006 }
1007
1008 //
1009 // Store data into internal buffer for use later
1010 //
1011 UsbDebugPortHandle->DataCount = (UINT8) Length;
1012 return TRUE;
1013 }
1014
1015 /**
1016 Initialize the debug port.
1017
1018 If Function is not NULL, Debug Communication Library will call this function
1019 by passing in the Context to be the first parameter. If needed, Debug Communication
1020 Library will create one debug port handle to be the second argument passing in
1021 calling the Function, otherwise it will pass NULL to be the second argument of
1022 Function.
1023
1024 If Function is NULL, and Context is not NULL, the Debug Communication Library could
1025 a) Return the same handle as passed in (as Context parameter).
1026 b) Ignore the input Context parameter and create new handle to be returned.
1027
1028 If parameter Function is NULL and Context is NULL, Debug Communication Library could
1029 created a new handle if needed and return it, otherwise it will return NULL.
1030
1031 @param[in] Context Context needed by callback function; it was optional.
1032 @param[in] Function Continue function called by Debug Communication library;
1033 it was optional.
1034
1035 @return The debug port handle created by Debug Communication Library if Function
1036 is not NULL.
1037
1038 **/
1039 DEBUG_PORT_HANDLE
1040 EFIAPI
1041 DebugPortInitialize (
1042 IN VOID *Context,
1043 IN DEBUG_PORT_CONTINUE Function
1044 )
1045 {
1046 USB3_DEBUG_PORT_HANDLE *UsbDebugPortHandle;
1047
1048 UsbDebugPortHandle = GetUsb3DebugPortInstance ();
1049 if (UsbDebugPortHandle == NULL) {
1050 return NULL;
1051 }
1052
1053 if (Function != NULL) {
1054 Function (Context, UsbDebugPortHandle);
1055 }
1056
1057 return (DEBUG_PORT_HANDLE)(UINTN)UsbDebugPortHandle;
1058 }
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