]> git.proxmox.com Git - mirror_edk2.git/blob - SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Internal.h
projects / mirror_edk2.git / blob
? search:


9da49f96440133224ecf53c77a04e1d39d03b11c
[mirror_edk2.git] / SourceLevelDebugPkg / Library / DebugCommunicationLibUsb3 / DebugCommunicationLibUsb3Internal.h
1 /** @file
2 Debug Port Library implementation based on usb3 debug port.
3
4 Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #ifndef __USB3_DEBUG_PORT_LIB_INTERNAL__
16 #define __USB3_DEBUG_PORT_LIB_INTERNAL__
17
18 #include <Uefi.h>
19 #include <Base.h>
20 #include <IndustryStandard/Usb.h>
21 #include <Library/IoLib.h>
22 #include <IndustryStandard/Pci.h>
23 #include <Library/PcdLib.h>
24 #include <Library/UefiLib.h>
25 #include <Library/UefiBootServicesTableLib.h>
26 #include <Library/MemoryAllocationLib.h>
27 #include <Library/DebugLib.h>
28 #include <Library/BaseMemoryLib.h>
29 #include <Library/BaseLib.h>
30 #include <Library/TimerLib.h>
31 #include <Library/DebugCommunicationLib.h>
32 #include <Library/PciLib.h>
33
34 //
35 // USB Debug GUID value
36 //
37 #define USB3_DBG_GUID \
38 { \
39 0xb2a56f4d, 0x9177, 0x4fc8, { 0xa6, 0x77, 0xdd, 0x96, 0x3e, 0xb4, 0xcb, 0x1b } \
40 }
41
42 //
43 // The state machine of usb debug port
44 //
45 #define USB3DBG_NO_DBG_CAB 0 // The XHCI host controller does not support debug capability
46 #define USB3DBG_DBG_CAB 1 // The XHCI host controller supports debug capability
47 #define USB3DBG_ENABLED 2 // The XHCI debug device is enabled
48 #define USB3DBG_NOT_ENABLED 4 // The XHCI debug device is not enabled
49
50 #define USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE 0x08
51
52 //
53 // MaxPacketSize for DbC Endpoint Descriptor IN and OUT
54 //
55 #define XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE 0x400
56
57 #define XHCI_DEBUG_DEVICE_VENDOR_ID 0x0525
58 #define XHCI_DEBUG_DEVICE_PRODUCT_ID 0x127A
59 #define XHCI_DEBUG_DEVICE_PROTOCOL 0xFF
60 #define XHCI_DEBUG_DEVICE_REVISION 0x00
61
62 #define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL
63 #define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000
64
65 #define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A
66 #define XHC_HCCPARAMS_OFFSET 0x10
67 #define XHC_CAPABILITY_ID_MASK 0xFF
68 #define XHC_NEXT_CAPABILITY_MASK 0xFF00
69
70 #define XHC_HCSPARAMS1_OFFSET 0x4 // Structural Parameters 1
71 #define XHC_USBCMD_OFFSET 0x0 // USB Command Register Offset
72 #define XHC_USBSTS_OFFSET 0x4 // USB Status Register Offset
73 #define XHC_PORTSC_OFFSET 0x400 // Port Status and Control Register Offset
74
75 #define XHC_USBCMD_RUN BIT0 // Run/Stop
76 #define XHC_USBCMD_RESET BIT1 // Host Controller Reset
77
78 #define XHC_USBSTS_HALT BIT0
79
80 //
81 // Indicate the timeout when data is transferred in microsecond. 0 means infinite timeout.
82 //
83 #define DATA_TRANSFER_WRITE_TIMEOUT 0
84 #define DATA_TRANSFER_READ_TIMEOUT 50000
85 #define DATA_TRANSFER_POLL_TIMEOUT 1000
86 #define XHC_DEBUG_PORT_1_MILLISECOND 1000
87 //
88 // XHCI port power off/on delay
89 //
90 #define XHC_DEBUG_PORT_ON_OFF_DELAY 100000
91
92 //
93 // USB debug device string descritpor (header size + unicode string length)
94 //
95 #define STRING0_DESC_LEN 4
96 #define MANU_DESC_LEN 12
97 #define PRODUCT_DESC_LEN 40
98 #define SERIAL_DESC_LEN 4
99
100 //
101 // Debug Capability Register Offset
102 //
103 #define XHC_DC_DCID 0x0
104 #define XHC_DC_DCDB 0x4
105 #define XHC_DC_DCERSTSZ 0x8
106 #define XHC_DC_DCERSTBA 0x10
107 #define XHC_DC_DCERDP 0x18
108 #define XHC_DC_DCCTRL 0x20
109 #define XHC_DC_DCST 0x24
110 #define XHC_DC_DCPORTSC 0x28
111 #define XHC_DC_DCCP 0x30
112 #define XHC_DC_DCDDI1 0x38
113 #define XHC_DC_DCDDI2 0x3C
114
115 #define TRB_TYPE_LINK 6
116
117 #define ERST_NUMBER 0x01
118 #define TR_RING_TRB_NUMBER 0x100
119 #define EVENT_RING_TRB_NUMBER 0x200
120
121 #define ED_BULK_OUT 2
122 #define ED_BULK_IN 6
123
124 #define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
125 #define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
126 #define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
127
128 //
129 // Endpoint Type (EP Type).
130 //
131 #define ED_NOT_VALID 0
132 #define ED_ISOCH_OUT 1
133 #define ED_BULK_OUT 2
134 #define ED_INTERRUPT_OUT 3
135 #define ED_CONTROL_BIDIR 4
136 #define ED_ISOCH_IN 5
137 #define ED_BULK_IN 6
138 #define ED_INTERRUPT_IN 7
139
140 //
141 // 6.4.5 TRB Completion Codes
142 //
143 #define TRB_COMPLETION_INVALID 0
144 #define TRB_COMPLETION_SUCCESS 1
145 #define TRB_COMPLETION_DATA_BUFFER_ERROR 2
146 #define TRB_COMPLETION_BABBLE_ERROR 3
147 #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
148 #define TRB_COMPLETION_TRB_ERROR 5
149 #define TRB_COMPLETION_STALL_ERROR 6
150 #define TRB_COMPLETION_SHORT_PACKET 13
151
152 //
153 // 6.4.6 TRB Types
154 //
155 #define TRB_TYPE_NORMAL 1
156 #define TRB_TYPE_SETUP_STAGE 2
157 #define TRB_TYPE_DATA_STAGE 3
158 #define TRB_TYPE_STATUS_STAGE 4
159 #define TRB_TYPE_ISOCH 5
160 #define TRB_TYPE_LINK 6
161 #define TRB_TYPE_EVENT_DATA 7
162 #define TRB_TYPE_NO_OP 8
163 #define TRB_TYPE_EN_SLOT 9
164 #define TRB_TYPE_DIS_SLOT 10
165 #define TRB_TYPE_ADDRESS_DEV 11
166 #define TRB_TYPE_CON_ENDPOINT 12
167 #define TRB_TYPE_EVALU_CONTXT 13
168 #define TRB_TYPE_RESET_ENDPOINT 14
169 #define TRB_TYPE_STOP_ENDPOINT 15
170 #define TRB_TYPE_SET_TR_DEQUE 16
171 #define TRB_TYPE_RESET_DEV 17
172 #define TRB_TYPE_GET_PORT_BANW 21
173 #define TRB_TYPE_FORCE_HEADER 22
174 #define TRB_TYPE_NO_OP_COMMAND 23
175 #define TRB_TYPE_TRANS_EVENT 32
176 #define TRB_TYPE_COMMAND_COMPLT_EVENT 33
177 #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
178 #define TRB_TYPE_HOST_CONTROLLER_EVENT 37
179 #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
180 #define TRB_TYPE_MFINDEX_WRAP_EVENT 39
181
182 //
183 // Convert millisecond to microsecond.
184 //
185 #define XHC_1_MILLISECOND (1000)
186 #define XHC_POLL_DELAY (1000)
187 #define XHC_GENERIC_TIMEOUT (10 * 1000)
188
189 #define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.
190 #define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.
191 #define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.
192 #define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.
193
194 //
195 // Transfer types, used in URB to identify the transfer type
196 //
197 #define XHC_CTRL_TRANSFER 0x01
198 #define XHC_BULK_TRANSFER 0x02
199 #define XHC_INT_TRANSFER_SYNC 0x04
200 #define XHC_INT_TRANSFER_ASYNC 0x08
201 #define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
202
203 //
204 // USB Transfer Results
205 //
206 #define EFI_USB_NOERROR 0x00
207 #define EFI_USB_ERR_NOTEXECUTE 0x01
208 #define EFI_USB_ERR_STALL 0x02
209 #define EFI_USB_ERR_BUFFER 0x04
210 #define EFI_USB_ERR_BABBLE 0x08
211 #define EFI_USB_ERR_NAK 0x10
212 #define EFI_USB_ERR_CRC 0x20
213 #define EFI_USB_ERR_TIMEOUT 0x40
214 #define EFI_USB_ERR_BITSTUFF 0x80
215 #define EFI_USB_ERR_SYSTEM 0x100
216
217 #pragma pack(1)
218
219 //
220 // 7.6.9 OUT/IN EP Context: 64 bytes
221 // 7.6.9.2 When used by the DbC it is always a 64 byte data structure
222 //
223 typedef struct _ENDPOINT_CONTEXT_64 {
224 UINT32 EPState:3;
225 UINT32 RsvdZ1:5;
226 UINT32 Mult:2; // set to 0
227 UINT32 MaxPStreams:5; // set to 0
228 UINT32 LSA:1; // set to 0
229 UINT32 Interval:8; // set to 0
230 UINT32 RsvdZ2:8;
231
232 UINT32 RsvdZ3:1;
233 UINT32 CErr:2;
234 UINT32 EPType:3;
235 UINT32 RsvdZ4:1;
236 UINT32 HID:1; // set to 0
237 UINT32 MaxBurstSize:8;
238 UINT32 MaxPacketSize:16;
239
240 UINT32 PtrLo;
241
242 UINT32 PtrHi;
243
244 UINT32 AverageTRBLength:16;
245 UINT32 MaxESITPayload:16; // set to 0
246
247 UINT32 RsvdZ5; // Reserved
248 UINT32 RsvdZ6;
249 UINT32 RsvdZ7;
250
251 UINT32 RsvdZ8;
252 UINT32 RsvdZ9;
253 UINT32 RsvdZ10;
254 UINT32 RsvdZ11;
255
256 UINT32 RsvdZ12;
257 UINT32 RsvdZ13;
258 UINT32 RsvdZ14;
259 UINT32 RsvdZ15;
260 } ENDPOINT_CONTEXT_64;
261
262 //
263 // 6.4.1.1 Normal TRB: 16 bytes
264 // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and
265 // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer
266 // Rings, and to define the Data stage information for Control Transfer Rings.
267 //
268 typedef struct _TRANSFER_TRB_NORMAL {
269 UINT32 TRBPtrLo;
270
271 UINT32 TRBPtrHi;
272
273 UINT32 Length:17;
274 UINT32 TDSize:5;
275 UINT32 IntTarget:10;
276
277 UINT32 CycleBit:1;
278 UINT32 ENT:1;
279 UINT32 ISP:1;
280 UINT32 NS:1;
281 UINT32 CH:1;
282 UINT32 IOC:1;
283 UINT32 IDT:1;
284 UINT32 RsvdZ1:2;
285 UINT32 BEI:1;
286 UINT32 Type:6;
287 UINT32 RsvdZ2:16;
288 } TRANSFER_TRB_NORMAL;
289
290 //
291 // 6.4.2.1 Transfer Event TRB: 16 bytes
292 // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1
293 // for more information on the use and operation of Transfer Events.
294 //
295 typedef struct _EVT_TRB_TRANSFER {
296 UINT32 TRBPtrLo;
297
298 UINT32 TRBPtrHi;
299
300 UINT32 Length:24;
301 UINT32 Completecode:8;
302
303 UINT32 CycleBit:1;
304 UINT32 RsvdZ1:1;
305 UINT32 ED:1;
306 UINT32 RsvdZ2:7;
307 UINT32 Type:6;
308 UINT32 EndpointId:5;
309 UINT32 RsvdZ3:3;
310 UINT32 SlotId:8;
311 } EVT_TRB_TRANSFER;
312
313 //
314 // 6.4.4.1 Link TRB: 16 bytes
315 // A Link TRB provides support for non-contiguous TRB Rings.
316 //
317 typedef struct _LINK_TRB {
318 UINT32 PtrLo;
319
320 UINT32 PtrHi;
321
322 UINT32 RsvdZ1:22;
323 UINT32 InterTarget:10;
324
325 UINT32 CycleBit:1;
326 UINT32 TC:1;
327 UINT32 RsvdZ2:2;
328 UINT32 CH:1;
329 UINT32 IOC:1;
330 UINT32 RsvdZ3:4;
331 UINT32 Type:6;
332 UINT32 RsvdZ4:16;
333 } LINK_TRB;
334
335 //
336 // TRB Template: 16 bytes
337 //
338 typedef struct _TRB_TEMPLATE {
339 UINT32 Parameter1;
340
341 UINT32 Parameter2;
342
343 UINT32 Status;
344
345 UINT32 CycleBit:1;
346 UINT32 RsvdZ1:9;
347 UINT32 Type:6;
348 UINT32 Control:16;
349 } TRB_TEMPLATE;
350
351 //
352 // Refer to XHCI 6.5 Event Ring Segment Table: 16 bytes
353 //
354 typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
355 UINT32 PtrLo;
356 UINT32 PtrHi;
357 UINT32 RingTrbSize:16;
358 UINT32 RsvdZ1:16;
359 UINT32 RsvdZ2;
360 } EVENT_RING_SEG_TABLE_ENTRY;
361
362 //
363 // Size: 40 bytes
364 //
365 typedef struct _EVENT_RING {
366 EFI_PHYSICAL_ADDRESS ERSTBase;
367 EFI_PHYSICAL_ADDRESS EventRingSeg0;
368 UINT32 TrbNumber;
369 EFI_PHYSICAL_ADDRESS EventRingEnqueue;
370 EFI_PHYSICAL_ADDRESS EventRingDequeue;
371 UINT32 EventRingCCS;
372 } EVENT_RING;
373
374 // Size: 32 bytes
375 typedef struct _TRANSFER_RING {
376 EFI_PHYSICAL_ADDRESS RingSeg0;
377 UINT32 TrbNumber;
378 EFI_PHYSICAL_ADDRESS RingEnqueue;
379 EFI_PHYSICAL_ADDRESS RingDequeue;
380 UINT32 RingPCS;
381 } TRANSFER_RING;
382
383 //
384 // Size: 64 bytes
385 //
386 typedef struct _DBC_INFO_CONTEXT {
387 UINT64 String0DescAddress;
388 UINT64 ManufacturerStrDescAddress;
389 UINT64 ProductStrDescAddress;
390 UINT64 SerialNumberStrDescAddress;
391 UINT64 String0Length:8;
392 UINT64 ManufacturerStrLength:8;
393 UINT64 ProductStrLength:8;
394 UINT64 SerialNumberStrLength:8;
395 UINT64 RsvdZ1:32;
396 UINT64 RsvdZ2;
397 UINT64 RsvdZ3;
398 UINT64 RsvdZ4;
399 } DBC_INFO_CONTEXT;
400
401 //
402 // Debug Capability Context Data Structure: 192 bytes
403 //
404 typedef struct _XHC_DC_CONTEXT {
405 DBC_INFO_CONTEXT DbcInfoContext;
406 ENDPOINT_CONTEXT_64 EpOutContext;
407 ENDPOINT_CONTEXT_64 EpInContext;
408 } XHC_DC_CONTEXT;
409
410 //
411 // Size: 16 bytes
412 //
413 typedef union _TRB {
414 TRB_TEMPLATE TrbTemplate;
415 TRANSFER_TRB_NORMAL TrbNormal;
416 } TRB;
417
418 ///
419 /// USB data transfer direction
420 ///
421 typedef enum {
422 EfiUsbDataIn,
423 EfiUsbDataOut,
424 EfiUsbNoData
425 } EFI_USB_DATA_DIRECTION;
426
427 //
428 // URB (Usb Request Block) contains information for all kinds of
429 // usb requests.
430 //
431 typedef struct _URB {
432 //
433 // Transfer data buffer
434 //
435 EFI_PHYSICAL_ADDRESS Data;
436 UINT32 DataLen;
437
438 //
439 // Execute result
440 //
441 UINT32 Result;
442 //
443 // Completed data length
444 //
445 UINT32 Completed;
446 //
447 // Tranfer Ring info
448 //
449 EFI_PHYSICAL_ADDRESS Ring;
450 EFI_PHYSICAL_ADDRESS Trb;
451 BOOLEAN Finished;
452 EFI_USB_DATA_DIRECTION Direction;
453 } URB;
454
455 typedef struct _USB3_DEBUG_PORT_INSTANCE {
456 UINT8 Initialized;
457
458 //
459 // The flag indicates debug device is ready
460 //
461 BOOLEAN DebugSupport;
462
463 //
464 // The flag indicates debug device is ready
465 //
466 BOOLEAN Ready;
467
468 //
469 // The flag indicates if USB 3.0 ports has been turn off/on power
470 //
471 BOOLEAN ChangePortPower;
472
473 //
474 // XHCI MMIO Base address
475 //
476 EFI_PHYSICAL_ADDRESS XhciMmioBase;
477
478 //
479 // XHCI OP RegisterBase address
480 //
481 EFI_PHYSICAL_ADDRESS XhciOpRegister;
482
483 //
484 // XHCI Debug Register Base Address
485 //
486 EFI_PHYSICAL_ADDRESS DebugCapabilityBase;
487
488 //
489 // XHCI Debug Capability offset
490 //
491 UINT64 DebugCapabilityOffset;
492
493 //
494 // XHCI Debug Context Address
495 //
496 EFI_PHYSICAL_ADDRESS DebugCapabilityContext;
497
498 //
499 // Transfer Ring
500 //
501 TRANSFER_RING TransferRingOut;
502 TRANSFER_RING TransferRingIn;
503
504 //
505 // EventRing
506 //
507 EVENT_RING EventRing;
508
509 //
510 // URB - Read
511 //
512 URB UrbOut;
513
514 //
515 // URB - Write
516 //
517 URB UrbIn;
518
519 //
520 // The available data length in the following data buffer.
521 //
522 UINT8 DataCount;
523 //
524 // The data buffer address for data read and poll.
525 //
526 EFI_PHYSICAL_ADDRESS Data;
527 } USB3_DEBUG_PORT_HANDLE;
528
529 #pragma pack()
530
531 /**
532 Read XHCI debug register.
533
534 @param Handle Debug port handle.
535 @param Offset The offset of the debug register.
536
537 @return The register content read
538
539 **/
540 UINT32
541 XhcReadDebugReg (
542 IN USB3_DEBUG_PORT_HANDLE *Handle,
543 IN UINT32 Offset
544 );
545
546 /**
547 Set one bit of the debug register while keeping other bits.
548
549 @param Handle Debug port handle.
550 @param Offset The offset of the debug register.
551 @param Bit The bit mask of the register to set.
552
553 **/
554 VOID
555 XhcSetDebugRegBit (
556 IN USB3_DEBUG_PORT_HANDLE *Handle,
557 IN UINT32 Offset,
558 IN UINT32 Bit
559 );
560
561 /**
562 Write the data to the debug register.
563
564 @param Handle Debug port handle.
565 @param Offset The offset of the debug register.
566 @param Data The data to write.
567
568 **/
569 VOID
570 XhcWriteDebugReg (
571 IN USB3_DEBUG_PORT_HANDLE *Handle,
572 IN UINT32 Offset,
573 IN UINT32 Data
574 );
575
576 /**
577 Verifies if the bit positions specified by a mask are set in a register.
578
579 @param[in, out] Register UNITN register
580 @param[in] BitMask 32-bit mask
581
582 @return BOOLEAN - TRUE if all bits specified by the mask are enabled.
583 - FALSE even if one of the bits specified by the mask
584 is not enabled.
585 **/
586 BOOLEAN
587 XhcIsBitSet(
588 UINTN Register,
589 UINT32 BitMask
590 );
591
592 /**
593 Sets bits as per the enabled bit positions in the mask.
594
595 @param[in, out] Register UINTN register
596 @param[in] BitMask 32-bit mask
597 **/
598 VOID
599 XhcSetR32Bit(
600 UINTN Register,
601 UINT32 BitMask
602 );
603
604 /**
605 Clears bits as per the enabled bit positions in the mask.
606
607 @param[in, out] Register UINTN register
608 @param[in] BitMask 32-bit mask
609 **/
610 VOID
611 XhcClearR32Bit(
612 IN OUT UINTN Register,
613 IN UINT32 BitMask
614 );
615
616 /**
617 Initialize USB3 debug port.
618
619 This method invokes various internal functions to facilitate
620 detection and initialization of USB3 debug port.
621
622 @retval RETURN_SUCCESS The serial device was initialized.
623 **/
624 RETURN_STATUS
625 EFIAPI
626 USB3Initialize (
627 VOID
628 );
629
630 /**
631 Return command register value in XHCI controller.
632
633 **/
634 UINT16
635 GetXhciPciCommand (
636 VOID
637 );
638
639 /**
640 Allocate aligned memory for XHC's usage.
641
642 @param BufferSize The size, in bytes, of the Buffer.
643
644 @return A pointer to the allocated buffer or NULL if allocation fails.
645
646 **/
647 VOID*
648 AllocateAlignBuffer (
649 IN UINTN BufferSize
650 );
651
652 /**
653 The real function to initialize USB3 debug port.
654
655 This method invokes various internal functions to facilitate
656 detection and initialization of USB3 debug port.
657
658 @retval RETURN_SUCCESS The serial device was initialized.
659 **/
660 RETURN_STATUS
661 EFIAPI
662 USB3InitializeReal (
663 VOID
664 );
665
666 /**
667 Submits bulk transfer to a bulk endpoint of a USB device.
668
669 @param Handle The instance of debug device.
670 @param Direction The direction of data transfer.
671 @param Data Array of pointers to the buffers of data to transmit
672 from or receive into.
673 @param DataLength The lenght of the data buffer.
674 @param Timeout Indicates the maximum time, in millisecond, which
675 the transfer is allowed to complete.
676
677 @retval EFI_SUCCESS The transfer was completed successfully.
678 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.
679 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
680 @retval EFI_TIMEOUT The transfer failed due to timeout.
681 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
682
683 **/
684 EFI_STATUS
685 EFIAPI
686 XhcDataTransfer (
687 IN USB3_DEBUG_PORT_HANDLE *Handle,
688 IN EFI_USB_DATA_DIRECTION Direction,
689 IN OUT VOID *Data,
690 IN OUT UINTN *DataLength,
691 IN UINTN Timeout
692 );
693
694 #endif //__USB3_DEBUG_PORT_LIB_INTERNAL__
EFI Development Kit II mirror for PVE