UefiCpuPkg/Application/Cpuid/Cpuid.c

   1 /** @file
   2   UEFI Application to display CPUID leaf information.
   3
   4   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include <Uefi.h>
  16 #include <Library/BaseLib.h>
  17 #include <Library/UefiLib.h>
  18 #include <Register/Cpuid.h>
  19
  20 ///
  21 /// Macro used to display the value of a bit field in a register returned by CPUID.
  22 ///
  23 #define PRINT_BIT_FIELD(Variable, FieldName) \
  24   Print (L"%5a%42a: %x\n", #Variable, #FieldName, Variable.Bits.FieldName);
  25
  26 ///
  27 /// Macro used to display the value of a register returned by CPUID.
  28 ///
  29 #define PRINT_VALUE(Variable, Description) \
  30   Print (L"%5a%42a: %x\n", #Variable, #Description, Variable);
  31
  32 ///
  33 /// Structure for cache description lookup table
  34 ///
  35 typedef struct {
  36   UINT8  CacheDescriptor;
  37   CHAR8  *Type;
  38   CHAR8  *Description;
  39 } CPUID_CACHE_INFO_DESCRIPTION;
  40
  41 ///
  42 /// Cache description lookup table
  43 ///
  44 CPUID_CACHE_INFO_DESCRIPTION  mCpuidCacheInfoDescription[] = {
  45   { 0x00 , "General"  , "Null descriptor, this byte contains no information" },
  46   { 0x01 , "TLB"      , "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries" },
  47   { 0x02 , "TLB"      , "Instruction TLB: 4 MByte pages, fully associative, 2 entries" },
  48   { 0x03 , "TLB"      , "Data TLB: 4 KByte pages, 4-way set associative, 64 entries" },
  49   { 0x04 , "TLB"      , "Data TLB: 4 MByte pages, 4-way set associative, 8 entries" },
  50   { 0x05 , "TLB"      , "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries" },
  51   { 0x06 , "Cache"    , "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size" },
  52   { 0x08 , "Cache"    , "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size" },
  53   { 0x09 , "Cache"    , "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size" },
  54   { 0x0A , "Cache"    , "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size" },
  55   { 0x0B , "TLB"      , "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries" },
  56   { 0x0C , "Cache"    , "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size" },
  57   { 0x0D , "Cache"    , "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size" },
  58   { 0x0E , "Cache"    , "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size" },
  59   { 0x1D , "Cache"    , "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size" },
  60   { 0x21 , "Cache"    , "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size" },
  61   { 0x22 , "Cache"    , "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector" },
  62   { 0x23 , "Cache"    , "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },
  63   { 0x24 , "Cache"    , "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size" },
  64   { 0x25 , "Cache"    , "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },
  65   { 0x29 , "Cache"    , "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },
  66   { 0x2C , "Cache"    , "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size" },
  67   { 0x30 , "Cache"    , "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size" },
  68   { 0x40 , "Cache"    , "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" },
  69   { 0x41 , "Cache"    , "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size" },
  70   { 0x42 , "Cache"    , "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size" },
  71   { 0x43 , "Cache"    , "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size" },
  72   { 0x44 , "Cache"    , "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size" },
  73   { 0x45 , "Cache"    , "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size" },
  74   { 0x46 , "Cache"    , "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size" },
  75   { 0x47 , "Cache"    , "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size" },
  76   { 0x48 , "Cache"    , "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size" },
  77   { 0x49 , "Cache"    , "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H). 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },
  78   { 0x4A , "Cache"    , "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size" },
  79   { 0x4B , "Cache"    , "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size" },
  80   { 0x4C , "Cache"    , "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size" },
  81   { 0x4D , "Cache"    , "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size" },
  82   { 0x4E , "Cache"    , "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size" },
  83   { 0x4F , "TLB"      , "Instruction TLB: 4 KByte pages, 32 entries" },
  84   { 0x50 , "TLB"      , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries" },
  85   { 0x51 , "TLB"      , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries" },
  86   { 0x52 , "TLB"      , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries" },
  87   { 0x55 , "TLB"      , "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries" },
  88   { 0x56 , "TLB"      , "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" },
  89   { 0x57 , "TLB"      , "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" },
  90   { 0x59 , "TLB"      , "Data TLB0: 4 KByte pages, fully associative, 16 entries" },
  91   { 0x5A , "TLB"      , "Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries" },
  92   { 0x5B , "TLB"      , "Data TLB: 4 KByte and 4 MByte pages, 64 entries" },
  93   { 0x5C , "TLB"      , "Data TLB: 4 KByte and 4 MByte pages,128 entries" },
  94   { 0x5D , "TLB"      , "Data TLB: 4 KByte and 4 MByte pages,256 entries" },
  95   { 0x60 , "Cache"    , "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" },
  96   { 0x61 , "TLB"      , "Instruction TLB: 4 KByte pages, fully associative, 48 entries" },
  97   { 0x63 , "TLB"      , "Data TLB: 1 GByte pages, 4-way set associative, 4 entries" },
  98   { 0x66 , "Cache"    , "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" },
  99   { 0x67 , "Cache"    , "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" },
 100   { 0x68 , "Cache"    , "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" },
 101   { 0x6A , "Cache"    , "uTLB: 4 KByte pages, 8-way set associative, 64 entries" },
 102   { 0x6B , "Cache"    , "DTLB: 4 KByte pages, 8-way set associative, 256 entries" },
 103   { 0x6C , "Cache"    , "DTLB: 2M/4M pages, 8-way set associative, 128 entries" },
 104   { 0x6D , "Cache"    , "DTLB: 1 GByte pages, fully associative, 16 entries" },
 105   { 0x70 , "Cache"    , "Trace cache: 12 K-uop, 8-way set associative" },
 106   { 0x71 , "Cache"    , "Trace cache: 16 K-uop, 8-way set associative" },
 107   { 0x72 , "Cache"    , "Trace cache: 32 K-uop, 8-way set associative" },
 108   { 0x76 , "TLB"      , "Instruction TLB: 2M/4M pages, fully associative, 8 entries" },
 109   { 0x78 , "Cache"    , "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size" },
 110   { 0x79 , "Cache"    , "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
 111   { 0x7A , "Cache"    , "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
 112   { 0x7B , "Cache"    , "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
 113   { 0x7C , "Cache"    , "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
 114   { 0x7D , "Cache"    , "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size" },
 115   { 0x7F , "Cache"    , "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size" },
 116   { 0x80 , "Cache"    , "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size" },
 117   { 0x82 , "Cache"    , "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size" },
 118   { 0x83 , "Cache"    , "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size" },
 119   { 0x84 , "Cache"    , "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size" },
 120   { 0x85 , "Cache"    , "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size" },
 121   { 0x86 , "Cache"    , "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },
 122   { 0x87 , "Cache"    , "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },
 123   { 0xA0 , "DTLB"     , "DTLB: 4k pages, fully associative, 32 entries" },
 124   { 0xB0 , "TLB"      , "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries" },
 125   { 0xB1 , "TLB"      , "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" },
 126   { 0xB2 , "TLB"      , "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries" },
 127   { 0xB3 , "TLB"      , "Data TLB: 4 KByte pages, 4-way set associative, 128 entries" },
 128   { 0xB4 , "TLB"      , "Data TLB1: 4 KByte pages, 4-way associative, 256 entries" },
 129   { 0xB5 , "TLB"      , "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries" },
 130   { 0xB6 , "TLB"      , "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries" },
 131   { 0xBA , "TLB"      , "Data TLB1: 4 KByte pages, 4-way associative, 64 entries" },
 132   { 0xC0 , "TLB"      , "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries" },
 133   { 0xC1 , "STLB"     , "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" },
 134   { 0xC2 , "DTLB"     , "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" },
 135   { 0xC3 , "STLB"     , "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." },
 136   { 0xCA , "STLB"     , "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" },
 137   { 0xD0 , "Cache"    , "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },
 138   { 0xD1 , "Cache"    , "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" },
 139   { 0xD2 , "Cache"    , "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size" },
 140   { 0xD6 , "Cache"    , "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },
 141   { 0xD7 , "Cache"    , "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size" },
 142   { 0xD8 , "Cache"    , "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size" },
 143   { 0xDC , "Cache"    , "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size" },
 144   { 0xDD , "Cache"    , "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size" },
 145   { 0xDE , "Cache"    , "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size" },
 146   { 0xE2 , "Cache"    , "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size" },
 147   { 0xE3 , "Cache"    , "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },
 148   { 0xE4 , "Cache"    , "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size" },
 149   { 0xEA , "Cache"    , "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size" },
 150   { 0xEB , "Cache"    , "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size" },
 151   { 0xEC , "Cache"    , "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size" },
 152   { 0xF0 , "Prefetch" , "64-Byte prefetching" },
 153   { 0xF1 , "Prefetch" , "128-Byte prefetching" },
 154   { 0xFF , "General"  , "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters" }
 155 };
 156
 157 ///
 158 /// The maximum supported CPUID leaf index starting from leaf 0x00000000.
 159 ///
 160 UINT32  gMaximumBasicFunction    = CPUID_SIGNATURE;
 161
 162 ///
 163 /// The maximum supported CPUID leaf index starting from leaf 0x80000000.
 164 ///
 165 UINT32  gMaximumExtendedFunction = CPUID_EXTENDED_FUNCTION;
 166
 167 /**
 168   Display CPUID_SIGNATURE leaf.
 169
 170 **/
 171 VOID
 172 CpuidSignature (
 173   VOID
 174   )
 175 {
 176   UINT32 Eax;
 177   UINT32 Ebx;
 178   UINT32 Ecx;
 179   UINT32 Edx;
 180   CHAR8  Signature[13];
 181
 182   AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
 183
 184   Print (L"CPUID_SIGNATURE (Leaf %08x)\n", CPUID_SIGNATURE);
 185   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, Ebx, Ecx, Edx);
 186   PRINT_VALUE (Eax, MaximumLeaf);
 187   *(UINT32 *)(Signature + 0) = Ebx;
 188   *(UINT32 *)(Signature + 4) = Edx;
 189   *(UINT32 *)(Signature + 8) = Ecx;
 190   Signature [12] = 0;
 191   Print (L"  Signature = %a\n", Signature);
 192
 193   gMaximumBasicFunction = Eax;
 194 }
 195
 196 /**
 197   Display CPUID_VERSION_INFO leaf.
 198
 199 **/
 200 VOID
 201 CpuidVersionInfo (
 202   VOID
 203   )
 204 {
 205   CPUID_VERSION_INFO_EAX  Eax;
 206   CPUID_VERSION_INFO_EBX  Ebx;
 207   CPUID_VERSION_INFO_ECX  Ecx;
 208   CPUID_VERSION_INFO_EDX  Edx;
 209   UINT32                  DisplayFamily;
 210   UINT32                  DisplayModel;
 211
 212   if (CPUID_VERSION_INFO > gMaximumBasicFunction) {
 213     return;
 214   }
 215
 216   AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
 217
 218   Print (L"CPUID_VERSION_INFO (Leaf %08x)\n", CPUID_VERSION_INFO);
 219   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
 220
 221   DisplayFamily = Eax.Bits.FamilyId;
 222   if (Eax.Bits.FamilyId == 0x0F) {
 223     DisplayFamily |= (Eax.Bits.ExtendedFamilyId << 4);
 224   }
 225
 226   DisplayModel = Eax.Bits.Model;
 227   if (Eax.Bits.FamilyId == 0x06 || Eax.Bits.FamilyId == 0x0f) {
 228     DisplayModel |= (Eax.Bits.ExtendedModelId << 4);
 229   }
 230
 231   Print (L"  Family = %x  Model = %x  Stepping = %x\n", DisplayFamily, DisplayModel, Eax.Bits.SteppingId);
 232
 233   PRINT_BIT_FIELD (Eax, SteppingId);
 234   PRINT_BIT_FIELD (Eax, Model);
 235   PRINT_BIT_FIELD (Eax, FamilyId);
 236   PRINT_BIT_FIELD (Eax, ProcessorType);
 237   PRINT_BIT_FIELD (Eax, ExtendedModelId);
 238   PRINT_BIT_FIELD (Eax, ExtendedFamilyId);
 239   PRINT_BIT_FIELD (Ebx, BrandIndex);
 240   PRINT_BIT_FIELD (Ebx, CacheLineSize);
 241   PRINT_BIT_FIELD (Ebx, MaximumAddressableIdsForLogicalProcessors);
 242   PRINT_BIT_FIELD (Ebx, InitialLocalApicId);
 243   PRINT_BIT_FIELD (Ecx, SSE3);
 244   PRINT_BIT_FIELD (Ecx, PCLMULQDQ);
 245   PRINT_BIT_FIELD (Ecx, DTES64);
 246   PRINT_BIT_FIELD (Ecx, MONITOR);
 247   PRINT_BIT_FIELD (Ecx, DS_CPL);
 248   PRINT_BIT_FIELD (Ecx, VMX);
 249   PRINT_BIT_FIELD (Ecx, SMX);
 250   PRINT_BIT_FIELD (Ecx, TM2);
 251   PRINT_BIT_FIELD (Ecx, SSSE3);
 252   PRINT_BIT_FIELD (Ecx, CNXT_ID);
 253   PRINT_BIT_FIELD (Ecx, SDBG);
 254   PRINT_BIT_FIELD (Ecx, FMA);
 255   PRINT_BIT_FIELD (Ecx, CMPXCHG16B);
 256   PRINT_BIT_FIELD (Ecx, xTPR_Update_Control);
 257   PRINT_BIT_FIELD (Ecx, PDCM);
 258   PRINT_BIT_FIELD (Ecx, PCID);
 259   PRINT_BIT_FIELD (Ecx, DCA);
 260   PRINT_BIT_FIELD (Ecx, SSE4_1);
 261   PRINT_BIT_FIELD (Ecx, SSE4_2);
 262   PRINT_BIT_FIELD (Ecx, x2APIC);
 263   PRINT_BIT_FIELD (Ecx, MOVBE);
 264   PRINT_BIT_FIELD (Ecx, POPCNT);
 265   PRINT_BIT_FIELD (Ecx, TSC_Deadline);
 266   PRINT_BIT_FIELD (Ecx, AESNI);
 267   PRINT_BIT_FIELD (Ecx, XSAVE);
 268   PRINT_BIT_FIELD (Ecx, OSXSAVE);
 269   PRINT_BIT_FIELD (Ecx, AVX);
 270   PRINT_BIT_FIELD (Ecx, F16C);
 271   PRINT_BIT_FIELD (Ecx, RDRAND);
 272   PRINT_BIT_FIELD (Edx, FPU);
 273   PRINT_BIT_FIELD (Edx, VME);
 274   PRINT_BIT_FIELD (Edx, DE);
 275   PRINT_BIT_FIELD (Edx, PSE);
 276   PRINT_BIT_FIELD (Edx, TSC);
 277   PRINT_BIT_FIELD (Edx, MSR);
 278   PRINT_BIT_FIELD (Edx, PAE);
 279   PRINT_BIT_FIELD (Edx, MCE);
 280   PRINT_BIT_FIELD (Edx, CX8);
 281   PRINT_BIT_FIELD (Edx, APIC);
 282   PRINT_BIT_FIELD (Edx, SEP);
 283   PRINT_BIT_FIELD (Edx, MTRR);
 284   PRINT_BIT_FIELD (Edx, PGE);
 285   PRINT_BIT_FIELD (Edx, MCA);
 286   PRINT_BIT_FIELD (Edx, CMOV);
 287   PRINT_BIT_FIELD (Edx, PAT);
 288   PRINT_BIT_FIELD (Edx, PSE_36);
 289   PRINT_BIT_FIELD (Edx, PSN);
 290   PRINT_BIT_FIELD (Edx, CLFSH);
 291   PRINT_BIT_FIELD (Edx, DS);
 292   PRINT_BIT_FIELD (Edx, ACPI);
 293   PRINT_BIT_FIELD (Edx, MMX);
 294   PRINT_BIT_FIELD (Edx, FXSR);
 295   PRINT_BIT_FIELD (Edx, SSE);
 296   PRINT_BIT_FIELD (Edx, SSE2);
 297   PRINT_BIT_FIELD (Edx, SS);
 298   PRINT_BIT_FIELD (Edx, HTT);
 299   PRINT_BIT_FIELD (Edx, TM);
 300   PRINT_BIT_FIELD (Edx, PBE);
 301 }
 302
 303 /**
 304   Lookup a cache description string from the mCpuidCacheInfoDescription table.
 305
 306   @param[in] CacheDescriptor  Cache descriptor value from CPUID_CACHE_INFO.
 307
 308 **/
 309 CPUID_CACHE_INFO_DESCRIPTION *
 310 LookupCacheDescription (
 311   UINT8  CacheDescriptor
 312   )
 313 {
 314   UINTN  NumDescriptors;
 315   UINTN  Descriptor;
 316
 317   if (CacheDescriptor == 0x00) {
 318     return NULL;
 319   }
 320   NumDescriptors = sizeof (mCpuidCacheInfoDescription)/sizeof (mCpuidCacheInfoDescription[0]);
 321   for (Descriptor = 0; Descriptor < NumDescriptors; Descriptor++) {
 322     if (CacheDescriptor == mCpuidCacheInfoDescription[Descriptor].CacheDescriptor) {
 323       return &mCpuidCacheInfoDescription[Descriptor];
 324     }
 325   }
 326   return NULL;
 327 }
 328
 329 /**
 330   Display CPUID_CACHE_INFO leaf for each supported cache descriptor.
 331
 332 **/
 333 VOID
 334 CpuidCacheInfo (
 335   VOID
 336   )
 337 {
 338   CPUID_CACHE_INFO_CACHE_TLB    Eax;
 339   CPUID_CACHE_INFO_CACHE_TLB    Ebx;
 340   CPUID_CACHE_INFO_CACHE_TLB    Ecx;
 341   CPUID_CACHE_INFO_CACHE_TLB    Edx;
 342   UINTN                         Index;
 343   CPUID_CACHE_INFO_DESCRIPTION  *CacheDescription;
 344
 345   if (CPUID_CACHE_INFO > gMaximumBasicFunction) {
 346     return;
 347   }
 348
 349   AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
 350
 351   Print (L"CPUID_CACHE_INFO (Leaf %08x)\n", CPUID_CACHE_INFO);
 352   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
 353   if (Eax.Bits.NotValid == 0) {
 354     //
 355     // Process Eax.CacheDescriptor[1..3].  Ignore Eax.CacheDescriptor[0]
 356     //
 357     for (Index = 1; Index < 4; Index++) {
 358       CacheDescription = LookupCacheDescription (Eax.CacheDescriptor[Index]);
 359       if (CacheDescription != NULL) {
 360         Print (L"  %-8a %a\n",
 361           CacheDescription->Type,
 362           CacheDescription->Description
 363           );
 364       }
 365     }
 366   }
 367   if (Ebx.Bits.NotValid == 0) {
 368     //
 369     // Process Ebx.CacheDescriptor[0..3]
 370     //
 371     for (Index = 0; Index < 4; Index++) {
 372       CacheDescription = LookupCacheDescription (Ebx.CacheDescriptor[Index]);
 373       if (CacheDescription != NULL) {
 374         Print (L"  %-8a %a\n",
 375           CacheDescription->Type,
 376           CacheDescription->Description
 377           );
 378       }
 379     }
 380   }
 381   if (Ecx.Bits.NotValid == 0) {
 382     //
 383     // Process Ecx.CacheDescriptor[0..3]
 384     //
 385     for (Index = 0; Index < 4; Index++) {
 386       CacheDescription = LookupCacheDescription (Ecx.CacheDescriptor[Index]);
 387       if (CacheDescription != NULL) {
 388         Print (L"  %-8a %a\n",
 389           CacheDescription->Type,
 390           CacheDescription->Description
 391           );
 392       }
 393     }
 394   }
 395   if (Edx.Bits.NotValid == 0) {
 396     //
 397     // Process Edx.CacheDescriptor[0..3]
 398     //
 399     for (Index = 0; Index < 4; Index++) {
 400       CacheDescription = LookupCacheDescription (Edx.CacheDescriptor[Index]);
 401       if (CacheDescription != NULL) {
 402         Print (L"  %-8a %a\n",
 403           CacheDescription->Type,
 404           CacheDescription->Description
 405           );
 406       }
 407     }
 408   }
 409 }
 410
 411 /**
 412   Display CPUID_SERIAL_NUMBER leaf if it is supported.
 413
 414 **/
 415 VOID
 416 CpuidSerialNumber (
 417   VOID
 418   )
 419 {
 420   CPUID_VERSION_INFO_EDX  VersionInfoEdx;
 421   UINT32                  Ecx;
 422   UINT32                  Edx;
 423
 424   Print (L"CPUID_SERIAL_NUMBER (Leaf %08x)\n", CPUID_SERIAL_NUMBER);
 425
 426   if (CPUID_SERIAL_NUMBER > gMaximumBasicFunction) {
 427     return;
 428   }
 429
 430   AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
 431   if (VersionInfoEdx.Bits.PSN == 0) {
 432     Print (L"  Not Supported\n");
 433     return;
 434   }
 435
 436   AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);
 437   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", 0, 0, Ecx, Edx);
 438   Print (L"  Processor Serial Number = %08x%08x%08x\n", 0, Edx, Ecx);
 439 }
 440
 441 /**
 442   Display CPUID_CACHE_PARAMS for all supported sub-leafs.
 443
 444 **/
 445 VOID
 446 CpuidCacheParams (
 447   VOID
 448   )
 449 {
 450   UINT32                  CacheLevel;
 451   CPUID_CACHE_PARAMS_EAX  Eax;
 452   CPUID_CACHE_PARAMS_EBX  Ebx;
 453   UINT32                  Ecx;
 454   CPUID_CACHE_PARAMS_EDX  Edx;
 455
 456   if (CPUID_CACHE_PARAMS > gMaximumBasicFunction) {
 457     return;
 458   }
 459
 460   CacheLevel = 0;
 461   do {
 462     AsmCpuidEx (
 463       CPUID_CACHE_PARAMS, CacheLevel,
 464       &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32
 465       );
 466     if (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL) {
 467       Print (L"CPUID_CACHE_PARAMS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_CACHE_PARAMS, CacheLevel);
 468       Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx, Edx.Uint32);
 469       PRINT_BIT_FIELD (Eax, CacheType);
 470       PRINT_BIT_FIELD (Eax, CacheLevel);
 471       PRINT_BIT_FIELD (Eax, SelfInitializingCache);
 472       PRINT_BIT_FIELD (Eax, FullyAssociativeCache);
 473       PRINT_BIT_FIELD (Eax, MaximumAddressableIdsForLogicalProcessors);
 474       PRINT_BIT_FIELD (Eax, MaximumAddressableIdsForProcessorCores);
 475       PRINT_BIT_FIELD (Ebx, LineSize);
 476       PRINT_BIT_FIELD (Ebx, LinePartitions);
 477       PRINT_BIT_FIELD (Ebx, Ways);
 478       PRINT_VALUE     (Ecx, NumberOfSets);
 479       PRINT_BIT_FIELD (Edx, Invalidate);
 480       PRINT_BIT_FIELD (Edx, CacheInclusiveness);
 481       PRINT_BIT_FIELD (Edx, ComplexCacheIndexing);
 482     }
 483     CacheLevel++;
 484   } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
 485 }
 486
 487 /**
 488   Display CPUID_MONITOR_MWAIT leaf.
 489
 490 **/
 491 VOID
 492 CpuidMonitorMwait (
 493   VOID
 494   )
 495 {
 496   CPUID_MONITOR_MWAIT_EAX  Eax;
 497   CPUID_MONITOR_MWAIT_EBX  Ebx;
 498   CPUID_MONITOR_MWAIT_ECX  Ecx;
 499   CPUID_MONITOR_MWAIT_EDX  Edx;
 500
 501   if (CPUID_MONITOR_MWAIT > gMaximumBasicFunction) {
 502     return;
 503   }
 504
 505   AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
 506
 507   Print (L"CPUID_MONITOR_MWAIT (Leaf %08x)\n", CPUID_MONITOR_MWAIT);
 508   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
 509
 510   PRINT_BIT_FIELD (Eax, SmallestMonitorLineSize);
 511   PRINT_BIT_FIELD (Ebx, LargestMonitorLineSize);
 512   PRINT_BIT_FIELD (Ecx, ExtensionsSupported);
 513   PRINT_BIT_FIELD (Ecx, InterruptAsBreak);
 514   PRINT_BIT_FIELD (Edx, C0States);
 515   PRINT_BIT_FIELD (Edx, C1States);
 516   PRINT_BIT_FIELD (Edx, C2States);
 517   PRINT_BIT_FIELD (Edx, C3States);
 518   PRINT_BIT_FIELD (Edx, C4States);
 519   PRINT_BIT_FIELD (Edx, C5States);
 520   PRINT_BIT_FIELD (Edx, C6States);
 521   PRINT_BIT_FIELD (Edx, C7States);
 522 }
 523
 524 /**
 525   Display CPUID_THERMAL_POWER_MANAGEMENT leaf.
 526
 527 **/
 528 VOID
 529 CpuidThermalPowerManagement (
 530   VOID
 531   )
 532 {
 533   CPUID_THERMAL_POWER_MANAGEMENT_EAX  Eax;
 534   CPUID_THERMAL_POWER_MANAGEMENT_EBX  Ebx;
 535   CPUID_THERMAL_POWER_MANAGEMENT_ECX  Ecx;
 536
 537   if (CPUID_THERMAL_POWER_MANAGEMENT > gMaximumBasicFunction) {
 538     return;
 539   }
 540
 541   AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
 542
 543   Print (L"CPUID_THERMAL_POWER_MANAGEMENT (Leaf %08x)\n", CPUID_THERMAL_POWER_MANAGEMENT);
 544   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, 0);
 545
 546   PRINT_BIT_FIELD (Eax, DigitalTemperatureSensor);
 547   PRINT_BIT_FIELD (Eax, TurboBoostTechnology);
 548   PRINT_BIT_FIELD (Eax, ARAT);
 549   PRINT_BIT_FIELD (Eax, PLN);
 550   PRINT_BIT_FIELD (Eax, ECMD);
 551   PRINT_BIT_FIELD (Eax, PTM);
 552   PRINT_BIT_FIELD (Eax, HWP);
 553   PRINT_BIT_FIELD (Eax, HWP_Notification);
 554   PRINT_BIT_FIELD (Eax, HWP_Activity_Window);
 555   PRINT_BIT_FIELD (Eax, HWP_Energy_Performance_Preference);
 556   PRINT_BIT_FIELD (Eax, HWP_Package_Level_Request);
 557   PRINT_BIT_FIELD (Eax, HDC);
 558   PRINT_BIT_FIELD (Ebx, InterruptThresholds);
 559   PRINT_BIT_FIELD (Ecx, HardwareCoordinationFeedback);
 560   PRINT_BIT_FIELD (Ecx, PerformanceEnergyBias);
 561 }
 562
 563 /**
 564   Display CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS for all supported sub-leafs.
 565
 566 **/
 567 VOID
 568 CpuidStructuredExtendedFeatureFlags (
 569   VOID
 570   )
 571 {
 572   UINT32                                       Eax;
 573   CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX  Ebx;
 574   CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX  Ecx;
 575   UINT32                                       SubLeaf;
 576
 577   if (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS > gMaximumBasicFunction) {
 578     return;
 579   }
 580
 581   AsmCpuidEx (
 582     CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
 583     CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
 584     &Eax, NULL, NULL, NULL
 585     );
 586   for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {
 587     AsmCpuidEx (
 588       CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
 589       SubLeaf,
 590       NULL, &Ebx.Uint32, &Ecx.Uint32, NULL
 591       );
 592     if (Ebx.Uint32 != 0 || Ecx.Uint32 != 0) {
 593       Print (L"CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, SubLeaf);
 594       Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0);
 595       PRINT_BIT_FIELD (Ebx, FSGSBASE);
 596       PRINT_BIT_FIELD (Ebx, IA32_TSC_ADJUST);
 597       PRINT_BIT_FIELD (Ebx, SGX);
 598       PRINT_BIT_FIELD (Ebx, BMI1);
 599       PRINT_BIT_FIELD (Ebx, HLE);
 600       PRINT_BIT_FIELD (Ebx, AVX2);
 601       PRINT_BIT_FIELD (Ebx, FDP_EXCPTN_ONLY);
 602       PRINT_BIT_FIELD (Ebx, SMEP);
 603       PRINT_BIT_FIELD (Ebx, BMI2);
 604       PRINT_BIT_FIELD (Ebx, EnhancedRepMovsbStosb);
 605       PRINT_BIT_FIELD (Ebx, INVPCID);
 606       PRINT_BIT_FIELD (Ebx, RTM);
 607       PRINT_BIT_FIELD (Ebx, PQM);
 608       PRINT_BIT_FIELD (Ebx, DeprecateFpuCsDs);
 609       PRINT_BIT_FIELD (Ebx, MPX);
 610       PRINT_BIT_FIELD (Ebx, PQE);
 611       PRINT_BIT_FIELD (Ebx, RDSEED);
 612       PRINT_BIT_FIELD (Ebx, ADX);
 613       PRINT_BIT_FIELD (Ebx, SMAP);
 614       PRINT_BIT_FIELD (Ebx, CLFLUSHOPT);
 615       PRINT_BIT_FIELD (Ebx, IntelProcessorTrace);
 616       PRINT_BIT_FIELD (Ecx, PREFETCHWT1);
 617       PRINT_BIT_FIELD (Ecx, PKU);
 618       PRINT_BIT_FIELD (Ecx, OSPKE);
 619     }
 620   }
 621 }
 622
 623 /**
 624   Display CPUID_DIRECT_CACHE_ACCESS_INFO leaf.
 625
 626 **/
 627 VOID
 628 CpuidDirectCacheAccessInfo (
 629   VOID
 630   )
 631 {
 632   UINT32  Eax;
 633
 634   if (CPUID_DIRECT_CACHE_ACCESS_INFO > gMaximumBasicFunction) {
 635     return;
 636   }
 637
 638   AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);
 639   Print (L"CPUID_DIRECT_CACHE_ACCESS_INFO (Leaf %08x)\n", CPUID_DIRECT_CACHE_ACCESS_INFO);
 640   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, 0, 0, 0);
 641 }
 642
 643 /**
 644   Display CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING leaf.
 645
 646 **/
 647 VOID
 648 CpuidArchitecturalPerformanceMonitoring (
 649   VOID
 650   )
 651 {
 652   CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX  Eax;
 653   CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX  Ebx;
 654   CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX  Edx;
 655
 656   if (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING > gMaximumBasicFunction) {
 657     return;
 658   }
 659
 660   AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);
 661   Print (L"CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (Leaf %08x)\n", CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING);
 662   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, Edx.Uint32);
 663   PRINT_BIT_FIELD (Eax, ArchPerfMonVerID);
 664   PRINT_BIT_FIELD (Eax, PerformanceMonitorCounters);
 665   PRINT_BIT_FIELD (Eax, PerformanceMonitorCounterWidth);
 666   PRINT_BIT_FIELD (Eax, EbxBitVectorLength);
 667   PRINT_BIT_FIELD (Ebx, UnhaltedCoreCycles);
 668   PRINT_BIT_FIELD (Ebx, InstructionsRetired);
 669   PRINT_BIT_FIELD (Ebx, UnhaltedReferenceCycles);
 670   PRINT_BIT_FIELD (Ebx, LastLevelCacheReferences);
 671   PRINT_BIT_FIELD (Ebx, LastLevelCacheMisses);
 672   PRINT_BIT_FIELD (Ebx, BranchInstructionsRetired);
 673   PRINT_BIT_FIELD (Ebx, AllBranchMispredictRetired);
 674   PRINT_BIT_FIELD (Edx, FixedFunctionPerformanceCounters);
 675   PRINT_BIT_FIELD (Edx, FixedFunctionPerformanceCounterWidth);
 676 }
 677
 678 /**
 679   Display CPUID_EXTENDED_TOPOLOGY leafs for all supported levels.
 680
 681 **/
 682 VOID
 683 CpuidExtendedTopology (
 684   VOID
 685   )
 686 {
 687   CPUID_EXTENDED_TOPOLOGY_EAX  Eax;
 688   CPUID_EXTENDED_TOPOLOGY_EBX  Ebx;
 689   CPUID_EXTENDED_TOPOLOGY_ECX  Ecx;
 690   UINT32                       Edx;
 691   UINT32                       LevelNumber;
 692
 693   if (CPUID_EXTENDED_TOPOLOGY > gMaximumBasicFunction) {
 694     return;
 695   }
 696
 697   LevelNumber = 0;
 698   do {
 699     AsmCpuidEx (
 700       CPUID_EXTENDED_TOPOLOGY, LevelNumber,
 701       &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx
 702       );
 703     if (Eax.Bits.ApicIdShift != 0) {
 704       Print (L"CPUID_EXTENDED_TOPOLOGY (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_TOPOLOGY, LevelNumber);
 705       Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx);
 706       PRINT_BIT_FIELD (Eax, ApicIdShift);
 707       PRINT_BIT_FIELD (Ebx, LogicalProcessors);
 708       PRINT_BIT_FIELD (Ecx, LevelNumber);
 709       PRINT_BIT_FIELD (Ecx, LevelType);
 710       PRINT_VALUE     (Edx, x2APIC_ID);
 711     }
 712     LevelNumber++;
 713   } while (Eax.Bits.ApicIdShift != 0);
 714 }
 715
 716 /**
 717   Display CPUID_EXTENDED_STATE sub-leaf.
 718
 719 **/
 720 VOID
 721 CpuidExtendedStateSubLeaf (
 722   VOID
 723   )
 724 {
 725   CPUID_EXTENDED_STATE_SUB_LEAF_EAX  Eax;
 726   UINT32                             Ebx;
 727   CPUID_EXTENDED_STATE_SUB_LEAF_ECX  Ecx;
 728   UINT32                             Edx;
 729
 730   AsmCpuidEx (
 731     CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,
 732     &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx
 733     );
 734   Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF);
 735   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx);
 736   PRINT_BIT_FIELD (Eax, XSAVEOPT);
 737   PRINT_BIT_FIELD (Eax, XSAVEC);
 738   PRINT_BIT_FIELD (Eax, XGETBV);
 739   PRINT_BIT_FIELD (Eax, XSAVES);
 740   PRINT_VALUE     (Ebx, EnabledSaveStateSize_XCR0_IA32_XSS);
 741   PRINT_BIT_FIELD (Ecx, XCR0);
 742   PRINT_BIT_FIELD (Ecx, PT);
 743   PRINT_BIT_FIELD (Ecx, XCR0_1);
 744   PRINT_VALUE     (Edx, IA32_XSS_Supported_32_63);
 745 }
 746
 747 /**
 748   Display CPUID_EXTENDED_STATE size and offset information sub-leaf.
 749
 750 **/
 751 VOID
 752 CpuidExtendedStateSizeOffset (
 753   VOID
 754   )
 755 {
 756   UINT32                                Eax;
 757   UINT32                                Ebx;
 758   CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX  Ecx;
 759   UINT32                                Edx;
 760   UINT32                                SubLeaf;
 761
 762   for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {
 763     AsmCpuidEx (
 764       CPUID_EXTENDED_STATE, SubLeaf,
 765       &Eax, &Ebx, &Ecx.Uint32, &Edx
 766       );
 767     if (Edx != 0) {
 768       Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, SubLeaf);
 769       Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, Ebx, Ecx.Uint32, Edx);
 770       PRINT_VALUE     (Eax, FeatureSaveStateSize);
 771       PRINT_VALUE     (Ebx, FeatureSaveStateOffset);
 772       PRINT_BIT_FIELD (Ecx, XSS);
 773       PRINT_BIT_FIELD (Ecx, Compacted);
 774     }
 775   }
 776 }
 777
 778 /**
 779   Display CPUID_EXTENDED_STATE main leaf and sub-leafs.
 780
 781 **/
 782 VOID
 783 CpuidExtendedStateMainLeaf (
 784   VOID
 785   )
 786 {
 787   CPUID_EXTENDED_STATE_MAIN_LEAF_EAX  Eax;
 788   UINT32                              Ebx;
 789   UINT32                              Ecx;
 790   UINT32                              Edx;
 791
 792   if (CPUID_EXTENDED_STATE > gMaximumBasicFunction) {
 793     return;
 794   }
 795
 796   AsmCpuidEx (
 797     CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,
 798     &Eax.Uint32, &Ebx, &Ecx, &Edx
 799     );
 800   Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF);
 801   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx, Ecx, Edx);
 802   PRINT_BIT_FIELD (Eax, x87);
 803   PRINT_BIT_FIELD (Eax, SSE);
 804   PRINT_BIT_FIELD (Eax, AVX);
 805   PRINT_BIT_FIELD (Eax, MPX);
 806   PRINT_BIT_FIELD (Eax, AVX_512);
 807   PRINT_BIT_FIELD (Eax, IA32_XSS);
 808   PRINT_BIT_FIELD (Eax, PKRU);
 809   PRINT_VALUE     (Ebx, EnabledSaveStateSize);
 810   PRINT_VALUE     (Ecx, SupportedSaveStateSize);
 811   PRINT_VALUE     (Edx, XCR0_Supported_32_63);
 812
 813   CpuidExtendedStateSubLeaf ();
 814   CpuidExtendedStateSizeOffset ();
 815 }
 816
 817 /**
 818   Display CPUID_PLATFORM_QOS_MONITORING enumeration sub-leaf.
 819
 820 **/
 821 VOID
 822 CpuidPlatformQosMonitoringEnumerationSubLeaf (
 823   VOID
 824   )
 825 {
 826   UINT32                                                  Ebx;
 827   CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX  Edx;
 828
 829   if (CPUID_PLATFORM_QOS_MONITORING > gMaximumBasicFunction) {
 830     return;
 831   }
 832
 833   AsmCpuidEx (
 834     CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF,
 835     NULL, &Ebx, NULL, &Edx.Uint32
 836     );
 837   Print (L"CPUID_PLATFORM_QOS_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF);
 838   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", 0, Ebx, 0, Edx.Uint32);
 839   PRINT_VALUE     (Ebx, Maximum_RMID_Range);
 840   PRINT_BIT_FIELD (Edx, L3CacheQosEnforcement);
 841 }
 842
 843 /**
 844   Display CPUID_PLATFORM_QOS_MONITORING capability sub-leaf.
 845
 846 **/
 847 VOID
 848 CpuidPlatformQosMonitoringCapabilitySubLeaf (
 849   VOID
 850   )
 851 {
 852   UINT32                                                 Ebx;
 853   UINT32                                                 Ecx;
 854   CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX  Edx;
 855
 856   if (CPUID_PLATFORM_QOS_MONITORING > gMaximumBasicFunction) {
 857     return;
 858   }
 859
 860   AsmCpuidEx (
 861     CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF,
 862     NULL, &Ebx, &Ecx, &Edx.Uint32
 863     );
 864   Print (L"CPUID_PLATFORM_QOS_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF);
 865   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32);
 866   PRINT_VALUE     (Ebx, OccupancyConversionFactor);
 867   PRINT_VALUE     (Ecx, Maximum_RMID_Range);
 868   PRINT_BIT_FIELD (Edx, L3CacheOccupancyMonitoring);
 869 }
 870
 871 /**
 872   Display CPUID_PLATFORM_QOS_ENFORCEMENT sub-leaf.
 873
 874 **/
 875 VOID
 876 CpuidPlatformQosEnforcementResidSubLeaf (
 877   VOID
 878   )
 879 {
 880   CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax;
 881   UINT32                                            Ebx;
 882   CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx;
 883   CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx;
 884
 885   AsmCpuidEx (
 886     CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF,
 887     &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32
 888     );
 889   Print (L"CPUID_PLATFORM_QOS_ENFORCEMENT (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF);
 890   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);
 891   PRINT_BIT_FIELD (Eax, CapacityLength);
 892   PRINT_VALUE     (Ebx, AllocationUnitBitMap);
 893   PRINT_BIT_FIELD (Ecx, CosUpdatesInfrequent);
 894   PRINT_BIT_FIELD (Ecx, CodeDataPrioritization);
 895   PRINT_BIT_FIELD (Edx, HighestCosNumber);
 896 }
 897
 898 /**
 899   Display CPUID_PLATFORM_QOS_ENFORCEMENT main leaf and sub-leaf.
 900
 901 **/
 902 VOID
 903 CpuidPlatformQosEnforcementMainLeaf (
 904   VOID
 905   )
 906 {
 907   CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX  Ebx;
 908
 909   if (CPUID_PLATFORM_QOS_ENFORCEMENT > gMaximumBasicFunction) {
 910     return;
 911   }
 912
 913   AsmCpuidEx (
 914     CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF,
 915     NULL, &Ebx.Uint32, NULL, NULL
 916     );
 917   Print (L"CPUID_PLATFORM_QOS_ENFORCEMENT (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF);
 918   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", 0, Ebx.Uint32, 0, 0);
 919   PRINT_BIT_FIELD (Ebx, L3CacheQosEnforcement);
 920
 921   CpuidPlatformQosEnforcementResidSubLeaf ();
 922 }
 923
 924 /**
 925   Display Sub-Leaf 0 Enumeration of Intel SGX Capabilities.
 926
 927 **/
 928 VOID
 929 CpuidEnumerationOfIntelSgxCapabilities0SubLeaf (
 930   VOID
 931   )
 932 {
 933   CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX  Eax;
 934   UINT32                                       Ebx;
 935   CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX  Edx;
 936
 937   AsmCpuidEx (
 938     CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,
 939     &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
 940     );
 941   Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF);
 942   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);
 943   PRINT_BIT_FIELD (Eax, SGX1);
 944   PRINT_BIT_FIELD (Eax, SGX2);
 945   PRINT_BIT_FIELD (Edx, MaxEnclaveSize_Not64);
 946   PRINT_BIT_FIELD (Edx, MaxEnclaveSize_64);
 947 }
 948
 949 /**
 950   Display Sub-Leaf 1 Enumeration of Intel SGX Capabilities.
 951
 952 **/
 953 VOID
 954 CpuidEnumerationOfIntelSgxCapabilities1SubLeaf (
 955   VOID
 956   )
 957 {
 958   UINT32                                       Eax;
 959   UINT32                                       Ebx;
 960   UINT32                                       Ecx;
 961   UINT32                                       Edx;
 962
 963   AsmCpuidEx (
 964     CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,
 965     &Eax, &Ebx, &Ecx, &Edx
 966     );
 967   Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF);
 968   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, Ebx, Ecx, Edx);
 969 }
 970
 971 /**
 972   Display Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.
 973
 974 **/
 975 VOID
 976 CpuidEnumerationOfIntelSgxResourcesSubLeaf (
 977   VOID
 978   )
 979 {
 980   CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX  Eax;
 981   CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX  Ebx;
 982   CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX  Ecx;
 983   CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX  Edx;
 984   UINT32                                               SubLeaf;
 985
 986   SubLeaf = CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF;
 987   do {
 988     AsmCpuidEx (
 989       CPUID_INTEL_SGX, SubLeaf,
 990       &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
 991       );
 992     if (Eax.Bits.SubLeafType == 0x1) {
 993       Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, SubLeaf);
 994       Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
 995       PRINT_BIT_FIELD (Eax, SubLeafType);
 996       PRINT_BIT_FIELD (Eax, LowAddressOfEpcSection);
 997       PRINT_BIT_FIELD (Ebx, HighAddressOfEpcSection);
 998       PRINT_BIT_FIELD (Ecx, EpcSection);
 999       PRINT_BIT_FIELD (Ecx, LowSizeOfEpcSection);
1000       PRINT_BIT_FIELD (Edx, HighSizeOfEpcSection);
1001     }
1002     SubLeaf++;
1003   } while (Eax.Bits.SubLeafType == 0x1);
1004 }
1005
1006 /**
1007   Display Intel SGX Resource Enumeration.
1008
1009 **/
1010 VOID
1011 CpuidEnumerationOfIntelSgx (
1012   VOID
1013   )
1014 {
1015   CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX  Ebx;
1016
1017   if (CPUID_INTEL_SGX > gMaximumBasicFunction) {
1018     return;
1019   }
1020
1021   AsmCpuidEx (
1022     CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
1023     CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
1024     NULL, &Ebx.Uint32, NULL, NULL
1025     );
1026   if (Ebx.Bits.SGX != 1) {
1027     //
1028     // Only if CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor has support
1029     // for Intel SGX.
1030     //
1031     return;
1032   }
1033
1034   CpuidEnumerationOfIntelSgxCapabilities0SubLeaf ();
1035   CpuidEnumerationOfIntelSgxCapabilities1SubLeaf ();
1036   CpuidEnumerationOfIntelSgxResourcesSubLeaf ();
1037 }
1038
1039 /**
1040   Display CPUID_INTEL_PROCESSOR_TRACE sub-leafs.
1041
1042   @param[in] MaximumSubLeaf  Maximum sub-leaf index for CPUID_INTEL_PROCESSOR_TRACE.
1043
1044 **/
1045 VOID
1046 CpuidIntelProcessorTraceSubLeaf (
1047   UINT32  MaximumSubLeaf
1048   )
1049 {
1050   UINT32                                    SubLeaf;
1051   CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX  Eax;
1052   CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX  Ebx;
1053
1054   for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {
1055     AsmCpuidEx (
1056       CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,
1057       &Eax.Uint32, &Ebx.Uint32, NULL, NULL
1058       );
1059     Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, SubLeaf);
1060     Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, 0);
1061     PRINT_BIT_FIELD (Eax, ConfigurableAddressRanges);
1062     PRINT_BIT_FIELD (Eax, MtcPeriodEncodings);
1063     PRINT_BIT_FIELD (Ebx, CycleThresholdEncodings);
1064     PRINT_BIT_FIELD (Ebx, PsbFrequencyEncodings);
1065   }
1066 }
1067
1068 /**
1069   Display CPUID_INTEL_PROCESSOR_TRACE main leaf and sub-leafs.
1070
1071 **/
1072 VOID
1073 CpuidIntelProcessorTraceMainLeaf (
1074   VOID
1075   )
1076 {
1077   UINT32                                     Eax;
1078   CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX  Ebx;
1079   CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX  Ecx;
1080
1081   if (CPUID_INTEL_PROCESSOR_TRACE > gMaximumBasicFunction) {
1082     return;
1083   }
1084
1085   AsmCpuidEx (
1086     CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
1087     &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL
1088     );
1089   Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF);
1090   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0);
1091   PRINT_VALUE     (Eax, MaximumSubLeaf);
1092   PRINT_BIT_FIELD (Ebx, Cr3Filter);
1093   PRINT_BIT_FIELD (Ebx, ConfigurablePsb);
1094   PRINT_BIT_FIELD (Ebx, IpTraceStopFiltering);
1095   PRINT_BIT_FIELD (Ebx, Mtc);
1096   PRINT_BIT_FIELD (Ecx, RTIT);
1097   PRINT_BIT_FIELD (Ecx, ToPA);
1098   PRINT_BIT_FIELD (Ecx, SingleRangeOutput);
1099   PRINT_BIT_FIELD (Ecx, TraceTransportSubsystem);
1100   PRINT_BIT_FIELD (Ecx, LIP);
1101
1102   CpuidIntelProcessorTraceSubLeaf (Eax);
1103 }
1104
1105 /**
1106   Display CPUID_TIME_STAMP_COUNTER leaf.
1107
1108 **/
1109 VOID
1110 CpuidTimeStampCounter (
1111   VOID
1112   )
1113 {
1114   UINT32  Eax;
1115   UINT32  Ebx;
1116
1117   if (CPUID_TIME_STAMP_COUNTER > gMaximumBasicFunction) {
1118     return;
1119   }
1120
1121   AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL);
1122   Print (L"CPUID_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_TIME_STAMP_COUNTER);
1123   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, Ebx, 0, 0);
1124 }
1125
1126 /**
1127   Display CPUID_PROCESSOR_FREQUENCY leaf.
1128
1129 **/
1130 VOID
1131 CpuidProcessorFrequency (
1132   VOID
1133   )
1134 {
1135   CPUID_PROCESSOR_FREQUENCY_EAX  Eax;
1136   CPUID_PROCESSOR_FREQUENCY_EBX  Ebx;
1137   CPUID_PROCESSOR_FREQUENCY_ECX  Ecx;
1138
1139   if (CPUID_PROCESSOR_FREQUENCY > gMaximumBasicFunction) {
1140     return;
1141   }
1142
1143   AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
1144   Print (L"CPUID_PROCESSOR_FREQUENCY (Leaf %08x)\n", CPUID_PROCESSOR_FREQUENCY);
1145   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, 0);
1146   PRINT_BIT_FIELD (Eax, ProcessorBaseFrequency);
1147   PRINT_BIT_FIELD (Ebx, MaximumFrequency);
1148   PRINT_BIT_FIELD (Ecx, BusFrequency);
1149 }
1150
1151 /**
1152   Display CPUID_SOC_VENDOR sub-leafs that contain the SoC Vendor Brand String.
1153   Also display these sub-leafs as a single SoC Vendor Brand String.
1154
1155 **/
1156 VOID
1157 CpuidSocVendorBrandString (
1158   VOID
1159   )
1160 {
1161   CPUID_SOC_VENDOR_BRAND_STRING_DATA  Eax;
1162   CPUID_SOC_VENDOR_BRAND_STRING_DATA  Ebx;
1163   CPUID_SOC_VENDOR_BRAND_STRING_DATA  Ecx;
1164   CPUID_SOC_VENDOR_BRAND_STRING_DATA  Edx;
1165   //
1166   // Array to store brand string from 3 brand string leafs with
1167   // 4 32-bit brand string values per leaf and an extra value to
1168   // null terminate the string.
1169   //
1170   UINT32                              BrandString[3 * 4 + 1];
1171
1172   AsmCpuidEx (
1173     CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,
1174     &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
1175     );
1176   Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1);
1177   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
1178   BrandString[0] = Eax.Uint32;
1179   BrandString[1] = Ebx.Uint32;
1180   BrandString[2] = Ecx.Uint32;
1181   BrandString[3] = Edx.Uint32;
1182
1183   AsmCpuidEx (
1184     CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,
1185     &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
1186     );
1187   Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2);
1188   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
1189   BrandString[4] = Eax.Uint32;
1190   BrandString[5] = Ebx.Uint32;
1191   BrandString[6] = Ecx.Uint32;
1192   BrandString[7] = Edx.Uint32;
1193
1194   AsmCpuidEx (
1195     CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,
1196     &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
1197     );
1198   Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3);
1199   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
1200   BrandString[8]  = Eax.Uint32;
1201   BrandString[9]  = Ebx.Uint32;
1202   BrandString[10] = Ecx.Uint32;
1203   BrandString[11] = Edx.Uint32;
1204
1205   BrandString[12] = 0;
1206
1207   Print (L"Vendor Brand String = %a\n", (CHAR8 *)BrandString);
1208 }
1209
1210 /**
1211   Display CPUID_SOC_VENDOR main leaf and sub-leafs.
1212
1213 **/
1214 VOID
1215 CpuidSocVendor (
1216   VOID
1217   )
1218 {
1219   UINT32                          Eax;
1220   CPUID_SOC_VENDOR_MAIN_LEAF_EBX  Ebx;
1221   UINT32                          Ecx;
1222   UINT32                          Edx;
1223
1224   if (CPUID_SOC_VENDOR > gMaximumBasicFunction) {
1225     return;
1226   }
1227
1228   AsmCpuidEx (
1229     CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,
1230     &Eax, &Ebx.Uint32, &Ecx, &Edx
1231     );
1232   Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF);
1233   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx);
1234   if (Eax < 3) {
1235     Print (L"  Not Supported\n");
1236     return;
1237   }
1238   PRINT_VALUE     (Eax, MaxSOCID_Index);
1239   PRINT_BIT_FIELD (Ebx, SocVendorId);
1240   PRINT_BIT_FIELD (Ebx, IsVendorScheme);
1241   PRINT_VALUE     (Ecx, ProjectID);
1242   PRINT_VALUE     (Edx, SteppingID);
1243   CpuidSocVendorBrandString ();
1244 }
1245
1246 /**
1247   Display CPUID_EXTENDED_FUNCTION leaf.
1248
1249 **/
1250 VOID
1251 CpuidExtendedFunction (
1252   VOID
1253   )
1254 {
1255   UINT32  Eax;
1256
1257   AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
1258   Print (L"CPUID_EXTENDED_FUNCTION (Leaf %08x)\n", CPUID_EXTENDED_FUNCTION);
1259   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, 0, 0, 0);
1260   PRINT_VALUE     (Eax, MaximumExtendedFunction);
1261
1262   gMaximumExtendedFunction = Eax;
1263 }
1264
1265 /**
1266   Display CPUID_EXTENDED_CPU_SIG leaf.
1267
1268 **/
1269 VOID
1270 CpuidExtendedCpuSig (
1271   VOID
1272   )
1273 {
1274   UINT32                      Eax;
1275   CPUID_EXTENDED_CPU_SIG_ECX  Ecx;
1276   CPUID_EXTENDED_CPU_SIG_EDX  Edx;
1277
1278   if (CPUID_EXTENDED_CPU_SIG > gMaximumExtendedFunction) {
1279     return;
1280   }
1281
1282   AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);
1283   Print (L"CPUID_EXTENDED_CPU_SIG (Leaf %08x)\n", CPUID_EXTENDED_CPU_SIG);
1284   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, 0, Ecx.Uint32, Edx.Uint32);
1285   PRINT_BIT_FIELD (Ecx, LAHF_SAHF);
1286   PRINT_BIT_FIELD (Ecx, LZCNT);
1287   PRINT_BIT_FIELD (Ecx, PREFETCHW);
1288   PRINT_BIT_FIELD (Edx, SYSCALL_SYSRET);
1289   PRINT_BIT_FIELD (Edx, NX);
1290   PRINT_BIT_FIELD (Edx, Page1GB);
1291   PRINT_BIT_FIELD (Edx, RDTSCP);
1292   PRINT_BIT_FIELD (Edx, LM);
1293 }
1294
1295 /**
1296   Display CPUID_BRAND_STRING1, CPUID_BRAND_STRING2 and  CPUID_BRAND_STRING3
1297   leafs.  Also display these three leafs as a single brand string.
1298
1299 **/
1300 VOID
1301 CpuidProcessorBrandString (
1302   VOID
1303   )
1304 {
1305   CPUID_BRAND_STRING_DATA  Eax;
1306   CPUID_BRAND_STRING_DATA  Ebx;
1307   CPUID_BRAND_STRING_DATA  Ecx;
1308   CPUID_BRAND_STRING_DATA  Edx;
1309   //
1310   // Array to store brand string from 3 brand string leafs with
1311   // 4 32-bit brand string values per leaf and an extra value to
1312   // null terminate the string.
1313   //
1314   UINT32                   BrandString[3 * 4 + 1];
1315
1316   if (CPUID_BRAND_STRING1 <= gMaximumExtendedFunction) {
1317     AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
1318     Print (L"CPUID_BRAND_STRING1 (Leaf %08x)\n", CPUID_BRAND_STRING1);
1319     Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
1320     BrandString[0] = Eax.Uint32;
1321     BrandString[1] = Ebx.Uint32;
1322     BrandString[2] = Ecx.Uint32;
1323     BrandString[3] = Edx.Uint32;
1324   }
1325
1326   if (CPUID_BRAND_STRING2 <= gMaximumExtendedFunction) {
1327     AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
1328     Print (L"CPUID_BRAND_STRING2 (Leaf %08x)\n", CPUID_BRAND_STRING2);
1329     Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
1330     BrandString[4] = Eax.Uint32;
1331     BrandString[5] = Ebx.Uint32;
1332     BrandString[6] = Ecx.Uint32;
1333     BrandString[7] = Edx.Uint32;
1334   }
1335
1336   if (CPUID_BRAND_STRING3 <= gMaximumExtendedFunction) {
1337     AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
1338     Print (L"CPUID_BRAND_STRING3 (Leaf %08x)\n", CPUID_BRAND_STRING3);
1339     Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
1340     BrandString[8]  = Eax.Uint32;
1341     BrandString[9]  = Ebx.Uint32;
1342     BrandString[10] = Ecx.Uint32;
1343     BrandString[11] = Edx.Uint32;
1344   }
1345
1346   BrandString[12] = 0;
1347
1348   Print (L"Brand String = %a\n", (CHAR8 *)BrandString);
1349 }
1350
1351 /**
1352   Display CPUID_EXTENDED_CACHE_INFO leaf.
1353
1354 **/
1355 VOID
1356 CpuidExtendedCacheInfo (
1357   VOID
1358   )
1359 {
1360   CPUID_EXTENDED_CACHE_INFO_ECX  Ecx;
1361
1362   if (CPUID_EXTENDED_CACHE_INFO > gMaximumExtendedFunction) {
1363     return;
1364   }
1365
1366   AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);
1367   Print (L"CPUID_EXTENDED_CACHE_INFO (Leaf %08x)\n", CPUID_EXTENDED_CACHE_INFO);
1368   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", 0, 0, Ecx.Uint32, 0);
1369   PRINT_BIT_FIELD (Ecx, CacheLineSize);
1370   PRINT_BIT_FIELD (Ecx, L2Associativity);
1371   PRINT_BIT_FIELD (Ecx, CacheSize);
1372 }
1373
1374 /**
1375   Display CPUID_EXTENDED_TIME_STAMP_COUNTER leaf.
1376
1377 **/
1378 VOID
1379 CpuidExtendedTimeStampCounter (
1380   VOID
1381   )
1382 {
1383   CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX  Edx;
1384
1385   if (CPUID_EXTENDED_TIME_STAMP_COUNTER > gMaximumExtendedFunction) {
1386     return;
1387   }
1388
1389   AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);
1390   Print (L"CPUID_EXTENDED_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_EXTENDED_TIME_STAMP_COUNTER);
1391   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", 0, 0, 0, Edx.Uint32);
1392   PRINT_BIT_FIELD (Edx, InvariantTsc);
1393 }
1394
1395 /**
1396   Display CPUID_VIR_PHY_ADDRESS_SIZE leaf.
1397
1398 **/
1399 VOID
1400 CpuidVirPhyAddressSize (
1401   VOID
1402   )
1403 {
1404   CPUID_VIR_PHY_ADDRESS_SIZE_EAX  Eax;
1405
1406   if (CPUID_VIR_PHY_ADDRESS_SIZE > gMaximumExtendedFunction) {
1407     return;
1408   }
1409
1410   AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);
1411   Print (L"CPUID_VIR_PHY_ADDRESS_SIZE (Leaf %08x)\n", CPUID_VIR_PHY_ADDRESS_SIZE);
1412   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, 0, 0, 0);
1413   PRINT_BIT_FIELD (Eax, PhysicalAddressBits);
1414   PRINT_BIT_FIELD (Eax, LinearAddressBits);
1415 }
1416
1417 /**
1418   The user Entry Point for Application. The user code starts with this function
1419   as the real entry point for the application.
1420
1421   @param[in] ImageHandle    The firmware allocated handle for the EFI image.
1422   @param[in] SystemTable    A pointer to the EFI System Table.
1423
1424   @retval EFI_SUCCESS       The entry point is executed successfully.
1425   @retval other             Some error occurs when executing this entry point.
1426
1427 **/
1428 EFI_STATUS
1429 EFIAPI
1430 UefiMain (
1431   IN EFI_HANDLE        ImageHandle,
1432   IN EFI_SYSTEM_TABLE  *SystemTable
1433   )
1434 {
1435   Print (L"UEFI CPUID Version 0.5\n");
1436
1437   CpuidSignature ();
1438   CpuidVersionInfo ();
1439   CpuidCacheInfo ();
1440   CpuidSerialNumber ();
1441   CpuidCacheParams();
1442   CpuidMonitorMwait ();
1443   CpuidThermalPowerManagement ();
1444   CpuidStructuredExtendedFeatureFlags ();
1445   CpuidDirectCacheAccessInfo();
1446   CpuidArchitecturalPerformanceMonitoring ();
1447   CpuidExtendedTopology ();
1448   CpuidExtendedStateMainLeaf ();
1449   CpuidPlatformQosMonitoringEnumerationSubLeaf ();
1450   CpuidPlatformQosMonitoringCapabilitySubLeaf ();
1451   CpuidPlatformQosEnforcementMainLeaf ();
1452   CpuidEnumerationOfIntelSgx ();
1453   CpuidIntelProcessorTraceMainLeaf ();
1454   CpuidTimeStampCounter ();
1455   CpuidProcessorFrequency ();
1456   CpuidSocVendor ();
1457   CpuidExtendedFunction ();
1458   CpuidExtendedCpuSig ();
1459   CpuidProcessorBrandString ();
1460   CpuidExtendedCacheInfo ();
1461   CpuidExtendedTimeStampCounter ();
1462   CpuidVirPhyAddressSize ();
1463
1464   return EFI_SUCCESS;
1465 }