Add CPU DXE driver for IA32 & X64 processor architectures.
[mirror_edk2.git] / UefiCpuPkg / CpuDxe / CpuDxe.c
1 /** @file
2 CPU DXE Module.
3
4 Copyright (c) 2008 - 2009, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "CpuDxe.h"
16
17 //
18 // Global Variables
19 //
20 IA32_IDT_GATE_DESCRIPTOR gIdtTable[INTERRUPT_VECTOR_NUMBER] = { 0 };
21
22 EFI_CPU_INTERRUPT_HANDLER ExternalVectorTable[0x100];
23 BOOLEAN InterruptState = FALSE;
24 EFI_HANDLE mCpuHandle = NULL;
25 BOOLEAN mIsFlushingGCD;
26 UINT8 mDefaultMemoryType = MTRR_CACHE_WRITE_BACK;
27 UINT64 mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
28 UINT64 mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;
29
30 FIXED_MTRR mFixedMtrrTable[] = {
31 {
32 MTRR_LIB_IA32_MTRR_FIX64K_00000,
33 0,
34 0x10000
35 },
36 {
37 MTRR_LIB_IA32_MTRR_FIX16K_80000,
38 0x80000,
39 0x4000
40 },
41 {
42 MTRR_LIB_IA32_MTRR_FIX16K_A0000,
43 0xA0000,
44 0x4000
45 },
46 {
47 MTRR_LIB_IA32_MTRR_FIX4K_C0000,
48 0xC0000,
49 0x1000
50 },
51 {
52 MTRR_LIB_IA32_MTRR_FIX4K_C8000,
53 0xC8000,
54 0x1000
55 },
56 {
57 MTRR_LIB_IA32_MTRR_FIX4K_D0000,
58 0xD0000,
59 0x1000
60 },
61 {
62 MTRR_LIB_IA32_MTRR_FIX4K_D8000,
63 0xD8000,
64 0x1000
65 },
66 {
67 MTRR_LIB_IA32_MTRR_FIX4K_E0000,
68 0xE0000,
69 0x1000
70 },
71 {
72 MTRR_LIB_IA32_MTRR_FIX4K_E8000,
73 0xE8000,
74 0x1000
75 },
76 {
77 MTRR_LIB_IA32_MTRR_FIX4K_F0000,
78 0xF0000,
79 0x1000
80 },
81 {
82 MTRR_LIB_IA32_MTRR_FIX4K_F8000,
83 0xF8000,
84 0x1000
85 },
86 };
87
88
89 EFI_CPU_ARCH_PROTOCOL gCpu = {
90 CpuFlushCpuDataCache,
91 CpuEnableInterrupt,
92 CpuDisableInterrupt,
93 CpuGetInterruptState,
94 CpuInit,
95 CpuRegisterInterruptHandler,
96 CpuGetTimerValue,
97 CpuSetMemoryAttributes,
98 1, // NumberOfTimers
99 4 // DmaBufferAlignment
100 };
101
102 //
103 // Error code flag indicating whether or not an error code will be
104 // pushed on the stack if an exception occurs.
105 //
106 // 1 means an error code will be pushed, otherwise 0
107 //
108 // bit 0 - exception 0
109 // bit 1 - exception 1
110 // etc.
111 //
112 UINT32 mErrorCodeFlag = 0x00027d00;
113
114 //
115 // CPU Arch Protocol Functions
116 //
117
118
119 /**
120 Common exception handler.
121
122 @param InterruptType Exception type
123 @param SystemContext EFI_SYSTEM_CONTEXT
124
125 **/
126 VOID
127 EFIAPI
128 CommonExceptionHandler (
129 IN EFI_EXCEPTION_TYPE InterruptType,
130 IN EFI_SYSTEM_CONTEXT SystemContext
131 )
132 {
133 #if defined (MDE_CPU_IA32)
134 DEBUG ((
135 EFI_D_ERROR,
136 "!!!! IA32 Exception Type - %08x !!!!\n",
137 InterruptType
138 ));
139 if (mErrorCodeFlag & (1 << InterruptType)) {
140 DEBUG ((
141 EFI_D_ERROR,
142 "ExceptionData - %08x\n",
143 SystemContext.SystemContextIa32->ExceptionData
144 ));
145 }
146 DEBUG ((
147 EFI_D_ERROR,
148 "CS - %04x, EIP - %08x, EFL - %08x, SS - %04x\n",
149 SystemContext.SystemContextIa32->Cs,
150 SystemContext.SystemContextIa32->Eip,
151 SystemContext.SystemContextIa32->Eflags,
152 SystemContext.SystemContextIa32->Ss
153 ));
154 DEBUG ((
155 EFI_D_ERROR,
156 "DS - %04x, ES - %04x, FS - %04x, GS - %04x\n",
157 SystemContext.SystemContextIa32->Ds,
158 SystemContext.SystemContextIa32->Es,
159 SystemContext.SystemContextIa32->Fs,
160 SystemContext.SystemContextIa32->Gs
161 ));
162 DEBUG ((
163 EFI_D_ERROR,
164 "EAX - %08x, EBX - %08x, ECX - %08x, EDX - %08x\n",
165 SystemContext.SystemContextIa32->Eax,
166 SystemContext.SystemContextIa32->Ebx,
167 SystemContext.SystemContextIa32->Ecx,
168 SystemContext.SystemContextIa32->Edx
169 ));
170 DEBUG ((
171 EFI_D_ERROR,
172 "ESP - %08x, EBP - %08x, ESI - %08x, EDI - %08x\n",
173 SystemContext.SystemContextIa32->Esp,
174 SystemContext.SystemContextIa32->Ebp,
175 SystemContext.SystemContextIa32->Esi,
176 SystemContext.SystemContextIa32->Edi
177 ));
178 DEBUG ((
179 EFI_D_ERROR,
180 "GDT - %08x LIM - %04x, IDT - %08x LIM - %04x\n",
181 SystemContext.SystemContextIa32->Gdtr[0],
182 SystemContext.SystemContextIa32->Gdtr[1],
183 SystemContext.SystemContextIa32->Idtr[0],
184 SystemContext.SystemContextIa32->Idtr[1]
185 ));
186 DEBUG ((
187 EFI_D_ERROR,
188 "LDT - %08x, TR - %08x\n",
189 SystemContext.SystemContextIa32->Ldtr,
190 SystemContext.SystemContextIa32->Tr
191 ));
192 DEBUG ((
193 EFI_D_ERROR,
194 "CR0 - %08x, CR2 - %08x, CR3 - %08x, CR4 - %08x\n",
195 SystemContext.SystemContextIa32->Cr0,
196 SystemContext.SystemContextIa32->Cr2,
197 SystemContext.SystemContextIa32->Cr3,
198 SystemContext.SystemContextIa32->Cr4
199 ));
200 DEBUG ((
201 EFI_D_ERROR,
202 "DR0 - %08x, DR1 - %08x, DR2 - %08x, DR3 - %08x\n",
203 SystemContext.SystemContextIa32->Dr0,
204 SystemContext.SystemContextIa32->Dr1,
205 SystemContext.SystemContextIa32->Dr2,
206 SystemContext.SystemContextIa32->Dr3
207 ));
208 DEBUG ((
209 EFI_D_ERROR,
210 "DR6 - %08x, DR7 - %08x\n",
211 SystemContext.SystemContextIa32->Dr6,
212 SystemContext.SystemContextIa32->Dr7
213 ));
214 #elif defined (MDE_CPU_X64)
215 DEBUG ((
216 EFI_D_ERROR,
217 "!!!! X64 Exception Type - %016lx !!!!\n",
218 (UINT64)InterruptType
219 ));
220 if (mErrorCodeFlag & (1 << InterruptType)) {
221 DEBUG ((
222 EFI_D_ERROR,
223 "ExceptionData - %016lx\n",
224 SystemContext.SystemContextX64->ExceptionData
225 ));
226 }
227 DEBUG ((
228 EFI_D_ERROR,
229 "RIP - %016lx, RFL - %016lx\n",
230 SystemContext.SystemContextX64->Rip,
231 SystemContext.SystemContextX64->Rflags
232 ));
233 DEBUG ((
234 EFI_D_ERROR,
235 "RAX - %016lx, RCX - %016lx, RDX - %016lx\n",
236 SystemContext.SystemContextX64->Rax,
237 SystemContext.SystemContextX64->Rcx,
238 SystemContext.SystemContextX64->Rdx
239 ));
240 DEBUG ((
241 EFI_D_ERROR,
242 "RBX - %016lx, RSP - %016lx, RBP - %016lx\n",
243 SystemContext.SystemContextX64->Rbx,
244 SystemContext.SystemContextX64->Rsp,
245 SystemContext.SystemContextX64->Rbp
246 ));
247 DEBUG ((
248 EFI_D_ERROR,
249 "RSI - %016lx, RDI - %016lx\n",
250 SystemContext.SystemContextX64->Rsi,
251 SystemContext.SystemContextX64->Rdi
252 ));
253 DEBUG ((
254 EFI_D_ERROR,
255 "R8 - %016lx, R9 - %016lx, R10 - %016lx\n",
256 SystemContext.SystemContextX64->R8,
257 SystemContext.SystemContextX64->R9,
258 SystemContext.SystemContextX64->R10
259 ));
260 DEBUG ((
261 EFI_D_ERROR,
262 "R11 - %016lx, R12 - %016lx, R13 - %016lx\n",
263 SystemContext.SystemContextX64->R11,
264 SystemContext.SystemContextX64->R12,
265 SystemContext.SystemContextX64->R13
266 ));
267 DEBUG ((
268 EFI_D_ERROR,
269 "R14 - %016lx, R15 - %016lx\n",
270 SystemContext.SystemContextX64->R14,
271 SystemContext.SystemContextX64->R15
272 ));
273 DEBUG ((
274 EFI_D_ERROR,
275 "CS - %04lx, DS - %04lx, ES - %04lx, FS - %04lx, GS - %04lx, SS - %04lx\n",
276 SystemContext.SystemContextX64->Cs,
277 SystemContext.SystemContextX64->Ds,
278 SystemContext.SystemContextX64->Es,
279 SystemContext.SystemContextX64->Fs,
280 SystemContext.SystemContextX64->Gs,
281 SystemContext.SystemContextX64->Ss
282 ));
283 DEBUG ((
284 EFI_D_ERROR,
285 "GDT - %016lx; %04lx, IDT - %016lx; %04lx\n",
286 SystemContext.SystemContextX64->Gdtr[0],
287 SystemContext.SystemContextX64->Gdtr[1],
288 SystemContext.SystemContextX64->Idtr[0],
289 SystemContext.SystemContextX64->Idtr[1]
290 ));
291 DEBUG ((
292 EFI_D_ERROR,
293 "LDT - %016lx, TR - %016lx\n",
294 SystemContext.SystemContextX64->Ldtr,
295 SystemContext.SystemContextX64->Tr
296 ));
297 DEBUG ((
298 EFI_D_ERROR,
299 "CR0 - %016lx, CR2 - %016lx, CR3 - %016lx\n",
300 SystemContext.SystemContextX64->Cr0,
301 SystemContext.SystemContextX64->Cr2,
302 SystemContext.SystemContextX64->Cr3
303 ));
304 DEBUG ((
305 EFI_D_ERROR,
306 "CR4 - %016lx, CR8 - %016lx\n",
307 SystemContext.SystemContextX64->Cr4,
308 SystemContext.SystemContextX64->Cr8
309 ));
310 DEBUG ((
311 EFI_D_ERROR,
312 "DR0 - %016lx, DR1 - %016lx, DR2 - %016lx\n",
313 SystemContext.SystemContextX64->Dr0,
314 SystemContext.SystemContextX64->Dr1,
315 SystemContext.SystemContextX64->Dr2
316 ));
317 DEBUG ((
318 EFI_D_ERROR,
319 "DR3 - %016lx, DR6 - %016lx, DR7 - %016lx\n",
320 SystemContext.SystemContextX64->Dr3,
321 SystemContext.SystemContextX64->Dr6,
322 SystemContext.SystemContextX64->Dr7
323 ));
324 #else
325 #error CPU type not supported for exception information dump!
326 #endif
327
328 //
329 // Hang the system with CpuSleep so the processor will enter a lower power
330 // state.
331 //
332 while (TRUE) {
333 CpuSleep ();
334 };
335 }
336
337
338 /**
339 Flush CPU data cache. If the instruction cache is fully coherent
340 with all DMA operations then function can just return EFI_SUCCESS.
341
342 @param This Protocol instance structure
343 @param Start Physical address to start flushing from.
344 @param Length Number of bytes to flush. Round up to chipset
345 granularity.
346 @param FlushType Specifies the type of flush operation to perform.
347
348 @retval EFI_SUCCESS If cache was flushed
349 @retval EFI_UNSUPPORTED If flush type is not supported.
350 @retval EFI_DEVICE_ERROR If requested range could not be flushed.
351
352 **/
353 EFI_STATUS
354 EFIAPI
355 CpuFlushCpuDataCache (
356 IN EFI_CPU_ARCH_PROTOCOL *This,
357 IN EFI_PHYSICAL_ADDRESS Start,
358 IN UINT64 Length,
359 IN EFI_CPU_FLUSH_TYPE FlushType
360 )
361 {
362 if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {
363 AsmWbinvd ();
364 return EFI_SUCCESS;
365 } else if (FlushType == EfiCpuFlushTypeInvalidate) {
366 AsmInvd ();
367 return EFI_SUCCESS;
368 } else {
369 return EFI_UNSUPPORTED;
370 }
371 }
372
373
374 /**
375 Enables CPU interrupts.
376
377 @param This Protocol instance structure
378
379 @retval EFI_SUCCESS If interrupts were enabled in the CPU
380 @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
381
382 **/
383 EFI_STATUS
384 EFIAPI
385 CpuEnableInterrupt (
386 IN EFI_CPU_ARCH_PROTOCOL *This
387 )
388 {
389 EnableInterrupts ();
390
391 InterruptState = TRUE;
392 return EFI_SUCCESS;
393 }
394
395
396 /**
397 Disables CPU interrupts.
398
399 @param This Protocol instance structure
400
401 @retval EFI_SUCCESS If interrupts were disabled in the CPU.
402 @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
403
404 **/
405 EFI_STATUS
406 EFIAPI
407 CpuDisableInterrupt (
408 IN EFI_CPU_ARCH_PROTOCOL *This
409 )
410 {
411 DisableInterrupts ();
412
413 InterruptState = FALSE;
414 return EFI_SUCCESS;
415 }
416
417
418 /**
419 Return the state of interrupts.
420
421 @param This Protocol instance structure
422 @param State Pointer to the CPU's current interrupt state
423
424 @retval EFI_SUCCESS If interrupts were disabled in the CPU.
425 @retval EFI_INVALID_PARAMETER State is NULL.
426
427 **/
428 EFI_STATUS
429 EFIAPI
430 CpuGetInterruptState (
431 IN EFI_CPU_ARCH_PROTOCOL *This,
432 OUT BOOLEAN *State
433 )
434 {
435 if (State == NULL) {
436 return EFI_INVALID_PARAMETER;
437 }
438
439 *State = InterruptState;
440 return EFI_SUCCESS;
441 }
442
443
444 /**
445 Generates an INIT to the CPU.
446
447 @param This Protocol instance structure
448 @param InitType Type of CPU INIT to perform
449
450 @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
451 seen.
452 @retval EFI_DEVICE_ERROR If CPU INIT failed.
453 @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
454
455 **/
456 EFI_STATUS
457 EFIAPI
458 CpuInit (
459 IN EFI_CPU_ARCH_PROTOCOL *This,
460 IN EFI_CPU_INIT_TYPE InitType
461 )
462 {
463 return EFI_UNSUPPORTED;
464 }
465
466
467 /**
468 Registers a function to be called from the CPU interrupt handler.
469
470 @param This Protocol instance structure
471 @param InterruptType Defines which interrupt to hook. IA-32
472 valid range is 0x00 through 0xFF
473 @param InterruptHandler A pointer to a function of type
474 EFI_CPU_INTERRUPT_HANDLER that is called
475 when a processor interrupt occurs. A null
476 pointer is an error condition.
477
478 @retval EFI_SUCCESS If handler installed or uninstalled.
479 @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
480 for InterruptType was previously installed.
481 @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
482 InterruptType was not previously installed.
483 @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
484 is not supported.
485
486 **/
487 EFI_STATUS
488 EFIAPI
489 CpuRegisterInterruptHandler (
490 IN EFI_CPU_ARCH_PROTOCOL *This,
491 IN EFI_EXCEPTION_TYPE InterruptType,
492 IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
493 )
494 {
495 if (InterruptType < 0 || InterruptType > 0xff) {
496 return EFI_UNSUPPORTED;
497 }
498
499 if (InterruptHandler == NULL && ExternalVectorTable[InterruptType] == NULL) {
500 return EFI_INVALID_PARAMETER;
501 }
502
503 if (InterruptHandler != NULL && ExternalVectorTable[InterruptType] != NULL) {
504 return EFI_ALREADY_STARTED;
505 }
506
507 ExternalVectorTable[InterruptType] = InterruptHandler;
508 return EFI_SUCCESS;
509 }
510
511
512 /**
513 Returns a timer value from one of the CPU's internal timers. There is no
514 inherent time interval between ticks but is a function of the CPU frequency.
515
516 @param This - Protocol instance structure.
517 @param TimerIndex - Specifies which CPU timer is requested.
518 @param TimerValue - Pointer to the returned timer value.
519 @param TimerPeriod - A pointer to the amount of time that passes
520 in femtoseconds (10-15) for each increment
521 of TimerValue. If TimerValue does not
522 increment at a predictable rate, then 0 is
523 returned. The amount of time that has
524 passed between two calls to GetTimerValue()
525 can be calculated with the formula
526 (TimerValue2 - TimerValue1) * TimerPeriod.
527 This parameter is optional and may be NULL.
528
529 @retval EFI_SUCCESS - If the CPU timer count was returned.
530 @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
531 @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
532 @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
533
534 **/
535 EFI_STATUS
536 EFIAPI
537 CpuGetTimerValue (
538 IN EFI_CPU_ARCH_PROTOCOL *This,
539 IN UINT32 TimerIndex,
540 OUT UINT64 *TimerValue,
541 OUT UINT64 *TimerPeriod OPTIONAL
542 )
543 {
544 if (TimerValue == NULL) {
545 return EFI_INVALID_PARAMETER;
546 }
547
548 if (TimerIndex != 0) {
549 return EFI_INVALID_PARAMETER;
550 }
551
552 *TimerValue = AsmReadTsc ();
553
554 if (TimerPeriod != NULL) {
555 //
556 // BugBug: Hard coded. Don't know how to do this generically
557 //
558 *TimerPeriod = 1000000000;
559 }
560
561 return EFI_SUCCESS;
562 }
563
564
565 /**
566 Set memory cacheability attributes for given range of memeory.
567
568 @param This Protocol instance structure
569 @param BaseAddress Specifies the start address of the
570 memory range
571 @param Length Specifies the length of the memory range
572 @param Attributes The memory cacheability for the memory range
573
574 @retval EFI_SUCCESS If the cacheability of that memory range is
575 set successfully
576 @retval EFI_UNSUPPORTED If the desired operation cannot be done
577 @retval EFI_INVALID_PARAMETER The input parameter is not correct,
578 such as Length = 0
579
580 **/
581 EFI_STATUS
582 EFIAPI
583 CpuSetMemoryAttributes (
584 IN EFI_CPU_ARCH_PROTOCOL *This,
585 IN EFI_PHYSICAL_ADDRESS BaseAddress,
586 IN UINT64 Length,
587 IN UINT64 Attributes
588 )
589 {
590 RETURN_STATUS Status;
591 MTRR_MEMORY_CACHE_TYPE CacheType;
592
593 DEBUG((EFI_D_ERROR, "CpuAp: SetMemorySpaceAttributes(BA=%08x, Len=%08x, Attr=%08x)\n", BaseAddress, Length, Attributes));
594
595 //
596 // If this function is called because GCD SetMemorySpaceAttributes () is called
597 // by RefreshGcdMemoryAttributes (), then we are just synchronzing GCD memory
598 // map with MTRR values. So there is no need to modify MTRRs, just return immediately
599 // to avoid unnecessary computing.
600 //
601 if (mIsFlushingGCD) {
602 DEBUG((EFI_D_ERROR, " Flushing GCD\n"));
603 return EFI_SUCCESS;
604 }
605
606 switch (Attributes) {
607 case EFI_MEMORY_UC:
608 CacheType = CacheUncacheable;
609 break;
610
611 case EFI_MEMORY_WC:
612 CacheType = CacheWriteCombining;
613 break;
614
615 case EFI_MEMORY_WT:
616 CacheType = CacheWriteThrough;
617 break;
618
619 case EFI_MEMORY_WP:
620 CacheType = CacheWriteProtected;
621 break;
622
623 case EFI_MEMORY_WB:
624 CacheType = CacheWriteBack;
625 break;
626
627 default:
628 return EFI_UNSUPPORTED;
629 }
630 //
631 // call MTRR libary function
632 //
633 DEBUG((EFI_D_ERROR, " MtrrSetMemoryAttribute()\n"));
634 Status = MtrrSetMemoryAttribute(
635 BaseAddress,
636 Length,
637 CacheType
638 );
639
640 MtrrDebugPrintAllMtrrs ();
641
642 return (EFI_STATUS) Status;
643 }
644
645 /**
646 Initializes the valid bits mask and valid address mask for MTRRs.
647
648 This function initializes the valid bits mask and valid address mask for MTRRs.
649
650 **/
651 VOID
652 InitializeMtrrMask (
653 VOID
654 )
655 {
656 UINT32 RegEax;
657 UINT8 PhysicalAddressBits;
658
659 AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
660
661 if (RegEax >= 0x80000008) {
662 AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
663
664 PhysicalAddressBits = (UINT8) RegEax;
665
666 mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;
667 mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;
668 } else {
669 mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;
670 mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
671 }
672 }
673
674 /**
675 Gets GCD Mem Space type from MTRR Type
676
677 This function gets GCD Mem Space type from MTRR Type
678
679 @param MtrrAttribute MTRR memory type
680
681 @return GCD Mem Space type
682
683 **/
684 UINT64
685 GetMemorySpaceAttributeFromMtrrType (
686 IN UINT8 MtrrAttributes
687 )
688 {
689 switch (MtrrAttributes) {
690 case MTRR_CACHE_UNCACHEABLE:
691 return EFI_MEMORY_UC;
692 case MTRR_CACHE_WRITE_COMBINING:
693 return EFI_MEMORY_WC;
694 case MTRR_CACHE_WRITE_THROUGH:
695 return EFI_MEMORY_WT;
696 case MTRR_CACHE_WRITE_PROTECTED:
697 return EFI_MEMORY_WP;
698 case MTRR_CACHE_WRITE_BACK:
699 return EFI_MEMORY_WB;
700 default:
701 return 0;
702 }
703 }
704
705 /**
706 Searches memory descriptors covered by given memory range.
707
708 This function searches into the Gcd Memory Space for descriptors
709 (from StartIndex to EndIndex) that contains the memory range
710 specified by BaseAddress and Length.
711
712 @param MemorySpaceMap Gcd Memory Space Map as array.
713 @param NumberOfDescriptors Number of descriptors in map.
714 @param BaseAddress BaseAddress for the requested range.
715 @param Length Length for the requested range.
716 @param StartIndex Start index into the Gcd Memory Space Map.
717 @param EndIndex End index into the Gcd Memory Space Map.
718
719 @retval EFI_SUCCESS Search successfully.
720 @retval EFI_NOT_FOUND The requested descriptors does not exist.
721
722 **/
723 EFI_STATUS
724 SearchGcdMemorySpaces (
725 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
726 IN UINTN NumberOfDescriptors,
727 IN EFI_PHYSICAL_ADDRESS BaseAddress,
728 IN UINT64 Length,
729 OUT UINTN *StartIndex,
730 OUT UINTN *EndIndex
731 )
732 {
733 UINTN Index;
734
735 *StartIndex = 0;
736 *EndIndex = 0;
737 for (Index = 0; Index < NumberOfDescriptors; Index++) {
738 if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&
739 BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
740 *StartIndex = Index;
741 }
742 if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&
743 BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
744 *EndIndex = Index;
745 return EFI_SUCCESS;
746 }
747 }
748 return EFI_NOT_FOUND;
749 }
750
751 /**
752 Sets the attributes for a specified range in Gcd Memory Space Map.
753
754 This function sets the attributes for a specified range in
755 Gcd Memory Space Map.
756
757 @param MemorySpaceMap Gcd Memory Space Map as array
758 @param NumberOfDescriptors Number of descriptors in map
759 @param BaseAddress BaseAddress for the range
760 @param Length Length for the range
761 @param Attributes Attributes to set
762
763 @retval EFI_SUCCESS Memory attributes set successfully
764 @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space
765
766 **/
767 EFI_STATUS
768 SetGcdMemorySpaceAttributes (
769 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
770 IN UINTN NumberOfDescriptors,
771 IN EFI_PHYSICAL_ADDRESS BaseAddress,
772 IN UINT64 Length,
773 IN UINT64 Attributes
774 )
775 {
776 EFI_STATUS Status;
777 UINTN Index;
778 UINTN StartIndex;
779 UINTN EndIndex;
780 EFI_PHYSICAL_ADDRESS RegionStart;
781 UINT64 RegionLength;
782
783 //
784 // Get all memory descriptors covered by the memory range
785 //
786 Status = SearchGcdMemorySpaces (
787 MemorySpaceMap,
788 NumberOfDescriptors,
789 BaseAddress,
790 Length,
791 &StartIndex,
792 &EndIndex
793 );
794 if (EFI_ERROR (Status)) {
795 return Status;
796 }
797
798 //
799 // Go through all related descriptors and set attributes accordingly
800 //
801 for (Index = StartIndex; Index <= EndIndex; Index++) {
802 if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
803 continue;
804 }
805 //
806 // Calculate the start and end address of the overlapping range
807 //
808 if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {
809 RegionStart = BaseAddress;
810 } else {
811 RegionStart = MemorySpaceMap[Index].BaseAddress;
812 }
813 if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
814 RegionLength = BaseAddress + Length - RegionStart;
815 } else {
816 RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
817 }
818 //
819 // Set memory attributes according to MTRR attribute and the original attribute of descriptor
820 //
821 gDS->SetMemorySpaceAttributes (
822 RegionStart,
823 RegionLength,
824 (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
825 );
826 }
827
828 return EFI_SUCCESS;
829 }
830
831
832 /**
833 Refreshes the GCD Memory Space attributes according to MTRRs.
834
835 This function refreshes the GCD Memory Space attributes according to MTRRs.
836
837 **/
838 VOID
839 RefreshGcdMemoryAttributes (
840 VOID
841 )
842 {
843 EFI_STATUS Status;
844 UINTN Index;
845 UINTN SubIndex;
846 UINT64 RegValue;
847 EFI_PHYSICAL_ADDRESS BaseAddress;
848 UINT64 Length;
849 UINT64 Attributes;
850 UINT64 CurrentAttributes;
851 UINT8 MtrrType;
852 UINTN NumberOfDescriptors;
853 EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
854 UINT64 DefaultAttributes;
855 VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
856 MTRR_FIXED_SETTINGS MtrrFixedSettings;
857
858 // mIsFlushingGCD = TRUE;
859 mIsFlushingGCD = FALSE;
860 MemorySpaceMap = NULL;
861
862 //
863 // Initialize the valid bits mask and valid address mask for MTRRs
864 //
865 InitializeMtrrMask ();
866
867 //
868 // Get the memory attribute of variable MTRRs
869 //
870 MtrrGetMemoryAttributeInVariableMtrr (
871 mValidMtrrBitsMask,
872 mValidMtrrAddressMask,
873 VariableMtrr
874 );
875
876 //
877 // Get the memory space map from GCD
878 //
879 Status = gDS->GetMemorySpaceMap (
880 &NumberOfDescriptors,
881 &MemorySpaceMap
882 );
883 ASSERT_EFI_ERROR (Status);
884
885 DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (mDefaultMemoryType);
886
887 //
888 // Set default attributes to all spaces.
889 //
890 for (Index = 0; Index < NumberOfDescriptors; Index++) {
891 if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
892 continue;
893 }
894 gDS->SetMemorySpaceAttributes (
895 MemorySpaceMap[Index].BaseAddress,
896 MemorySpaceMap[Index].Length,
897 (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) |
898 (MemorySpaceMap[Index].Capabilities & DefaultAttributes)
899 );
900 }
901
902 //
903 // Go for variable MTRRs with WB attribute
904 //
905 for (Index = 0; Index < FIRMWARE_VARIABLE_MTRR_NUMBER; Index++) {
906 if (VariableMtrr[Index].Valid &&
907 VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) {
908 SetGcdMemorySpaceAttributes (
909 MemorySpaceMap,
910 NumberOfDescriptors,
911 VariableMtrr[Index].BaseAddress,
912 VariableMtrr[Index].Length,
913 EFI_MEMORY_WB
914 );
915 }
916 }
917 //
918 // Go for variable MTRRs with Non-WB attribute
919 //
920 for (Index = 0; Index < FIRMWARE_VARIABLE_MTRR_NUMBER; Index++) {
921 if (VariableMtrr[Index].Valid &&
922 VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK) {
923 Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8) VariableMtrr[Index].Type);
924 SetGcdMemorySpaceAttributes (
925 MemorySpaceMap,
926 NumberOfDescriptors,
927 VariableMtrr[Index].BaseAddress,
928 VariableMtrr[Index].Length,
929 Attributes
930 );
931 }
932 }
933
934 //
935 // Go for fixed MTRRs
936 //
937 Attributes = 0;
938 BaseAddress = 0;
939 Length = 0;
940 MtrrGetFixedMtrr (&MtrrFixedSettings);
941 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {
942 RegValue = MtrrFixedSettings.Mtrr[Index];
943 //
944 // Check for continuous fixed MTRR sections
945 //
946 for (SubIndex = 0; SubIndex < 8; SubIndex++) {
947 MtrrType = (UINT8) RShiftU64 (RegValue, SubIndex * 8);
948 CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType);
949 if (Length == 0) {
950 //
951 // A new MTRR attribute begins
952 //
953 Attributes = CurrentAttributes;
954 } else {
955 //
956 // If fixed MTRR attribute changed, then set memory attribute for previous atrribute
957 //
958 if (CurrentAttributes != Attributes) {
959 SetGcdMemorySpaceAttributes (
960 MemorySpaceMap,
961 NumberOfDescriptors,
962 BaseAddress,
963 Length,
964 Attributes
965 );
966 BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex;
967 Length = 0;
968 Attributes = CurrentAttributes;
969 }
970 }
971 Length += mFixedMtrrTable[Index].Length;
972 }
973 }
974 //
975 // Handle the last fixed MTRR region
976 //
977 SetGcdMemorySpaceAttributes (
978 MemorySpaceMap,
979 NumberOfDescriptors,
980 BaseAddress,
981 Length,
982 Attributes
983 );
984
985 //
986 // Free memory space map allocated by GCD service GetMemorySpaceMap ()
987 //
988 if (MemorySpaceMap != NULL) {
989 FreePool (MemorySpaceMap);
990 }
991
992 mIsFlushingGCD = FALSE;
993 }
994
995
996 /**
997 Initialize Interrupt Descriptor Table for interrupt handling.
998
999 **/
1000 STATIC
1001 VOID
1002 InitInterruptDescriptorTable (
1003 VOID
1004 )
1005 {
1006 EFI_STATUS Status;
1007 VOID *IdtPtrAlignmentBuffer;
1008 IA32_DESCRIPTOR *IdtPtr;
1009 UINTN Index;
1010 UINTN CurrentHandler;
1011
1012 SetMem (ExternalVectorTable, sizeof(ExternalVectorTable), 0);
1013
1014 //
1015 // Intialize IDT
1016 //
1017 CurrentHandler = (UINTN)AsmIdtVector00;
1018 for (Index = 0; Index < INTERRUPT_VECTOR_NUMBER; Index ++, CurrentHandler += 0x08) {
1019 gIdtTable[Index].Bits.OffsetLow = (UINT16)CurrentHandler;
1020 gIdtTable[Index].Bits.Selector = AsmReadCs();
1021 gIdtTable[Index].Bits.Reserved_0 = 0;
1022 gIdtTable[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
1023 gIdtTable[Index].Bits.OffsetHigh = (UINT16)(CurrentHandler >> 16);
1024 #if defined (MDE_CPU_X64)
1025 gIdtTable[Index].Bits.OffsetUpper = (UINT32)(CurrentHandler >> 32);
1026 gIdtTable[Index].Bits.Reserved_1 = 0;
1027 #endif
1028 }
1029
1030 //
1031 // Load IDT Pointer
1032 //
1033 IdtPtrAlignmentBuffer = AllocatePool (sizeof (*IdtPtr) + 16);
1034 IdtPtr = ALIGN_POINTER (IdtPtrAlignmentBuffer, 16);
1035 IdtPtr->Base = (UINT32)(((UINTN)(VOID*) gIdtTable) & (BASE_4GB-1));
1036 IdtPtr->Limit = sizeof (gIdtTable) - 1;
1037 AsmWriteIdtr (IdtPtr);
1038 FreePool (IdtPtrAlignmentBuffer);
1039
1040 //
1041 // Initialize Exception Handlers
1042 //
1043 for (Index = 0; Index < 32; Index++) {
1044 Status = CpuRegisterInterruptHandler (&gCpu, Index, CommonExceptionHandler);
1045 ASSERT_EFI_ERROR (Status);
1046 }
1047
1048 //
1049 // Set the pointer to the array of C based exception handling routines.
1050 //
1051 InitializeExternalVectorTablePtr (ExternalVectorTable);
1052
1053 }
1054
1055
1056 /**
1057 Initialize the state information for the CPU Architectural Protocol.
1058
1059 @param ImageHandle Image handle this driver.
1060 @param SystemTable Pointer to the System Table.
1061
1062 @retval EFI_SUCCESS Thread can be successfully created
1063 @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
1064 @retval EFI_DEVICE_ERROR Cannot create the thread
1065
1066 **/
1067 EFI_STATUS
1068 EFIAPI
1069 InitializeCpu (
1070 IN EFI_HANDLE ImageHandle,
1071 IN EFI_SYSTEM_TABLE *SystemTable
1072 )
1073 {
1074 EFI_STATUS Status;
1075
1076 //
1077 // Make sure interrupts are disabled
1078 //
1079 DisableInterrupts ();
1080
1081 //
1082 // Init GDT for DXE
1083 //
1084 InitGlobalDescriptorTable ();
1085
1086 //
1087 // Setup IDT pointer, IDT and interrupt entry points
1088 //
1089 InitInterruptDescriptorTable ();
1090
1091 //
1092 // Install CPU Architectural Protocol
1093 //
1094 Status = gBS->InstallMultipleProtocolInterfaces (
1095 &mCpuHandle,
1096 &gEfiCpuArchProtocolGuid, &gCpu,
1097 NULL
1098 );
1099 ASSERT_EFI_ERROR (Status);
1100
1101 //
1102 // Refresh GCD memory space map according to MTRR value.
1103 //
1104 RefreshGcdMemoryAttributes ();
1105
1106 return Status;
1107 }
1108