UefiCpuPkg/CpuDxe/CpuDxe.c

   1 /** @file
   2   CPU DXE Module to produce CPU ARCH Protocol.
   3
   4   Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include "CpuDxe.h"
  16 #include "CpuMp.h"
  17 #include "CpuPageTable.h"
  18
  19 #define CACHE_ATTRIBUTE_MASK   (EFI_MEMORY_UC | EFI_MEMORY_WC | EFI_MEMORY_WT | EFI_MEMORY_WB | EFI_MEMORY_UCE | EFI_MEMORY_WP)
  20 #define MEMORY_ATTRIBUTE_MASK  (EFI_MEMORY_RP | EFI_MEMORY_XP | EFI_MEMORY_RO)
  21
  22 //
  23 // Global Variables
  24 //
  25 BOOLEAN                   InterruptState = FALSE;
  26 EFI_HANDLE                mCpuHandle = NULL;
  27 BOOLEAN                   mIsFlushingGCD;
  28 UINT64                    mValidMtrrAddressMask;
  29 UINT64                    mValidMtrrBitsMask;
  30 UINT64                    mTimerPeriod = 0;
  31
  32 FIXED_MTRR    mFixedMtrrTable[] = {
  33   {
  34     MSR_IA32_MTRR_FIX64K_00000,
  35     0,
  36     0x10000
  37   },
  38   {
  39     MSR_IA32_MTRR_FIX16K_80000,
  40     0x80000,
  41     0x4000
  42   },
  43   {
  44     MSR_IA32_MTRR_FIX16K_A0000,
  45     0xA0000,
  46     0x4000
  47   },
  48   {
  49     MSR_IA32_MTRR_FIX4K_C0000,
  50     0xC0000,
  51     0x1000
  52   },
  53   {
  54     MSR_IA32_MTRR_FIX4K_C8000,
  55     0xC8000,
  56     0x1000
  57   },
  58   {
  59     MSR_IA32_MTRR_FIX4K_D0000,
  60     0xD0000,
  61     0x1000
  62   },
  63   {
  64     MSR_IA32_MTRR_FIX4K_D8000,
  65     0xD8000,
  66     0x1000
  67   },
  68   {
  69     MSR_IA32_MTRR_FIX4K_E0000,
  70     0xE0000,
  71     0x1000
  72   },
  73   {
  74     MSR_IA32_MTRR_FIX4K_E8000,
  75     0xE8000,
  76     0x1000
  77   },
  78   {
  79     MSR_IA32_MTRR_FIX4K_F0000,
  80     0xF0000,
  81     0x1000
  82   },
  83   {
  84     MSR_IA32_MTRR_FIX4K_F8000,
  85     0xF8000,
  86     0x1000
  87   },
  88 };
  89
  90
  91 EFI_CPU_ARCH_PROTOCOL  gCpu = {
  92   CpuFlushCpuDataCache,
  93   CpuEnableInterrupt,
  94   CpuDisableInterrupt,
  95   CpuGetInterruptState,
  96   CpuInit,
  97   CpuRegisterInterruptHandler,
  98   CpuGetTimerValue,
  99   CpuSetMemoryAttributes,
 100   1,                          // NumberOfTimers
 101   4                           // DmaBufferAlignment
 102 };
 103
 104 //
 105 // CPU Arch Protocol Functions
 106 //
 107
 108 /**
 109   Flush CPU data cache. If the instruction cache is fully coherent
 110   with all DMA operations then function can just return EFI_SUCCESS.
 111
 112   @param  This              Protocol instance structure
 113   @param  Start             Physical address to start flushing from.
 114   @param  Length            Number of bytes to flush. Round up to chipset
 115                             granularity.
 116   @param  FlushType         Specifies the type of flush operation to perform.
 117
 118   @retval EFI_SUCCESS       If cache was flushed
 119   @retval EFI_UNSUPPORTED   If flush type is not supported.
 120   @retval EFI_DEVICE_ERROR  If requested range could not be flushed.
 121
 122 **/
 123 EFI_STATUS
 124 EFIAPI
 125 CpuFlushCpuDataCache (
 126   IN EFI_CPU_ARCH_PROTOCOL     *This,
 127   IN EFI_PHYSICAL_ADDRESS      Start,
 128   IN UINT64                    Length,
 129   IN EFI_CPU_FLUSH_TYPE        FlushType
 130   )
 131 {
 132   if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {
 133     AsmWbinvd ();
 134     return EFI_SUCCESS;
 135   } else if (FlushType == EfiCpuFlushTypeInvalidate) {
 136     AsmInvd ();
 137     return EFI_SUCCESS;
 138   } else {
 139     return EFI_UNSUPPORTED;
 140   }
 141 }
 142
 143
 144 /**
 145   Enables CPU interrupts.
 146
 147   @param  This              Protocol instance structure
 148
 149   @retval EFI_SUCCESS       If interrupts were enabled in the CPU
 150   @retval EFI_DEVICE_ERROR  If interrupts could not be enabled on the CPU.
 151
 152 **/
 153 EFI_STATUS
 154 EFIAPI
 155 CpuEnableInterrupt (
 156   IN EFI_CPU_ARCH_PROTOCOL          *This
 157   )
 158 {
 159   EnableInterrupts ();
 160
 161   InterruptState = TRUE;
 162   return EFI_SUCCESS;
 163 }
 164
 165
 166 /**
 167   Disables CPU interrupts.
 168
 169   @param  This              Protocol instance structure
 170
 171   @retval EFI_SUCCESS       If interrupts were disabled in the CPU.
 172   @retval EFI_DEVICE_ERROR  If interrupts could not be disabled on the CPU.
 173
 174 **/
 175 EFI_STATUS
 176 EFIAPI
 177 CpuDisableInterrupt (
 178   IN EFI_CPU_ARCH_PROTOCOL     *This
 179   )
 180 {
 181   DisableInterrupts ();
 182
 183   InterruptState = FALSE;
 184   return EFI_SUCCESS;
 185 }
 186
 187
 188 /**
 189   Return the state of interrupts.
 190
 191   @param  This                   Protocol instance structure
 192   @param  State                  Pointer to the CPU's current interrupt state
 193
 194   @retval EFI_SUCCESS            If interrupts were disabled in the CPU.
 195   @retval EFI_INVALID_PARAMETER  State is NULL.
 196
 197 **/
 198 EFI_STATUS
 199 EFIAPI
 200 CpuGetInterruptState (
 201   IN  EFI_CPU_ARCH_PROTOCOL     *This,
 202   OUT BOOLEAN                   *State
 203   )
 204 {
 205   if (State == NULL) {
 206     return EFI_INVALID_PARAMETER;
 207   }
 208
 209   *State = InterruptState;
 210   return EFI_SUCCESS;
 211 }
 212
 213
 214 /**
 215   Generates an INIT to the CPU.
 216
 217   @param  This              Protocol instance structure
 218   @param  InitType          Type of CPU INIT to perform
 219
 220   @retval EFI_SUCCESS       If CPU INIT occurred. This value should never be
 221                             seen.
 222   @retval EFI_DEVICE_ERROR  If CPU INIT failed.
 223   @retval EFI_UNSUPPORTED   Requested type of CPU INIT not supported.
 224
 225 **/
 226 EFI_STATUS
 227 EFIAPI
 228 CpuInit (
 229   IN EFI_CPU_ARCH_PROTOCOL      *This,
 230   IN EFI_CPU_INIT_TYPE          InitType
 231   )
 232 {
 233   return EFI_UNSUPPORTED;
 234 }
 235
 236
 237 /**
 238   Registers a function to be called from the CPU interrupt handler.
 239
 240   @param  This                   Protocol instance structure
 241   @param  InterruptType          Defines which interrupt to hook. IA-32
 242                                  valid range is 0x00 through 0xFF
 243   @param  InterruptHandler       A pointer to a function of type
 244                                  EFI_CPU_INTERRUPT_HANDLER that is called
 245                                  when a processor interrupt occurs.  A null
 246                                  pointer is an error condition.
 247
 248   @retval EFI_SUCCESS            If handler installed or uninstalled.
 249   @retval EFI_ALREADY_STARTED    InterruptHandler is not NULL, and a handler
 250                                  for InterruptType was previously installed.
 251   @retval EFI_INVALID_PARAMETER  InterruptHandler is NULL, and a handler for
 252                                  InterruptType was not previously installed.
 253   @retval EFI_UNSUPPORTED        The interrupt specified by InterruptType
 254                                  is not supported.
 255
 256 **/
 257 EFI_STATUS
 258 EFIAPI
 259 CpuRegisterInterruptHandler (
 260   IN EFI_CPU_ARCH_PROTOCOL         *This,
 261   IN EFI_EXCEPTION_TYPE            InterruptType,
 262   IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler
 263   )
 264 {
 265   return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
 266 }
 267
 268
 269 /**
 270   Returns a timer value from one of the CPU's internal timers. There is no
 271   inherent time interval between ticks but is a function of the CPU frequency.
 272
 273   @param  This                - Protocol instance structure.
 274   @param  TimerIndex          - Specifies which CPU timer is requested.
 275   @param  TimerValue          - Pointer to the returned timer value.
 276   @param  TimerPeriod         - A pointer to the amount of time that passes
 277                                 in femtoseconds (10-15) for each increment
 278                                 of TimerValue. If TimerValue does not
 279                                 increment at a predictable rate, then 0 is
 280                                 returned.  The amount of time that has
 281                                 passed between two calls to GetTimerValue()
 282                                 can be calculated with the formula
 283                                 (TimerValue2 - TimerValue1) * TimerPeriod.
 284                                 This parameter is optional and may be NULL.
 285
 286   @retval EFI_SUCCESS           - If the CPU timer count was returned.
 287   @retval EFI_UNSUPPORTED       - If the CPU does not have any readable timers.
 288   @retval EFI_DEVICE_ERROR      - If an error occurred while reading the timer.
 289   @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
 290
 291 **/
 292 EFI_STATUS
 293 EFIAPI
 294 CpuGetTimerValue (
 295   IN  EFI_CPU_ARCH_PROTOCOL     *This,
 296   IN  UINT32                    TimerIndex,
 297   OUT UINT64                    *TimerValue,
 298   OUT UINT64                    *TimerPeriod OPTIONAL
 299   )
 300 {
 301   UINT64          BeginValue;
 302   UINT64          EndValue;
 303
 304   if (TimerValue == NULL) {
 305     return EFI_INVALID_PARAMETER;
 306   }
 307
 308   if (TimerIndex != 0) {
 309     return EFI_INVALID_PARAMETER;
 310   }
 311
 312   *TimerValue = AsmReadTsc ();
 313
 314   if (TimerPeriod != NULL) {
 315     if (mTimerPeriod == 0) {
 316       //
 317       // Read time stamp counter before and after delay of 100 microseconds
 318       //
 319       BeginValue = AsmReadTsc ();
 320       MicroSecondDelay (100);
 321       EndValue   = AsmReadTsc ();
 322       //
 323       // Calculate the actual frequency
 324       //
 325       mTimerPeriod = DivU64x64Remainder (
 326                        MultU64x32 (
 327                          1000 * 1000 * 1000,
 328                          100
 329                          ),
 330                        EndValue - BeginValue,
 331                        NULL
 332                        );
 333     }
 334     *TimerPeriod = mTimerPeriod;
 335   }
 336
 337   return EFI_SUCCESS;
 338 }
 339
 340 /**
 341   A minimal wrapper function that allows MtrrSetAllMtrrs() to be passed to
 342   EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() as Procedure.
 343
 344   @param[in] Buffer  Pointer to an MTRR_SETTINGS object, to be passed to
 345                      MtrrSetAllMtrrs().
 346 **/
 347 VOID
 348 EFIAPI
 349 SetMtrrsFromBuffer (
 350   IN VOID *Buffer
 351   )
 352 {
 353   MtrrSetAllMtrrs (Buffer);
 354 }
 355
 356 /**
 357   Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.
 358
 359   This function modifies the attributes for the memory region specified by BaseAddress and
 360   Length from their current attributes to the attributes specified by Attributes.
 361
 362   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
 363   @param  BaseAddress      The physical address that is the start address of a memory region.
 364   @param  Length           The size in bytes of the memory region.
 365   @param  Attributes       The bit mask of attributes to set for the memory region.
 366
 367   @retval EFI_SUCCESS           The attributes were set for the memory region.
 368   @retval EFI_ACCESS_DENIED     The attributes for the memory resource range specified by
 369                                 BaseAddress and Length cannot be modified.
 370   @retval EFI_INVALID_PARAMETER Length is zero.
 371                                 Attributes specified an illegal combination of attributes that
 372                                 cannot be set together.
 373   @retval EFI_OUT_OF_RESOURCES  There are not enough system resources to modify the attributes of
 374                                 the memory resource range.
 375   @retval EFI_UNSUPPORTED       The processor does not support one or more bytes of the memory
 376                                 resource range specified by BaseAddress and Length.
 377                                 The bit mask of attributes is not support for the memory resource
 378                                 range specified by BaseAddress and Length.
 379
 380 **/
 381 EFI_STATUS
 382 EFIAPI
 383 CpuSetMemoryAttributes (
 384   IN EFI_CPU_ARCH_PROTOCOL     *This,
 385   IN EFI_PHYSICAL_ADDRESS      BaseAddress,
 386   IN UINT64                    Length,
 387   IN UINT64                    Attributes
 388   )
 389 {
 390   RETURN_STATUS             Status;
 391   MTRR_MEMORY_CACHE_TYPE    CacheType;
 392   EFI_STATUS                MpStatus;
 393   EFI_MP_SERVICES_PROTOCOL  *MpService;
 394   MTRR_SETTINGS             MtrrSettings;
 395   UINT64                    CacheAttributes;
 396   UINT64                    MemoryAttributes;
 397   MTRR_MEMORY_CACHE_TYPE    CurrentCacheType;
 398
 399   //
 400   // If this function is called because GCD SetMemorySpaceAttributes () is called
 401   // by RefreshGcdMemoryAttributes (), then we are just synchronzing GCD memory
 402   // map with MTRR values. So there is no need to modify MTRRs, just return immediately
 403   // to avoid unnecessary computing.
 404   //
 405   if (mIsFlushingGCD) {
 406     DEBUG((DEBUG_INFO, "  Flushing GCD\n"));
 407     return EFI_SUCCESS;
 408   }
 409
 410
 411   CacheAttributes = Attributes & CACHE_ATTRIBUTE_MASK;
 412   MemoryAttributes = Attributes & MEMORY_ATTRIBUTE_MASK;
 413
 414   if (Attributes != (CacheAttributes | MemoryAttributes)) {
 415     return EFI_INVALID_PARAMETER;
 416   }
 417
 418   if (CacheAttributes != 0) {
 419     if (!IsMtrrSupported ()) {
 420       return EFI_UNSUPPORTED;
 421     }
 422
 423     switch (CacheAttributes) {
 424     case EFI_MEMORY_UC:
 425       CacheType = CacheUncacheable;
 426       break;
 427
 428     case EFI_MEMORY_WC:
 429       CacheType = CacheWriteCombining;
 430       break;
 431
 432     case EFI_MEMORY_WT:
 433       CacheType = CacheWriteThrough;
 434       break;
 435
 436     case EFI_MEMORY_WP:
 437       CacheType = CacheWriteProtected;
 438       break;
 439
 440     case EFI_MEMORY_WB:
 441       CacheType = CacheWriteBack;
 442       break;
 443
 444     default:
 445       return EFI_INVALID_PARAMETER;
 446     }
 447     CurrentCacheType = MtrrGetMemoryAttribute(BaseAddress);
 448     if (CurrentCacheType != CacheType) {
 449       //
 450       // call MTRR libary function
 451       //
 452       Status = MtrrSetMemoryAttribute (
 453                  BaseAddress,
 454                  Length,
 455                  CacheType
 456                  );
 457
 458       if (!RETURN_ERROR (Status)) {
 459         MpStatus = gBS->LocateProtocol (
 460                           &gEfiMpServiceProtocolGuid,
 461                           NULL,
 462                           (VOID **)&MpService
 463                           );
 464         //
 465         // Synchronize the update with all APs
 466         //
 467         if (!EFI_ERROR (MpStatus)) {
 468           MtrrGetAllMtrrs (&MtrrSettings);
 469           MpStatus = MpService->StartupAllAPs (
 470                                   MpService,          // This
 471                                   SetMtrrsFromBuffer, // Procedure
 472                                   FALSE,              // SingleThread
 473                                   NULL,               // WaitEvent
 474                                   0,                  // TimeoutInMicrosecsond
 475                                   &MtrrSettings,      // ProcedureArgument
 476                                   NULL                // FailedCpuList
 477                                   );
 478           ASSERT (MpStatus == EFI_SUCCESS || MpStatus == EFI_NOT_STARTED);
 479         }
 480       }
 481       if (EFI_ERROR(Status)) {
 482         return Status;
 483       }
 484     }
 485   }
 486
 487   //
 488   // Set memory attribute by page table
 489   //
 490   return AssignMemoryPageAttributes (NULL, BaseAddress, Length, MemoryAttributes, AllocatePages);
 491 }
 492
 493 /**
 494   Initializes the valid bits mask and valid address mask for MTRRs.
 495
 496   This function initializes the valid bits mask and valid address mask for MTRRs.
 497
 498 **/
 499 VOID
 500 InitializeMtrrMask (
 501   VOID
 502   )
 503 {
 504   UINT32                              RegEax;
 505   UINT8                               PhysicalAddressBits;
 506
 507   AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
 508
 509   if (RegEax >= 0x80000008) {
 510     AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
 511
 512     PhysicalAddressBits = (UINT8) RegEax;
 513   } else {
 514     PhysicalAddressBits = 36;
 515   }
 516
 517   mValidMtrrBitsMask    = LShiftU64 (1, PhysicalAddressBits) - 1;
 518   mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;
 519 }
 520
 521 /**
 522   Gets GCD Mem Space type from MTRR Type.
 523
 524   This function gets GCD Mem Space type from MTRR Type.
 525
 526   @param  MtrrAttributes  MTRR memory type
 527
 528   @return GCD Mem Space type
 529
 530 **/
 531 UINT64
 532 GetMemorySpaceAttributeFromMtrrType (
 533   IN UINT8                MtrrAttributes
 534   )
 535 {
 536   switch (MtrrAttributes) {
 537   case MTRR_CACHE_UNCACHEABLE:
 538     return EFI_MEMORY_UC;
 539   case MTRR_CACHE_WRITE_COMBINING:
 540     return EFI_MEMORY_WC;
 541   case MTRR_CACHE_WRITE_THROUGH:
 542     return EFI_MEMORY_WT;
 543   case MTRR_CACHE_WRITE_PROTECTED:
 544     return EFI_MEMORY_WP;
 545   case MTRR_CACHE_WRITE_BACK:
 546     return EFI_MEMORY_WB;
 547   default:
 548     return 0;
 549   }
 550 }
 551
 552 /**
 553   Searches memory descriptors covered by given memory range.
 554
 555   This function searches into the Gcd Memory Space for descriptors
 556   (from StartIndex to EndIndex) that contains the memory range
 557   specified by BaseAddress and Length.
 558
 559   @param  MemorySpaceMap       Gcd Memory Space Map as array.
 560   @param  NumberOfDescriptors  Number of descriptors in map.
 561   @param  BaseAddress          BaseAddress for the requested range.
 562   @param  Length               Length for the requested range.
 563   @param  StartIndex           Start index into the Gcd Memory Space Map.
 564   @param  EndIndex             End index into the Gcd Memory Space Map.
 565
 566   @retval EFI_SUCCESS          Search successfully.
 567   @retval EFI_NOT_FOUND        The requested descriptors does not exist.
 568
 569 **/
 570 EFI_STATUS
 571 SearchGcdMemorySpaces (
 572   IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap,
 573   IN UINTN                               NumberOfDescriptors,
 574   IN EFI_PHYSICAL_ADDRESS                BaseAddress,
 575   IN UINT64                              Length,
 576   OUT UINTN                              *StartIndex,
 577   OUT UINTN                              *EndIndex
 578   )
 579 {
 580   UINTN           Index;
 581
 582   *StartIndex = 0;
 583   *EndIndex   = 0;
 584   for (Index = 0; Index < NumberOfDescriptors; Index++) {
 585     if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&
 586         BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
 587       *StartIndex = Index;
 588     }
 589     if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&
 590         BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
 591       *EndIndex = Index;
 592       return EFI_SUCCESS;
 593     }
 594   }
 595   return EFI_NOT_FOUND;
 596 }
 597
 598 /**
 599   Sets the attributes for a specified range in Gcd Memory Space Map.
 600
 601   This function sets the attributes for a specified range in
 602   Gcd Memory Space Map.
 603
 604   @param  MemorySpaceMap       Gcd Memory Space Map as array
 605   @param  NumberOfDescriptors  Number of descriptors in map
 606   @param  BaseAddress          BaseAddress for the range
 607   @param  Length               Length for the range
 608   @param  Attributes           Attributes to set
 609
 610   @retval EFI_SUCCESS          Memory attributes set successfully
 611   @retval EFI_NOT_FOUND        The specified range does not exist in Gcd Memory Space
 612
 613 **/
 614 EFI_STATUS
 615 SetGcdMemorySpaceAttributes (
 616   IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap,
 617   IN UINTN                               NumberOfDescriptors,
 618   IN EFI_PHYSICAL_ADDRESS                BaseAddress,
 619   IN UINT64                              Length,
 620   IN UINT64                              Attributes
 621   )
 622 {
 623   EFI_STATUS            Status;
 624   UINTN                 Index;
 625   UINTN                 StartIndex;
 626   UINTN                 EndIndex;
 627   EFI_PHYSICAL_ADDRESS  RegionStart;
 628   UINT64                RegionLength;
 629
 630   //
 631   // Get all memory descriptors covered by the memory range
 632   //
 633   Status = SearchGcdMemorySpaces (
 634              MemorySpaceMap,
 635              NumberOfDescriptors,
 636              BaseAddress,
 637              Length,
 638              &StartIndex,
 639              &EndIndex
 640              );
 641   if (EFI_ERROR (Status)) {
 642     return Status;
 643   }
 644
 645   //
 646   // Go through all related descriptors and set attributes accordingly
 647   //
 648   for (Index = StartIndex; Index <= EndIndex; Index++) {
 649     if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
 650       continue;
 651     }
 652     //
 653     // Calculate the start and end address of the overlapping range
 654     //
 655     if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {
 656       RegionStart = BaseAddress;
 657     } else {
 658       RegionStart = MemorySpaceMap[Index].BaseAddress;
 659     }
 660     if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
 661       RegionLength = BaseAddress + Length - RegionStart;
 662     } else {
 663       RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
 664     }
 665     //
 666     // Set memory attributes according to MTRR attribute and the original attribute of descriptor
 667     //
 668     gDS->SetMemorySpaceAttributes (
 669            RegionStart,
 670            RegionLength,
 671            (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
 672            );
 673   }
 674
 675   return EFI_SUCCESS;
 676 }
 677
 678
 679 /**
 680   Refreshes the GCD Memory Space attributes according to MTRRs.
 681
 682   This function refreshes the GCD Memory Space attributes according to MTRRs.
 683
 684 **/
 685 VOID
 686 RefreshMemoryAttributesFromMtrr (
 687   VOID
 688   )
 689 {
 690   EFI_STATUS                          Status;
 691   UINTN                               Index;
 692   UINTN                               SubIndex;
 693   UINT64                              RegValue;
 694   EFI_PHYSICAL_ADDRESS                BaseAddress;
 695   UINT64                              Length;
 696   UINT64                              Attributes;
 697   UINT64                              CurrentAttributes;
 698   UINT8                               MtrrType;
 699   UINTN                               NumberOfDescriptors;
 700   EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap;
 701   UINT64                              DefaultAttributes;
 702   VARIABLE_MTRR                       VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
 703   MTRR_FIXED_SETTINGS                 MtrrFixedSettings;
 704   UINT32                              FirmwareVariableMtrrCount;
 705   UINT8                               DefaultMemoryType;
 706
 707   FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();
 708   ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);
 709
 710   MemorySpaceMap = NULL;
 711
 712   //
 713   // Initialize the valid bits mask and valid address mask for MTRRs
 714   //
 715   InitializeMtrrMask ();
 716
 717   //
 718   // Get the memory attribute of variable MTRRs
 719   //
 720   MtrrGetMemoryAttributeInVariableMtrr (
 721     mValidMtrrBitsMask,
 722     mValidMtrrAddressMask,
 723     VariableMtrr
 724     );
 725
 726   //
 727   // Get the memory space map from GCD
 728   //
 729   Status = gDS->GetMemorySpaceMap (
 730                   &NumberOfDescriptors,
 731                   &MemorySpaceMap
 732                   );
 733   ASSERT_EFI_ERROR (Status);
 734
 735   DefaultMemoryType = (UINT8) MtrrGetDefaultMemoryType ();
 736   DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (DefaultMemoryType);
 737
 738   //
 739   // Set default attributes to all spaces.
 740   //
 741   for (Index = 0; Index < NumberOfDescriptors; Index++) {
 742     if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
 743       continue;
 744     }
 745     gDS->SetMemorySpaceAttributes (
 746            MemorySpaceMap[Index].BaseAddress,
 747            MemorySpaceMap[Index].Length,
 748            (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) |
 749            (MemorySpaceMap[Index].Capabilities & DefaultAttributes)
 750            );
 751   }
 752
 753   //
 754   // Go for variable MTRRs with WB attribute
 755   //
 756   for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
 757     if (VariableMtrr[Index].Valid &&
 758         VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) {
 759       SetGcdMemorySpaceAttributes (
 760         MemorySpaceMap,
 761         NumberOfDescriptors,
 762         VariableMtrr[Index].BaseAddress,
 763         VariableMtrr[Index].Length,
 764         EFI_MEMORY_WB
 765         );
 766     }
 767   }
 768
 769   //
 770   // Go for variable MTRRs with the attribute except for WB and UC attributes
 771   //
 772   for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
 773     if (VariableMtrr[Index].Valid &&
 774         VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK &&
 775         VariableMtrr[Index].Type != MTRR_CACHE_UNCACHEABLE) {
 776       Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8) VariableMtrr[Index].Type);
 777       SetGcdMemorySpaceAttributes (
 778         MemorySpaceMap,
 779         NumberOfDescriptors,
 780         VariableMtrr[Index].BaseAddress,
 781         VariableMtrr[Index].Length,
 782         Attributes
 783         );
 784     }
 785   }
 786
 787   //
 788   // Go for variable MTRRs with UC attribute
 789   //
 790   for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
 791     if (VariableMtrr[Index].Valid &&
 792         VariableMtrr[Index].Type == MTRR_CACHE_UNCACHEABLE) {
 793       SetGcdMemorySpaceAttributes (
 794         MemorySpaceMap,
 795         NumberOfDescriptors,
 796         VariableMtrr[Index].BaseAddress,
 797         VariableMtrr[Index].Length,
 798         EFI_MEMORY_UC
 799         );
 800     }
 801   }
 802
 803   //
 804   // Go for fixed MTRRs
 805   //
 806   Attributes  = 0;
 807   BaseAddress = 0;
 808   Length      = 0;
 809   MtrrGetFixedMtrr (&MtrrFixedSettings);
 810   for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {
 811     RegValue = MtrrFixedSettings.Mtrr[Index];
 812     //
 813     // Check for continuous fixed MTRR sections
 814     //
 815     for (SubIndex = 0; SubIndex < 8; SubIndex++) {
 816       MtrrType = (UINT8) RShiftU64 (RegValue, SubIndex * 8);
 817       CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType);
 818       if (Length == 0) {
 819         //
 820         // A new MTRR attribute begins
 821         //
 822         Attributes = CurrentAttributes;
 823       } else {
 824         //
 825         // If fixed MTRR attribute changed, then set memory attribute for previous atrribute
 826         //
 827         if (CurrentAttributes != Attributes) {
 828           SetGcdMemorySpaceAttributes (
 829             MemorySpaceMap,
 830             NumberOfDescriptors,
 831             BaseAddress,
 832             Length,
 833             Attributes
 834             );
 835           BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex;
 836           Length = 0;
 837           Attributes = CurrentAttributes;
 838         }
 839       }
 840       Length += mFixedMtrrTable[Index].Length;
 841     }
 842   }
 843   //
 844   // Handle the last fixed MTRR region
 845   //
 846   SetGcdMemorySpaceAttributes (
 847     MemorySpaceMap,
 848     NumberOfDescriptors,
 849     BaseAddress,
 850     Length,
 851     Attributes
 852     );
 853
 854   //
 855   // Free memory space map allocated by GCD service GetMemorySpaceMap ()
 856   //
 857   if (MemorySpaceMap != NULL) {
 858     FreePool (MemorySpaceMap);
 859   }
 860 }
 861
 862 /**
 863  Check if paging is enabled or not.
 864 **/
 865 BOOLEAN
 866 IsPagingAndPageAddressExtensionsEnabled (
 867   VOID
 868   )
 869 {
 870   IA32_CR0  Cr0;
 871   IA32_CR4  Cr4;
 872
 873   Cr0.UintN = AsmReadCr0 ();
 874   Cr4.UintN = AsmReadCr4 ();
 875
 876   return ((Cr0.Bits.PG != 0) && (Cr4.Bits.PAE != 0));
 877 }
 878
 879 /**
 880   Refreshes the GCD Memory Space attributes according to MTRRs and Paging.
 881
 882   This function refreshes the GCD Memory Space attributes according to MTRRs
 883   and page tables.
 884
 885 **/
 886 VOID
 887 RefreshGcdMemoryAttributes (
 888   VOID
 889   )
 890 {
 891   mIsFlushingGCD = TRUE;
 892
 893   if (IsMtrrSupported ()) {
 894     RefreshMemoryAttributesFromMtrr ();
 895   }
 896
 897   if (IsPagingAndPageAddressExtensionsEnabled ()) {
 898     RefreshGcdMemoryAttributesFromPaging ();
 899   }
 900
 901   mIsFlushingGCD = FALSE;
 902 }
 903
 904 /**
 905   Initialize Interrupt Descriptor Table for interrupt handling.
 906
 907 **/
 908 VOID
 909 InitInterruptDescriptorTable (
 910   VOID
 911   )
 912 {
 913   EFI_STATUS                     Status;
 914   EFI_VECTOR_HANDOFF_INFO        *VectorInfoList;
 915   EFI_VECTOR_HANDOFF_INFO        *VectorInfo;
 916
 917   VectorInfo = NULL;
 918   Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **) &VectorInfoList);
 919   if (Status == EFI_SUCCESS && VectorInfoList != NULL) {
 920     VectorInfo = VectorInfoList;
 921   }
 922   Status = InitializeCpuInterruptHandlers (VectorInfo);
 923   ASSERT_EFI_ERROR (Status);
 924 }
 925
 926
 927 /**
 928   Callback function for idle events.
 929
 930   @param  Event                 Event whose notification function is being invoked.
 931   @param  Context               The pointer to the notification function's context,
 932                                 which is implementation-dependent.
 933
 934 **/
 935 VOID
 936 EFIAPI
 937 IdleLoopEventCallback (
 938   IN EFI_EVENT                Event,
 939   IN VOID                     *Context
 940   )
 941 {
 942   CpuSleep ();
 943 }
 944
 945 /**
 946   Ensure the compatibility of a memory space descriptor with the MMIO aperture.
 947
 948   The memory space descriptor can come from the GCD memory space map, or it can
 949   represent a gap between two neighboring memory space descriptors. In the
 950   latter case, the GcdMemoryType field is expected to be
 951   EfiGcdMemoryTypeNonExistent.
 952
 953   If the memory space descriptor already has type
 954   EfiGcdMemoryTypeMemoryMappedIo, and its capabilities are a superset of the
 955   required capabilities, then no action is taken -- it is by definition
 956   compatible with the aperture.
 957
 958   Otherwise, the intersection of the memory space descriptor is calculated with
 959   the aperture. If the intersection is the empty set (no overlap), no action is
 960   taken; the memory space descriptor is compatible with the aperture.
 961
 962   Otherwise, the type of the descriptor is investigated again. If the type is
 963   EfiGcdMemoryTypeNonExistent (representing a gap, or a genuine descriptor with
 964   such a type), then an attempt is made to add the intersection as MMIO space
 965   to the GCD memory space map, with the specified capabilities. This ensures
 966   continuity for the aperture, and the descriptor is deemed compatible with the
 967   aperture.
 968
 969   Otherwise, the memory space descriptor is incompatible with the MMIO
 970   aperture.
 971
 972   @param[in] Base         Base address of the aperture.
 973   @param[in] Length       Length of the aperture.
 974   @param[in] Capabilities Capabilities required by the aperture.
 975   @param[in] Descriptor   The descriptor to ensure compatibility with the
 976                           aperture for.
 977
 978   @retval EFI_SUCCESS            The descriptor is compatible. The GCD memory
 979                                  space map may have been updated, for
 980                                  continuity within the aperture.
 981   @retval EFI_INVALID_PARAMETER  The descriptor is incompatible.
 982   @return                        Error codes from gDS->AddMemorySpace().
 983 **/
 984 EFI_STATUS
 985 IntersectMemoryDescriptor (
 986   IN  UINT64                                Base,
 987   IN  UINT64                                Length,
 988   IN  UINT64                                Capabilities,
 989   IN  CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor
 990   )
 991 {
 992   UINT64                                    IntersectionBase;
 993   UINT64                                    IntersectionEnd;
 994   EFI_STATUS                                Status;
 995
 996   if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo &&
 997       (Descriptor->Capabilities & Capabilities) == Capabilities) {
 998     return EFI_SUCCESS;
 999   }
1000
1001   IntersectionBase = MAX (Base, Descriptor->BaseAddress);
1002   IntersectionEnd = MIN (Base + Length,
1003                       Descriptor->BaseAddress + Descriptor->Length);
1004   if (IntersectionBase >= IntersectionEnd) {
1005     //
1006     // The descriptor and the aperture don't overlap.
1007     //
1008     return EFI_SUCCESS;
1009   }
1010
1011   if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
1012     Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo,
1013                     IntersectionBase, IntersectionEnd - IntersectionBase,
1014                     Capabilities);
1015
1016     DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
1017       "%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__,
1018       IntersectionBase, IntersectionEnd, Status));
1019     return Status;
1020   }
1021
1022   DEBUG ((DEBUG_ERROR, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "
1023     "with aperture [%Lx, %Lx) cap %Lx\n", gEfiCallerBaseName, __FUNCTION__,
1024     Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length,
1025     (UINT32)Descriptor->GcdMemoryType, Descriptor->Capabilities,
1026     Base, Base + Length, Capabilities));
1027   return EFI_INVALID_PARAMETER;
1028 }
1029
1030 /**
1031   Add MMIO space to GCD.
1032   The routine checks the GCD database and only adds those which are
1033   not added in the specified range to GCD.
1034
1035   @param Base         Base address of the MMIO space.
1036   @param Length       Length of the MMIO space.
1037   @param Capabilities Capabilities of the MMIO space.
1038
1039   @retval EFI_SUCCES The MMIO space was added successfully.
1040 **/
1041 EFI_STATUS
1042 AddMemoryMappedIoSpace (
1043   IN  UINT64                            Base,
1044   IN  UINT64                            Length,
1045   IN  UINT64                            Capabilities
1046   )
1047 {
1048   EFI_STATUS                            Status;
1049   UINTN                                 Index;
1050   UINTN                                 NumberOfDescriptors;
1051   EFI_GCD_MEMORY_SPACE_DESCRIPTOR       *MemorySpaceMap;
1052
1053   Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
1054   if (EFI_ERROR (Status)) {
1055     DEBUG ((DEBUG_ERROR, "%a: %a: GetMemorySpaceMap(): %r\n",
1056       gEfiCallerBaseName, __FUNCTION__, Status));
1057     return Status;
1058   }
1059
1060   for (Index = 0; Index < NumberOfDescriptors; Index++) {
1061     Status = IntersectMemoryDescriptor (Base, Length, Capabilities,
1062                &MemorySpaceMap[Index]);
1063     if (EFI_ERROR (Status)) {
1064       goto FreeMemorySpaceMap;
1065     }
1066   }
1067
1068   DEBUG_CODE (
1069     //
1070     // Make sure there are adjacent descriptors covering [Base, Base + Length).
1071     // It is possible that they have not been merged; merging can be prevented
1072     // by allocation and different capabilities.
1073     //
1074     UINT64                          CheckBase;
1075     EFI_STATUS                      CheckStatus;
1076     EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;
1077
1078     for (CheckBase = Base;
1079          CheckBase < Base + Length;
1080          CheckBase = Descriptor.BaseAddress + Descriptor.Length) {
1081       CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);
1082       ASSERT_EFI_ERROR (CheckStatus);
1083       ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);
1084       ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);
1085     }
1086     );
1087
1088 FreeMemorySpaceMap:
1089   FreePool (MemorySpaceMap);
1090
1091   return Status;
1092 }
1093
1094 /**
1095   Add and allocate CPU local APIC memory mapped space.
1096
1097   @param[in]ImageHandle     Image handle this driver.
1098
1099 **/
1100 VOID
1101 AddLocalApicMemorySpace (
1102   IN EFI_HANDLE               ImageHandle
1103   )
1104 {
1105   EFI_STATUS              Status;
1106   EFI_PHYSICAL_ADDRESS    BaseAddress;
1107
1108   BaseAddress = (EFI_PHYSICAL_ADDRESS) GetLocalApicBaseAddress();
1109   Status = AddMemoryMappedIoSpace (BaseAddress, SIZE_4KB, EFI_MEMORY_UC);
1110   ASSERT_EFI_ERROR (Status);
1111
1112   //
1113   // Try to allocate APIC memory mapped space, does not check return
1114   // status because it may be allocated by other driver, or DXE Core if
1115   // this range is built into Memory Allocation HOB.
1116   //
1117   Status = gDS->AllocateMemorySpace (
1118                   EfiGcdAllocateAddress,
1119                   EfiGcdMemoryTypeMemoryMappedIo,
1120                   0,
1121                   SIZE_4KB,
1122                   &BaseAddress,
1123                   ImageHandle,
1124                   NULL
1125                   );
1126   if (EFI_ERROR (Status)) {
1127     DEBUG ((DEBUG_INFO, "%a: %a: AllocateMemorySpace() Status - %r\n",
1128                          gEfiCallerBaseName, __FUNCTION__, Status));
1129   }
1130 }
1131
1132 /**
1133   Initialize the state information for the CPU Architectural Protocol.
1134
1135   @param ImageHandle     Image handle this driver.
1136   @param SystemTable     Pointer to the System Table.
1137
1138   @retval EFI_SUCCESS           Thread can be successfully created
1139   @retval EFI_OUT_OF_RESOURCES  Cannot allocate protocol data structure
1140   @retval EFI_DEVICE_ERROR      Cannot create the thread
1141
1142 **/
1143 EFI_STATUS
1144 EFIAPI
1145 InitializeCpu (
1146   IN EFI_HANDLE                            ImageHandle,
1147   IN EFI_SYSTEM_TABLE                      *SystemTable
1148   )
1149 {
1150   EFI_STATUS  Status;
1151   EFI_EVENT   IdleLoopEvent;
1152
1153   InitializePageTableLib();
1154
1155   InitializeFloatingPointUnits ();
1156
1157   //
1158   // Make sure interrupts are disabled
1159   //
1160   DisableInterrupts ();
1161
1162   //
1163   // Init GDT for DXE
1164   //
1165   InitGlobalDescriptorTable ();
1166
1167   //
1168   // Setup IDT pointer, IDT and interrupt entry points
1169   //
1170   InitInterruptDescriptorTable ();
1171
1172   //
1173   // Install CPU Architectural Protocol
1174   //
1175   Status = gBS->InstallMultipleProtocolInterfaces (
1176                   &mCpuHandle,
1177                   &gEfiCpuArchProtocolGuid, &gCpu,
1178                   NULL
1179                   );
1180   ASSERT_EFI_ERROR (Status);
1181
1182   //
1183   // Refresh GCD memory space map according to MTRR value.
1184   //
1185   RefreshGcdMemoryAttributes ();
1186
1187   //
1188   // Add and allocate local APIC memory mapped space
1189   //
1190   AddLocalApicMemorySpace (ImageHandle);
1191
1192   //
1193   // Setup a callback for idle events
1194   //
1195   Status = gBS->CreateEventEx (
1196                   EVT_NOTIFY_SIGNAL,
1197                   TPL_NOTIFY,
1198                   IdleLoopEventCallback,
1199                   NULL,
1200                   &gIdleLoopEventGuid,
1201                   &IdleLoopEvent
1202                   );
1203   ASSERT_EFI_ERROR (Status);
1204
1205   InitializeMpSupport ();
1206
1207   return Status;
1208 }
1209