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Add DEBUG() macros for DEBUG_CACHE to MTRR Library show all changes memory caches...
[mirror_edk2.git] / UefiCpuPkg / CpuDxe / CpuDxe.c
1 /** @file
2 CPU DXE Module.
3
4 Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "CpuDxe.h"
16
17 //
18 // Global Variables
19 //
20 IA32_IDT_GATE_DESCRIPTOR gIdtTable[INTERRUPT_VECTOR_NUMBER] = { 0 };
21
22 EFI_CPU_INTERRUPT_HANDLER ExternalVectorTable[0x100];
23 BOOLEAN InterruptState = FALSE;
24 EFI_HANDLE mCpuHandle = NULL;
25 BOOLEAN mIsFlushingGCD;
26 UINT8 mDefaultMemoryType = MTRR_CACHE_WRITE_BACK;
27 UINT64 mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
28 UINT64 mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;
29
30 FIXED_MTRR mFixedMtrrTable[] = {
31 {
32 MTRR_LIB_IA32_MTRR_FIX64K_00000,
33 0,
34 0x10000
35 },
36 {
37 MTRR_LIB_IA32_MTRR_FIX16K_80000,
38 0x80000,
39 0x4000
40 },
41 {
42 MTRR_LIB_IA32_MTRR_FIX16K_A0000,
43 0xA0000,
44 0x4000
45 },
46 {
47 MTRR_LIB_IA32_MTRR_FIX4K_C0000,
48 0xC0000,
49 0x1000
50 },
51 {
52 MTRR_LIB_IA32_MTRR_FIX4K_C8000,
53 0xC8000,
54 0x1000
55 },
56 {
57 MTRR_LIB_IA32_MTRR_FIX4K_D0000,
58 0xD0000,
59 0x1000
60 },
61 {
62 MTRR_LIB_IA32_MTRR_FIX4K_D8000,
63 0xD8000,
64 0x1000
65 },
66 {
67 MTRR_LIB_IA32_MTRR_FIX4K_E0000,
68 0xE0000,
69 0x1000
70 },
71 {
72 MTRR_LIB_IA32_MTRR_FIX4K_E8000,
73 0xE8000,
74 0x1000
75 },
76 {
77 MTRR_LIB_IA32_MTRR_FIX4K_F0000,
78 0xF0000,
79 0x1000
80 },
81 {
82 MTRR_LIB_IA32_MTRR_FIX4K_F8000,
83 0xF8000,
84 0x1000
85 },
86 };
87
88
89 EFI_CPU_ARCH_PROTOCOL gCpu = {
90 CpuFlushCpuDataCache,
91 CpuEnableInterrupt,
92 CpuDisableInterrupt,
93 CpuGetInterruptState,
94 CpuInit,
95 CpuRegisterInterruptHandler,
96 CpuGetTimerValue,
97 CpuSetMemoryAttributes,
98 1, // NumberOfTimers
99 4 // DmaBufferAlignment
100 };
101
102 //
103 // Error code flag indicating whether or not an error code will be
104 // pushed on the stack if an exception occurs.
105 //
106 // 1 means an error code will be pushed, otherwise 0
107 //
108 // bit 0 - exception 0
109 // bit 1 - exception 1
110 // etc.
111 //
112 UINT32 mErrorCodeFlag = 0x00027d00;
113
114 //
115 // Local function prototypes
116 //
117
118 /**
119 Set Interrupt Descriptor Table Handler Address.
120
121 @param Index The Index of the interrupt descriptor table handle.
122 @param Handler Handler address.
123
124 **/
125 VOID
126 SetInterruptDescriptorTableHandlerAddress (
127 IN UINTN Index,
128 IN VOID *Handler OPTIONAL
129 );
130
131 //
132 // CPU Arch Protocol Functions
133 //
134
135
136 /**
137 Common exception handler.
138
139 @param InterruptType Exception type
140 @param SystemContext EFI_SYSTEM_CONTEXT
141
142 **/
143 VOID
144 EFIAPI
145 CommonExceptionHandler (
146 IN EFI_EXCEPTION_TYPE InterruptType,
147 IN EFI_SYSTEM_CONTEXT SystemContext
148 )
149 {
150 #if defined (MDE_CPU_IA32)
151 DEBUG ((
152 EFI_D_ERROR,
153 "!!!! IA32 Exception Type - %08x !!!!\n",
154 InterruptType
155 ));
156 if ((mErrorCodeFlag & (1 << InterruptType)) != 0) {
157 DEBUG ((
158 EFI_D_ERROR,
159 "ExceptionData - %08x\n",
160 SystemContext.SystemContextIa32->ExceptionData
161 ));
162 }
163 DEBUG ((
164 EFI_D_ERROR,
165 "CS - %04x, EIP - %08x, EFL - %08x, SS - %04x\n",
166 SystemContext.SystemContextIa32->Cs,
167 SystemContext.SystemContextIa32->Eip,
168 SystemContext.SystemContextIa32->Eflags,
169 SystemContext.SystemContextIa32->Ss
170 ));
171 DEBUG ((
172 EFI_D_ERROR,
173 "DS - %04x, ES - %04x, FS - %04x, GS - %04x\n",
174 SystemContext.SystemContextIa32->Ds,
175 SystemContext.SystemContextIa32->Es,
176 SystemContext.SystemContextIa32->Fs,
177 SystemContext.SystemContextIa32->Gs
178 ));
179 DEBUG ((
180 EFI_D_ERROR,
181 "EAX - %08x, EBX - %08x, ECX - %08x, EDX - %08x\n",
182 SystemContext.SystemContextIa32->Eax,
183 SystemContext.SystemContextIa32->Ebx,
184 SystemContext.SystemContextIa32->Ecx,
185 SystemContext.SystemContextIa32->Edx
186 ));
187 DEBUG ((
188 EFI_D_ERROR,
189 "ESP - %08x, EBP - %08x, ESI - %08x, EDI - %08x\n",
190 SystemContext.SystemContextIa32->Esp,
191 SystemContext.SystemContextIa32->Ebp,
192 SystemContext.SystemContextIa32->Esi,
193 SystemContext.SystemContextIa32->Edi
194 ));
195 DEBUG ((
196 EFI_D_ERROR,
197 "GDT - %08x LIM - %04x, IDT - %08x LIM - %04x\n",
198 SystemContext.SystemContextIa32->Gdtr[0],
199 SystemContext.SystemContextIa32->Gdtr[1],
200 SystemContext.SystemContextIa32->Idtr[0],
201 SystemContext.SystemContextIa32->Idtr[1]
202 ));
203 DEBUG ((
204 EFI_D_ERROR,
205 "LDT - %08x, TR - %08x\n",
206 SystemContext.SystemContextIa32->Ldtr,
207 SystemContext.SystemContextIa32->Tr
208 ));
209 DEBUG ((
210 EFI_D_ERROR,
211 "CR0 - %08x, CR2 - %08x, CR3 - %08x, CR4 - %08x\n",
212 SystemContext.SystemContextIa32->Cr0,
213 SystemContext.SystemContextIa32->Cr2,
214 SystemContext.SystemContextIa32->Cr3,
215 SystemContext.SystemContextIa32->Cr4
216 ));
217 DEBUG ((
218 EFI_D_ERROR,
219 "DR0 - %08x, DR1 - %08x, DR2 - %08x, DR3 - %08x\n",
220 SystemContext.SystemContextIa32->Dr0,
221 SystemContext.SystemContextIa32->Dr1,
222 SystemContext.SystemContextIa32->Dr2,
223 SystemContext.SystemContextIa32->Dr3
224 ));
225 DEBUG ((
226 EFI_D_ERROR,
227 "DR6 - %08x, DR7 - %08x\n",
228 SystemContext.SystemContextIa32->Dr6,
229 SystemContext.SystemContextIa32->Dr7
230 ));
231 #elif defined (MDE_CPU_X64)
232 DEBUG ((
233 EFI_D_ERROR,
234 "!!!! X64 Exception Type - %016lx !!!!\n",
235 (UINT64)InterruptType
236 ));
237 if ((mErrorCodeFlag & (1 << InterruptType)) != 0) {
238 DEBUG ((
239 EFI_D_ERROR,
240 "ExceptionData - %016lx\n",
241 SystemContext.SystemContextX64->ExceptionData
242 ));
243 }
244 DEBUG ((
245 EFI_D_ERROR,
246 "RIP - %016lx, RFL - %016lx\n",
247 SystemContext.SystemContextX64->Rip,
248 SystemContext.SystemContextX64->Rflags
249 ));
250 DEBUG ((
251 EFI_D_ERROR,
252 "RAX - %016lx, RCX - %016lx, RDX - %016lx\n",
253 SystemContext.SystemContextX64->Rax,
254 SystemContext.SystemContextX64->Rcx,
255 SystemContext.SystemContextX64->Rdx
256 ));
257 DEBUG ((
258 EFI_D_ERROR,
259 "RBX - %016lx, RSP - %016lx, RBP - %016lx\n",
260 SystemContext.SystemContextX64->Rbx,
261 SystemContext.SystemContextX64->Rsp,
262 SystemContext.SystemContextX64->Rbp
263 ));
264 DEBUG ((
265 EFI_D_ERROR,
266 "RSI - %016lx, RDI - %016lx\n",
267 SystemContext.SystemContextX64->Rsi,
268 SystemContext.SystemContextX64->Rdi
269 ));
270 DEBUG ((
271 EFI_D_ERROR,
272 "R8 - %016lx, R9 - %016lx, R10 - %016lx\n",
273 SystemContext.SystemContextX64->R8,
274 SystemContext.SystemContextX64->R9,
275 SystemContext.SystemContextX64->R10
276 ));
277 DEBUG ((
278 EFI_D_ERROR,
279 "R11 - %016lx, R12 - %016lx, R13 - %016lx\n",
280 SystemContext.SystemContextX64->R11,
281 SystemContext.SystemContextX64->R12,
282 SystemContext.SystemContextX64->R13
283 ));
284 DEBUG ((
285 EFI_D_ERROR,
286 "R14 - %016lx, R15 - %016lx\n",
287 SystemContext.SystemContextX64->R14,
288 SystemContext.SystemContextX64->R15
289 ));
290 DEBUG ((
291 EFI_D_ERROR,
292 "CS - %04lx, DS - %04lx, ES - %04lx, FS - %04lx, GS - %04lx, SS - %04lx\n",
293 SystemContext.SystemContextX64->Cs,
294 SystemContext.SystemContextX64->Ds,
295 SystemContext.SystemContextX64->Es,
296 SystemContext.SystemContextX64->Fs,
297 SystemContext.SystemContextX64->Gs,
298 SystemContext.SystemContextX64->Ss
299 ));
300 DEBUG ((
301 EFI_D_ERROR,
302 "GDT - %016lx; %04lx, IDT - %016lx; %04lx\n",
303 SystemContext.SystemContextX64->Gdtr[0],
304 SystemContext.SystemContextX64->Gdtr[1],
305 SystemContext.SystemContextX64->Idtr[0],
306 SystemContext.SystemContextX64->Idtr[1]
307 ));
308 DEBUG ((
309 EFI_D_ERROR,
310 "LDT - %016lx, TR - %016lx\n",
311 SystemContext.SystemContextX64->Ldtr,
312 SystemContext.SystemContextX64->Tr
313 ));
314 DEBUG ((
315 EFI_D_ERROR,
316 "CR0 - %016lx, CR2 - %016lx, CR3 - %016lx\n",
317 SystemContext.SystemContextX64->Cr0,
318 SystemContext.SystemContextX64->Cr2,
319 SystemContext.SystemContextX64->Cr3
320 ));
321 DEBUG ((
322 EFI_D_ERROR,
323 "CR4 - %016lx, CR8 - %016lx\n",
324 SystemContext.SystemContextX64->Cr4,
325 SystemContext.SystemContextX64->Cr8
326 ));
327 DEBUG ((
328 EFI_D_ERROR,
329 "DR0 - %016lx, DR1 - %016lx, DR2 - %016lx\n",
330 SystemContext.SystemContextX64->Dr0,
331 SystemContext.SystemContextX64->Dr1,
332 SystemContext.SystemContextX64->Dr2
333 ));
334 DEBUG ((
335 EFI_D_ERROR,
336 "DR3 - %016lx, DR6 - %016lx, DR7 - %016lx\n",
337 SystemContext.SystemContextX64->Dr3,
338 SystemContext.SystemContextX64->Dr6,
339 SystemContext.SystemContextX64->Dr7
340 ));
341 #else
342 #error CPU type not supported for exception information dump!
343 #endif
344
345 //
346 // Hang the system with CpuSleep so the processor will enter a lower power
347 // state.
348 //
349 while (TRUE) {
350 CpuSleep ();
351 };
352 }
353
354
355 /**
356 Flush CPU data cache. If the instruction cache is fully coherent
357 with all DMA operations then function can just return EFI_SUCCESS.
358
359 @param This Protocol instance structure
360 @param Start Physical address to start flushing from.
361 @param Length Number of bytes to flush. Round up to chipset
362 granularity.
363 @param FlushType Specifies the type of flush operation to perform.
364
365 @retval EFI_SUCCESS If cache was flushed
366 @retval EFI_UNSUPPORTED If flush type is not supported.
367 @retval EFI_DEVICE_ERROR If requested range could not be flushed.
368
369 **/
370 EFI_STATUS
371 EFIAPI
372 CpuFlushCpuDataCache (
373 IN EFI_CPU_ARCH_PROTOCOL *This,
374 IN EFI_PHYSICAL_ADDRESS Start,
375 IN UINT64 Length,
376 IN EFI_CPU_FLUSH_TYPE FlushType
377 )
378 {
379 if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {
380 AsmWbinvd ();
381 return EFI_SUCCESS;
382 } else if (FlushType == EfiCpuFlushTypeInvalidate) {
383 AsmInvd ();
384 return EFI_SUCCESS;
385 } else {
386 return EFI_UNSUPPORTED;
387 }
388 }
389
390
391 /**
392 Enables CPU interrupts.
393
394 @param This Protocol instance structure
395
396 @retval EFI_SUCCESS If interrupts were enabled in the CPU
397 @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
398
399 **/
400 EFI_STATUS
401 EFIAPI
402 CpuEnableInterrupt (
403 IN EFI_CPU_ARCH_PROTOCOL *This
404 )
405 {
406 EnableInterrupts ();
407
408 InterruptState = TRUE;
409 return EFI_SUCCESS;
410 }
411
412
413 /**
414 Disables CPU interrupts.
415
416 @param This Protocol instance structure
417
418 @retval EFI_SUCCESS If interrupts were disabled in the CPU.
419 @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
420
421 **/
422 EFI_STATUS
423 EFIAPI
424 CpuDisableInterrupt (
425 IN EFI_CPU_ARCH_PROTOCOL *This
426 )
427 {
428 DisableInterrupts ();
429
430 InterruptState = FALSE;
431 return EFI_SUCCESS;
432 }
433
434
435 /**
436 Return the state of interrupts.
437
438 @param This Protocol instance structure
439 @param State Pointer to the CPU's current interrupt state
440
441 @retval EFI_SUCCESS If interrupts were disabled in the CPU.
442 @retval EFI_INVALID_PARAMETER State is NULL.
443
444 **/
445 EFI_STATUS
446 EFIAPI
447 CpuGetInterruptState (
448 IN EFI_CPU_ARCH_PROTOCOL *This,
449 OUT BOOLEAN *State
450 )
451 {
452 if (State == NULL) {
453 return EFI_INVALID_PARAMETER;
454 }
455
456 *State = InterruptState;
457 return EFI_SUCCESS;
458 }
459
460
461 /**
462 Generates an INIT to the CPU.
463
464 @param This Protocol instance structure
465 @param InitType Type of CPU INIT to perform
466
467 @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
468 seen.
469 @retval EFI_DEVICE_ERROR If CPU INIT failed.
470 @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
471
472 **/
473 EFI_STATUS
474 EFIAPI
475 CpuInit (
476 IN EFI_CPU_ARCH_PROTOCOL *This,
477 IN EFI_CPU_INIT_TYPE InitType
478 )
479 {
480 return EFI_UNSUPPORTED;
481 }
482
483
484 /**
485 Registers a function to be called from the CPU interrupt handler.
486
487 @param This Protocol instance structure
488 @param InterruptType Defines which interrupt to hook. IA-32
489 valid range is 0x00 through 0xFF
490 @param InterruptHandler A pointer to a function of type
491 EFI_CPU_INTERRUPT_HANDLER that is called
492 when a processor interrupt occurs. A null
493 pointer is an error condition.
494
495 @retval EFI_SUCCESS If handler installed or uninstalled.
496 @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
497 for InterruptType was previously installed.
498 @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
499 InterruptType was not previously installed.
500 @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
501 is not supported.
502
503 **/
504 EFI_STATUS
505 EFIAPI
506 CpuRegisterInterruptHandler (
507 IN EFI_CPU_ARCH_PROTOCOL *This,
508 IN EFI_EXCEPTION_TYPE InterruptType,
509 IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
510 )
511 {
512 if (InterruptType < 0 || InterruptType > 0xff) {
513 return EFI_UNSUPPORTED;
514 }
515
516 if (InterruptHandler == NULL && ExternalVectorTable[InterruptType] == NULL) {
517 return EFI_INVALID_PARAMETER;
518 }
519
520 if (InterruptHandler != NULL && ExternalVectorTable[InterruptType] != NULL) {
521 return EFI_ALREADY_STARTED;
522 }
523
524 SetInterruptDescriptorTableHandlerAddress ((UINTN)InterruptType, NULL);
525 ExternalVectorTable[InterruptType] = InterruptHandler;
526 return EFI_SUCCESS;
527 }
528
529
530 /**
531 Returns a timer value from one of the CPU's internal timers. There is no
532 inherent time interval between ticks but is a function of the CPU frequency.
533
534 @param This - Protocol instance structure.
535 @param TimerIndex - Specifies which CPU timer is requested.
536 @param TimerValue - Pointer to the returned timer value.
537 @param TimerPeriod - A pointer to the amount of time that passes
538 in femtoseconds (10-15) for each increment
539 of TimerValue. If TimerValue does not
540 increment at a predictable rate, then 0 is
541 returned. The amount of time that has
542 passed between two calls to GetTimerValue()
543 can be calculated with the formula
544 (TimerValue2 - TimerValue1) * TimerPeriod.
545 This parameter is optional and may be NULL.
546
547 @retval EFI_SUCCESS - If the CPU timer count was returned.
548 @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
549 @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
550 @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
551
552 **/
553 EFI_STATUS
554 EFIAPI
555 CpuGetTimerValue (
556 IN EFI_CPU_ARCH_PROTOCOL *This,
557 IN UINT32 TimerIndex,
558 OUT UINT64 *TimerValue,
559 OUT UINT64 *TimerPeriod OPTIONAL
560 )
561 {
562 if (TimerValue == NULL) {
563 return EFI_INVALID_PARAMETER;
564 }
565
566 if (TimerIndex != 0) {
567 return EFI_INVALID_PARAMETER;
568 }
569
570 *TimerValue = AsmReadTsc ();
571
572 if (TimerPeriod != NULL) {
573 //
574 // BugBug: Hard coded. Don't know how to do this generically
575 //
576 *TimerPeriod = 1000000000;
577 }
578
579 return EFI_SUCCESS;
580 }
581
582
583 /**
584 Set memory cacheability attributes for given range of memeory.
585
586 @param This Protocol instance structure
587 @param BaseAddress Specifies the start address of the
588 memory range
589 @param Length Specifies the length of the memory range
590 @param Attributes The memory cacheability for the memory range
591
592 @retval EFI_SUCCESS If the cacheability of that memory range is
593 set successfully
594 @retval EFI_UNSUPPORTED If the desired operation cannot be done
595 @retval EFI_INVALID_PARAMETER The input parameter is not correct,
596 such as Length = 0
597
598 **/
599 EFI_STATUS
600 EFIAPI
601 CpuSetMemoryAttributes (
602 IN EFI_CPU_ARCH_PROTOCOL *This,
603 IN EFI_PHYSICAL_ADDRESS BaseAddress,
604 IN UINT64 Length,
605 IN UINT64 Attributes
606 )
607 {
608 RETURN_STATUS Status;
609 MTRR_MEMORY_CACHE_TYPE CacheType;
610
611 if (!IsMtrrSupported ()) {
612 return EFI_UNSUPPORTED;
613 }
614
615 //
616 // If this function is called because GCD SetMemorySpaceAttributes () is called
617 // by RefreshGcdMemoryAttributes (), then we are just synchronzing GCD memory
618 // map with MTRR values. So there is no need to modify MTRRs, just return immediately
619 // to avoid unnecessary computing.
620 //
621 if (mIsFlushingGCD) {
622 DEBUG((EFI_D_ERROR, " Flushing GCD\n"));
623 return EFI_SUCCESS;
624 }
625
626 switch (Attributes) {
627 case EFI_MEMORY_UC:
628 CacheType = CacheUncacheable;
629 break;
630
631 case EFI_MEMORY_WC:
632 CacheType = CacheWriteCombining;
633 break;
634
635 case EFI_MEMORY_WT:
636 CacheType = CacheWriteThrough;
637 break;
638
639 case EFI_MEMORY_WP:
640 CacheType = CacheWriteProtected;
641 break;
642
643 case EFI_MEMORY_WB:
644 CacheType = CacheWriteBack;
645 break;
646
647 default:
648 return EFI_UNSUPPORTED;
649 }
650 //
651 // call MTRR libary function
652 //
653 Status = MtrrSetMemoryAttribute (
654 BaseAddress,
655 Length,
656 CacheType
657 );
658
659 return (EFI_STATUS) Status;
660 }
661
662 /**
663 Initializes the valid bits mask and valid address mask for MTRRs.
664
665 This function initializes the valid bits mask and valid address mask for MTRRs.
666
667 **/
668 VOID
669 InitializeMtrrMask (
670 VOID
671 )
672 {
673 UINT32 RegEax;
674 UINT8 PhysicalAddressBits;
675
676 AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
677
678 if (RegEax >= 0x80000008) {
679 AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
680
681 PhysicalAddressBits = (UINT8) RegEax;
682
683 mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;
684 mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;
685 } else {
686 mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;
687 mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
688 }
689 }
690
691 /**
692 Gets GCD Mem Space type from MTRR Type.
693
694 This function gets GCD Mem Space type from MTRR Type.
695
696 @param MtrrAttributes MTRR memory type
697
698 @return GCD Mem Space type
699
700 **/
701 UINT64
702 GetMemorySpaceAttributeFromMtrrType (
703 IN UINT8 MtrrAttributes
704 )
705 {
706 switch (MtrrAttributes) {
707 case MTRR_CACHE_UNCACHEABLE:
708 return EFI_MEMORY_UC;
709 case MTRR_CACHE_WRITE_COMBINING:
710 return EFI_MEMORY_WC;
711 case MTRR_CACHE_WRITE_THROUGH:
712 return EFI_MEMORY_WT;
713 case MTRR_CACHE_WRITE_PROTECTED:
714 return EFI_MEMORY_WP;
715 case MTRR_CACHE_WRITE_BACK:
716 return EFI_MEMORY_WB;
717 default:
718 return 0;
719 }
720 }
721
722 /**
723 Searches memory descriptors covered by given memory range.
724
725 This function searches into the Gcd Memory Space for descriptors
726 (from StartIndex to EndIndex) that contains the memory range
727 specified by BaseAddress and Length.
728
729 @param MemorySpaceMap Gcd Memory Space Map as array.
730 @param NumberOfDescriptors Number of descriptors in map.
731 @param BaseAddress BaseAddress for the requested range.
732 @param Length Length for the requested range.
733 @param StartIndex Start index into the Gcd Memory Space Map.
734 @param EndIndex End index into the Gcd Memory Space Map.
735
736 @retval EFI_SUCCESS Search successfully.
737 @retval EFI_NOT_FOUND The requested descriptors does not exist.
738
739 **/
740 EFI_STATUS
741 SearchGcdMemorySpaces (
742 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
743 IN UINTN NumberOfDescriptors,
744 IN EFI_PHYSICAL_ADDRESS BaseAddress,
745 IN UINT64 Length,
746 OUT UINTN *StartIndex,
747 OUT UINTN *EndIndex
748 )
749 {
750 UINTN Index;
751
752 *StartIndex = 0;
753 *EndIndex = 0;
754 for (Index = 0; Index < NumberOfDescriptors; Index++) {
755 if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&
756 BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
757 *StartIndex = Index;
758 }
759 if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&
760 BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
761 *EndIndex = Index;
762 return EFI_SUCCESS;
763 }
764 }
765 return EFI_NOT_FOUND;
766 }
767
768 /**
769 Sets the attributes for a specified range in Gcd Memory Space Map.
770
771 This function sets the attributes for a specified range in
772 Gcd Memory Space Map.
773
774 @param MemorySpaceMap Gcd Memory Space Map as array
775 @param NumberOfDescriptors Number of descriptors in map
776 @param BaseAddress BaseAddress for the range
777 @param Length Length for the range
778 @param Attributes Attributes to set
779
780 @retval EFI_SUCCESS Memory attributes set successfully
781 @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space
782
783 **/
784 EFI_STATUS
785 SetGcdMemorySpaceAttributes (
786 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
787 IN UINTN NumberOfDescriptors,
788 IN EFI_PHYSICAL_ADDRESS BaseAddress,
789 IN UINT64 Length,
790 IN UINT64 Attributes
791 )
792 {
793 EFI_STATUS Status;
794 UINTN Index;
795 UINTN StartIndex;
796 UINTN EndIndex;
797 EFI_PHYSICAL_ADDRESS RegionStart;
798 UINT64 RegionLength;
799
800 //
801 // Get all memory descriptors covered by the memory range
802 //
803 Status = SearchGcdMemorySpaces (
804 MemorySpaceMap,
805 NumberOfDescriptors,
806 BaseAddress,
807 Length,
808 &StartIndex,
809 &EndIndex
810 );
811 if (EFI_ERROR (Status)) {
812 return Status;
813 }
814
815 //
816 // Go through all related descriptors and set attributes accordingly
817 //
818 for (Index = StartIndex; Index <= EndIndex; Index++) {
819 if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
820 continue;
821 }
822 //
823 // Calculate the start and end address of the overlapping range
824 //
825 if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {
826 RegionStart = BaseAddress;
827 } else {
828 RegionStart = MemorySpaceMap[Index].BaseAddress;
829 }
830 if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
831 RegionLength = BaseAddress + Length - RegionStart;
832 } else {
833 RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
834 }
835 //
836 // Set memory attributes according to MTRR attribute and the original attribute of descriptor
837 //
838 gDS->SetMemorySpaceAttributes (
839 RegionStart,
840 RegionLength,
841 (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
842 );
843 }
844
845 return EFI_SUCCESS;
846 }
847
848
849 /**
850 Refreshes the GCD Memory Space attributes according to MTRRs.
851
852 This function refreshes the GCD Memory Space attributes according to MTRRs.
853
854 **/
855 VOID
856 RefreshGcdMemoryAttributes (
857 VOID
858 )
859 {
860 EFI_STATUS Status;
861 UINTN Index;
862 UINTN SubIndex;
863 UINT64 RegValue;
864 EFI_PHYSICAL_ADDRESS BaseAddress;
865 UINT64 Length;
866 UINT64 Attributes;
867 UINT64 CurrentAttributes;
868 UINT8 MtrrType;
869 UINTN NumberOfDescriptors;
870 EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
871 UINT64 DefaultAttributes;
872 VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
873 MTRR_FIXED_SETTINGS MtrrFixedSettings;
874 UINT32 FirmwareVariableMtrrCount;
875
876 if (!IsMtrrSupported ()) {
877 return;
878 }
879
880 FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();
881 ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);
882
883 // mIsFlushingGCD = TRUE;
884 mIsFlushingGCD = FALSE;
885 MemorySpaceMap = NULL;
886
887 //
888 // Initialize the valid bits mask and valid address mask for MTRRs
889 //
890 InitializeMtrrMask ();
891
892 //
893 // Get the memory attribute of variable MTRRs
894 //
895 MtrrGetMemoryAttributeInVariableMtrr (
896 mValidMtrrBitsMask,
897 mValidMtrrAddressMask,
898 VariableMtrr
899 );
900
901 //
902 // Get the memory space map from GCD
903 //
904 Status = gDS->GetMemorySpaceMap (
905 &NumberOfDescriptors,
906 &MemorySpaceMap
907 );
908 ASSERT_EFI_ERROR (Status);
909
910 DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (mDefaultMemoryType);
911
912 //
913 // Set default attributes to all spaces.
914 //
915 for (Index = 0; Index < NumberOfDescriptors; Index++) {
916 if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
917 continue;
918 }
919 gDS->SetMemorySpaceAttributes (
920 MemorySpaceMap[Index].BaseAddress,
921 MemorySpaceMap[Index].Length,
922 (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) |
923 (MemorySpaceMap[Index].Capabilities & DefaultAttributes)
924 );
925 }
926
927 //
928 // Go for variable MTRRs with WB attribute
929 //
930 for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
931 if (VariableMtrr[Index].Valid &&
932 VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) {
933 SetGcdMemorySpaceAttributes (
934 MemorySpaceMap,
935 NumberOfDescriptors,
936 VariableMtrr[Index].BaseAddress,
937 VariableMtrr[Index].Length,
938 EFI_MEMORY_WB
939 );
940 }
941 }
942 //
943 // Go for variable MTRRs with Non-WB attribute
944 //
945 for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
946 if (VariableMtrr[Index].Valid &&
947 VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK) {
948 Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8) VariableMtrr[Index].Type);
949 SetGcdMemorySpaceAttributes (
950 MemorySpaceMap,
951 NumberOfDescriptors,
952 VariableMtrr[Index].BaseAddress,
953 VariableMtrr[Index].Length,
954 Attributes
955 );
956 }
957 }
958
959 //
960 // Go for fixed MTRRs
961 //
962 Attributes = 0;
963 BaseAddress = 0;
964 Length = 0;
965 MtrrGetFixedMtrr (&MtrrFixedSettings);
966 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {
967 RegValue = MtrrFixedSettings.Mtrr[Index];
968 //
969 // Check for continuous fixed MTRR sections
970 //
971 for (SubIndex = 0; SubIndex < 8; SubIndex++) {
972 MtrrType = (UINT8) RShiftU64 (RegValue, SubIndex * 8);
973 CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType);
974 if (Length == 0) {
975 //
976 // A new MTRR attribute begins
977 //
978 Attributes = CurrentAttributes;
979 } else {
980 //
981 // If fixed MTRR attribute changed, then set memory attribute for previous atrribute
982 //
983 if (CurrentAttributes != Attributes) {
984 SetGcdMemorySpaceAttributes (
985 MemorySpaceMap,
986 NumberOfDescriptors,
987 BaseAddress,
988 Length,
989 Attributes
990 );
991 BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex;
992 Length = 0;
993 Attributes = CurrentAttributes;
994 }
995 }
996 Length += mFixedMtrrTable[Index].Length;
997 }
998 }
999 //
1000 // Handle the last fixed MTRR region
1001 //
1002 SetGcdMemorySpaceAttributes (
1003 MemorySpaceMap,
1004 NumberOfDescriptors,
1005 BaseAddress,
1006 Length,
1007 Attributes
1008 );
1009
1010 //
1011 // Free memory space map allocated by GCD service GetMemorySpaceMap ()
1012 //
1013 if (MemorySpaceMap != NULL) {
1014 FreePool (MemorySpaceMap);
1015 }
1016
1017 mIsFlushingGCD = FALSE;
1018 }
1019
1020 /**
1021 Set Interrupt Descriptor Table Handler Address.
1022
1023 @param Index The Index of the interrupt descriptor table handle.
1024 @param Handler Handler address.
1025
1026 **/
1027 VOID
1028 SetInterruptDescriptorTableHandlerAddress (
1029 IN UINTN Index,
1030 IN VOID *Handler OPTIONAL
1031 )
1032 {
1033 UINTN UintnHandler;
1034
1035 if (Handler != NULL) {
1036 UintnHandler = (UINTN) Handler;
1037 } else {
1038 UintnHandler = ((UINTN) AsmIdtVector00) + (8 * Index);
1039 }
1040
1041 gIdtTable[Index].Bits.OffsetLow = (UINT16)UintnHandler;
1042 gIdtTable[Index].Bits.Reserved_0 = 0;
1043 gIdtTable[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
1044 gIdtTable[Index].Bits.OffsetHigh = (UINT16)(UintnHandler >> 16);
1045 #if defined (MDE_CPU_X64)
1046 gIdtTable[Index].Bits.OffsetUpper = (UINT32)(UintnHandler >> 32);
1047 gIdtTable[Index].Bits.Reserved_1 = 0;
1048 #endif
1049 }
1050
1051
1052 /**
1053 Initialize Interrupt Descriptor Table for interrupt handling.
1054
1055 **/
1056 VOID
1057 InitInterruptDescriptorTable (
1058 VOID
1059 )
1060 {
1061 EFI_STATUS Status;
1062 IA32_DESCRIPTOR OldIdtPtr;
1063 IA32_IDT_GATE_DESCRIPTOR *OldIdt;
1064 UINTN OldIdtSize;
1065 VOID *IdtPtrAlignmentBuffer;
1066 IA32_DESCRIPTOR *IdtPtr;
1067 UINTN Index;
1068 UINT16 CurrentCs;
1069 VOID *IntHandler;
1070
1071 SetMem (ExternalVectorTable, sizeof(ExternalVectorTable), 0);
1072
1073 //
1074 // Get original IDT address and size.
1075 //
1076 AsmReadIdtr ((IA32_DESCRIPTOR *) &OldIdtPtr);
1077
1078 if ((OldIdtPtr.Base != 0) && ((OldIdtPtr.Limit & 7) == 7)) {
1079 OldIdt = (IA32_IDT_GATE_DESCRIPTOR*) OldIdtPtr.Base;
1080 OldIdtSize = (OldIdtPtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR);
1081 } else {
1082 OldIdt = NULL;
1083 OldIdtSize = 0;
1084 }
1085
1086 //
1087 // Intialize IDT
1088 //
1089 CurrentCs = AsmReadCs();
1090 for (Index = 0; Index < INTERRUPT_VECTOR_NUMBER; Index ++) {
1091 //
1092 // If the old IDT had a handler for this interrupt, then
1093 // preserve it.
1094 //
1095 if (Index < OldIdtSize) {
1096 IntHandler =
1097 (VOID*) (
1098 OldIdt[Index].Bits.OffsetLow +
1099 (OldIdt[Index].Bits.OffsetHigh << 16)
1100 #if defined (MDE_CPU_X64)
1101 + (((UINTN) OldIdt[Index].Bits.OffsetUpper) << 32)
1102 #endif
1103 );
1104 } else {
1105 IntHandler = NULL;
1106 }
1107
1108 gIdtTable[Index].Bits.Selector = CurrentCs;
1109 gIdtTable[Index].Bits.Reserved_0 = 0;
1110 gIdtTable[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
1111 SetInterruptDescriptorTableHandlerAddress (Index, IntHandler);
1112 }
1113
1114 //
1115 // Load IDT Pointer
1116 //
1117 IdtPtrAlignmentBuffer = AllocatePool (sizeof (*IdtPtr) + 16);
1118 IdtPtr = ALIGN_POINTER (IdtPtrAlignmentBuffer, 16);
1119 IdtPtr->Base = (UINT32)(((UINTN)(VOID*) gIdtTable) & (BASE_4GB-1));
1120 IdtPtr->Limit = (UINT16) (sizeof (gIdtTable) - 1);
1121
1122 AsmWriteIdtr (IdtPtr);
1123
1124 FreePool (IdtPtrAlignmentBuffer);
1125
1126 //
1127 // Initialize Exception Handlers
1128 //
1129 for (Index = 0; Index < 32; Index++) {
1130 Status = CpuRegisterInterruptHandler (&gCpu, Index, CommonExceptionHandler);
1131 ASSERT_EFI_ERROR (Status);
1132 }
1133
1134 //
1135 // Set the pointer to the array of C based exception handling routines.
1136 //
1137 InitializeExternalVectorTablePtr (ExternalVectorTable);
1138
1139 }
1140
1141
1142 /**
1143 Initialize the state information for the CPU Architectural Protocol.
1144
1145 @param ImageHandle Image handle this driver.
1146 @param SystemTable Pointer to the System Table.
1147
1148 @retval EFI_SUCCESS Thread can be successfully created
1149 @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
1150 @retval EFI_DEVICE_ERROR Cannot create the thread
1151
1152 **/
1153 EFI_STATUS
1154 EFIAPI
1155 InitializeCpu (
1156 IN EFI_HANDLE ImageHandle,
1157 IN EFI_SYSTEM_TABLE *SystemTable
1158 )
1159 {
1160 EFI_STATUS Status;
1161
1162 //
1163 // Make sure interrupts are disabled
1164 //
1165 DisableInterrupts ();
1166
1167 //
1168 // Init GDT for DXE
1169 //
1170 InitGlobalDescriptorTable ();
1171
1172 //
1173 // Setup IDT pointer, IDT and interrupt entry points
1174 //
1175 InitInterruptDescriptorTable ();
1176
1177 //
1178 // Install CPU Architectural Protocol
1179 //
1180 Status = gBS->InstallMultipleProtocolInterfaces (
1181 &mCpuHandle,
1182 &gEfiCpuArchProtocolGuid, &gCpu,
1183 NULL
1184 );
1185 ASSERT_EFI_ERROR (Status);
1186
1187 //
1188 // Refresh GCD memory space map according to MTRR value.
1189 //
1190 RefreshGcdMemoryAttributes ();
1191
1192 return Status;
1193 }
1194
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