UefiCpuPkg/CpuDxe/CpuDxe.c

   1 /** @file
   2   CPU DXE Module.
   3
   4   Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include "CpuDxe.h"
  16
  17 //
  18 // Global Variables
  19 //
  20 IA32_IDT_GATE_DESCRIPTOR  gIdtTable[INTERRUPT_VECTOR_NUMBER] = { 0 };
  21
  22 EFI_CPU_INTERRUPT_HANDLER ExternalVectorTable[0x100];
  23 BOOLEAN                   InterruptState = FALSE;
  24 EFI_HANDLE                mCpuHandle = NULL;
  25 BOOLEAN                   mIsFlushingGCD;
  26 UINT8                     mDefaultMemoryType    = MTRR_CACHE_WRITE_BACK;
  27 UINT64                    mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
  28 UINT64                    mValidMtrrBitsMask    = MTRR_LIB_MSR_VALID_MASK;
  29
  30 FIXED_MTRR    mFixedMtrrTable[] = {
  31   {
  32     MTRR_LIB_IA32_MTRR_FIX64K_00000,
  33     0,
  34     0x10000
  35   },
  36   {
  37     MTRR_LIB_IA32_MTRR_FIX16K_80000,
  38     0x80000,
  39     0x4000
  40   },
  41   {
  42     MTRR_LIB_IA32_MTRR_FIX16K_A0000,
  43     0xA0000,
  44     0x4000
  45   },
  46   {
  47     MTRR_LIB_IA32_MTRR_FIX4K_C0000,
  48     0xC0000,
  49     0x1000
  50   },
  51   {
  52     MTRR_LIB_IA32_MTRR_FIX4K_C8000,
  53     0xC8000,
  54     0x1000
  55   },
  56   {
  57     MTRR_LIB_IA32_MTRR_FIX4K_D0000,
  58     0xD0000,
  59     0x1000
  60   },
  61   {
  62     MTRR_LIB_IA32_MTRR_FIX4K_D8000,
  63     0xD8000,
  64     0x1000
  65   },
  66   {
  67     MTRR_LIB_IA32_MTRR_FIX4K_E0000,
  68     0xE0000,
  69     0x1000
  70   },
  71   {
  72     MTRR_LIB_IA32_MTRR_FIX4K_E8000,
  73     0xE8000,
  74     0x1000
  75   },
  76   {
  77     MTRR_LIB_IA32_MTRR_FIX4K_F0000,
  78     0xF0000,
  79     0x1000
  80   },
  81   {
  82     MTRR_LIB_IA32_MTRR_FIX4K_F8000,
  83     0xF8000,
  84     0x1000
  85   },
  86 };
  87
  88
  89 EFI_CPU_ARCH_PROTOCOL  gCpu = {
  90   CpuFlushCpuDataCache,
  91   CpuEnableInterrupt,
  92   CpuDisableInterrupt,
  93   CpuGetInterruptState,
  94   CpuInit,
  95   CpuRegisterInterruptHandler,
  96   CpuGetTimerValue,
  97   CpuSetMemoryAttributes,
  98   1,                          // NumberOfTimers
  99   4                           // DmaBufferAlignment
 100 };
 101
 102 //
 103 // Error code flag indicating whether or not an error code will be
 104 // pushed on the stack if an exception occurs.
 105 //
 106 // 1 means an error code will be pushed, otherwise 0
 107 //
 108 // bit 0 - exception 0
 109 // bit 1 - exception 1
 110 // etc.
 111 //
 112 UINT32 mErrorCodeFlag = 0x00027d00;
 113
 114 //
 115 // Local function prototypes
 116 //
 117
 118 /**
 119   Set Interrupt Descriptor Table Handler Address.
 120
 121   @param Index        The Index of the interrupt descriptor table handle.
 122   @param Handler      Handler address.
 123
 124 **/
 125 VOID
 126 SetInterruptDescriptorTableHandlerAddress (
 127   IN UINTN Index,
 128   IN VOID  *Handler  OPTIONAL
 129   );
 130
 131 //
 132 // CPU Arch Protocol Functions
 133 //
 134
 135
 136 /**
 137   Common exception handler.
 138
 139   @param  InterruptType  Exception type
 140   @param  SystemContext  EFI_SYSTEM_CONTEXT
 141
 142 **/
 143 VOID
 144 EFIAPI
 145 CommonExceptionHandler (
 146   IN EFI_EXCEPTION_TYPE   InterruptType,
 147   IN EFI_SYSTEM_CONTEXT   SystemContext
 148   )
 149 {
 150 #if defined (MDE_CPU_IA32)
 151   DEBUG ((
 152     EFI_D_ERROR,
 153     "!!!! IA32 Exception Type - %08x !!!!\n",
 154     InterruptType
 155     ));
 156   if ((mErrorCodeFlag & (1 << InterruptType)) != 0) {
 157     DEBUG ((
 158       EFI_D_ERROR,
 159       "ExceptionData - %08x\n",
 160       SystemContext.SystemContextIa32->ExceptionData
 161       ));
 162   }
 163   DEBUG ((
 164     EFI_D_ERROR,
 165     "CS  - %04x,     EIP - %08x, EFL - %08x, SS  - %04x\n",
 166     SystemContext.SystemContextIa32->Cs,
 167     SystemContext.SystemContextIa32->Eip,
 168     SystemContext.SystemContextIa32->Eflags,
 169     SystemContext.SystemContextIa32->Ss
 170     ));
 171   DEBUG ((
 172     EFI_D_ERROR,
 173     "DS  - %04x,     ES  - %04x,     FS  - %04x,     GS  - %04x\n",
 174     SystemContext.SystemContextIa32->Ds,
 175     SystemContext.SystemContextIa32->Es,
 176     SystemContext.SystemContextIa32->Fs,
 177     SystemContext.SystemContextIa32->Gs
 178     ));
 179   DEBUG ((
 180     EFI_D_ERROR,
 181     "EAX - %08x, EBX - %08x, ECX - %08x, EDX - %08x\n",
 182     SystemContext.SystemContextIa32->Eax,
 183     SystemContext.SystemContextIa32->Ebx,
 184     SystemContext.SystemContextIa32->Ecx,
 185     SystemContext.SystemContextIa32->Edx
 186     ));
 187   DEBUG ((
 188     EFI_D_ERROR,
 189     "ESP - %08x, EBP - %08x, ESI - %08x, EDI - %08x\n",
 190     SystemContext.SystemContextIa32->Esp,
 191     SystemContext.SystemContextIa32->Ebp,
 192     SystemContext.SystemContextIa32->Esi,
 193     SystemContext.SystemContextIa32->Edi
 194     ));
 195   DEBUG ((
 196     EFI_D_ERROR,
 197     "GDT - %08x  LIM - %04x,     IDT - %08x  LIM - %04x\n",
 198     SystemContext.SystemContextIa32->Gdtr[0],
 199     SystemContext.SystemContextIa32->Gdtr[1],
 200     SystemContext.SystemContextIa32->Idtr[0],
 201     SystemContext.SystemContextIa32->Idtr[1]
 202     ));
 203   DEBUG ((
 204     EFI_D_ERROR,
 205     "LDT - %08x, TR  - %08x\n",
 206     SystemContext.SystemContextIa32->Ldtr,
 207     SystemContext.SystemContextIa32->Tr
 208     ));
 209   DEBUG ((
 210     EFI_D_ERROR,
 211     "CR0 - %08x, CR2 - %08x, CR3 - %08x, CR4 - %08x\n",
 212     SystemContext.SystemContextIa32->Cr0,
 213     SystemContext.SystemContextIa32->Cr2,
 214     SystemContext.SystemContextIa32->Cr3,
 215     SystemContext.SystemContextIa32->Cr4
 216     ));
 217   DEBUG ((
 218     EFI_D_ERROR,
 219     "DR0 - %08x, DR1 - %08x, DR2 - %08x, DR3 - %08x\n",
 220     SystemContext.SystemContextIa32->Dr0,
 221     SystemContext.SystemContextIa32->Dr1,
 222     SystemContext.SystemContextIa32->Dr2,
 223     SystemContext.SystemContextIa32->Dr3
 224     ));
 225   DEBUG ((
 226     EFI_D_ERROR,
 227     "DR6 - %08x, DR7 - %08x\n",
 228     SystemContext.SystemContextIa32->Dr6,
 229     SystemContext.SystemContextIa32->Dr7
 230     ));
 231 #elif defined (MDE_CPU_X64)
 232   DEBUG ((
 233     EFI_D_ERROR,
 234     "!!!! X64 Exception Type - %016lx !!!!\n",
 235     (UINT64)InterruptType
 236     ));
 237   if ((mErrorCodeFlag & (1 << InterruptType)) != 0) {
 238     DEBUG ((
 239       EFI_D_ERROR,
 240       "ExceptionData - %016lx\n",
 241       SystemContext.SystemContextX64->ExceptionData
 242       ));
 243   }
 244   DEBUG ((
 245     EFI_D_ERROR,
 246     "RIP - %016lx, RFL - %016lx\n",
 247     SystemContext.SystemContextX64->Rip,
 248     SystemContext.SystemContextX64->Rflags
 249     ));
 250   DEBUG ((
 251     EFI_D_ERROR,
 252     "RAX - %016lx, RCX - %016lx, RDX - %016lx\n",
 253     SystemContext.SystemContextX64->Rax,
 254     SystemContext.SystemContextX64->Rcx,
 255     SystemContext.SystemContextX64->Rdx
 256     ));
 257   DEBUG ((
 258     EFI_D_ERROR,
 259     "RBX - %016lx, RSP - %016lx, RBP - %016lx\n",
 260     SystemContext.SystemContextX64->Rbx,
 261     SystemContext.SystemContextX64->Rsp,
 262     SystemContext.SystemContextX64->Rbp
 263     ));
 264   DEBUG ((
 265     EFI_D_ERROR,
 266     "RSI - %016lx, RDI - %016lx\n",
 267     SystemContext.SystemContextX64->Rsi,
 268     SystemContext.SystemContextX64->Rdi
 269     ));
 270   DEBUG ((
 271     EFI_D_ERROR,
 272     "R8  - %016lx, R9  - %016lx, R10 - %016lx\n",
 273     SystemContext.SystemContextX64->R8,
 274     SystemContext.SystemContextX64->R9,
 275     SystemContext.SystemContextX64->R10
 276     ));
 277   DEBUG ((
 278     EFI_D_ERROR,
 279     "R11 - %016lx, R12 - %016lx, R13 - %016lx\n",
 280     SystemContext.SystemContextX64->R11,
 281     SystemContext.SystemContextX64->R12,
 282     SystemContext.SystemContextX64->R13
 283     ));
 284   DEBUG ((
 285     EFI_D_ERROR,
 286     "R14 - %016lx, R15 - %016lx\n",
 287     SystemContext.SystemContextX64->R14,
 288     SystemContext.SystemContextX64->R15
 289     ));
 290   DEBUG ((
 291     EFI_D_ERROR,
 292     "CS  - %04lx, DS  - %04lx, ES  - %04lx, FS  - %04lx, GS  - %04lx, SS  - %04lx\n",
 293     SystemContext.SystemContextX64->Cs,
 294     SystemContext.SystemContextX64->Ds,
 295     SystemContext.SystemContextX64->Es,
 296     SystemContext.SystemContextX64->Fs,
 297     SystemContext.SystemContextX64->Gs,
 298     SystemContext.SystemContextX64->Ss
 299     ));
 300   DEBUG ((
 301     EFI_D_ERROR,
 302     "GDT - %016lx; %04lx,                   IDT - %016lx; %04lx\n",
 303     SystemContext.SystemContextX64->Gdtr[0],
 304     SystemContext.SystemContextX64->Gdtr[1],
 305     SystemContext.SystemContextX64->Idtr[0],
 306     SystemContext.SystemContextX64->Idtr[1]
 307     ));
 308   DEBUG ((
 309     EFI_D_ERROR,
 310     "LDT - %016lx, TR  - %016lx\n",
 311     SystemContext.SystemContextX64->Ldtr,
 312     SystemContext.SystemContextX64->Tr
 313     ));
 314   DEBUG ((
 315     EFI_D_ERROR,
 316     "CR0 - %016lx, CR2 - %016lx, CR3 - %016lx\n",
 317     SystemContext.SystemContextX64->Cr0,
 318     SystemContext.SystemContextX64->Cr2,
 319     SystemContext.SystemContextX64->Cr3
 320     ));
 321   DEBUG ((
 322     EFI_D_ERROR,
 323     "CR4 - %016lx, CR8 - %016lx\n",
 324     SystemContext.SystemContextX64->Cr4,
 325     SystemContext.SystemContextX64->Cr8
 326     ));
 327   DEBUG ((
 328     EFI_D_ERROR,
 329     "DR0 - %016lx, DR1 - %016lx, DR2 - %016lx\n",
 330     SystemContext.SystemContextX64->Dr0,
 331     SystemContext.SystemContextX64->Dr1,
 332     SystemContext.SystemContextX64->Dr2
 333     ));
 334   DEBUG ((
 335     EFI_D_ERROR,
 336     "DR3 - %016lx, DR6 - %016lx, DR7 - %016lx\n",
 337     SystemContext.SystemContextX64->Dr3,
 338     SystemContext.SystemContextX64->Dr6,
 339     SystemContext.SystemContextX64->Dr7
 340     ));
 341 #else
 342 #error CPU type not supported for exception information dump!
 343 #endif
 344
 345   //
 346   // Hang the system with CpuSleep so the processor will enter a lower power
 347   // state.
 348   //
 349   while (TRUE) {
 350     CpuSleep ();
 351   };
 352 }
 353
 354
 355 /**
 356   Flush CPU data cache. If the instruction cache is fully coherent
 357   with all DMA operations then function can just return EFI_SUCCESS.
 358
 359   @param  This              Protocol instance structure
 360   @param  Start             Physical address to start flushing from.
 361   @param  Length            Number of bytes to flush. Round up to chipset
 362                             granularity.
 363   @param  FlushType         Specifies the type of flush operation to perform.
 364
 365   @retval EFI_SUCCESS       If cache was flushed
 366   @retval EFI_UNSUPPORTED   If flush type is not supported.
 367   @retval EFI_DEVICE_ERROR  If requested range could not be flushed.
 368
 369 **/
 370 EFI_STATUS
 371 EFIAPI
 372 CpuFlushCpuDataCache (
 373   IN EFI_CPU_ARCH_PROTOCOL     *This,
 374   IN EFI_PHYSICAL_ADDRESS      Start,
 375   IN UINT64                    Length,
 376   IN EFI_CPU_FLUSH_TYPE        FlushType
 377   )
 378 {
 379   if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {
 380     AsmWbinvd ();
 381     return EFI_SUCCESS;
 382   } else if (FlushType == EfiCpuFlushTypeInvalidate) {
 383     AsmInvd ();
 384     return EFI_SUCCESS;
 385   } else {
 386     return EFI_UNSUPPORTED;
 387   }
 388 }
 389
 390
 391 /**
 392   Enables CPU interrupts.
 393
 394   @param  This              Protocol instance structure
 395
 396   @retval EFI_SUCCESS       If interrupts were enabled in the CPU
 397   @retval EFI_DEVICE_ERROR  If interrupts could not be enabled on the CPU.
 398
 399 **/
 400 EFI_STATUS
 401 EFIAPI
 402 CpuEnableInterrupt (
 403   IN EFI_CPU_ARCH_PROTOCOL          *This
 404   )
 405 {
 406   EnableInterrupts ();
 407
 408   InterruptState = TRUE;
 409   return EFI_SUCCESS;
 410 }
 411
 412
 413 /**
 414   Disables CPU interrupts.
 415
 416   @param  This              Protocol instance structure
 417
 418   @retval EFI_SUCCESS       If interrupts were disabled in the CPU.
 419   @retval EFI_DEVICE_ERROR  If interrupts could not be disabled on the CPU.
 420
 421 **/
 422 EFI_STATUS
 423 EFIAPI
 424 CpuDisableInterrupt (
 425   IN EFI_CPU_ARCH_PROTOCOL     *This
 426   )
 427 {
 428   DisableInterrupts ();
 429
 430   InterruptState = FALSE;
 431   return EFI_SUCCESS;
 432 }
 433
 434
 435 /**
 436   Return the state of interrupts.
 437
 438   @param  This                   Protocol instance structure
 439   @param  State                  Pointer to the CPU's current interrupt state
 440
 441   @retval EFI_SUCCESS            If interrupts were disabled in the CPU.
 442   @retval EFI_INVALID_PARAMETER  State is NULL.
 443
 444 **/
 445 EFI_STATUS
 446 EFIAPI
 447 CpuGetInterruptState (
 448   IN  EFI_CPU_ARCH_PROTOCOL     *This,
 449   OUT BOOLEAN                   *State
 450   )
 451 {
 452   if (State == NULL) {
 453     return EFI_INVALID_PARAMETER;
 454   }
 455
 456   *State = InterruptState;
 457   return EFI_SUCCESS;
 458 }
 459
 460
 461 /**
 462   Generates an INIT to the CPU.
 463
 464   @param  This              Protocol instance structure
 465   @param  InitType          Type of CPU INIT to perform
 466
 467   @retval EFI_SUCCESS       If CPU INIT occurred. This value should never be
 468                             seen.
 469   @retval EFI_DEVICE_ERROR  If CPU INIT failed.
 470   @retval EFI_UNSUPPORTED   Requested type of CPU INIT not supported.
 471
 472 **/
 473 EFI_STATUS
 474 EFIAPI
 475 CpuInit (
 476   IN EFI_CPU_ARCH_PROTOCOL      *This,
 477   IN EFI_CPU_INIT_TYPE          InitType
 478   )
 479 {
 480   return EFI_UNSUPPORTED;
 481 }
 482
 483
 484 /**
 485   Registers a function to be called from the CPU interrupt handler.
 486
 487   @param  This                   Protocol instance structure
 488   @param  InterruptType          Defines which interrupt to hook. IA-32
 489                                  valid range is 0x00 through 0xFF
 490   @param  InterruptHandler       A pointer to a function of type
 491                                  EFI_CPU_INTERRUPT_HANDLER that is called
 492                                  when a processor interrupt occurs.  A null
 493                                  pointer is an error condition.
 494
 495   @retval EFI_SUCCESS            If handler installed or uninstalled.
 496   @retval EFI_ALREADY_STARTED    InterruptHandler is not NULL, and a handler
 497                                  for InterruptType was previously installed.
 498   @retval EFI_INVALID_PARAMETER  InterruptHandler is NULL, and a handler for
 499                                  InterruptType was not previously installed.
 500   @retval EFI_UNSUPPORTED        The interrupt specified by InterruptType
 501                                  is not supported.
 502
 503 **/
 504 EFI_STATUS
 505 EFIAPI
 506 CpuRegisterInterruptHandler (
 507   IN EFI_CPU_ARCH_PROTOCOL         *This,
 508   IN EFI_EXCEPTION_TYPE            InterruptType,
 509   IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler
 510   )
 511 {
 512   if (InterruptType < 0 || InterruptType > 0xff) {
 513     return EFI_UNSUPPORTED;
 514   }
 515
 516   if (InterruptHandler == NULL && ExternalVectorTable[InterruptType] == NULL) {
 517     return EFI_INVALID_PARAMETER;
 518   }
 519
 520   if (InterruptHandler != NULL && ExternalVectorTable[InterruptType] != NULL) {
 521     return EFI_ALREADY_STARTED;
 522   }
 523
 524   SetInterruptDescriptorTableHandlerAddress ((UINTN)InterruptType, NULL);
 525   ExternalVectorTable[InterruptType] = InterruptHandler;
 526   return EFI_SUCCESS;
 527 }
 528
 529
 530 /**
 531   Returns a timer value from one of the CPU's internal timers. There is no
 532   inherent time interval between ticks but is a function of the CPU frequency.
 533
 534   @param  This                - Protocol instance structure.
 535   @param  TimerIndex          - Specifies which CPU timer is requested.
 536   @param  TimerValue          - Pointer to the returned timer value.
 537   @param  TimerPeriod         - A pointer to the amount of time that passes
 538                                 in femtoseconds (10-15) for each increment
 539                                 of TimerValue. If TimerValue does not
 540                                 increment at a predictable rate, then 0 is
 541                                 returned.  The amount of time that has
 542                                 passed between two calls to GetTimerValue()
 543                                 can be calculated with the formula
 544                                 (TimerValue2 - TimerValue1) * TimerPeriod.
 545                                 This parameter is optional and may be NULL.
 546
 547   @retval EFI_SUCCESS           - If the CPU timer count was returned.
 548   @retval EFI_UNSUPPORTED       - If the CPU does not have any readable timers.
 549   @retval EFI_DEVICE_ERROR      - If an error occurred while reading the timer.
 550   @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
 551
 552 **/
 553 EFI_STATUS
 554 EFIAPI
 555 CpuGetTimerValue (
 556   IN  EFI_CPU_ARCH_PROTOCOL     *This,
 557   IN  UINT32                    TimerIndex,
 558   OUT UINT64                    *TimerValue,
 559   OUT UINT64                    *TimerPeriod OPTIONAL
 560   )
 561 {
 562   if (TimerValue == NULL) {
 563     return EFI_INVALID_PARAMETER;
 564   }
 565
 566   if (TimerIndex != 0) {
 567     return EFI_INVALID_PARAMETER;
 568   }
 569
 570   *TimerValue = AsmReadTsc ();
 571
 572   if (TimerPeriod != NULL) {
 573       //
 574       // BugBug: Hard coded. Don't know how to do this generically
 575       //
 576       *TimerPeriod = 1000000000;
 577   }
 578
 579   return EFI_SUCCESS;
 580 }
 581
 582
 583 /**
 584   Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.
 585
 586   This function modifies the attributes for the memory region specified by BaseAddress and
 587   Length from their current attributes to the attributes specified by Attributes.
 588
 589   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
 590   @param  BaseAddress      The physical address that is the start address of a memory region.
 591   @param  Length           The size in bytes of the memory region.
 592   @param  Attributes       The bit mask of attributes to set for the memory region.
 593
 594   @retval EFI_SUCCESS           The attributes were set for the memory region.
 595   @retval EFI_ACCESS_DENIED     The attributes for the memory resource range specified by
 596                                 BaseAddress and Length cannot be modified.
 597   @retval EFI_INVALID_PARAMETER Length is zero.
 598                                 Attributes specified an illegal combination of attributes that
 599                                 cannot be set together.
 600   @retval EFI_OUT_OF_RESOURCES  There are not enough system resources to modify the attributes of
 601                                 the memory resource range.
 602   @retval EFI_UNSUPPORTED       The processor does not support one or more bytes of the memory
 603                                 resource range specified by BaseAddress and Length.
 604                                 The bit mask of attributes is not support for the memory resource
 605                                 range specified by BaseAddress and Length.
 606
 607 **/
 608 EFI_STATUS
 609 EFIAPI
 610 CpuSetMemoryAttributes (
 611   IN EFI_CPU_ARCH_PROTOCOL     *This,
 612   IN EFI_PHYSICAL_ADDRESS      BaseAddress,
 613   IN UINT64                    Length,
 614   IN UINT64                    Attributes
 615   )
 616 {
 617   RETURN_STATUS             Status;
 618   MTRR_MEMORY_CACHE_TYPE    CacheType;
 619
 620   if (!IsMtrrSupported ()) {
 621     return EFI_UNSUPPORTED;
 622   }
 623
 624   //
 625   // If this function is called because GCD SetMemorySpaceAttributes () is called
 626   // by RefreshGcdMemoryAttributes (), then we are just synchronzing GCD memory
 627   // map with MTRR values. So there is no need to modify MTRRs, just return immediately
 628   // to avoid unnecessary computing.
 629   //
 630   if (mIsFlushingGCD) {
 631     DEBUG((EFI_D_ERROR, "  Flushing GCD\n"));
 632       return EFI_SUCCESS;
 633     }
 634
 635   switch (Attributes) {
 636   case EFI_MEMORY_UC:
 637     CacheType = CacheUncacheable;
 638     break;
 639
 640   case EFI_MEMORY_WC:
 641     CacheType = CacheWriteCombining;
 642     break;
 643
 644   case EFI_MEMORY_WT:
 645     CacheType = CacheWriteThrough;
 646     break;
 647
 648   case EFI_MEMORY_WP:
 649     CacheType = CacheWriteProtected;
 650     break;
 651
 652   case EFI_MEMORY_WB:
 653     CacheType = CacheWriteBack;
 654     break;
 655
 656   case EFI_MEMORY_UCE:
 657   case EFI_MEMORY_RP:
 658   case EFI_MEMORY_XP:
 659   case EFI_MEMORY_RUNTIME:
 660     return EFI_UNSUPPORTED;
 661
 662   default:
 663     return EFI_INVALID_PARAMETER;
 664   }
 665   //
 666   // call MTRR libary function
 667   //
 668   Status = MtrrSetMemoryAttribute (
 669              BaseAddress,
 670              Length,
 671              CacheType
 672              );
 673
 674   return (EFI_STATUS) Status;
 675 }
 676
 677 /**
 678   Initializes the valid bits mask and valid address mask for MTRRs.
 679
 680   This function initializes the valid bits mask and valid address mask for MTRRs.
 681
 682 **/
 683 VOID
 684 InitializeMtrrMask (
 685   VOID
 686   )
 687 {
 688   UINT32                              RegEax;
 689   UINT8                               PhysicalAddressBits;
 690
 691   AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
 692
 693   if (RegEax >= 0x80000008) {
 694     AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
 695
 696     PhysicalAddressBits = (UINT8) RegEax;
 697
 698     mValidMtrrBitsMask    = LShiftU64 (1, PhysicalAddressBits) - 1;
 699     mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;
 700   } else {
 701     mValidMtrrBitsMask    = MTRR_LIB_MSR_VALID_MASK;
 702     mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
 703   }
 704 }
 705
 706 /**
 707   Gets GCD Mem Space type from MTRR Type.
 708
 709   This function gets GCD Mem Space type from MTRR Type.
 710
 711   @param  MtrrAttributes  MTRR memory type
 712
 713   @return GCD Mem Space type
 714
 715 **/
 716 UINT64
 717 GetMemorySpaceAttributeFromMtrrType (
 718   IN UINT8                MtrrAttributes
 719   )
 720 {
 721   switch (MtrrAttributes) {
 722   case MTRR_CACHE_UNCACHEABLE:
 723     return EFI_MEMORY_UC;
 724   case MTRR_CACHE_WRITE_COMBINING:
 725     return EFI_MEMORY_WC;
 726   case MTRR_CACHE_WRITE_THROUGH:
 727     return EFI_MEMORY_WT;
 728   case MTRR_CACHE_WRITE_PROTECTED:
 729     return EFI_MEMORY_WP;
 730   case MTRR_CACHE_WRITE_BACK:
 731     return EFI_MEMORY_WB;
 732   default:
 733     return 0;
 734   }
 735 }
 736
 737 /**
 738   Searches memory descriptors covered by given memory range.
 739
 740   This function searches into the Gcd Memory Space for descriptors
 741   (from StartIndex to EndIndex) that contains the memory range
 742   specified by BaseAddress and Length.
 743
 744   @param  MemorySpaceMap       Gcd Memory Space Map as array.
 745   @param  NumberOfDescriptors  Number of descriptors in map.
 746   @param  BaseAddress          BaseAddress for the requested range.
 747   @param  Length               Length for the requested range.
 748   @param  StartIndex           Start index into the Gcd Memory Space Map.
 749   @param  EndIndex             End index into the Gcd Memory Space Map.
 750
 751   @retval EFI_SUCCESS          Search successfully.
 752   @retval EFI_NOT_FOUND        The requested descriptors does not exist.
 753
 754 **/
 755 EFI_STATUS
 756 SearchGcdMemorySpaces (
 757   IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap,
 758   IN UINTN                               NumberOfDescriptors,
 759   IN EFI_PHYSICAL_ADDRESS                BaseAddress,
 760   IN UINT64                              Length,
 761   OUT UINTN                              *StartIndex,
 762   OUT UINTN                              *EndIndex
 763   )
 764 {
 765   UINTN           Index;
 766
 767   *StartIndex = 0;
 768   *EndIndex   = 0;
 769   for (Index = 0; Index < NumberOfDescriptors; Index++) {
 770     if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&
 771         BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
 772       *StartIndex = Index;
 773     }
 774     if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&
 775         BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
 776       *EndIndex = Index;
 777       return EFI_SUCCESS;
 778     }
 779   }
 780   return EFI_NOT_FOUND;
 781 }
 782
 783 /**
 784   Sets the attributes for a specified range in Gcd Memory Space Map.
 785
 786   This function sets the attributes for a specified range in
 787   Gcd Memory Space Map.
 788
 789   @param  MemorySpaceMap       Gcd Memory Space Map as array
 790   @param  NumberOfDescriptors  Number of descriptors in map
 791   @param  BaseAddress          BaseAddress for the range
 792   @param  Length               Length for the range
 793   @param  Attributes           Attributes to set
 794
 795   @retval EFI_SUCCESS          Memory attributes set successfully
 796   @retval EFI_NOT_FOUND        The specified range does not exist in Gcd Memory Space
 797
 798 **/
 799 EFI_STATUS
 800 SetGcdMemorySpaceAttributes (
 801   IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap,
 802   IN UINTN                               NumberOfDescriptors,
 803   IN EFI_PHYSICAL_ADDRESS                BaseAddress,
 804   IN UINT64                              Length,
 805   IN UINT64                              Attributes
 806   )
 807 {
 808   EFI_STATUS            Status;
 809   UINTN                 Index;
 810   UINTN                 StartIndex;
 811   UINTN                 EndIndex;
 812   EFI_PHYSICAL_ADDRESS  RegionStart;
 813   UINT64                RegionLength;
 814
 815   //
 816   // Get all memory descriptors covered by the memory range
 817   //
 818   Status = SearchGcdMemorySpaces (
 819              MemorySpaceMap,
 820              NumberOfDescriptors,
 821              BaseAddress,
 822              Length,
 823              &StartIndex,
 824              &EndIndex
 825              );
 826   if (EFI_ERROR (Status)) {
 827     return Status;
 828   }
 829
 830   //
 831   // Go through all related descriptors and set attributes accordingly
 832   //
 833   for (Index = StartIndex; Index <= EndIndex; Index++) {
 834     if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
 835       continue;
 836     }
 837     //
 838     // Calculate the start and end address of the overlapping range
 839     //
 840     if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {
 841       RegionStart = BaseAddress;
 842     } else {
 843       RegionStart = MemorySpaceMap[Index].BaseAddress;
 844     }
 845     if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
 846       RegionLength = BaseAddress + Length - RegionStart;
 847     } else {
 848       RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
 849     }
 850     //
 851     // Set memory attributes according to MTRR attribute and the original attribute of descriptor
 852     //
 853     gDS->SetMemorySpaceAttributes (
 854            RegionStart,
 855            RegionLength,
 856            (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
 857            );
 858   }
 859
 860   return EFI_SUCCESS;
 861 }
 862
 863
 864 /**
 865   Refreshes the GCD Memory Space attributes according to MTRRs.
 866
 867   This function refreshes the GCD Memory Space attributes according to MTRRs.
 868
 869 **/
 870 VOID
 871 RefreshGcdMemoryAttributes (
 872   VOID
 873   )
 874 {
 875   EFI_STATUS                          Status;
 876   UINTN                               Index;
 877   UINTN                               SubIndex;
 878   UINT64                              RegValue;
 879   EFI_PHYSICAL_ADDRESS                BaseAddress;
 880   UINT64                              Length;
 881   UINT64                              Attributes;
 882   UINT64                              CurrentAttributes;
 883   UINT8                               MtrrType;
 884   UINTN                               NumberOfDescriptors;
 885   EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap;
 886   UINT64                              DefaultAttributes;
 887   VARIABLE_MTRR                       VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
 888   MTRR_FIXED_SETTINGS                 MtrrFixedSettings;
 889   UINT32                              FirmwareVariableMtrrCount;
 890
 891   if (!IsMtrrSupported ()) {
 892     return;
 893   }
 894
 895   FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();
 896   ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);
 897
 898 //  mIsFlushingGCD = TRUE;
 899   mIsFlushingGCD = FALSE;
 900   MemorySpaceMap = NULL;
 901
 902   //
 903   // Initialize the valid bits mask and valid address mask for MTRRs
 904   //
 905   InitializeMtrrMask ();
 906
 907   //
 908   // Get the memory attribute of variable MTRRs
 909   //
 910   MtrrGetMemoryAttributeInVariableMtrr (
 911     mValidMtrrBitsMask,
 912     mValidMtrrAddressMask,
 913     VariableMtrr
 914     );
 915
 916   //
 917   // Get the memory space map from GCD
 918   //
 919   Status = gDS->GetMemorySpaceMap (
 920                   &NumberOfDescriptors,
 921                   &MemorySpaceMap
 922                   );
 923   ASSERT_EFI_ERROR (Status);
 924
 925   DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (mDefaultMemoryType);
 926
 927   //
 928   // Set default attributes to all spaces.
 929   //
 930   for (Index = 0; Index < NumberOfDescriptors; Index++) {
 931     if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
 932       continue;
 933     }
 934     gDS->SetMemorySpaceAttributes (
 935            MemorySpaceMap[Index].BaseAddress,
 936            MemorySpaceMap[Index].Length,
 937            (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) |
 938            (MemorySpaceMap[Index].Capabilities & DefaultAttributes)
 939            );
 940   }
 941
 942   //
 943   // Go for variable MTRRs with WB attribute
 944   //
 945   for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
 946     if (VariableMtrr[Index].Valid &&
 947         VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) {
 948       SetGcdMemorySpaceAttributes (
 949         MemorySpaceMap,
 950         NumberOfDescriptors,
 951         VariableMtrr[Index].BaseAddress,
 952         VariableMtrr[Index].Length,
 953         EFI_MEMORY_WB
 954         );
 955     }
 956   }
 957   //
 958   // Go for variable MTRRs with Non-WB attribute
 959   //
 960   for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
 961     if (VariableMtrr[Index].Valid &&
 962         VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK) {
 963       Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8) VariableMtrr[Index].Type);
 964       SetGcdMemorySpaceAttributes (
 965         MemorySpaceMap,
 966         NumberOfDescriptors,
 967         VariableMtrr[Index].BaseAddress,
 968         VariableMtrr[Index].Length,
 969         Attributes
 970         );
 971     }
 972   }
 973
 974   //
 975   // Go for fixed MTRRs
 976   //
 977   Attributes  = 0;
 978   BaseAddress = 0;
 979   Length      = 0;
 980   MtrrGetFixedMtrr (&MtrrFixedSettings);
 981   for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {
 982     RegValue = MtrrFixedSettings.Mtrr[Index];
 983     //
 984     // Check for continuous fixed MTRR sections
 985     //
 986     for (SubIndex = 0; SubIndex < 8; SubIndex++) {
 987       MtrrType = (UINT8) RShiftU64 (RegValue, SubIndex * 8);
 988       CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType);
 989       if (Length == 0) {
 990         //
 991         // A new MTRR attribute begins
 992         //
 993         Attributes = CurrentAttributes;
 994       } else {
 995         //
 996         // If fixed MTRR attribute changed, then set memory attribute for previous atrribute
 997         //
 998         if (CurrentAttributes != Attributes) {
 999           SetGcdMemorySpaceAttributes (
1000             MemorySpaceMap,
1001             NumberOfDescriptors,
1002             BaseAddress,
1003             Length,
1004             Attributes
1005             );
1006           BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex;
1007           Length = 0;
1008           Attributes = CurrentAttributes;
1009         }
1010       }
1011       Length += mFixedMtrrTable[Index].Length;
1012     }
1013   }
1014   //
1015   // Handle the last fixed MTRR region
1016   //
1017   SetGcdMemorySpaceAttributes (
1018     MemorySpaceMap,
1019     NumberOfDescriptors,
1020     BaseAddress,
1021     Length,
1022     Attributes
1023     );
1024
1025   //
1026   // Free memory space map allocated by GCD service GetMemorySpaceMap ()
1027   //
1028   if (MemorySpaceMap != NULL) {
1029     FreePool (MemorySpaceMap);
1030   }
1031
1032   mIsFlushingGCD = FALSE;
1033 }
1034
1035 /**
1036   Set Interrupt Descriptor Table Handler Address.
1037
1038   @param Index        The Index of the interrupt descriptor table handle.
1039   @param Handler      Handler address.
1040
1041 **/
1042 VOID
1043 SetInterruptDescriptorTableHandlerAddress (
1044   IN UINTN Index,
1045   IN VOID  *Handler  OPTIONAL
1046   )
1047 {
1048   UINTN                     UintnHandler;
1049
1050   if (Handler != NULL) {
1051     UintnHandler = (UINTN) Handler;
1052   } else {
1053     UintnHandler = ((UINTN) AsmIdtVector00) + (8 * Index);
1054   }
1055
1056   gIdtTable[Index].Bits.OffsetLow   = (UINT16)UintnHandler;
1057   gIdtTable[Index].Bits.Reserved_0  = 0;
1058   gIdtTable[Index].Bits.GateType    = IA32_IDT_GATE_TYPE_INTERRUPT_32;
1059   gIdtTable[Index].Bits.OffsetHigh  = (UINT16)(UintnHandler >> 16);
1060 #if defined (MDE_CPU_X64)
1061   gIdtTable[Index].Bits.OffsetUpper = (UINT32)(UintnHandler >> 32);
1062   gIdtTable[Index].Bits.Reserved_1  = 0;
1063 #endif
1064 }
1065
1066
1067 /**
1068   Initialize Interrupt Descriptor Table for interrupt handling.
1069
1070 **/
1071 VOID
1072 InitInterruptDescriptorTable (
1073   VOID
1074   )
1075 {
1076   EFI_STATUS                Status;
1077   IA32_DESCRIPTOR           OldIdtPtr;
1078   IA32_IDT_GATE_DESCRIPTOR  *OldIdt;
1079   UINTN                     OldIdtSize;
1080   VOID                      *IdtPtrAlignmentBuffer;
1081   IA32_DESCRIPTOR           *IdtPtr;
1082   UINTN                     Index;
1083   UINT16                    CurrentCs;
1084   VOID                      *IntHandler;
1085
1086   SetMem (ExternalVectorTable, sizeof(ExternalVectorTable), 0);
1087
1088   //
1089   // Get original IDT address and size.
1090   //
1091   AsmReadIdtr ((IA32_DESCRIPTOR *) &OldIdtPtr);
1092
1093   if ((OldIdtPtr.Base != 0) && ((OldIdtPtr.Limit & 7) == 7)) {
1094     OldIdt = (IA32_IDT_GATE_DESCRIPTOR*) OldIdtPtr.Base;
1095     OldIdtSize = (OldIdtPtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR);
1096   } else {
1097     OldIdt = NULL;
1098     OldIdtSize = 0;
1099   }
1100
1101   //
1102   // Intialize IDT
1103   //
1104   CurrentCs = AsmReadCs();
1105   for (Index = 0; Index < INTERRUPT_VECTOR_NUMBER; Index ++) {
1106     //
1107     // If the old IDT had a handler for this interrupt, then
1108     // preserve it.
1109     //
1110     if (Index < OldIdtSize) {
1111       IntHandler =
1112         (VOID*) (
1113           OldIdt[Index].Bits.OffsetLow +
1114           (OldIdt[Index].Bits.OffsetHigh << 16)
1115 #if defined (MDE_CPU_X64)
1116             + (((UINTN) OldIdt[Index].Bits.OffsetUpper) << 32)
1117 #endif
1118           );
1119     } else {
1120       IntHandler = NULL;
1121     }
1122
1123     gIdtTable[Index].Bits.Selector    = CurrentCs;
1124     gIdtTable[Index].Bits.Reserved_0  = 0;
1125     gIdtTable[Index].Bits.GateType    = IA32_IDT_GATE_TYPE_INTERRUPT_32;
1126     SetInterruptDescriptorTableHandlerAddress (Index, IntHandler);
1127   }
1128
1129   //
1130   // Load IDT Pointer
1131   //
1132   IdtPtrAlignmentBuffer = AllocatePool (sizeof (*IdtPtr) + 16);
1133   IdtPtr = ALIGN_POINTER (IdtPtrAlignmentBuffer, 16);
1134   IdtPtr->Base = (UINT32)(((UINTN)(VOID*) gIdtTable) & (BASE_4GB-1));
1135   IdtPtr->Limit = (UINT16) (sizeof (gIdtTable) - 1);
1136
1137   AsmWriteIdtr (IdtPtr);
1138
1139   FreePool (IdtPtrAlignmentBuffer);
1140
1141   //
1142   // Initialize Exception Handlers
1143   //
1144   for (Index = 0; Index < 32; Index++) {
1145     Status = CpuRegisterInterruptHandler (&gCpu, Index, CommonExceptionHandler);
1146     ASSERT_EFI_ERROR (Status);
1147   }
1148
1149   //
1150   // Set the pointer to the array of C based exception handling routines.
1151   //
1152   InitializeExternalVectorTablePtr (ExternalVectorTable);
1153
1154 }
1155
1156
1157 /**
1158   Initialize the state information for the CPU Architectural Protocol.
1159
1160   @param ImageHandle     Image handle this driver.
1161   @param SystemTable     Pointer to the System Table.
1162
1163   @retval EFI_SUCCESS           Thread can be successfully created
1164   @retval EFI_OUT_OF_RESOURCES  Cannot allocate protocol data structure
1165   @retval EFI_DEVICE_ERROR      Cannot create the thread
1166
1167 **/
1168 EFI_STATUS
1169 EFIAPI
1170 InitializeCpu (
1171   IN EFI_HANDLE                            ImageHandle,
1172   IN EFI_SYSTEM_TABLE                      *SystemTable
1173   )
1174 {
1175   EFI_STATUS  Status;
1176
1177   //
1178   // Make sure interrupts are disabled
1179   //
1180   DisableInterrupts ();
1181
1182   //
1183   // Init GDT for DXE
1184   //
1185   InitGlobalDescriptorTable ();
1186
1187   //
1188   // Setup IDT pointer, IDT and interrupt entry points
1189   //
1190   InitInterruptDescriptorTable ();
1191
1192   //
1193   // Install CPU Architectural Protocol
1194   //
1195   Status = gBS->InstallMultipleProtocolInterfaces (
1196                   &mCpuHandle,
1197                   &gEfiCpuArchProtocolGuid, &gCpu,
1198                   NULL
1199                   );
1200   ASSERT_EFI_ERROR (Status);
1201
1202   //
1203   // Refresh GCD memory space map according to MTRR value.
1204   //
1205   RefreshGcdMemoryAttributes ();
1206
1207   return Status;
1208 }
1209