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Add explicit type cast to suppress possible warning of precession loss.
[mirror_edk2.git] / UefiCpuPkg / CpuDxe / CpuDxe.c
1 /** @file
2 CPU DXE Module.
3
4 Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "CpuDxe.h"
16
17 //
18 // Global Variables
19 //
20 IA32_IDT_GATE_DESCRIPTOR gIdtTable[INTERRUPT_VECTOR_NUMBER] = { 0 };
21
22 EFI_CPU_INTERRUPT_HANDLER ExternalVectorTable[0x100];
23 BOOLEAN InterruptState = FALSE;
24 EFI_HANDLE mCpuHandle = NULL;
25 BOOLEAN mIsFlushingGCD;
26 UINT8 mDefaultMemoryType = MTRR_CACHE_WRITE_BACK;
27 UINT64 mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
28 UINT64 mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;
29
30 FIXED_MTRR mFixedMtrrTable[] = {
31 {
32 MTRR_LIB_IA32_MTRR_FIX64K_00000,
33 0,
34 0x10000
35 },
36 {
37 MTRR_LIB_IA32_MTRR_FIX16K_80000,
38 0x80000,
39 0x4000
40 },
41 {
42 MTRR_LIB_IA32_MTRR_FIX16K_A0000,
43 0xA0000,
44 0x4000
45 },
46 {
47 MTRR_LIB_IA32_MTRR_FIX4K_C0000,
48 0xC0000,
49 0x1000
50 },
51 {
52 MTRR_LIB_IA32_MTRR_FIX4K_C8000,
53 0xC8000,
54 0x1000
55 },
56 {
57 MTRR_LIB_IA32_MTRR_FIX4K_D0000,
58 0xD0000,
59 0x1000
60 },
61 {
62 MTRR_LIB_IA32_MTRR_FIX4K_D8000,
63 0xD8000,
64 0x1000
65 },
66 {
67 MTRR_LIB_IA32_MTRR_FIX4K_E0000,
68 0xE0000,
69 0x1000
70 },
71 {
72 MTRR_LIB_IA32_MTRR_FIX4K_E8000,
73 0xE8000,
74 0x1000
75 },
76 {
77 MTRR_LIB_IA32_MTRR_FIX4K_F0000,
78 0xF0000,
79 0x1000
80 },
81 {
82 MTRR_LIB_IA32_MTRR_FIX4K_F8000,
83 0xF8000,
84 0x1000
85 },
86 };
87
88
89 EFI_CPU_ARCH_PROTOCOL gCpu = {
90 CpuFlushCpuDataCache,
91 CpuEnableInterrupt,
92 CpuDisableInterrupt,
93 CpuGetInterruptState,
94 CpuInit,
95 CpuRegisterInterruptHandler,
96 CpuGetTimerValue,
97 CpuSetMemoryAttributes,
98 1, // NumberOfTimers
99 4 // DmaBufferAlignment
100 };
101
102 //
103 // Error code flag indicating whether or not an error code will be
104 // pushed on the stack if an exception occurs.
105 //
106 // 1 means an error code will be pushed, otherwise 0
107 //
108 // bit 0 - exception 0
109 // bit 1 - exception 1
110 // etc.
111 //
112 UINT32 mErrorCodeFlag = 0x00027d00;
113
114 //
115 // CPU Arch Protocol Functions
116 //
117
118
119 /**
120 Common exception handler.
121
122 @param InterruptType Exception type
123 @param SystemContext EFI_SYSTEM_CONTEXT
124
125 **/
126 VOID
127 EFIAPI
128 CommonExceptionHandler (
129 IN EFI_EXCEPTION_TYPE InterruptType,
130 IN EFI_SYSTEM_CONTEXT SystemContext
131 )
132 {
133 #if defined (MDE_CPU_IA32)
134 DEBUG ((
135 EFI_D_ERROR,
136 "!!!! IA32 Exception Type - %08x !!!!\n",
137 InterruptType
138 ));
139 if ((mErrorCodeFlag & (1 << InterruptType)) != 0) {
140 DEBUG ((
141 EFI_D_ERROR,
142 "ExceptionData - %08x\n",
143 SystemContext.SystemContextIa32->ExceptionData
144 ));
145 }
146 DEBUG ((
147 EFI_D_ERROR,
148 "CS - %04x, EIP - %08x, EFL - %08x, SS - %04x\n",
149 SystemContext.SystemContextIa32->Cs,
150 SystemContext.SystemContextIa32->Eip,
151 SystemContext.SystemContextIa32->Eflags,
152 SystemContext.SystemContextIa32->Ss
153 ));
154 DEBUG ((
155 EFI_D_ERROR,
156 "DS - %04x, ES - %04x, FS - %04x, GS - %04x\n",
157 SystemContext.SystemContextIa32->Ds,
158 SystemContext.SystemContextIa32->Es,
159 SystemContext.SystemContextIa32->Fs,
160 SystemContext.SystemContextIa32->Gs
161 ));
162 DEBUG ((
163 EFI_D_ERROR,
164 "EAX - %08x, EBX - %08x, ECX - %08x, EDX - %08x\n",
165 SystemContext.SystemContextIa32->Eax,
166 SystemContext.SystemContextIa32->Ebx,
167 SystemContext.SystemContextIa32->Ecx,
168 SystemContext.SystemContextIa32->Edx
169 ));
170 DEBUG ((
171 EFI_D_ERROR,
172 "ESP - %08x, EBP - %08x, ESI - %08x, EDI - %08x\n",
173 SystemContext.SystemContextIa32->Esp,
174 SystemContext.SystemContextIa32->Ebp,
175 SystemContext.SystemContextIa32->Esi,
176 SystemContext.SystemContextIa32->Edi
177 ));
178 DEBUG ((
179 EFI_D_ERROR,
180 "GDT - %08x LIM - %04x, IDT - %08x LIM - %04x\n",
181 SystemContext.SystemContextIa32->Gdtr[0],
182 SystemContext.SystemContextIa32->Gdtr[1],
183 SystemContext.SystemContextIa32->Idtr[0],
184 SystemContext.SystemContextIa32->Idtr[1]
185 ));
186 DEBUG ((
187 EFI_D_ERROR,
188 "LDT - %08x, TR - %08x\n",
189 SystemContext.SystemContextIa32->Ldtr,
190 SystemContext.SystemContextIa32->Tr
191 ));
192 DEBUG ((
193 EFI_D_ERROR,
194 "CR0 - %08x, CR2 - %08x, CR3 - %08x, CR4 - %08x\n",
195 SystemContext.SystemContextIa32->Cr0,
196 SystemContext.SystemContextIa32->Cr2,
197 SystemContext.SystemContextIa32->Cr3,
198 SystemContext.SystemContextIa32->Cr4
199 ));
200 DEBUG ((
201 EFI_D_ERROR,
202 "DR0 - %08x, DR1 - %08x, DR2 - %08x, DR3 - %08x\n",
203 SystemContext.SystemContextIa32->Dr0,
204 SystemContext.SystemContextIa32->Dr1,
205 SystemContext.SystemContextIa32->Dr2,
206 SystemContext.SystemContextIa32->Dr3
207 ));
208 DEBUG ((
209 EFI_D_ERROR,
210 "DR6 - %08x, DR7 - %08x\n",
211 SystemContext.SystemContextIa32->Dr6,
212 SystemContext.SystemContextIa32->Dr7
213 ));
214 #elif defined (MDE_CPU_X64)
215 DEBUG ((
216 EFI_D_ERROR,
217 "!!!! X64 Exception Type - %016lx !!!!\n",
218 (UINT64)InterruptType
219 ));
220 if ((mErrorCodeFlag & (1 << InterruptType)) != 0) {
221 DEBUG ((
222 EFI_D_ERROR,
223 "ExceptionData - %016lx\n",
224 SystemContext.SystemContextX64->ExceptionData
225 ));
226 }
227 DEBUG ((
228 EFI_D_ERROR,
229 "RIP - %016lx, RFL - %016lx\n",
230 SystemContext.SystemContextX64->Rip,
231 SystemContext.SystemContextX64->Rflags
232 ));
233 DEBUG ((
234 EFI_D_ERROR,
235 "RAX - %016lx, RCX - %016lx, RDX - %016lx\n",
236 SystemContext.SystemContextX64->Rax,
237 SystemContext.SystemContextX64->Rcx,
238 SystemContext.SystemContextX64->Rdx
239 ));
240 DEBUG ((
241 EFI_D_ERROR,
242 "RBX - %016lx, RSP - %016lx, RBP - %016lx\n",
243 SystemContext.SystemContextX64->Rbx,
244 SystemContext.SystemContextX64->Rsp,
245 SystemContext.SystemContextX64->Rbp
246 ));
247 DEBUG ((
248 EFI_D_ERROR,
249 "RSI - %016lx, RDI - %016lx\n",
250 SystemContext.SystemContextX64->Rsi,
251 SystemContext.SystemContextX64->Rdi
252 ));
253 DEBUG ((
254 EFI_D_ERROR,
255 "R8 - %016lx, R9 - %016lx, R10 - %016lx\n",
256 SystemContext.SystemContextX64->R8,
257 SystemContext.SystemContextX64->R9,
258 SystemContext.SystemContextX64->R10
259 ));
260 DEBUG ((
261 EFI_D_ERROR,
262 "R11 - %016lx, R12 - %016lx, R13 - %016lx\n",
263 SystemContext.SystemContextX64->R11,
264 SystemContext.SystemContextX64->R12,
265 SystemContext.SystemContextX64->R13
266 ));
267 DEBUG ((
268 EFI_D_ERROR,
269 "R14 - %016lx, R15 - %016lx\n",
270 SystemContext.SystemContextX64->R14,
271 SystemContext.SystemContextX64->R15
272 ));
273 DEBUG ((
274 EFI_D_ERROR,
275 "CS - %04lx, DS - %04lx, ES - %04lx, FS - %04lx, GS - %04lx, SS - %04lx\n",
276 SystemContext.SystemContextX64->Cs,
277 SystemContext.SystemContextX64->Ds,
278 SystemContext.SystemContextX64->Es,
279 SystemContext.SystemContextX64->Fs,
280 SystemContext.SystemContextX64->Gs,
281 SystemContext.SystemContextX64->Ss
282 ));
283 DEBUG ((
284 EFI_D_ERROR,
285 "GDT - %016lx; %04lx, IDT - %016lx; %04lx\n",
286 SystemContext.SystemContextX64->Gdtr[0],
287 SystemContext.SystemContextX64->Gdtr[1],
288 SystemContext.SystemContextX64->Idtr[0],
289 SystemContext.SystemContextX64->Idtr[1]
290 ));
291 DEBUG ((
292 EFI_D_ERROR,
293 "LDT - %016lx, TR - %016lx\n",
294 SystemContext.SystemContextX64->Ldtr,
295 SystemContext.SystemContextX64->Tr
296 ));
297 DEBUG ((
298 EFI_D_ERROR,
299 "CR0 - %016lx, CR2 - %016lx, CR3 - %016lx\n",
300 SystemContext.SystemContextX64->Cr0,
301 SystemContext.SystemContextX64->Cr2,
302 SystemContext.SystemContextX64->Cr3
303 ));
304 DEBUG ((
305 EFI_D_ERROR,
306 "CR4 - %016lx, CR8 - %016lx\n",
307 SystemContext.SystemContextX64->Cr4,
308 SystemContext.SystemContextX64->Cr8
309 ));
310 DEBUG ((
311 EFI_D_ERROR,
312 "DR0 - %016lx, DR1 - %016lx, DR2 - %016lx\n",
313 SystemContext.SystemContextX64->Dr0,
314 SystemContext.SystemContextX64->Dr1,
315 SystemContext.SystemContextX64->Dr2
316 ));
317 DEBUG ((
318 EFI_D_ERROR,
319 "DR3 - %016lx, DR6 - %016lx, DR7 - %016lx\n",
320 SystemContext.SystemContextX64->Dr3,
321 SystemContext.SystemContextX64->Dr6,
322 SystemContext.SystemContextX64->Dr7
323 ));
324 #else
325 #error CPU type not supported for exception information dump!
326 #endif
327
328 //
329 // Hang the system with CpuSleep so the processor will enter a lower power
330 // state.
331 //
332 while (TRUE) {
333 CpuSleep ();
334 };
335 }
336
337
338 /**
339 Flush CPU data cache. If the instruction cache is fully coherent
340 with all DMA operations then function can just return EFI_SUCCESS.
341
342 @param This Protocol instance structure
343 @param Start Physical address to start flushing from.
344 @param Length Number of bytes to flush. Round up to chipset
345 granularity.
346 @param FlushType Specifies the type of flush operation to perform.
347
348 @retval EFI_SUCCESS If cache was flushed
349 @retval EFI_UNSUPPORTED If flush type is not supported.
350 @retval EFI_DEVICE_ERROR If requested range could not be flushed.
351
352 **/
353 EFI_STATUS
354 EFIAPI
355 CpuFlushCpuDataCache (
356 IN EFI_CPU_ARCH_PROTOCOL *This,
357 IN EFI_PHYSICAL_ADDRESS Start,
358 IN UINT64 Length,
359 IN EFI_CPU_FLUSH_TYPE FlushType
360 )
361 {
362 if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {
363 AsmWbinvd ();
364 return EFI_SUCCESS;
365 } else if (FlushType == EfiCpuFlushTypeInvalidate) {
366 AsmInvd ();
367 return EFI_SUCCESS;
368 } else {
369 return EFI_UNSUPPORTED;
370 }
371 }
372
373
374 /**
375 Enables CPU interrupts.
376
377 @param This Protocol instance structure
378
379 @retval EFI_SUCCESS If interrupts were enabled in the CPU
380 @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
381
382 **/
383 EFI_STATUS
384 EFIAPI
385 CpuEnableInterrupt (
386 IN EFI_CPU_ARCH_PROTOCOL *This
387 )
388 {
389 EnableInterrupts ();
390
391 InterruptState = TRUE;
392 return EFI_SUCCESS;
393 }
394
395
396 /**
397 Disables CPU interrupts.
398
399 @param This Protocol instance structure
400
401 @retval EFI_SUCCESS If interrupts were disabled in the CPU.
402 @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
403
404 **/
405 EFI_STATUS
406 EFIAPI
407 CpuDisableInterrupt (
408 IN EFI_CPU_ARCH_PROTOCOL *This
409 )
410 {
411 DisableInterrupts ();
412
413 InterruptState = FALSE;
414 return EFI_SUCCESS;
415 }
416
417
418 /**
419 Return the state of interrupts.
420
421 @param This Protocol instance structure
422 @param State Pointer to the CPU's current interrupt state
423
424 @retval EFI_SUCCESS If interrupts were disabled in the CPU.
425 @retval EFI_INVALID_PARAMETER State is NULL.
426
427 **/
428 EFI_STATUS
429 EFIAPI
430 CpuGetInterruptState (
431 IN EFI_CPU_ARCH_PROTOCOL *This,
432 OUT BOOLEAN *State
433 )
434 {
435 if (State == NULL) {
436 return EFI_INVALID_PARAMETER;
437 }
438
439 *State = InterruptState;
440 return EFI_SUCCESS;
441 }
442
443
444 /**
445 Generates an INIT to the CPU.
446
447 @param This Protocol instance structure
448 @param InitType Type of CPU INIT to perform
449
450 @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
451 seen.
452 @retval EFI_DEVICE_ERROR If CPU INIT failed.
453 @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
454
455 **/
456 EFI_STATUS
457 EFIAPI
458 CpuInit (
459 IN EFI_CPU_ARCH_PROTOCOL *This,
460 IN EFI_CPU_INIT_TYPE InitType
461 )
462 {
463 return EFI_UNSUPPORTED;
464 }
465
466
467 /**
468 Registers a function to be called from the CPU interrupt handler.
469
470 @param This Protocol instance structure
471 @param InterruptType Defines which interrupt to hook. IA-32
472 valid range is 0x00 through 0xFF
473 @param InterruptHandler A pointer to a function of type
474 EFI_CPU_INTERRUPT_HANDLER that is called
475 when a processor interrupt occurs. A null
476 pointer is an error condition.
477
478 @retval EFI_SUCCESS If handler installed or uninstalled.
479 @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
480 for InterruptType was previously installed.
481 @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
482 InterruptType was not previously installed.
483 @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
484 is not supported.
485
486 **/
487 EFI_STATUS
488 EFIAPI
489 CpuRegisterInterruptHandler (
490 IN EFI_CPU_ARCH_PROTOCOL *This,
491 IN EFI_EXCEPTION_TYPE InterruptType,
492 IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
493 )
494 {
495 if (InterruptType < 0 || InterruptType > 0xff) {
496 return EFI_UNSUPPORTED;
497 }
498
499 if (InterruptHandler == NULL && ExternalVectorTable[InterruptType] == NULL) {
500 return EFI_INVALID_PARAMETER;
501 }
502
503 if (InterruptHandler != NULL && ExternalVectorTable[InterruptType] != NULL) {
504 return EFI_ALREADY_STARTED;
505 }
506
507 ExternalVectorTable[InterruptType] = InterruptHandler;
508 return EFI_SUCCESS;
509 }
510
511
512 /**
513 Returns a timer value from one of the CPU's internal timers. There is no
514 inherent time interval between ticks but is a function of the CPU frequency.
515
516 @param This - Protocol instance structure.
517 @param TimerIndex - Specifies which CPU timer is requested.
518 @param TimerValue - Pointer to the returned timer value.
519 @param TimerPeriod - A pointer to the amount of time that passes
520 in femtoseconds (10-15) for each increment
521 of TimerValue. If TimerValue does not
522 increment at a predictable rate, then 0 is
523 returned. The amount of time that has
524 passed between two calls to GetTimerValue()
525 can be calculated with the formula
526 (TimerValue2 - TimerValue1) * TimerPeriod.
527 This parameter is optional and may be NULL.
528
529 @retval EFI_SUCCESS - If the CPU timer count was returned.
530 @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
531 @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
532 @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
533
534 **/
535 EFI_STATUS
536 EFIAPI
537 CpuGetTimerValue (
538 IN EFI_CPU_ARCH_PROTOCOL *This,
539 IN UINT32 TimerIndex,
540 OUT UINT64 *TimerValue,
541 OUT UINT64 *TimerPeriod OPTIONAL
542 )
543 {
544 if (TimerValue == NULL) {
545 return EFI_INVALID_PARAMETER;
546 }
547
548 if (TimerIndex != 0) {
549 return EFI_INVALID_PARAMETER;
550 }
551
552 *TimerValue = AsmReadTsc ();
553
554 if (TimerPeriod != NULL) {
555 //
556 // BugBug: Hard coded. Don't know how to do this generically
557 //
558 *TimerPeriod = 1000000000;
559 }
560
561 return EFI_SUCCESS;
562 }
563
564
565 /**
566 Set memory cacheability attributes for given range of memeory.
567
568 @param This Protocol instance structure
569 @param BaseAddress Specifies the start address of the
570 memory range
571 @param Length Specifies the length of the memory range
572 @param Attributes The memory cacheability for the memory range
573
574 @retval EFI_SUCCESS If the cacheability of that memory range is
575 set successfully
576 @retval EFI_UNSUPPORTED If the desired operation cannot be done
577 @retval EFI_INVALID_PARAMETER The input parameter is not correct,
578 such as Length = 0
579
580 **/
581 EFI_STATUS
582 EFIAPI
583 CpuSetMemoryAttributes (
584 IN EFI_CPU_ARCH_PROTOCOL *This,
585 IN EFI_PHYSICAL_ADDRESS BaseAddress,
586 IN UINT64 Length,
587 IN UINT64 Attributes
588 )
589 {
590 RETURN_STATUS Status;
591 MTRR_MEMORY_CACHE_TYPE CacheType;
592
593 if (!IsMtrrSupported ()) {
594 return EFI_UNSUPPORTED;
595 }
596
597 DEBUG((EFI_D_ERROR, "CpuAp: SetMemorySpaceAttributes(BA=%08x, Len=%08x, Attr=%08x)\n", BaseAddress, Length, Attributes));
598
599 //
600 // If this function is called because GCD SetMemorySpaceAttributes () is called
601 // by RefreshGcdMemoryAttributes (), then we are just synchronzing GCD memory
602 // map with MTRR values. So there is no need to modify MTRRs, just return immediately
603 // to avoid unnecessary computing.
604 //
605 if (mIsFlushingGCD) {
606 DEBUG((EFI_D_ERROR, " Flushing GCD\n"));
607 return EFI_SUCCESS;
608 }
609
610 switch (Attributes) {
611 case EFI_MEMORY_UC:
612 CacheType = CacheUncacheable;
613 break;
614
615 case EFI_MEMORY_WC:
616 CacheType = CacheWriteCombining;
617 break;
618
619 case EFI_MEMORY_WT:
620 CacheType = CacheWriteThrough;
621 break;
622
623 case EFI_MEMORY_WP:
624 CacheType = CacheWriteProtected;
625 break;
626
627 case EFI_MEMORY_WB:
628 CacheType = CacheWriteBack;
629 break;
630
631 default:
632 return EFI_UNSUPPORTED;
633 }
634 //
635 // call MTRR libary function
636 //
637 DEBUG((EFI_D_ERROR, " MtrrSetMemoryAttribute()\n"));
638 Status = MtrrSetMemoryAttribute(
639 BaseAddress,
640 Length,
641 CacheType
642 );
643
644 MtrrDebugPrintAllMtrrs ();
645
646 return (EFI_STATUS) Status;
647 }
648
649 /**
650 Initializes the valid bits mask and valid address mask for MTRRs.
651
652 This function initializes the valid bits mask and valid address mask for MTRRs.
653
654 **/
655 VOID
656 InitializeMtrrMask (
657 VOID
658 )
659 {
660 UINT32 RegEax;
661 UINT8 PhysicalAddressBits;
662
663 AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
664
665 if (RegEax >= 0x80000008) {
666 AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
667
668 PhysicalAddressBits = (UINT8) RegEax;
669
670 mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;
671 mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;
672 } else {
673 mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;
674 mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
675 }
676 }
677
678 /**
679 Gets GCD Mem Space type from MTRR Type.
680
681 This function gets GCD Mem Space type from MTRR Type.
682
683 @param MtrrAttributes MTRR memory type
684
685 @return GCD Mem Space type
686
687 **/
688 UINT64
689 GetMemorySpaceAttributeFromMtrrType (
690 IN UINT8 MtrrAttributes
691 )
692 {
693 switch (MtrrAttributes) {
694 case MTRR_CACHE_UNCACHEABLE:
695 return EFI_MEMORY_UC;
696 case MTRR_CACHE_WRITE_COMBINING:
697 return EFI_MEMORY_WC;
698 case MTRR_CACHE_WRITE_THROUGH:
699 return EFI_MEMORY_WT;
700 case MTRR_CACHE_WRITE_PROTECTED:
701 return EFI_MEMORY_WP;
702 case MTRR_CACHE_WRITE_BACK:
703 return EFI_MEMORY_WB;
704 default:
705 return 0;
706 }
707 }
708
709 /**
710 Searches memory descriptors covered by given memory range.
711
712 This function searches into the Gcd Memory Space for descriptors
713 (from StartIndex to EndIndex) that contains the memory range
714 specified by BaseAddress and Length.
715
716 @param MemorySpaceMap Gcd Memory Space Map as array.
717 @param NumberOfDescriptors Number of descriptors in map.
718 @param BaseAddress BaseAddress for the requested range.
719 @param Length Length for the requested range.
720 @param StartIndex Start index into the Gcd Memory Space Map.
721 @param EndIndex End index into the Gcd Memory Space Map.
722
723 @retval EFI_SUCCESS Search successfully.
724 @retval EFI_NOT_FOUND The requested descriptors does not exist.
725
726 **/
727 EFI_STATUS
728 SearchGcdMemorySpaces (
729 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
730 IN UINTN NumberOfDescriptors,
731 IN EFI_PHYSICAL_ADDRESS BaseAddress,
732 IN UINT64 Length,
733 OUT UINTN *StartIndex,
734 OUT UINTN *EndIndex
735 )
736 {
737 UINTN Index;
738
739 *StartIndex = 0;
740 *EndIndex = 0;
741 for (Index = 0; Index < NumberOfDescriptors; Index++) {
742 if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&
743 BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
744 *StartIndex = Index;
745 }
746 if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&
747 BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
748 *EndIndex = Index;
749 return EFI_SUCCESS;
750 }
751 }
752 return EFI_NOT_FOUND;
753 }
754
755 /**
756 Sets the attributes for a specified range in Gcd Memory Space Map.
757
758 This function sets the attributes for a specified range in
759 Gcd Memory Space Map.
760
761 @param MemorySpaceMap Gcd Memory Space Map as array
762 @param NumberOfDescriptors Number of descriptors in map
763 @param BaseAddress BaseAddress for the range
764 @param Length Length for the range
765 @param Attributes Attributes to set
766
767 @retval EFI_SUCCESS Memory attributes set successfully
768 @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space
769
770 **/
771 EFI_STATUS
772 SetGcdMemorySpaceAttributes (
773 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
774 IN UINTN NumberOfDescriptors,
775 IN EFI_PHYSICAL_ADDRESS BaseAddress,
776 IN UINT64 Length,
777 IN UINT64 Attributes
778 )
779 {
780 EFI_STATUS Status;
781 UINTN Index;
782 UINTN StartIndex;
783 UINTN EndIndex;
784 EFI_PHYSICAL_ADDRESS RegionStart;
785 UINT64 RegionLength;
786
787 //
788 // Get all memory descriptors covered by the memory range
789 //
790 Status = SearchGcdMemorySpaces (
791 MemorySpaceMap,
792 NumberOfDescriptors,
793 BaseAddress,
794 Length,
795 &StartIndex,
796 &EndIndex
797 );
798 if (EFI_ERROR (Status)) {
799 return Status;
800 }
801
802 //
803 // Go through all related descriptors and set attributes accordingly
804 //
805 for (Index = StartIndex; Index <= EndIndex; Index++) {
806 if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
807 continue;
808 }
809 //
810 // Calculate the start and end address of the overlapping range
811 //
812 if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {
813 RegionStart = BaseAddress;
814 } else {
815 RegionStart = MemorySpaceMap[Index].BaseAddress;
816 }
817 if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
818 RegionLength = BaseAddress + Length - RegionStart;
819 } else {
820 RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
821 }
822 //
823 // Set memory attributes according to MTRR attribute and the original attribute of descriptor
824 //
825 gDS->SetMemorySpaceAttributes (
826 RegionStart,
827 RegionLength,
828 (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
829 );
830 }
831
832 return EFI_SUCCESS;
833 }
834
835
836 /**
837 Refreshes the GCD Memory Space attributes according to MTRRs.
838
839 This function refreshes the GCD Memory Space attributes according to MTRRs.
840
841 **/
842 VOID
843 RefreshGcdMemoryAttributes (
844 VOID
845 )
846 {
847 EFI_STATUS Status;
848 UINTN Index;
849 UINTN SubIndex;
850 UINT64 RegValue;
851 EFI_PHYSICAL_ADDRESS BaseAddress;
852 UINT64 Length;
853 UINT64 Attributes;
854 UINT64 CurrentAttributes;
855 UINT8 MtrrType;
856 UINTN NumberOfDescriptors;
857 EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
858 UINT64 DefaultAttributes;
859 VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
860 MTRR_FIXED_SETTINGS MtrrFixedSettings;
861 UINT32 FirmwareVariableMtrrCount;
862
863 if (!IsMtrrSupported ()) {
864 return;
865 }
866
867 FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();
868 ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);
869
870 // mIsFlushingGCD = TRUE;
871 mIsFlushingGCD = FALSE;
872 MemorySpaceMap = NULL;
873
874 //
875 // Initialize the valid bits mask and valid address mask for MTRRs
876 //
877 InitializeMtrrMask ();
878
879 //
880 // Get the memory attribute of variable MTRRs
881 //
882 MtrrGetMemoryAttributeInVariableMtrr (
883 mValidMtrrBitsMask,
884 mValidMtrrAddressMask,
885 VariableMtrr
886 );
887
888 //
889 // Get the memory space map from GCD
890 //
891 Status = gDS->GetMemorySpaceMap (
892 &NumberOfDescriptors,
893 &MemorySpaceMap
894 );
895 ASSERT_EFI_ERROR (Status);
896
897 DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (mDefaultMemoryType);
898
899 //
900 // Set default attributes to all spaces.
901 //
902 for (Index = 0; Index < NumberOfDescriptors; Index++) {
903 if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
904 continue;
905 }
906 gDS->SetMemorySpaceAttributes (
907 MemorySpaceMap[Index].BaseAddress,
908 MemorySpaceMap[Index].Length,
909 (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) |
910 (MemorySpaceMap[Index].Capabilities & DefaultAttributes)
911 );
912 }
913
914 //
915 // Go for variable MTRRs with WB attribute
916 //
917 for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
918 if (VariableMtrr[Index].Valid &&
919 VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) {
920 SetGcdMemorySpaceAttributes (
921 MemorySpaceMap,
922 NumberOfDescriptors,
923 VariableMtrr[Index].BaseAddress,
924 VariableMtrr[Index].Length,
925 EFI_MEMORY_WB
926 );
927 }
928 }
929 //
930 // Go for variable MTRRs with Non-WB attribute
931 //
932 for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
933 if (VariableMtrr[Index].Valid &&
934 VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK) {
935 Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8) VariableMtrr[Index].Type);
936 SetGcdMemorySpaceAttributes (
937 MemorySpaceMap,
938 NumberOfDescriptors,
939 VariableMtrr[Index].BaseAddress,
940 VariableMtrr[Index].Length,
941 Attributes
942 );
943 }
944 }
945
946 //
947 // Go for fixed MTRRs
948 //
949 Attributes = 0;
950 BaseAddress = 0;
951 Length = 0;
952 MtrrGetFixedMtrr (&MtrrFixedSettings);
953 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {
954 RegValue = MtrrFixedSettings.Mtrr[Index];
955 //
956 // Check for continuous fixed MTRR sections
957 //
958 for (SubIndex = 0; SubIndex < 8; SubIndex++) {
959 MtrrType = (UINT8) RShiftU64 (RegValue, SubIndex * 8);
960 CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType);
961 if (Length == 0) {
962 //
963 // A new MTRR attribute begins
964 //
965 Attributes = CurrentAttributes;
966 } else {
967 //
968 // If fixed MTRR attribute changed, then set memory attribute for previous atrribute
969 //
970 if (CurrentAttributes != Attributes) {
971 SetGcdMemorySpaceAttributes (
972 MemorySpaceMap,
973 NumberOfDescriptors,
974 BaseAddress,
975 Length,
976 Attributes
977 );
978 BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex;
979 Length = 0;
980 Attributes = CurrentAttributes;
981 }
982 }
983 Length += mFixedMtrrTable[Index].Length;
984 }
985 }
986 //
987 // Handle the last fixed MTRR region
988 //
989 SetGcdMemorySpaceAttributes (
990 MemorySpaceMap,
991 NumberOfDescriptors,
992 BaseAddress,
993 Length,
994 Attributes
995 );
996
997 //
998 // Free memory space map allocated by GCD service GetMemorySpaceMap ()
999 //
1000 if (MemorySpaceMap != NULL) {
1001 FreePool (MemorySpaceMap);
1002 }
1003
1004 mIsFlushingGCD = FALSE;
1005 }
1006
1007
1008 /**
1009 Initialize Interrupt Descriptor Table for interrupt handling.
1010
1011 **/
1012 VOID
1013 InitInterruptDescriptorTable (
1014 VOID
1015 )
1016 {
1017 EFI_STATUS Status;
1018 VOID *IdtPtrAlignmentBuffer;
1019 IA32_DESCRIPTOR *IdtPtr;
1020 UINTN Index;
1021 UINTN CurrentHandler;
1022 IA32_DESCRIPTOR Idtr;
1023
1024 SetMem (ExternalVectorTable, sizeof(ExternalVectorTable), 0);
1025
1026 //
1027 // Intialize IDT
1028 //
1029 CurrentHandler = (UINTN)AsmIdtVector00;
1030 for (Index = 0; Index < INTERRUPT_VECTOR_NUMBER; Index ++, CurrentHandler += 0x08) {
1031 gIdtTable[Index].Bits.OffsetLow = (UINT16)CurrentHandler;
1032 gIdtTable[Index].Bits.Reserved_0 = 0;
1033 gIdtTable[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
1034 gIdtTable[Index].Bits.OffsetHigh = (UINT16)(CurrentHandler >> 16);
1035 #if defined (MDE_CPU_X64)
1036 gIdtTable[Index].Bits.OffsetUpper = (UINT32)(CurrentHandler >> 32);
1037 gIdtTable[Index].Bits.Reserved_1 = 0;
1038 #endif
1039 }
1040
1041 //
1042 // Get original IDT address and size.
1043 //
1044 AsmReadIdtr ((IA32_DESCRIPTOR *) &Idtr);
1045
1046 //
1047 // Copy original IDT entry.
1048 //
1049 CopyMem (&gIdtTable[0], (VOID *) Idtr.Base, Idtr.Limit + 1);
1050
1051 //
1052 // Update all IDT enties to use cuurent CS value
1053 //
1054 for (Index = 0; Index < INTERRUPT_VECTOR_NUMBER; Index ++, CurrentHandler += 0x08) {
1055 gIdtTable[Index].Bits.Selector = AsmReadCs();
1056 }
1057
1058 //
1059 // Load IDT Pointer
1060 //
1061 IdtPtrAlignmentBuffer = AllocatePool (sizeof (*IdtPtr) + 16);
1062 IdtPtr = ALIGN_POINTER (IdtPtrAlignmentBuffer, 16);
1063 IdtPtr->Base = (UINT32)(((UINTN)(VOID*) gIdtTable) & (BASE_4GB-1));
1064 IdtPtr->Limit = (UINT16) (sizeof (gIdtTable) - 1);
1065
1066 AsmWriteIdtr (IdtPtr);
1067
1068 FreePool (IdtPtrAlignmentBuffer);
1069
1070 //
1071 // Initialize Exception Handlers
1072 //
1073 for (Index = 0; Index < 32; Index++) {
1074 Status = CpuRegisterInterruptHandler (&gCpu, Index, CommonExceptionHandler);
1075 ASSERT_EFI_ERROR (Status);
1076 }
1077
1078 //
1079 // Set the pointer to the array of C based exception handling routines.
1080 //
1081 InitializeExternalVectorTablePtr (ExternalVectorTable);
1082
1083 }
1084
1085
1086 /**
1087 Initialize the state information for the CPU Architectural Protocol.
1088
1089 @param ImageHandle Image handle this driver.
1090 @param SystemTable Pointer to the System Table.
1091
1092 @retval EFI_SUCCESS Thread can be successfully created
1093 @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
1094 @retval EFI_DEVICE_ERROR Cannot create the thread
1095
1096 **/
1097 EFI_STATUS
1098 EFIAPI
1099 InitializeCpu (
1100 IN EFI_HANDLE ImageHandle,
1101 IN EFI_SYSTEM_TABLE *SystemTable
1102 )
1103 {
1104 EFI_STATUS Status;
1105
1106 //
1107 // Make sure interrupts are disabled
1108 //
1109 DisableInterrupts ();
1110
1111 //
1112 // Init GDT for DXE
1113 //
1114 InitGlobalDescriptorTable ();
1115
1116 //
1117 // Setup IDT pointer, IDT and interrupt entry points
1118 //
1119 InitInterruptDescriptorTable ();
1120
1121 //
1122 // Install CPU Architectural Protocol
1123 //
1124 Status = gBS->InstallMultipleProtocolInterfaces (
1125 &mCpuHandle,
1126 &gEfiCpuArchProtocolGuid, &gCpu,
1127 NULL
1128 );
1129 ASSERT_EFI_ERROR (Status);
1130
1131 //
1132 // Refresh GCD memory space map according to MTRR value.
1133 //
1134 RefreshGcdMemoryAttributes ();
1135
1136 return Status;
1137 }
1138
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