UefiCpuPkg/CpuDxe/CpuDxe.c

   1 /** @file
   2   CPU DXE Module.
   3
   4   Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include "CpuDxe.h"
  16 #include "CpuMp.h"
  17
  18 //
  19 // Global Variables
  20 //
  21 BOOLEAN                   InterruptState = FALSE;
  22 EFI_HANDLE                mCpuHandle = NULL;
  23 BOOLEAN                   mIsFlushingGCD;
  24 UINT64                    mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
  25 UINT64                    mValidMtrrBitsMask    = MTRR_LIB_MSR_VALID_MASK;
  26
  27 FIXED_MTRR    mFixedMtrrTable[] = {
  28   {
  29     MTRR_LIB_IA32_MTRR_FIX64K_00000,
  30     0,
  31     0x10000
  32   },
  33   {
  34     MTRR_LIB_IA32_MTRR_FIX16K_80000,
  35     0x80000,
  36     0x4000
  37   },
  38   {
  39     MTRR_LIB_IA32_MTRR_FIX16K_A0000,
  40     0xA0000,
  41     0x4000
  42   },
  43   {
  44     MTRR_LIB_IA32_MTRR_FIX4K_C0000,
  45     0xC0000,
  46     0x1000
  47   },
  48   {
  49     MTRR_LIB_IA32_MTRR_FIX4K_C8000,
  50     0xC8000,
  51     0x1000
  52   },
  53   {
  54     MTRR_LIB_IA32_MTRR_FIX4K_D0000,
  55     0xD0000,
  56     0x1000
  57   },
  58   {
  59     MTRR_LIB_IA32_MTRR_FIX4K_D8000,
  60     0xD8000,
  61     0x1000
  62   },
  63   {
  64     MTRR_LIB_IA32_MTRR_FIX4K_E0000,
  65     0xE0000,
  66     0x1000
  67   },
  68   {
  69     MTRR_LIB_IA32_MTRR_FIX4K_E8000,
  70     0xE8000,
  71     0x1000
  72   },
  73   {
  74     MTRR_LIB_IA32_MTRR_FIX4K_F0000,
  75     0xF0000,
  76     0x1000
  77   },
  78   {
  79     MTRR_LIB_IA32_MTRR_FIX4K_F8000,
  80     0xF8000,
  81     0x1000
  82   },
  83 };
  84
  85
  86 EFI_CPU_ARCH_PROTOCOL  gCpu = {
  87   CpuFlushCpuDataCache,
  88   CpuEnableInterrupt,
  89   CpuDisableInterrupt,
  90   CpuGetInterruptState,
  91   CpuInit,
  92   CpuRegisterInterruptHandler,
  93   CpuGetTimerValue,
  94   CpuSetMemoryAttributes,
  95   1,                          // NumberOfTimers
  96   4                           // DmaBufferAlignment
  97 };
  98
  99 //
 100 // CPU Arch Protocol Functions
 101 //
 102
 103 /**
 104   Flush CPU data cache. If the instruction cache is fully coherent
 105   with all DMA operations then function can just return EFI_SUCCESS.
 106
 107   @param  This              Protocol instance structure
 108   @param  Start             Physical address to start flushing from.
 109   @param  Length            Number of bytes to flush. Round up to chipset
 110                             granularity.
 111   @param  FlushType         Specifies the type of flush operation to perform.
 112
 113   @retval EFI_SUCCESS       If cache was flushed
 114   @retval EFI_UNSUPPORTED   If flush type is not supported.
 115   @retval EFI_DEVICE_ERROR  If requested range could not be flushed.
 116
 117 **/
 118 EFI_STATUS
 119 EFIAPI
 120 CpuFlushCpuDataCache (
 121   IN EFI_CPU_ARCH_PROTOCOL     *This,
 122   IN EFI_PHYSICAL_ADDRESS      Start,
 123   IN UINT64                    Length,
 124   IN EFI_CPU_FLUSH_TYPE        FlushType
 125   )
 126 {
 127   if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {
 128     AsmWbinvd ();
 129     return EFI_SUCCESS;
 130   } else if (FlushType == EfiCpuFlushTypeInvalidate) {
 131     AsmInvd ();
 132     return EFI_SUCCESS;
 133   } else {
 134     return EFI_UNSUPPORTED;
 135   }
 136 }
 137
 138
 139 /**
 140   Enables CPU interrupts.
 141
 142   @param  This              Protocol instance structure
 143
 144   @retval EFI_SUCCESS       If interrupts were enabled in the CPU
 145   @retval EFI_DEVICE_ERROR  If interrupts could not be enabled on the CPU.
 146
 147 **/
 148 EFI_STATUS
 149 EFIAPI
 150 CpuEnableInterrupt (
 151   IN EFI_CPU_ARCH_PROTOCOL          *This
 152   )
 153 {
 154   EnableInterrupts ();
 155
 156   InterruptState = TRUE;
 157   return EFI_SUCCESS;
 158 }
 159
 160
 161 /**
 162   Disables CPU interrupts.
 163
 164   @param  This              Protocol instance structure
 165
 166   @retval EFI_SUCCESS       If interrupts were disabled in the CPU.
 167   @retval EFI_DEVICE_ERROR  If interrupts could not be disabled on the CPU.
 168
 169 **/
 170 EFI_STATUS
 171 EFIAPI
 172 CpuDisableInterrupt (
 173   IN EFI_CPU_ARCH_PROTOCOL     *This
 174   )
 175 {
 176   DisableInterrupts ();
 177
 178   InterruptState = FALSE;
 179   return EFI_SUCCESS;
 180 }
 181
 182
 183 /**
 184   Return the state of interrupts.
 185
 186   @param  This                   Protocol instance structure
 187   @param  State                  Pointer to the CPU's current interrupt state
 188
 189   @retval EFI_SUCCESS            If interrupts were disabled in the CPU.
 190   @retval EFI_INVALID_PARAMETER  State is NULL.
 191
 192 **/
 193 EFI_STATUS
 194 EFIAPI
 195 CpuGetInterruptState (
 196   IN  EFI_CPU_ARCH_PROTOCOL     *This,
 197   OUT BOOLEAN                   *State
 198   )
 199 {
 200   if (State == NULL) {
 201     return EFI_INVALID_PARAMETER;
 202   }
 203
 204   *State = InterruptState;
 205   return EFI_SUCCESS;
 206 }
 207
 208
 209 /**
 210   Generates an INIT to the CPU.
 211
 212   @param  This              Protocol instance structure
 213   @param  InitType          Type of CPU INIT to perform
 214
 215   @retval EFI_SUCCESS       If CPU INIT occurred. This value should never be
 216                             seen.
 217   @retval EFI_DEVICE_ERROR  If CPU INIT failed.
 218   @retval EFI_UNSUPPORTED   Requested type of CPU INIT not supported.
 219
 220 **/
 221 EFI_STATUS
 222 EFIAPI
 223 CpuInit (
 224   IN EFI_CPU_ARCH_PROTOCOL      *This,
 225   IN EFI_CPU_INIT_TYPE          InitType
 226   )
 227 {
 228   return EFI_UNSUPPORTED;
 229 }
 230
 231
 232 /**
 233   Registers a function to be called from the CPU interrupt handler.
 234
 235   @param  This                   Protocol instance structure
 236   @param  InterruptType          Defines which interrupt to hook. IA-32
 237                                  valid range is 0x00 through 0xFF
 238   @param  InterruptHandler       A pointer to a function of type
 239                                  EFI_CPU_INTERRUPT_HANDLER that is called
 240                                  when a processor interrupt occurs.  A null
 241                                  pointer is an error condition.
 242
 243   @retval EFI_SUCCESS            If handler installed or uninstalled.
 244   @retval EFI_ALREADY_STARTED    InterruptHandler is not NULL, and a handler
 245                                  for InterruptType was previously installed.
 246   @retval EFI_INVALID_PARAMETER  InterruptHandler is NULL, and a handler for
 247                                  InterruptType was not previously installed.
 248   @retval EFI_UNSUPPORTED        The interrupt specified by InterruptType
 249                                  is not supported.
 250
 251 **/
 252 EFI_STATUS
 253 EFIAPI
 254 CpuRegisterInterruptHandler (
 255   IN EFI_CPU_ARCH_PROTOCOL         *This,
 256   IN EFI_EXCEPTION_TYPE            InterruptType,
 257   IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler
 258   )
 259 {
 260   return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
 261 }
 262
 263
 264 /**
 265   Returns a timer value from one of the CPU's internal timers. There is no
 266   inherent time interval between ticks but is a function of the CPU frequency.
 267
 268   @param  This                - Protocol instance structure.
 269   @param  TimerIndex          - Specifies which CPU timer is requested.
 270   @param  TimerValue          - Pointer to the returned timer value.
 271   @param  TimerPeriod         - A pointer to the amount of time that passes
 272                                 in femtoseconds (10-15) for each increment
 273                                 of TimerValue. If TimerValue does not
 274                                 increment at a predictable rate, then 0 is
 275                                 returned.  The amount of time that has
 276                                 passed between two calls to GetTimerValue()
 277                                 can be calculated with the formula
 278                                 (TimerValue2 - TimerValue1) * TimerPeriod.
 279                                 This parameter is optional and may be NULL.
 280
 281   @retval EFI_SUCCESS           - If the CPU timer count was returned.
 282   @retval EFI_UNSUPPORTED       - If the CPU does not have any readable timers.
 283   @retval EFI_DEVICE_ERROR      - If an error occurred while reading the timer.
 284   @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
 285
 286 **/
 287 EFI_STATUS
 288 EFIAPI
 289 CpuGetTimerValue (
 290   IN  EFI_CPU_ARCH_PROTOCOL     *This,
 291   IN  UINT32                    TimerIndex,
 292   OUT UINT64                    *TimerValue,
 293   OUT UINT64                    *TimerPeriod OPTIONAL
 294   )
 295 {
 296   if (TimerValue == NULL) {
 297     return EFI_INVALID_PARAMETER;
 298   }
 299
 300   if (TimerIndex != 0) {
 301     return EFI_INVALID_PARAMETER;
 302   }
 303
 304   *TimerValue = AsmReadTsc ();
 305
 306   if (TimerPeriod != NULL) {
 307       //
 308       // BugBug: Hard coded. Don't know how to do this generically
 309       //
 310       *TimerPeriod = 1000000000;
 311   }
 312
 313   return EFI_SUCCESS;
 314 }
 315
 316
 317 /**
 318   Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.
 319
 320   This function modifies the attributes for the memory region specified by BaseAddress and
 321   Length from their current attributes to the attributes specified by Attributes.
 322
 323   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
 324   @param  BaseAddress      The physical address that is the start address of a memory region.
 325   @param  Length           The size in bytes of the memory region.
 326   @param  Attributes       The bit mask of attributes to set for the memory region.
 327
 328   @retval EFI_SUCCESS           The attributes were set for the memory region.
 329   @retval EFI_ACCESS_DENIED     The attributes for the memory resource range specified by
 330                                 BaseAddress and Length cannot be modified.
 331   @retval EFI_INVALID_PARAMETER Length is zero.
 332                                 Attributes specified an illegal combination of attributes that
 333                                 cannot be set together.
 334   @retval EFI_OUT_OF_RESOURCES  There are not enough system resources to modify the attributes of
 335                                 the memory resource range.
 336   @retval EFI_UNSUPPORTED       The processor does not support one or more bytes of the memory
 337                                 resource range specified by BaseAddress and Length.
 338                                 The bit mask of attributes is not support for the memory resource
 339                                 range specified by BaseAddress and Length.
 340
 341 **/
 342 EFI_STATUS
 343 EFIAPI
 344 CpuSetMemoryAttributes (
 345   IN EFI_CPU_ARCH_PROTOCOL     *This,
 346   IN EFI_PHYSICAL_ADDRESS      BaseAddress,
 347   IN UINT64                    Length,
 348   IN UINT64                    Attributes
 349   )
 350 {
 351   RETURN_STATUS             Status;
 352   MTRR_MEMORY_CACHE_TYPE    CacheType;
 353
 354   if (!IsMtrrSupported ()) {
 355     return EFI_UNSUPPORTED;
 356   }
 357
 358   //
 359   // If this function is called because GCD SetMemorySpaceAttributes () is called
 360   // by RefreshGcdMemoryAttributes (), then we are just synchronzing GCD memory
 361   // map with MTRR values. So there is no need to modify MTRRs, just return immediately
 362   // to avoid unnecessary computing.
 363   //
 364   if (mIsFlushingGCD) {
 365     DEBUG((EFI_D_INFO, "  Flushing GCD\n"));
 366     return EFI_SUCCESS;
 367   }
 368
 369   switch (Attributes) {
 370   case EFI_MEMORY_UC:
 371     CacheType = CacheUncacheable;
 372     break;
 373
 374   case EFI_MEMORY_WC:
 375     CacheType = CacheWriteCombining;
 376     break;
 377
 378   case EFI_MEMORY_WT:
 379     CacheType = CacheWriteThrough;
 380     break;
 381
 382   case EFI_MEMORY_WP:
 383     CacheType = CacheWriteProtected;
 384     break;
 385
 386   case EFI_MEMORY_WB:
 387     CacheType = CacheWriteBack;
 388     break;
 389
 390   case EFI_MEMORY_UCE:
 391   case EFI_MEMORY_RP:
 392   case EFI_MEMORY_XP:
 393   case EFI_MEMORY_RUNTIME:
 394     return EFI_UNSUPPORTED;
 395
 396   default:
 397     return EFI_INVALID_PARAMETER;
 398   }
 399   //
 400   // call MTRR libary function
 401   //
 402   Status = MtrrSetMemoryAttribute (
 403              BaseAddress,
 404              Length,
 405              CacheType
 406              );
 407
 408   return (EFI_STATUS) Status;
 409 }
 410
 411 /**
 412   Initializes the valid bits mask and valid address mask for MTRRs.
 413
 414   This function initializes the valid bits mask and valid address mask for MTRRs.
 415
 416 **/
 417 VOID
 418 InitializeMtrrMask (
 419   VOID
 420   )
 421 {
 422   UINT32                              RegEax;
 423   UINT8                               PhysicalAddressBits;
 424
 425   AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
 426
 427   if (RegEax >= 0x80000008) {
 428     AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
 429
 430     PhysicalAddressBits = (UINT8) RegEax;
 431
 432     mValidMtrrBitsMask    = LShiftU64 (1, PhysicalAddressBits) - 1;
 433     mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;
 434   } else {
 435     mValidMtrrBitsMask    = MTRR_LIB_MSR_VALID_MASK;
 436     mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
 437   }
 438 }
 439
 440 /**
 441   Gets GCD Mem Space type from MTRR Type.
 442
 443   This function gets GCD Mem Space type from MTRR Type.
 444
 445   @param  MtrrAttributes  MTRR memory type
 446
 447   @return GCD Mem Space type
 448
 449 **/
 450 UINT64
 451 GetMemorySpaceAttributeFromMtrrType (
 452   IN UINT8                MtrrAttributes
 453   )
 454 {
 455   switch (MtrrAttributes) {
 456   case MTRR_CACHE_UNCACHEABLE:
 457     return EFI_MEMORY_UC;
 458   case MTRR_CACHE_WRITE_COMBINING:
 459     return EFI_MEMORY_WC;
 460   case MTRR_CACHE_WRITE_THROUGH:
 461     return EFI_MEMORY_WT;
 462   case MTRR_CACHE_WRITE_PROTECTED:
 463     return EFI_MEMORY_WP;
 464   case MTRR_CACHE_WRITE_BACK:
 465     return EFI_MEMORY_WB;
 466   default:
 467     return 0;
 468   }
 469 }
 470
 471 /**
 472   Searches memory descriptors covered by given memory range.
 473
 474   This function searches into the Gcd Memory Space for descriptors
 475   (from StartIndex to EndIndex) that contains the memory range
 476   specified by BaseAddress and Length.
 477
 478   @param  MemorySpaceMap       Gcd Memory Space Map as array.
 479   @param  NumberOfDescriptors  Number of descriptors in map.
 480   @param  BaseAddress          BaseAddress for the requested range.
 481   @param  Length               Length for the requested range.
 482   @param  StartIndex           Start index into the Gcd Memory Space Map.
 483   @param  EndIndex             End index into the Gcd Memory Space Map.
 484
 485   @retval EFI_SUCCESS          Search successfully.
 486   @retval EFI_NOT_FOUND        The requested descriptors does not exist.
 487
 488 **/
 489 EFI_STATUS
 490 SearchGcdMemorySpaces (
 491   IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap,
 492   IN UINTN                               NumberOfDescriptors,
 493   IN EFI_PHYSICAL_ADDRESS                BaseAddress,
 494   IN UINT64                              Length,
 495   OUT UINTN                              *StartIndex,
 496   OUT UINTN                              *EndIndex
 497   )
 498 {
 499   UINTN           Index;
 500
 501   *StartIndex = 0;
 502   *EndIndex   = 0;
 503   for (Index = 0; Index < NumberOfDescriptors; Index++) {
 504     if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&
 505         BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
 506       *StartIndex = Index;
 507     }
 508     if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&
 509         BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
 510       *EndIndex = Index;
 511       return EFI_SUCCESS;
 512     }
 513   }
 514   return EFI_NOT_FOUND;
 515 }
 516
 517 /**
 518   Sets the attributes for a specified range in Gcd Memory Space Map.
 519
 520   This function sets the attributes for a specified range in
 521   Gcd Memory Space Map.
 522
 523   @param  MemorySpaceMap       Gcd Memory Space Map as array
 524   @param  NumberOfDescriptors  Number of descriptors in map
 525   @param  BaseAddress          BaseAddress for the range
 526   @param  Length               Length for the range
 527   @param  Attributes           Attributes to set
 528
 529   @retval EFI_SUCCESS          Memory attributes set successfully
 530   @retval EFI_NOT_FOUND        The specified range does not exist in Gcd Memory Space
 531
 532 **/
 533 EFI_STATUS
 534 SetGcdMemorySpaceAttributes (
 535   IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap,
 536   IN UINTN                               NumberOfDescriptors,
 537   IN EFI_PHYSICAL_ADDRESS                BaseAddress,
 538   IN UINT64                              Length,
 539   IN UINT64                              Attributes
 540   )
 541 {
 542   EFI_STATUS            Status;
 543   UINTN                 Index;
 544   UINTN                 StartIndex;
 545   UINTN                 EndIndex;
 546   EFI_PHYSICAL_ADDRESS  RegionStart;
 547   UINT64                RegionLength;
 548
 549   //
 550   // Get all memory descriptors covered by the memory range
 551   //
 552   Status = SearchGcdMemorySpaces (
 553              MemorySpaceMap,
 554              NumberOfDescriptors,
 555              BaseAddress,
 556              Length,
 557              &StartIndex,
 558              &EndIndex
 559              );
 560   if (EFI_ERROR (Status)) {
 561     return Status;
 562   }
 563
 564   //
 565   // Go through all related descriptors and set attributes accordingly
 566   //
 567   for (Index = StartIndex; Index <= EndIndex; Index++) {
 568     if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
 569       continue;
 570     }
 571     //
 572     // Calculate the start and end address of the overlapping range
 573     //
 574     if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {
 575       RegionStart = BaseAddress;
 576     } else {
 577       RegionStart = MemorySpaceMap[Index].BaseAddress;
 578     }
 579     if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
 580       RegionLength = BaseAddress + Length - RegionStart;
 581     } else {
 582       RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
 583     }
 584     //
 585     // Set memory attributes according to MTRR attribute and the original attribute of descriptor
 586     //
 587     gDS->SetMemorySpaceAttributes (
 588            RegionStart,
 589            RegionLength,
 590            (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
 591            );
 592   }
 593
 594   return EFI_SUCCESS;
 595 }
 596
 597
 598 /**
 599   Refreshes the GCD Memory Space attributes according to MTRRs.
 600
 601   This function refreshes the GCD Memory Space attributes according to MTRRs.
 602
 603 **/
 604 VOID
 605 RefreshGcdMemoryAttributes (
 606   VOID
 607   )
 608 {
 609   EFI_STATUS                          Status;
 610   UINTN                               Index;
 611   UINTN                               SubIndex;
 612   UINT64                              RegValue;
 613   EFI_PHYSICAL_ADDRESS                BaseAddress;
 614   UINT64                              Length;
 615   UINT64                              Attributes;
 616   UINT64                              CurrentAttributes;
 617   UINT8                               MtrrType;
 618   UINTN                               NumberOfDescriptors;
 619   EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap;
 620   UINT64                              DefaultAttributes;
 621   VARIABLE_MTRR                       VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
 622   MTRR_FIXED_SETTINGS                 MtrrFixedSettings;
 623   UINT32                              FirmwareVariableMtrrCount;
 624   UINT8                               DefaultMemoryType;
 625
 626   if (!IsMtrrSupported ()) {
 627     return;
 628   }
 629
 630   FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();
 631   ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);
 632
 633   mIsFlushingGCD = TRUE;
 634   MemorySpaceMap = NULL;
 635
 636   //
 637   // Initialize the valid bits mask and valid address mask for MTRRs
 638   //
 639   InitializeMtrrMask ();
 640
 641   //
 642   // Get the memory attribute of variable MTRRs
 643   //
 644   MtrrGetMemoryAttributeInVariableMtrr (
 645     mValidMtrrBitsMask,
 646     mValidMtrrAddressMask,
 647     VariableMtrr
 648     );
 649
 650   //
 651   // Get the memory space map from GCD
 652   //
 653   Status = gDS->GetMemorySpaceMap (
 654                   &NumberOfDescriptors,
 655                   &MemorySpaceMap
 656                   );
 657   ASSERT_EFI_ERROR (Status);
 658
 659   DefaultMemoryType = (UINT8) MtrrGetDefaultMemoryType ();
 660   DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (DefaultMemoryType);
 661
 662   //
 663   // Set default attributes to all spaces.
 664   //
 665   for (Index = 0; Index < NumberOfDescriptors; Index++) {
 666     if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
 667       continue;
 668     }
 669     gDS->SetMemorySpaceAttributes (
 670            MemorySpaceMap[Index].BaseAddress,
 671            MemorySpaceMap[Index].Length,
 672            (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) |
 673            (MemorySpaceMap[Index].Capabilities & DefaultAttributes)
 674            );
 675   }
 676
 677   //
 678   // Go for variable MTRRs with WB attribute
 679   //
 680   for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
 681     if (VariableMtrr[Index].Valid &&
 682         VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) {
 683       SetGcdMemorySpaceAttributes (
 684         MemorySpaceMap,
 685         NumberOfDescriptors,
 686         VariableMtrr[Index].BaseAddress,
 687         VariableMtrr[Index].Length,
 688         EFI_MEMORY_WB
 689         );
 690     }
 691   }
 692
 693   //
 694   // Go for variable MTRRs with the attribute except for WB and UC attributes
 695   //
 696   for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
 697     if (VariableMtrr[Index].Valid &&
 698         VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK &&
 699         VariableMtrr[Index].Type != MTRR_CACHE_UNCACHEABLE) {
 700       Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8) VariableMtrr[Index].Type);
 701       SetGcdMemorySpaceAttributes (
 702         MemorySpaceMap,
 703         NumberOfDescriptors,
 704         VariableMtrr[Index].BaseAddress,
 705         VariableMtrr[Index].Length,
 706         Attributes
 707         );
 708     }
 709   }
 710
 711   //
 712   // Go for variable MTRRs with UC attribute
 713   //
 714   for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
 715     if (VariableMtrr[Index].Valid &&
 716         VariableMtrr[Index].Type == MTRR_CACHE_UNCACHEABLE) {
 717       SetGcdMemorySpaceAttributes (
 718         MemorySpaceMap,
 719         NumberOfDescriptors,
 720         VariableMtrr[Index].BaseAddress,
 721         VariableMtrr[Index].Length,
 722         EFI_MEMORY_UC
 723         );
 724     }
 725   }
 726
 727   //
 728   // Go for fixed MTRRs
 729   //
 730   Attributes  = 0;
 731   BaseAddress = 0;
 732   Length      = 0;
 733   MtrrGetFixedMtrr (&MtrrFixedSettings);
 734   for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {
 735     RegValue = MtrrFixedSettings.Mtrr[Index];
 736     //
 737     // Check for continuous fixed MTRR sections
 738     //
 739     for (SubIndex = 0; SubIndex < 8; SubIndex++) {
 740       MtrrType = (UINT8) RShiftU64 (RegValue, SubIndex * 8);
 741       CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType);
 742       if (Length == 0) {
 743         //
 744         // A new MTRR attribute begins
 745         //
 746         Attributes = CurrentAttributes;
 747       } else {
 748         //
 749         // If fixed MTRR attribute changed, then set memory attribute for previous atrribute
 750         //
 751         if (CurrentAttributes != Attributes) {
 752           SetGcdMemorySpaceAttributes (
 753             MemorySpaceMap,
 754             NumberOfDescriptors,
 755             BaseAddress,
 756             Length,
 757             Attributes
 758             );
 759           BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex;
 760           Length = 0;
 761           Attributes = CurrentAttributes;
 762         }
 763       }
 764       Length += mFixedMtrrTable[Index].Length;
 765     }
 766   }
 767   //
 768   // Handle the last fixed MTRR region
 769   //
 770   SetGcdMemorySpaceAttributes (
 771     MemorySpaceMap,
 772     NumberOfDescriptors,
 773     BaseAddress,
 774     Length,
 775     Attributes
 776     );
 777
 778   //
 779   // Free memory space map allocated by GCD service GetMemorySpaceMap ()
 780   //
 781   if (MemorySpaceMap != NULL) {
 782     FreePool (MemorySpaceMap);
 783   }
 784
 785   mIsFlushingGCD = FALSE;
 786 }
 787
 788 /**
 789   Initialize Interrupt Descriptor Table for interrupt handling.
 790
 791 **/
 792 VOID
 793 InitInterruptDescriptorTable (
 794   VOID
 795   )
 796 {
 797   EFI_STATUS                     Status;
 798   EFI_VECTOR_HANDOFF_INFO        *VectorInfoList;
 799   EFI_VECTOR_HANDOFF_INFO        *VectorInfo;
 800
 801   VectorInfo = NULL;
 802   Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **) &VectorInfoList);
 803   if (Status == EFI_SUCCESS && VectorInfoList != NULL) {
 804     VectorInfo = VectorInfoList;
 805   }
 806   Status = InitializeCpuInterruptHandlers (VectorInfo);
 807   ASSERT_EFI_ERROR (Status);
 808 }
 809
 810
 811 /**
 812   Callback function for idle events.
 813
 814   @param  Event                 Event whose notification function is being invoked.
 815   @param  Context               The pointer to the notification function's context,
 816                                 which is implementation-dependent.
 817
 818 **/
 819 VOID
 820 EFIAPI
 821 IdleLoopEventCallback (
 822   IN EFI_EVENT                Event,
 823   IN VOID                     *Context
 824   )
 825 {
 826   CpuSleep ();
 827 }
 828
 829
 830 /**
 831   Initialize the state information for the CPU Architectural Protocol.
 832
 833   @param ImageHandle     Image handle this driver.
 834   @param SystemTable     Pointer to the System Table.
 835
 836   @retval EFI_SUCCESS           Thread can be successfully created
 837   @retval EFI_OUT_OF_RESOURCES  Cannot allocate protocol data structure
 838   @retval EFI_DEVICE_ERROR      Cannot create the thread
 839
 840 **/
 841 EFI_STATUS
 842 EFIAPI
 843 InitializeCpu (
 844   IN EFI_HANDLE                            ImageHandle,
 845   IN EFI_SYSTEM_TABLE                      *SystemTable
 846   )
 847 {
 848   EFI_STATUS  Status;
 849   EFI_EVENT   IdleLoopEvent;
 850
 851   InitializeFloatingPointUnits ();
 852
 853   //
 854   // Make sure interrupts are disabled
 855   //
 856   DisableInterrupts ();
 857
 858   //
 859   // Init GDT for DXE
 860   //
 861   InitGlobalDescriptorTable ();
 862
 863   //
 864   // Setup IDT pointer, IDT and interrupt entry points
 865   //
 866   InitInterruptDescriptorTable ();
 867
 868   //
 869   // Enable the local APIC for Virtual Wire Mode.
 870   //
 871   ProgramVirtualWireMode ();
 872
 873   //
 874   // Install CPU Architectural Protocol
 875   //
 876   Status = gBS->InstallMultipleProtocolInterfaces (
 877                   &mCpuHandle,
 878                   &gEfiCpuArchProtocolGuid, &gCpu,
 879                   NULL
 880                   );
 881   ASSERT_EFI_ERROR (Status);
 882
 883   //
 884   // Refresh GCD memory space map according to MTRR value.
 885   //
 886   RefreshGcdMemoryAttributes ();
 887
 888   //
 889   // Setup a callback for idle events
 890   //
 891   Status = gBS->CreateEventEx (
 892                   EVT_NOTIFY_SIGNAL,
 893                   TPL_NOTIFY,
 894                   IdleLoopEventCallback,
 895                   NULL,
 896                   &gIdleLoopEventGuid,
 897                   &IdleLoopEvent
 898                   );
 899   ASSERT_EFI_ERROR (Status);
 900
 901   InitializeMpSupport ();
 902
 903   return Status;
 904 }
 905