UefiCpuPkg/CpuDxe/CpuDxe.c

   1 /** @file
   2   CPU DXE Module to produce CPU ARCH Protocol.
   3
   4   Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include "CpuDxe.h"
  16 #include "CpuMp.h"
  17 #include "CpuPageTable.h"
  18
  19 #define CACHE_ATTRIBUTE_MASK   (EFI_MEMORY_UC | EFI_MEMORY_WC | EFI_MEMORY_WT | EFI_MEMORY_WB | EFI_MEMORY_UCE | EFI_MEMORY_WP)
  20 #define MEMORY_ATTRIBUTE_MASK  (EFI_MEMORY_RP | EFI_MEMORY_XP | EFI_MEMORY_RO)
  21
  22 //
  23 // Global Variables
  24 //
  25 BOOLEAN                   InterruptState = FALSE;
  26 EFI_HANDLE                mCpuHandle = NULL;
  27 BOOLEAN                   mIsFlushingGCD;
  28 UINT64                    mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
  29 UINT64                    mValidMtrrBitsMask    = MTRR_LIB_MSR_VALID_MASK;
  30 UINT64                    mTimerPeriod = 0;
  31
  32 FIXED_MTRR    mFixedMtrrTable[] = {
  33   {
  34     MTRR_LIB_IA32_MTRR_FIX64K_00000,
  35     0,
  36     0x10000
  37   },
  38   {
  39     MTRR_LIB_IA32_MTRR_FIX16K_80000,
  40     0x80000,
  41     0x4000
  42   },
  43   {
  44     MTRR_LIB_IA32_MTRR_FIX16K_A0000,
  45     0xA0000,
  46     0x4000
  47   },
  48   {
  49     MTRR_LIB_IA32_MTRR_FIX4K_C0000,
  50     0xC0000,
  51     0x1000
  52   },
  53   {
  54     MTRR_LIB_IA32_MTRR_FIX4K_C8000,
  55     0xC8000,
  56     0x1000
  57   },
  58   {
  59     MTRR_LIB_IA32_MTRR_FIX4K_D0000,
  60     0xD0000,
  61     0x1000
  62   },
  63   {
  64     MTRR_LIB_IA32_MTRR_FIX4K_D8000,
  65     0xD8000,
  66     0x1000
  67   },
  68   {
  69     MTRR_LIB_IA32_MTRR_FIX4K_E0000,
  70     0xE0000,
  71     0x1000
  72   },
  73   {
  74     MTRR_LIB_IA32_MTRR_FIX4K_E8000,
  75     0xE8000,
  76     0x1000
  77   },
  78   {
  79     MTRR_LIB_IA32_MTRR_FIX4K_F0000,
  80     0xF0000,
  81     0x1000
  82   },
  83   {
  84     MTRR_LIB_IA32_MTRR_FIX4K_F8000,
  85     0xF8000,
  86     0x1000
  87   },
  88 };
  89
  90
  91 EFI_CPU_ARCH_PROTOCOL  gCpu = {
  92   CpuFlushCpuDataCache,
  93   CpuEnableInterrupt,
  94   CpuDisableInterrupt,
  95   CpuGetInterruptState,
  96   CpuInit,
  97   CpuRegisterInterruptHandler,
  98   CpuGetTimerValue,
  99   CpuSetMemoryAttributes,
 100   1,                          // NumberOfTimers
 101   4                           // DmaBufferAlignment
 102 };
 103
 104 //
 105 // CPU Arch Protocol Functions
 106 //
 107
 108 /**
 109   Flush CPU data cache. If the instruction cache is fully coherent
 110   with all DMA operations then function can just return EFI_SUCCESS.
 111
 112   @param  This              Protocol instance structure
 113   @param  Start             Physical address to start flushing from.
 114   @param  Length            Number of bytes to flush. Round up to chipset
 115                             granularity.
 116   @param  FlushType         Specifies the type of flush operation to perform.
 117
 118   @retval EFI_SUCCESS       If cache was flushed
 119   @retval EFI_UNSUPPORTED   If flush type is not supported.
 120   @retval EFI_DEVICE_ERROR  If requested range could not be flushed.
 121
 122 **/
 123 EFI_STATUS
 124 EFIAPI
 125 CpuFlushCpuDataCache (
 126   IN EFI_CPU_ARCH_PROTOCOL     *This,
 127   IN EFI_PHYSICAL_ADDRESS      Start,
 128   IN UINT64                    Length,
 129   IN EFI_CPU_FLUSH_TYPE        FlushType
 130   )
 131 {
 132   if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {
 133     AsmWbinvd ();
 134     return EFI_SUCCESS;
 135   } else if (FlushType == EfiCpuFlushTypeInvalidate) {
 136     AsmInvd ();
 137     return EFI_SUCCESS;
 138   } else {
 139     return EFI_UNSUPPORTED;
 140   }
 141 }
 142
 143
 144 /**
 145   Enables CPU interrupts.
 146
 147   @param  This              Protocol instance structure
 148
 149   @retval EFI_SUCCESS       If interrupts were enabled in the CPU
 150   @retval EFI_DEVICE_ERROR  If interrupts could not be enabled on the CPU.
 151
 152 **/
 153 EFI_STATUS
 154 EFIAPI
 155 CpuEnableInterrupt (
 156   IN EFI_CPU_ARCH_PROTOCOL          *This
 157   )
 158 {
 159   EnableInterrupts ();
 160
 161   InterruptState = TRUE;
 162   return EFI_SUCCESS;
 163 }
 164
 165
 166 /**
 167   Disables CPU interrupts.
 168
 169   @param  This              Protocol instance structure
 170
 171   @retval EFI_SUCCESS       If interrupts were disabled in the CPU.
 172   @retval EFI_DEVICE_ERROR  If interrupts could not be disabled on the CPU.
 173
 174 **/
 175 EFI_STATUS
 176 EFIAPI
 177 CpuDisableInterrupt (
 178   IN EFI_CPU_ARCH_PROTOCOL     *This
 179   )
 180 {
 181   DisableInterrupts ();
 182
 183   InterruptState = FALSE;
 184   return EFI_SUCCESS;
 185 }
 186
 187
 188 /**
 189   Return the state of interrupts.
 190
 191   @param  This                   Protocol instance structure
 192   @param  State                  Pointer to the CPU's current interrupt state
 193
 194   @retval EFI_SUCCESS            If interrupts were disabled in the CPU.
 195   @retval EFI_INVALID_PARAMETER  State is NULL.
 196
 197 **/
 198 EFI_STATUS
 199 EFIAPI
 200 CpuGetInterruptState (
 201   IN  EFI_CPU_ARCH_PROTOCOL     *This,
 202   OUT BOOLEAN                   *State
 203   )
 204 {
 205   if (State == NULL) {
 206     return EFI_INVALID_PARAMETER;
 207   }
 208
 209   *State = InterruptState;
 210   return EFI_SUCCESS;
 211 }
 212
 213
 214 /**
 215   Generates an INIT to the CPU.
 216
 217   @param  This              Protocol instance structure
 218   @param  InitType          Type of CPU INIT to perform
 219
 220   @retval EFI_SUCCESS       If CPU INIT occurred. This value should never be
 221                             seen.
 222   @retval EFI_DEVICE_ERROR  If CPU INIT failed.
 223   @retval EFI_UNSUPPORTED   Requested type of CPU INIT not supported.
 224
 225 **/
 226 EFI_STATUS
 227 EFIAPI
 228 CpuInit (
 229   IN EFI_CPU_ARCH_PROTOCOL      *This,
 230   IN EFI_CPU_INIT_TYPE          InitType
 231   )
 232 {
 233   return EFI_UNSUPPORTED;
 234 }
 235
 236
 237 /**
 238   Registers a function to be called from the CPU interrupt handler.
 239
 240   @param  This                   Protocol instance structure
 241   @param  InterruptType          Defines which interrupt to hook. IA-32
 242                                  valid range is 0x00 through 0xFF
 243   @param  InterruptHandler       A pointer to a function of type
 244                                  EFI_CPU_INTERRUPT_HANDLER that is called
 245                                  when a processor interrupt occurs.  A null
 246                                  pointer is an error condition.
 247
 248   @retval EFI_SUCCESS            If handler installed or uninstalled.
 249   @retval EFI_ALREADY_STARTED    InterruptHandler is not NULL, and a handler
 250                                  for InterruptType was previously installed.
 251   @retval EFI_INVALID_PARAMETER  InterruptHandler is NULL, and a handler for
 252                                  InterruptType was not previously installed.
 253   @retval EFI_UNSUPPORTED        The interrupt specified by InterruptType
 254                                  is not supported.
 255
 256 **/
 257 EFI_STATUS
 258 EFIAPI
 259 CpuRegisterInterruptHandler (
 260   IN EFI_CPU_ARCH_PROTOCOL         *This,
 261   IN EFI_EXCEPTION_TYPE            InterruptType,
 262   IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler
 263   )
 264 {
 265   return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
 266 }
 267
 268
 269 /**
 270   Returns a timer value from one of the CPU's internal timers. There is no
 271   inherent time interval between ticks but is a function of the CPU frequency.
 272
 273   @param  This                - Protocol instance structure.
 274   @param  TimerIndex          - Specifies which CPU timer is requested.
 275   @param  TimerValue          - Pointer to the returned timer value.
 276   @param  TimerPeriod         - A pointer to the amount of time that passes
 277                                 in femtoseconds (10-15) for each increment
 278                                 of TimerValue. If TimerValue does not
 279                                 increment at a predictable rate, then 0 is
 280                                 returned.  The amount of time that has
 281                                 passed between two calls to GetTimerValue()
 282                                 can be calculated with the formula
 283                                 (TimerValue2 - TimerValue1) * TimerPeriod.
 284                                 This parameter is optional and may be NULL.
 285
 286   @retval EFI_SUCCESS           - If the CPU timer count was returned.
 287   @retval EFI_UNSUPPORTED       - If the CPU does not have any readable timers.
 288   @retval EFI_DEVICE_ERROR      - If an error occurred while reading the timer.
 289   @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
 290
 291 **/
 292 EFI_STATUS
 293 EFIAPI
 294 CpuGetTimerValue (
 295   IN  EFI_CPU_ARCH_PROTOCOL     *This,
 296   IN  UINT32                    TimerIndex,
 297   OUT UINT64                    *TimerValue,
 298   OUT UINT64                    *TimerPeriod OPTIONAL
 299   )
 300 {
 301   UINT64          BeginValue;
 302   UINT64          EndValue;
 303
 304   if (TimerValue == NULL) {
 305     return EFI_INVALID_PARAMETER;
 306   }
 307
 308   if (TimerIndex != 0) {
 309     return EFI_INVALID_PARAMETER;
 310   }
 311
 312   *TimerValue = AsmReadTsc ();
 313
 314   if (TimerPeriod != NULL) {
 315     if (mTimerPeriod == 0) {
 316       //
 317       // Read time stamp counter before and after delay of 100 microseconds
 318       //
 319       BeginValue = AsmReadTsc ();
 320       MicroSecondDelay (100);
 321       EndValue   = AsmReadTsc ();
 322       //
 323       // Calculate the actual frequency
 324       //
 325       mTimerPeriod = DivU64x64Remainder (
 326                        MultU64x32 (
 327                          1000 * 1000 * 1000,
 328                          100
 329                          ),
 330                        EndValue - BeginValue,
 331                        NULL
 332                        );
 333     }
 334     *TimerPeriod = mTimerPeriod;
 335   }
 336
 337   return EFI_SUCCESS;
 338 }
 339
 340 /**
 341   A minimal wrapper function that allows MtrrSetAllMtrrs() to be passed to
 342   EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() as Procedure.
 343
 344   @param[in] Buffer  Pointer to an MTRR_SETTINGS object, to be passed to
 345                      MtrrSetAllMtrrs().
 346 **/
 347 VOID
 348 EFIAPI
 349 SetMtrrsFromBuffer (
 350   IN VOID *Buffer
 351   )
 352 {
 353   MtrrSetAllMtrrs (Buffer);
 354 }
 355
 356 /**
 357   Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.
 358
 359   This function modifies the attributes for the memory region specified by BaseAddress and
 360   Length from their current attributes to the attributes specified by Attributes.
 361
 362   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
 363   @param  BaseAddress      The physical address that is the start address of a memory region.
 364   @param  Length           The size in bytes of the memory region.
 365   @param  Attributes       The bit mask of attributes to set for the memory region.
 366
 367   @retval EFI_SUCCESS           The attributes were set for the memory region.
 368   @retval EFI_ACCESS_DENIED     The attributes for the memory resource range specified by
 369                                 BaseAddress and Length cannot be modified.
 370   @retval EFI_INVALID_PARAMETER Length is zero.
 371                                 Attributes specified an illegal combination of attributes that
 372                                 cannot be set together.
 373   @retval EFI_OUT_OF_RESOURCES  There are not enough system resources to modify the attributes of
 374                                 the memory resource range.
 375   @retval EFI_UNSUPPORTED       The processor does not support one or more bytes of the memory
 376                                 resource range specified by BaseAddress and Length.
 377                                 The bit mask of attributes is not support for the memory resource
 378                                 range specified by BaseAddress and Length.
 379
 380 **/
 381 EFI_STATUS
 382 EFIAPI
 383 CpuSetMemoryAttributes (
 384   IN EFI_CPU_ARCH_PROTOCOL     *This,
 385   IN EFI_PHYSICAL_ADDRESS      BaseAddress,
 386   IN UINT64                    Length,
 387   IN UINT64                    Attributes
 388   )
 389 {
 390   RETURN_STATUS             Status;
 391   MTRR_MEMORY_CACHE_TYPE    CacheType;
 392   EFI_STATUS                MpStatus;
 393   EFI_MP_SERVICES_PROTOCOL  *MpService;
 394   MTRR_SETTINGS             MtrrSettings;
 395   UINT64                    CacheAttributes;
 396   UINT64                    MemoryAttributes;
 397   MTRR_MEMORY_CACHE_TYPE    CurrentCacheType;
 398
 399   //
 400   // If this function is called because GCD SetMemorySpaceAttributes () is called
 401   // by RefreshGcdMemoryAttributes (), then we are just synchronzing GCD memory
 402   // map with MTRR values. So there is no need to modify MTRRs, just return immediately
 403   // to avoid unnecessary computing.
 404   //
 405   if (mIsFlushingGCD) {
 406     DEBUG((EFI_D_INFO, "  Flushing GCD\n"));
 407     return EFI_SUCCESS;
 408   }
 409
 410
 411   CacheAttributes = Attributes & CACHE_ATTRIBUTE_MASK;
 412   MemoryAttributes = Attributes & MEMORY_ATTRIBUTE_MASK;
 413
 414   if (Attributes != (CacheAttributes | MemoryAttributes)) {
 415     return EFI_INVALID_PARAMETER;
 416   }
 417
 418   if (CacheAttributes != 0) {
 419     if (!IsMtrrSupported ()) {
 420       return EFI_UNSUPPORTED;
 421     }
 422
 423     switch (CacheAttributes) {
 424     case EFI_MEMORY_UC:
 425       CacheType = CacheUncacheable;
 426       break;
 427
 428     case EFI_MEMORY_WC:
 429       CacheType = CacheWriteCombining;
 430       break;
 431
 432     case EFI_MEMORY_WT:
 433       CacheType = CacheWriteThrough;
 434       break;
 435
 436     case EFI_MEMORY_WP:
 437       CacheType = CacheWriteProtected;
 438       break;
 439
 440     case EFI_MEMORY_WB:
 441       CacheType = CacheWriteBack;
 442       break;
 443
 444     default:
 445       return EFI_INVALID_PARAMETER;
 446     }
 447     CurrentCacheType = MtrrGetMemoryAttribute(BaseAddress);
 448     if (CurrentCacheType != CacheType) {
 449       //
 450       // call MTRR libary function
 451       //
 452       Status = MtrrSetMemoryAttribute (
 453                  BaseAddress,
 454                  Length,
 455                  CacheType
 456                  );
 457
 458       if (!RETURN_ERROR (Status)) {
 459         MpStatus = gBS->LocateProtocol (
 460                           &gEfiMpServiceProtocolGuid,
 461                           NULL,
 462                           (VOID **)&MpService
 463                           );
 464         //
 465         // Synchronize the update with all APs
 466         //
 467         if (!EFI_ERROR (MpStatus)) {
 468           MtrrGetAllMtrrs (&MtrrSettings);
 469           MpStatus = MpService->StartupAllAPs (
 470                                   MpService,          // This
 471                                   SetMtrrsFromBuffer, // Procedure
 472                                   FALSE,              // SingleThread
 473                                   NULL,               // WaitEvent
 474                                   0,                  // TimeoutInMicrosecsond
 475                                   &MtrrSettings,      // ProcedureArgument
 476                                   NULL                // FailedCpuList
 477                                   );
 478           ASSERT (MpStatus == EFI_SUCCESS || MpStatus == EFI_NOT_STARTED);
 479         }
 480       }
 481       if (EFI_ERROR(Status)) {
 482         return Status;
 483       }
 484     }
 485   }
 486
 487   //
 488   // Set memory attribute by page table
 489   //
 490   return AssignMemoryPageAttributes (NULL, BaseAddress, Length, MemoryAttributes, AllocatePages);
 491 }
 492
 493 /**
 494   Initializes the valid bits mask and valid address mask for MTRRs.
 495
 496   This function initializes the valid bits mask and valid address mask for MTRRs.
 497
 498 **/
 499 VOID
 500 InitializeMtrrMask (
 501   VOID
 502   )
 503 {
 504   UINT32                              RegEax;
 505   UINT8                               PhysicalAddressBits;
 506
 507   AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
 508
 509   if (RegEax >= 0x80000008) {
 510     AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
 511
 512     PhysicalAddressBits = (UINT8) RegEax;
 513
 514     mValidMtrrBitsMask    = LShiftU64 (1, PhysicalAddressBits) - 1;
 515     mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;
 516   } else {
 517     mValidMtrrBitsMask    = MTRR_LIB_MSR_VALID_MASK;
 518     mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
 519   }
 520 }
 521
 522 /**
 523   Gets GCD Mem Space type from MTRR Type.
 524
 525   This function gets GCD Mem Space type from MTRR Type.
 526
 527   @param  MtrrAttributes  MTRR memory type
 528
 529   @return GCD Mem Space type
 530
 531 **/
 532 UINT64
 533 GetMemorySpaceAttributeFromMtrrType (
 534   IN UINT8                MtrrAttributes
 535   )
 536 {
 537   switch (MtrrAttributes) {
 538   case MTRR_CACHE_UNCACHEABLE:
 539     return EFI_MEMORY_UC;
 540   case MTRR_CACHE_WRITE_COMBINING:
 541     return EFI_MEMORY_WC;
 542   case MTRR_CACHE_WRITE_THROUGH:
 543     return EFI_MEMORY_WT;
 544   case MTRR_CACHE_WRITE_PROTECTED:
 545     return EFI_MEMORY_WP;
 546   case MTRR_CACHE_WRITE_BACK:
 547     return EFI_MEMORY_WB;
 548   default:
 549     return 0;
 550   }
 551 }
 552
 553 /**
 554   Searches memory descriptors covered by given memory range.
 555
 556   This function searches into the Gcd Memory Space for descriptors
 557   (from StartIndex to EndIndex) that contains the memory range
 558   specified by BaseAddress and Length.
 559
 560   @param  MemorySpaceMap       Gcd Memory Space Map as array.
 561   @param  NumberOfDescriptors  Number of descriptors in map.
 562   @param  BaseAddress          BaseAddress for the requested range.
 563   @param  Length               Length for the requested range.
 564   @param  StartIndex           Start index into the Gcd Memory Space Map.
 565   @param  EndIndex             End index into the Gcd Memory Space Map.
 566
 567   @retval EFI_SUCCESS          Search successfully.
 568   @retval EFI_NOT_FOUND        The requested descriptors does not exist.
 569
 570 **/
 571 EFI_STATUS
 572 SearchGcdMemorySpaces (
 573   IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap,
 574   IN UINTN                               NumberOfDescriptors,
 575   IN EFI_PHYSICAL_ADDRESS                BaseAddress,
 576   IN UINT64                              Length,
 577   OUT UINTN                              *StartIndex,
 578   OUT UINTN                              *EndIndex
 579   )
 580 {
 581   UINTN           Index;
 582
 583   *StartIndex = 0;
 584   *EndIndex   = 0;
 585   for (Index = 0; Index < NumberOfDescriptors; Index++) {
 586     if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&
 587         BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
 588       *StartIndex = Index;
 589     }
 590     if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&
 591         BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
 592       *EndIndex = Index;
 593       return EFI_SUCCESS;
 594     }
 595   }
 596   return EFI_NOT_FOUND;
 597 }
 598
 599 /**
 600   Sets the attributes for a specified range in Gcd Memory Space Map.
 601
 602   This function sets the attributes for a specified range in
 603   Gcd Memory Space Map.
 604
 605   @param  MemorySpaceMap       Gcd Memory Space Map as array
 606   @param  NumberOfDescriptors  Number of descriptors in map
 607   @param  BaseAddress          BaseAddress for the range
 608   @param  Length               Length for the range
 609   @param  Attributes           Attributes to set
 610
 611   @retval EFI_SUCCESS          Memory attributes set successfully
 612   @retval EFI_NOT_FOUND        The specified range does not exist in Gcd Memory Space
 613
 614 **/
 615 EFI_STATUS
 616 SetGcdMemorySpaceAttributes (
 617   IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap,
 618   IN UINTN                               NumberOfDescriptors,
 619   IN EFI_PHYSICAL_ADDRESS                BaseAddress,
 620   IN UINT64                              Length,
 621   IN UINT64                              Attributes
 622   )
 623 {
 624   EFI_STATUS            Status;
 625   UINTN                 Index;
 626   UINTN                 StartIndex;
 627   UINTN                 EndIndex;
 628   EFI_PHYSICAL_ADDRESS  RegionStart;
 629   UINT64                RegionLength;
 630
 631   //
 632   // Get all memory descriptors covered by the memory range
 633   //
 634   Status = SearchGcdMemorySpaces (
 635              MemorySpaceMap,
 636              NumberOfDescriptors,
 637              BaseAddress,
 638              Length,
 639              &StartIndex,
 640              &EndIndex
 641              );
 642   if (EFI_ERROR (Status)) {
 643     return Status;
 644   }
 645
 646   //
 647   // Go through all related descriptors and set attributes accordingly
 648   //
 649   for (Index = StartIndex; Index <= EndIndex; Index++) {
 650     if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
 651       continue;
 652     }
 653     //
 654     // Calculate the start and end address of the overlapping range
 655     //
 656     if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {
 657       RegionStart = BaseAddress;
 658     } else {
 659       RegionStart = MemorySpaceMap[Index].BaseAddress;
 660     }
 661     if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
 662       RegionLength = BaseAddress + Length - RegionStart;
 663     } else {
 664       RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
 665     }
 666     //
 667     // Set memory attributes according to MTRR attribute and the original attribute of descriptor
 668     //
 669     gDS->SetMemorySpaceAttributes (
 670            RegionStart,
 671            RegionLength,
 672            (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
 673            );
 674   }
 675
 676   return EFI_SUCCESS;
 677 }
 678
 679
 680 /**
 681   Refreshes the GCD Memory Space attributes according to MTRRs.
 682
 683   This function refreshes the GCD Memory Space attributes according to MTRRs.
 684
 685 **/
 686 VOID
 687 RefreshGcdMemoryAttributes (
 688   VOID
 689   )
 690 {
 691   EFI_STATUS                          Status;
 692   UINTN                               Index;
 693   UINTN                               SubIndex;
 694   UINT64                              RegValue;
 695   EFI_PHYSICAL_ADDRESS                BaseAddress;
 696   UINT64                              Length;
 697   UINT64                              Attributes;
 698   UINT64                              CurrentAttributes;
 699   UINT8                               MtrrType;
 700   UINTN                               NumberOfDescriptors;
 701   EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap;
 702   UINT64                              DefaultAttributes;
 703   VARIABLE_MTRR                       VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
 704   MTRR_FIXED_SETTINGS                 MtrrFixedSettings;
 705   UINT32                              FirmwareVariableMtrrCount;
 706   UINT8                               DefaultMemoryType;
 707
 708   if (!IsMtrrSupported ()) {
 709     return;
 710   }
 711
 712   FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();
 713   ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);
 714
 715   mIsFlushingGCD = TRUE;
 716   MemorySpaceMap = NULL;
 717
 718   //
 719   // Initialize the valid bits mask and valid address mask for MTRRs
 720   //
 721   InitializeMtrrMask ();
 722
 723   //
 724   // Get the memory attribute of variable MTRRs
 725   //
 726   MtrrGetMemoryAttributeInVariableMtrr (
 727     mValidMtrrBitsMask,
 728     mValidMtrrAddressMask,
 729     VariableMtrr
 730     );
 731
 732   //
 733   // Get the memory space map from GCD
 734   //
 735   Status = gDS->GetMemorySpaceMap (
 736                   &NumberOfDescriptors,
 737                   &MemorySpaceMap
 738                   );
 739   ASSERT_EFI_ERROR (Status);
 740
 741   DefaultMemoryType = (UINT8) MtrrGetDefaultMemoryType ();
 742   DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (DefaultMemoryType);
 743
 744   //
 745   // Set default attributes to all spaces.
 746   //
 747   for (Index = 0; Index < NumberOfDescriptors; Index++) {
 748     if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
 749       continue;
 750     }
 751     gDS->SetMemorySpaceAttributes (
 752            MemorySpaceMap[Index].BaseAddress,
 753            MemorySpaceMap[Index].Length,
 754            (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) |
 755            (MemorySpaceMap[Index].Capabilities & DefaultAttributes)
 756            );
 757   }
 758
 759   //
 760   // Go for variable MTRRs with WB attribute
 761   //
 762   for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
 763     if (VariableMtrr[Index].Valid &&
 764         VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) {
 765       SetGcdMemorySpaceAttributes (
 766         MemorySpaceMap,
 767         NumberOfDescriptors,
 768         VariableMtrr[Index].BaseAddress,
 769         VariableMtrr[Index].Length,
 770         EFI_MEMORY_WB
 771         );
 772     }
 773   }
 774
 775   //
 776   // Go for variable MTRRs with the attribute except for WB and UC attributes
 777   //
 778   for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
 779     if (VariableMtrr[Index].Valid &&
 780         VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK &&
 781         VariableMtrr[Index].Type != MTRR_CACHE_UNCACHEABLE) {
 782       Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8) VariableMtrr[Index].Type);
 783       SetGcdMemorySpaceAttributes (
 784         MemorySpaceMap,
 785         NumberOfDescriptors,
 786         VariableMtrr[Index].BaseAddress,
 787         VariableMtrr[Index].Length,
 788         Attributes
 789         );
 790     }
 791   }
 792
 793   //
 794   // Go for variable MTRRs with UC attribute
 795   //
 796   for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
 797     if (VariableMtrr[Index].Valid &&
 798         VariableMtrr[Index].Type == MTRR_CACHE_UNCACHEABLE) {
 799       SetGcdMemorySpaceAttributes (
 800         MemorySpaceMap,
 801         NumberOfDescriptors,
 802         VariableMtrr[Index].BaseAddress,
 803         VariableMtrr[Index].Length,
 804         EFI_MEMORY_UC
 805         );
 806     }
 807   }
 808
 809   //
 810   // Go for fixed MTRRs
 811   //
 812   Attributes  = 0;
 813   BaseAddress = 0;
 814   Length      = 0;
 815   MtrrGetFixedMtrr (&MtrrFixedSettings);
 816   for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {
 817     RegValue = MtrrFixedSettings.Mtrr[Index];
 818     //
 819     // Check for continuous fixed MTRR sections
 820     //
 821     for (SubIndex = 0; SubIndex < 8; SubIndex++) {
 822       MtrrType = (UINT8) RShiftU64 (RegValue, SubIndex * 8);
 823       CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType);
 824       if (Length == 0) {
 825         //
 826         // A new MTRR attribute begins
 827         //
 828         Attributes = CurrentAttributes;
 829       } else {
 830         //
 831         // If fixed MTRR attribute changed, then set memory attribute for previous atrribute
 832         //
 833         if (CurrentAttributes != Attributes) {
 834           SetGcdMemorySpaceAttributes (
 835             MemorySpaceMap,
 836             NumberOfDescriptors,
 837             BaseAddress,
 838             Length,
 839             Attributes
 840             );
 841           BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex;
 842           Length = 0;
 843           Attributes = CurrentAttributes;
 844         }
 845       }
 846       Length += mFixedMtrrTable[Index].Length;
 847     }
 848   }
 849   //
 850   // Handle the last fixed MTRR region
 851   //
 852   SetGcdMemorySpaceAttributes (
 853     MemorySpaceMap,
 854     NumberOfDescriptors,
 855     BaseAddress,
 856     Length,
 857     Attributes
 858     );
 859
 860   //
 861   // Free memory space map allocated by GCD service GetMemorySpaceMap ()
 862   //
 863   if (MemorySpaceMap != NULL) {
 864     FreePool (MemorySpaceMap);
 865   }
 866
 867   mIsFlushingGCD = FALSE;
 868 }
 869
 870 /**
 871   Initialize Interrupt Descriptor Table for interrupt handling.
 872
 873 **/
 874 VOID
 875 InitInterruptDescriptorTable (
 876   VOID
 877   )
 878 {
 879   EFI_STATUS                     Status;
 880   EFI_VECTOR_HANDOFF_INFO        *VectorInfoList;
 881   EFI_VECTOR_HANDOFF_INFO        *VectorInfo;
 882
 883   VectorInfo = NULL;
 884   Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **) &VectorInfoList);
 885   if (Status == EFI_SUCCESS && VectorInfoList != NULL) {
 886     VectorInfo = VectorInfoList;
 887   }
 888   Status = InitializeCpuInterruptHandlers (VectorInfo);
 889   ASSERT_EFI_ERROR (Status);
 890 }
 891
 892
 893 /**
 894   Callback function for idle events.
 895
 896   @param  Event                 Event whose notification function is being invoked.
 897   @param  Context               The pointer to the notification function's context,
 898                                 which is implementation-dependent.
 899
 900 **/
 901 VOID
 902 EFIAPI
 903 IdleLoopEventCallback (
 904   IN EFI_EVENT                Event,
 905   IN VOID                     *Context
 906   )
 907 {
 908   CpuSleep ();
 909 }
 910
 911 /**
 912   Ensure the compatibility of a memory space descriptor with the MMIO aperture.
 913
 914   The memory space descriptor can come from the GCD memory space map, or it can
 915   represent a gap between two neighboring memory space descriptors. In the
 916   latter case, the GcdMemoryType field is expected to be
 917   EfiGcdMemoryTypeNonExistent.
 918
 919   If the memory space descriptor already has type
 920   EfiGcdMemoryTypeMemoryMappedIo, and its capabilities are a superset of the
 921   required capabilities, then no action is taken -- it is by definition
 922   compatible with the aperture.
 923
 924   Otherwise, the intersection of the memory space descriptor is calculated with
 925   the aperture. If the intersection is the empty set (no overlap), no action is
 926   taken; the memory space descriptor is compatible with the aperture.
 927
 928   Otherwise, the type of the descriptor is investigated again. If the type is
 929   EfiGcdMemoryTypeNonExistent (representing a gap, or a genuine descriptor with
 930   such a type), then an attempt is made to add the intersection as MMIO space
 931   to the GCD memory space map, with the specified capabilities. This ensures
 932   continuity for the aperture, and the descriptor is deemed compatible with the
 933   aperture.
 934
 935   Otherwise, the memory space descriptor is incompatible with the MMIO
 936   aperture.
 937
 938   @param[in] Base         Base address of the aperture.
 939   @param[in] Length       Length of the aperture.
 940   @param[in] Capabilities Capabilities required by the aperture.
 941   @param[in] Descriptor   The descriptor to ensure compatibility with the
 942                           aperture for.
 943
 944   @retval EFI_SUCCESS            The descriptor is compatible. The GCD memory
 945                                  space map may have been updated, for
 946                                  continuity within the aperture.
 947   @retval EFI_INVALID_PARAMETER  The descriptor is incompatible.
 948   @return                        Error codes from gDS->AddMemorySpace().
 949 **/
 950 EFI_STATUS
 951 IntersectMemoryDescriptor (
 952   IN  UINT64                                Base,
 953   IN  UINT64                                Length,
 954   IN  UINT64                                Capabilities,
 955   IN  CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor
 956   )
 957 {
 958   UINT64                                    IntersectionBase;
 959   UINT64                                    IntersectionEnd;
 960   EFI_STATUS                                Status;
 961
 962   if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo &&
 963       (Descriptor->Capabilities & Capabilities) == Capabilities) {
 964     return EFI_SUCCESS;
 965   }
 966
 967   IntersectionBase = MAX (Base, Descriptor->BaseAddress);
 968   IntersectionEnd = MIN (Base + Length,
 969                       Descriptor->BaseAddress + Descriptor->Length);
 970   if (IntersectionBase >= IntersectionEnd) {
 971     //
 972     // The descriptor and the aperture don't overlap.
 973     //
 974     return EFI_SUCCESS;
 975   }
 976
 977   if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
 978     Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo,
 979                     IntersectionBase, IntersectionEnd - IntersectionBase,
 980                     Capabilities);
 981
 982     DEBUG ((EFI_ERROR (Status) ? EFI_D_ERROR : EFI_D_VERBOSE,
 983       "%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__,
 984       IntersectionBase, IntersectionEnd, Status));
 985     return Status;
 986   }
 987
 988   DEBUG ((EFI_D_ERROR, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "
 989     "with aperture [%Lx, %Lx) cap %Lx\n", gEfiCallerBaseName, __FUNCTION__,
 990     Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length,
 991     (UINT32)Descriptor->GcdMemoryType, Descriptor->Capabilities,
 992     Base, Base + Length, Capabilities));
 993   return EFI_INVALID_PARAMETER;
 994 }
 995
 996 /**
 997   Add MMIO space to GCD.
 998   The routine checks the GCD database and only adds those which are
 999   not added in the specified range to GCD.
1000
1001   @param Base         Base address of the MMIO space.
1002   @param Length       Length of the MMIO space.
1003   @param Capabilities Capabilities of the MMIO space.
1004
1005   @retval EFI_SUCCES The MMIO space was added successfully.
1006 **/
1007 EFI_STATUS
1008 AddMemoryMappedIoSpace (
1009   IN  UINT64                            Base,
1010   IN  UINT64                            Length,
1011   IN  UINT64                            Capabilities
1012   )
1013 {
1014   EFI_STATUS                            Status;
1015   UINTN                                 Index;
1016   UINTN                                 NumberOfDescriptors;
1017   EFI_GCD_MEMORY_SPACE_DESCRIPTOR       *MemorySpaceMap;
1018
1019   Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
1020   if (EFI_ERROR (Status)) {
1021     DEBUG ((EFI_D_ERROR, "%a: %a: GetMemorySpaceMap(): %r\n",
1022       gEfiCallerBaseName, __FUNCTION__, Status));
1023     return Status;
1024   }
1025
1026   for (Index = 0; Index < NumberOfDescriptors; Index++) {
1027     Status = IntersectMemoryDescriptor (Base, Length, Capabilities,
1028                &MemorySpaceMap[Index]);
1029     if (EFI_ERROR (Status)) {
1030       goto FreeMemorySpaceMap;
1031     }
1032   }
1033
1034   DEBUG_CODE (
1035     //
1036     // Make sure there are adjacent descriptors covering [Base, Base + Length).
1037     // It is possible that they have not been merged; merging can be prevented
1038     // by allocation and different capabilities.
1039     //
1040     UINT64                          CheckBase;
1041     EFI_STATUS                      CheckStatus;
1042     EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;
1043
1044     for (CheckBase = Base;
1045          CheckBase < Base + Length;
1046          CheckBase = Descriptor.BaseAddress + Descriptor.Length) {
1047       CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);
1048       ASSERT_EFI_ERROR (CheckStatus);
1049       ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);
1050       ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);
1051     }
1052     );
1053
1054 FreeMemorySpaceMap:
1055   FreePool (MemorySpaceMap);
1056
1057   return Status;
1058 }
1059
1060 /**
1061   Add and allocate CPU local APIC memory mapped space.
1062
1063   @param[in]ImageHandle     Image handle this driver.
1064
1065 **/
1066 VOID
1067 AddLocalApicMemorySpace (
1068   IN EFI_HANDLE               ImageHandle
1069   )
1070 {
1071   EFI_STATUS              Status;
1072   EFI_PHYSICAL_ADDRESS    BaseAddress;
1073
1074   BaseAddress = (EFI_PHYSICAL_ADDRESS) GetLocalApicBaseAddress();
1075   Status = AddMemoryMappedIoSpace (BaseAddress, SIZE_4KB, EFI_MEMORY_UC);
1076   ASSERT_EFI_ERROR (Status);
1077
1078   Status = gDS->AllocateMemorySpace (
1079                   EfiGcdAllocateAddress,
1080                   EfiGcdMemoryTypeMemoryMappedIo,
1081                   0,
1082                   SIZE_4KB,
1083                   &BaseAddress,
1084                   ImageHandle,
1085                   NULL
1086                   );
1087   ASSERT_EFI_ERROR (Status);
1088 }
1089
1090 /**
1091   Initialize the state information for the CPU Architectural Protocol.
1092
1093   @param ImageHandle     Image handle this driver.
1094   @param SystemTable     Pointer to the System Table.
1095
1096   @retval EFI_SUCCESS           Thread can be successfully created
1097   @retval EFI_OUT_OF_RESOURCES  Cannot allocate protocol data structure
1098   @retval EFI_DEVICE_ERROR      Cannot create the thread
1099
1100 **/
1101 EFI_STATUS
1102 EFIAPI
1103 InitializeCpu (
1104   IN EFI_HANDLE                            ImageHandle,
1105   IN EFI_SYSTEM_TABLE                      *SystemTable
1106   )
1107 {
1108   EFI_STATUS  Status;
1109   EFI_EVENT   IdleLoopEvent;
1110
1111   InitializePageTableLib();
1112
1113   InitializeFloatingPointUnits ();
1114
1115   //
1116   // Make sure interrupts are disabled
1117   //
1118   DisableInterrupts ();
1119
1120   //
1121   // Init GDT for DXE
1122   //
1123   InitGlobalDescriptorTable ();
1124
1125   //
1126   // Setup IDT pointer, IDT and interrupt entry points
1127   //
1128   InitInterruptDescriptorTable ();
1129
1130   //
1131   // Enable the local APIC for Virtual Wire Mode.
1132   //
1133   ProgramVirtualWireMode ();
1134
1135   //
1136   // Install CPU Architectural Protocol
1137   //
1138   Status = gBS->InstallMultipleProtocolInterfaces (
1139                   &mCpuHandle,
1140                   &gEfiCpuArchProtocolGuid, &gCpu,
1141                   NULL
1142                   );
1143   ASSERT_EFI_ERROR (Status);
1144
1145   //
1146   // Refresh GCD memory space map according to MTRR value.
1147   //
1148   RefreshGcdMemoryAttributes ();
1149
1150   //
1151   // Add and allocate local APIC memory mapped space
1152   //
1153   AddLocalApicMemorySpace (ImageHandle);
1154
1155   //
1156   // Setup a callback for idle events
1157   //
1158   Status = gBS->CreateEventEx (
1159                   EVT_NOTIFY_SIGNAL,
1160                   TPL_NOTIFY,
1161                   IdleLoopEventCallback,
1162                   NULL,
1163                   &gIdleLoopEventGuid,
1164                   &IdleLoopEvent
1165                   );
1166   ASSERT_EFI_ERROR (Status);
1167
1168   InitializeMpSupport ();
1169
1170   return Status;
1171 }
1172