2 Produces the CPU I/O 2 Protocol.
4 Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
11 #include "CpuIo2Dxe.h"
14 // Handle for the CPU I/O 2 Protocol
16 EFI_HANDLE mHandle
= NULL
;
19 // CPU I/O 2 Protocol instance
21 EFI_CPU_IO2_PROTOCOL mCpuIo2
= {
33 // Lookup table for increment values based on transfer widths
36 1, // EfiCpuIoWidthUint8
37 2, // EfiCpuIoWidthUint16
38 4, // EfiCpuIoWidthUint32
39 8, // EfiCpuIoWidthUint64
40 0, // EfiCpuIoWidthFifoUint8
41 0, // EfiCpuIoWidthFifoUint16
42 0, // EfiCpuIoWidthFifoUint32
43 0, // EfiCpuIoWidthFifoUint64
44 1, // EfiCpuIoWidthFillUint8
45 2, // EfiCpuIoWidthFillUint16
46 4, // EfiCpuIoWidthFillUint32
47 8 // EfiCpuIoWidthFillUint64
51 // Lookup table for increment values based on transfer widths
53 UINT8 mOutStride
[] = {
54 1, // EfiCpuIoWidthUint8
55 2, // EfiCpuIoWidthUint16
56 4, // EfiCpuIoWidthUint32
57 8, // EfiCpuIoWidthUint64
58 1, // EfiCpuIoWidthFifoUint8
59 2, // EfiCpuIoWidthFifoUint16
60 4, // EfiCpuIoWidthFifoUint32
61 8, // EfiCpuIoWidthFifoUint64
62 0, // EfiCpuIoWidthFillUint8
63 0, // EfiCpuIoWidthFillUint16
64 0, // EfiCpuIoWidthFillUint32
65 0 // EfiCpuIoWidthFillUint64
69 Check parameters to a CPU I/O 2 Protocol service request.
71 The I/O operations are carried out exactly as requested. The caller is responsible
72 for satisfying any alignment and I/O width restrictions that a PI System on a
73 platform might require. For example on some platforms, width requests of
74 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
75 be handled by the driver.
77 @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.
78 @param[in] Width Signifies the width of the I/O or Memory operation.
79 @param[in] Address The base address of the I/O operation.
80 @param[in] Count The number of I/O operations to perform. The number of
81 bytes moved is Width size * Count, starting at Address.
82 @param[in] Buffer For read operations, the destination buffer to store the results.
83 For write operations, the source buffer from which to write data.
85 @retval EFI_SUCCESS The parameters for this request pass the checks.
86 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
87 @retval EFI_INVALID_PARAMETER Buffer is NULL.
88 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
89 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
90 and Count is not valid for this PI system.
95 IN BOOLEAN MmioOperation
,
96 IN EFI_CPU_IO_PROTOCOL_WIDTH Width
,
106 // Check to see if Buffer is NULL
108 if (Buffer
== NULL
) {
109 return EFI_INVALID_PARAMETER
;
113 // Check to see if Width is in the valid range
115 if ((UINT32
)Width
>= EfiCpuIoWidthMaximum
) {
116 return EFI_INVALID_PARAMETER
;
120 // For FIFO type, the target address won't increase during the access,
121 // so treat Count as 1
123 if ((Width
>= EfiCpuIoWidthFifoUint8
) && (Width
<= EfiCpuIoWidthFifoUint64
)) {
128 // Check to see if Width is in the valid range for I/O Port operations
130 Width
= (EFI_CPU_IO_PROTOCOL_WIDTH
)(Width
& 0x03);
131 if (!MmioOperation
&& (Width
== EfiCpuIoWidthUint64
)) {
132 return EFI_INVALID_PARAMETER
;
136 // Check to see if Address is aligned
138 if ((Address
& ((UINT64
)mInStride
[Width
] - 1)) != 0) {
139 return EFI_UNSUPPORTED
;
143 // Check to see if any address associated with this transfer exceeds the maximum
144 // allowed address. The maximum address implied by the parameters passed in is
145 // Address + Size * Count. If the following condition is met, then the transfer
148 // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
150 // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
151 // can also be the maximum integer value supported by the CPU, this range
152 // check must be adjusted to avoid all oveflow conditions.
154 // The following form of the range check is equivalent but assumes that
155 // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).
157 Limit
= (MmioOperation
? MAX_ADDRESS
: MAX_IO_PORT_ADDRESS
);
159 if (Address
> Limit
) {
160 return EFI_UNSUPPORTED
;
163 MaxCount
= RShiftU64 (Limit
, Width
);
164 if (MaxCount
< (Count
- 1)) {
165 return EFI_UNSUPPORTED
;
168 if (Address
> LShiftU64 (MaxCount
- Count
+ 1, Width
)) {
169 return EFI_UNSUPPORTED
;
174 // Check to see if Buffer is aligned
175 // (IA-32 allows UINT64 and INT64 data types to be 32-bit aligned.)
177 if (((UINTN
)Buffer
& ((MIN (sizeof (UINTN
), mInStride
[Width
]) - 1))) != 0) {
178 return EFI_UNSUPPORTED
;
185 Reads memory-mapped registers.
187 The I/O operations are carried out exactly as requested. The caller is responsible
188 for satisfying any alignment and I/O width restrictions that a PI System on a
189 platform might require. For example on some platforms, width requests of
190 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
191 be handled by the driver.
193 If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
194 or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
195 each of the Count operations that is performed.
197 If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
198 EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
199 incremented for each of the Count operations that is performed. The read or
200 write operation is performed Count times on the same Address.
202 If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
203 EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
204 incremented for each of the Count operations that is performed. The read or
205 write operation is performed Count times from the first element of Buffer.
207 @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
208 @param[in] Width Signifies the width of the I/O or Memory operation.
209 @param[in] Address The base address of the I/O operation.
210 @param[in] Count The number of I/O operations to perform. The number of
211 bytes moved is Width size * Count, starting at Address.
212 @param[out] Buffer For read operations, the destination buffer to store the results.
213 For write operations, the source buffer from which to write data.
215 @retval EFI_SUCCESS The data was read from or written to the PI system.
216 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
217 @retval EFI_INVALID_PARAMETER Buffer is NULL.
218 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
219 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
220 and Count is not valid for this PI system.
225 CpuMemoryServiceRead (
226 IN EFI_CPU_IO2_PROTOCOL
*This
,
227 IN EFI_CPU_IO_PROTOCOL_WIDTH Width
,
236 EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth
;
239 Status
= CpuIoCheckParameter (TRUE
, Width
, Address
, Count
, Buffer
);
240 if (EFI_ERROR (Status
)) {
245 // Select loop based on the width of the transfer
247 InStride
= mInStride
[Width
];
248 OutStride
= mOutStride
[Width
];
249 OperationWidth
= (EFI_CPU_IO_PROTOCOL_WIDTH
)(Width
& 0x03);
250 for (Uint8Buffer
= Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
251 if (OperationWidth
== EfiCpuIoWidthUint8
) {
252 *Uint8Buffer
= MmioRead8 ((UINTN
)Address
);
253 } else if (OperationWidth
== EfiCpuIoWidthUint16
) {
254 *((UINT16
*)Uint8Buffer
) = MmioRead16 ((UINTN
)Address
);
255 } else if (OperationWidth
== EfiCpuIoWidthUint32
) {
256 *((UINT32
*)Uint8Buffer
) = MmioRead32 ((UINTN
)Address
);
257 } else if (OperationWidth
== EfiCpuIoWidthUint64
) {
258 *((UINT64
*)Uint8Buffer
) = MmioRead64 ((UINTN
)Address
);
266 Writes memory-mapped registers.
268 The I/O operations are carried out exactly as requested. The caller is responsible
269 for satisfying any alignment and I/O width restrictions that a PI System on a
270 platform might require. For example on some platforms, width requests of
271 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
272 be handled by the driver.
274 If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
275 or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
276 each of the Count operations that is performed.
278 If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
279 EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
280 incremented for each of the Count operations that is performed. The read or
281 write operation is performed Count times on the same Address.
283 If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
284 EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
285 incremented for each of the Count operations that is performed. The read or
286 write operation is performed Count times from the first element of Buffer.
288 @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
289 @param[in] Width Signifies the width of the I/O or Memory operation.
290 @param[in] Address The base address of the I/O operation.
291 @param[in] Count The number of I/O operations to perform. The number of
292 bytes moved is Width size * Count, starting at Address.
293 @param[in] Buffer For read operations, the destination buffer to store the results.
294 For write operations, the source buffer from which to write data.
296 @retval EFI_SUCCESS The data was read from or written to the PI system.
297 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
298 @retval EFI_INVALID_PARAMETER Buffer is NULL.
299 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
300 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
301 and Count is not valid for this PI system.
306 CpuMemoryServiceWrite (
307 IN EFI_CPU_IO2_PROTOCOL
*This
,
308 IN EFI_CPU_IO_PROTOCOL_WIDTH Width
,
317 EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth
;
320 Status
= CpuIoCheckParameter (TRUE
, Width
, Address
, Count
, Buffer
);
321 if (EFI_ERROR (Status
)) {
326 // Select loop based on the width of the transfer
328 InStride
= mInStride
[Width
];
329 OutStride
= mOutStride
[Width
];
330 OperationWidth
= (EFI_CPU_IO_PROTOCOL_WIDTH
)(Width
& 0x03);
331 for (Uint8Buffer
= Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
332 if (OperationWidth
== EfiCpuIoWidthUint8
) {
333 MmioWrite8 ((UINTN
)Address
, *Uint8Buffer
);
334 } else if (OperationWidth
== EfiCpuIoWidthUint16
) {
335 MmioWrite16 ((UINTN
)Address
, *((UINT16
*)Uint8Buffer
));
336 } else if (OperationWidth
== EfiCpuIoWidthUint32
) {
337 MmioWrite32 ((UINTN
)Address
, *((UINT32
*)Uint8Buffer
));
338 } else if (OperationWidth
== EfiCpuIoWidthUint64
) {
339 MmioWrite64 ((UINTN
)Address
, *((UINT64
*)Uint8Buffer
));
349 The I/O operations are carried out exactly as requested. The caller is responsible
350 for satisfying any alignment and I/O width restrictions that a PI System on a
351 platform might require. For example on some platforms, width requests of
352 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
353 be handled by the driver.
355 If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
356 or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
357 each of the Count operations that is performed.
359 If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
360 EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
361 incremented for each of the Count operations that is performed. The read or
362 write operation is performed Count times on the same Address.
364 If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
365 EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
366 incremented for each of the Count operations that is performed. The read or
367 write operation is performed Count times from the first element of Buffer.
369 @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
370 @param[in] Width Signifies the width of the I/O or Memory operation.
371 @param[in] Address The base address of the I/O operation.
372 @param[in] Count The number of I/O operations to perform. The number of
373 bytes moved is Width size * Count, starting at Address.
374 @param[out] Buffer For read operations, the destination buffer to store the results.
375 For write operations, the source buffer from which to write data.
377 @retval EFI_SUCCESS The data was read from or written to the PI system.
378 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
379 @retval EFI_INVALID_PARAMETER Buffer is NULL.
380 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
381 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
382 and Count is not valid for this PI system.
388 IN EFI_CPU_IO2_PROTOCOL
*This
,
389 IN EFI_CPU_IO_PROTOCOL_WIDTH Width
,
398 EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth
;
401 Status
= CpuIoCheckParameter (FALSE
, Width
, Address
, Count
, Buffer
);
402 if (EFI_ERROR (Status
)) {
407 // Select loop based on the width of the transfer
409 InStride
= mInStride
[Width
];
410 OutStride
= mOutStride
[Width
];
411 OperationWidth
= (EFI_CPU_IO_PROTOCOL_WIDTH
)(Width
& 0x03);
414 // Fifo operations supported for (mInStride[Width] == 0)
417 switch (OperationWidth
) {
418 case EfiCpuIoWidthUint8
:
419 IoReadFifo8 ((UINTN
)Address
, Count
, Buffer
);
421 case EfiCpuIoWidthUint16
:
422 IoReadFifo16 ((UINTN
)Address
, Count
, Buffer
);
424 case EfiCpuIoWidthUint32
:
425 IoReadFifo32 ((UINTN
)Address
, Count
, Buffer
);
429 // The CpuIoCheckParameter call above will ensure that this
430 // path is not taken.
437 for (Uint8Buffer
= Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
438 if (OperationWidth
== EfiCpuIoWidthUint8
) {
439 *Uint8Buffer
= IoRead8 ((UINTN
)Address
);
440 } else if (OperationWidth
== EfiCpuIoWidthUint16
) {
441 *((UINT16
*)Uint8Buffer
) = IoRead16 ((UINTN
)Address
);
442 } else if (OperationWidth
== EfiCpuIoWidthUint32
) {
443 *((UINT32
*)Uint8Buffer
) = IoRead32 ((UINTN
)Address
);
453 The I/O operations are carried out exactly as requested. The caller is responsible
454 for satisfying any alignment and I/O width restrictions that a PI System on a
455 platform might require. For example on some platforms, width requests of
456 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
457 be handled by the driver.
459 If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
460 or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
461 each of the Count operations that is performed.
463 If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
464 EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
465 incremented for each of the Count operations that is performed. The read or
466 write operation is performed Count times on the same Address.
468 If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
469 EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
470 incremented for each of the Count operations that is performed. The read or
471 write operation is performed Count times from the first element of Buffer.
473 @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
474 @param[in] Width Signifies the width of the I/O or Memory operation.
475 @param[in] Address The base address of the I/O operation.
476 @param[in] Count The number of I/O operations to perform. The number of
477 bytes moved is Width size * Count, starting at Address.
478 @param[in] Buffer For read operations, the destination buffer to store the results.
479 For write operations, the source buffer from which to write data.
481 @retval EFI_SUCCESS The data was read from or written to the PI system.
482 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
483 @retval EFI_INVALID_PARAMETER Buffer is NULL.
484 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
485 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
486 and Count is not valid for this PI system.
492 IN EFI_CPU_IO2_PROTOCOL
*This
,
493 IN EFI_CPU_IO_PROTOCOL_WIDTH Width
,
502 EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth
;
506 // Make sure the parameters are valid
508 Status
= CpuIoCheckParameter (FALSE
, Width
, Address
, Count
, Buffer
);
509 if (EFI_ERROR (Status
)) {
514 // Select loop based on the width of the transfer
516 InStride
= mInStride
[Width
];
517 OutStride
= mOutStride
[Width
];
518 OperationWidth
= (EFI_CPU_IO_PROTOCOL_WIDTH
)(Width
& 0x03);
521 // Fifo operations supported for (mInStride[Width] == 0)
524 switch (OperationWidth
) {
525 case EfiCpuIoWidthUint8
:
526 IoWriteFifo8 ((UINTN
)Address
, Count
, Buffer
);
528 case EfiCpuIoWidthUint16
:
529 IoWriteFifo16 ((UINTN
)Address
, Count
, Buffer
);
531 case EfiCpuIoWidthUint32
:
532 IoWriteFifo32 ((UINTN
)Address
, Count
, Buffer
);
536 // The CpuIoCheckParameter call above will ensure that this
537 // path is not taken.
544 for (Uint8Buffer
= (UINT8
*)Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
545 if (OperationWidth
== EfiCpuIoWidthUint8
) {
546 IoWrite8 ((UINTN
)Address
, *Uint8Buffer
);
547 } else if (OperationWidth
== EfiCpuIoWidthUint16
) {
548 IoWrite16 ((UINTN
)Address
, *((UINT16
*)Uint8Buffer
));
549 } else if (OperationWidth
== EfiCpuIoWidthUint32
) {
550 IoWrite32 ((UINTN
)Address
, *((UINT32
*)Uint8Buffer
));
558 The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
560 @param[in] ImageHandle The firmware allocated handle for the EFI image.
561 @param[in] SystemTable A pointer to the EFI System Table.
563 @retval EFI_SUCCESS The entry point is executed successfully.
564 @retval other Some error occurs when executing this entry point.
570 IN EFI_HANDLE ImageHandle
,
571 IN EFI_SYSTEM_TABLE
*SystemTable
576 ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL
, &gEfiCpuIo2ProtocolGuid
);
577 Status
= gBS
->InstallMultipleProtocolInterfaces (
579 &gEfiCpuIo2ProtocolGuid
,
583 ASSERT_EFI_ERROR (Status
);