1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; This is the assembly code for MP support
19 ;-------------------------------------------------------------------------------
22 extern ASM_PFX(InitializeFloatingPointUnits)
28 ;-------------------------------------------------------------------------------------
29 ;RendezvousFunnelProc procedure follows. All APs execute their procedure. This
30 ;procedure serializes all the AP processors through an Init sequence. It must be
31 ;noted that APs arrive here very raw...ie: real mode, no stack.
32 ;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC
34 ;-------------------------------------------------------------------------------------
35 global ASM_PFX(RendezvousFunnelProc)
36 ASM_PFX(RendezvousFunnelProc):
37 RendezvousFunnelProcStart:
38 ; At this point CS = 0x(vv00) and ip= 0x0.
39 ; Save BIST information to ebp firstly
42 mov ebp, eax ; Save BIST information
52 mov si, BufferStartLocation
55 mov di, ModeOffsetLocation
57 mov di, CodeSegmentLocation
61 mov [di],dx ; Patch long mode CS
64 mov [di],eax ; Patch address
73 mov di, DataSegmentLocation
74 mov edi, [di] ; Save long mode DS in edi
76 mov si, Cr3Location ; Save CR3 in ecx
80 mov ds, ax ; Clear data segment
82 mov eax, cr0 ; Get control register 0
83 or eax, 000000003h ; Set PE bit (bit #0) & MP
90 mov cr3, ecx ; Load CR3
92 mov ecx, 0c0000080h ; EFER MSR number
94 bts eax, 8 ; Set LME=1
97 mov eax, cr0 ; Read CR0
98 bts eax, 31 ; Set PG=1
99 mov cr0, eax ; Write CR0
101 jmp 0:strict dword 0 ; far jump to long mode
111 add edi, LockLocation
112 mov rax, NotVacantFlag
115 xchg qword [edi], rax
116 cmp rax, NotVacantFlag
120 add edi, NumApsExecutingLoction
126 add edi, StackSizeLocation
129 add edi, StackStartAddressLocation
137 add edi, LockLocation
138 xchg qword [edi], rax
141 push rbp ; push BIST data at top of AP stack
142 xor rbp, rbp ; clear ebp for call stack trace
146 mov rax, ASM_PFX(InitializeFloatingPointUnits)
148 call rax ; Call assembly function to initialize FPU per UEFI spec
151 mov edx, ebx ; edx is NumApsExecuting
153 add ecx, LockLocation ; rcx is address of exchange info data buffer
156 add edi, ApProcedureLocation
160 call rax ; invoke C function
164 RendezvousFunnelProcEnd:
166 ;-------------------------------------------------------------------------------------
167 ; AsmGetAddressMap (&AddressMap);
168 ;-------------------------------------------------------------------------------------
169 global ASM_PFX(AsmGetAddressMap)
170 ASM_PFX(AsmGetAddressMap):
171 mov rax, ASM_PFX(RendezvousFunnelProc)
173 mov qword [rcx + 8h], LongModeStart - RendezvousFunnelProcStart
174 mov qword [rcx + 10h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart
177 ;-------------------------------------------------------------------------------------
178 ;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is
179 ;about to become an AP. It switches it'stack with the current AP.
180 ;AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo);
181 ;-------------------------------------------------------------------------------------
182 global ASM_PFX(AsmExchangeRole)
183 ASM_PFX(AsmExchangeRole):
184 ; DO NOT call other functions in this function, since 2 CPU may use 1 stack
185 ; at the same time. If 1 CPU try to call a function, stack will be corrupted.
209 ; rsi contains MyInfo pointer
212 ; rdi contains OthersInfo pointer
215 ;Store EFLAGS, GDTR and IDTR regiter to stack
220 ; Store the its StackPointer
223 ; update its switch state to STORED
224 mov byte [rsi], CPU_SWITCH_STATE_STORED
227 ; wait until the other CPU finish storing its state
228 cmp byte [rdi], CPU_SWITCH_STATE_STORED
231 jmp WaitForOtherStored
234 ; Since another CPU already stored its state, load them
241 ; load its future StackPointer
244 ; update the other CPU's switch state to LOADED
245 mov byte [rdi], CPU_SWITCH_STATE_LOADED
248 ; wait until the other CPU finish loading new state,
249 ; otherwise the data in stack may corrupt
250 cmp byte [rsi], CPU_SWITCH_STATE_LOADED
253 jmp WaitForOtherLoaded
256 ; since the other CPU already get the data it want, leave this procedure