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1 /** @file
2 Definitions for CPU S3 data.
3
4 Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7 **/
8
9 #ifndef _ACPI_CPU_DATA_H_
10 #define _ACPI_CPU_DATA_H_
11
12 //
13 // Register types in register table
14 //
15 typedef enum {
16 Msr,
17 ControlRegister,
18 MemoryMapped,
19 CacheControl,
20
21 //
22 // Semaphore type used to control the execute sequence of the Msr.
23 // It will be insert between two Msr which has execute dependence.
24 //
25 Semaphore,
26 InvalidReg
27 } REGISTER_TYPE;
28
29 //
30 // Describe the dependency type for different features.
31 // The value set to CPU_REGISTER_TABLE_ENTRY.Value when the REGISTER_TYPE is Semaphore.
32 //
33 typedef enum {
34 NoneDepType,
35 ThreadDepType,
36 CoreDepType,
37 PackageDepType,
38 InvalidDepType
39 } CPU_FEATURE_DEPENDENCE_TYPE;
40
41 //
42 // CPU information.
43 //
44 typedef struct {
45 //
46 // Record the package count in this CPU.
47 //
48 UINT32 PackageCount;
49 //
50 // Record the max core count in this CPU.
51 // Different packages may have different core count, this value
52 // save the max core count in all the packages.
53 //
54 UINT32 MaxCoreCount;
55 //
56 // Record the max thread count in this CPU.
57 // Different cores may have different thread count, this value
58 // save the max thread count in all the cores.
59 //
60 UINT32 MaxThreadCount;
61 //
62 // This field points to an array.
63 // This array saves valid core count (type UINT32) of each package.
64 // The array has PackageCount elements.
65 //
66 // If the platform does not support MSR setting at S3 resume, and
67 // therefore it doesn't need the dependency semaphores, it should set
68 // this field to 0.
69 //
70 EFI_PHYSICAL_ADDRESS ValidCoreCountPerPackage;
71 } CPU_STATUS_INFORMATION;
72
73 //
74 // Element of register table entry
75 //
76 typedef struct {
77 REGISTER_TYPE RegisterType; // offset 0 - 3
78 UINT32 Index; // offset 4 - 7
79 UINT8 ValidBitStart; // offset 8
80 UINT8 ValidBitLength; // offset 9
81 UINT16 Reserved; // offset 10 - 11
82 UINT32 HighIndex; // offset 12-15, only valid for MemoryMapped
83 UINT64 Value; // offset 16-23
84 } CPU_REGISTER_TABLE_ENTRY;
85
86 //
87 // Register table definition, including current table length,
88 // allocated size of this table, and pointer to the list of table entries.
89 //
90 typedef struct {
91 //
92 // The number of valid entries in the RegisterTableEntry buffer
93 //
94 UINT32 TableLength;
95 UINT32 NumberBeforeReset;
96 //
97 // The size, in bytes, of the RegisterTableEntry buffer
98 //
99 UINT32 AllocatedSize;
100 //
101 // The initial APIC ID of the CPU this register table applies to
102 //
103 UINT32 InitialApicId;
104 //
105 // Physical address of CPU_REGISTER_TABLE_ENTRY structures.
106 //
107 EFI_PHYSICAL_ADDRESS RegisterTableEntry;
108 } CPU_REGISTER_TABLE;
109
110 //
111 // Data structure that is required for ACPI S3 resume. The PCD
112 // PcdCpuS3DataAddress must be set to the physical address where this structure
113 // is allocated
114 //
115 typedef struct {
116 //
117 // Physical address of 4KB buffer allocated below 1MB from memory of type
118 // EfiReservedMemoryType. The buffer is not required to be initialized, but
119 // it is recommended that the buffer be zero-filled. This buffer is used to
120 // wake APs during an ACPI S3 resume.
121 //
122 EFI_PHYSICAL_ADDRESS StartupVector;
123 //
124 // Physical address of structure of type IA32_DESCRIPTOR. The
125 // IA32_DESCRIPTOR structure provides the base address and length of a GDT
126 // The GDT must be filled in with the GDT contents that are
127 // used during an ACPI S3 resume. This is typically the contents of the GDT
128 // used by the boot processor when the platform is booted.
129 //
130 EFI_PHYSICAL_ADDRESS GdtrProfile;
131 //
132 // Physical address of structure of type IA32_DESCRIPTOR. The
133 // IA32_DESCRIPTOR structure provides the base address and length of an IDT.
134 // The IDT must be filled in with the IDT contents that are
135 // used during an ACPI S3 resume. This is typically the contents of the IDT
136 // used by the boot processor when the platform is booted.
137 //
138 EFI_PHYSICAL_ADDRESS IdtrProfile;
139 //
140 // Physical address of a buffer that is used as stacks during ACPI S3 resume.
141 // The total size of this buffer, in bytes, is NumberOfCpus * StackSize. This
142 // structure must be allocated from memory of type EfiACPIMemoryNVS.
143 //
144 EFI_PHYSICAL_ADDRESS StackAddress;
145 //
146 // The size, in bytes, of the stack provided to each CPU during ACPI S3 resume.
147 //
148 UINT32 StackSize;
149 //
150 // The number of CPUs. If a platform does not support hot plug CPUs, then
151 // this is the number of CPUs detected when the platform is booted, regardless
152 // of being enabled or disabled. If a platform does support hot plug CPUs,
153 // then this is the maximum number of CPUs that the platform supports.
154 //
155 UINT32 NumberOfCpus;
156 //
157 // Physical address of structure of type MTRR_SETTINGS that contains a copy
158 // of the MTRR settings that are compatible with the MTRR settings used by
159 // the boot processor when the platform was booted. These MTRR settings are
160 // used during an ACPI S3 resume.
161 //
162 EFI_PHYSICAL_ADDRESS MtrrTable;
163 //
164 // Physical address of an array of CPU_REGISTER_TABLE structures, with
165 // NumberOfCpus entries. If a register table is not required, then the
166 // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to 0.
167 // If TableLength is > 0, then elements of RegisterTableEntry are used to
168 // initialize the CPU that matches InitialApicId, during an ACPI S3 resume,
169 // before SMBASE relocation is performed.
170 //
171 EFI_PHYSICAL_ADDRESS PreSmmInitRegisterTable;
172 //
173 // Physical address of an array of CPU_REGISTER_TABLE structures, with
174 // NumberOfCpus entries. If a register table is not required, then the
175 // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to 0.
176 // If TableLength is > 0, then elements of RegisterTableEntry are used to
177 // initialize the CPU that matches InitialApicId, during an ACPI S3 resume,
178 // after SMBASE relocation is performed.
179 //
180 EFI_PHYSICAL_ADDRESS RegisterTable;
181 //
182 // Physical address of a buffer that contains the machine check handler that
183 // is used during an ACPI S3 Resume. In order for this machine check
184 // handler to be active on an AP during an ACPI S3 resume, the machine check
185 // vector in the IDT provided by IdtrProfile must be initialized to transfer
186 // control to this physical address.
187 //
188 EFI_PHYSICAL_ADDRESS ApMachineCheckHandlerBase;
189 //
190 // The size, in bytes, of the machine check handler that is used during an
191 // ACPI S3 Resume. If this field is 0, then a machine check handler is not
192 // provided.
193 //
194 UINT32 ApMachineCheckHandlerSize;
195 //
196 // CPU information which is required when set the register table.
197 //
198 CPU_STATUS_INFORMATION CpuStatus;
199 //
200 // Location info for each AP.
201 // It points to an array which saves all APs location info.
202 // The array count is the AP count in this CPU.
203 //
204 // If the platform does not support MSR setting at S3 resume, and
205 // therefore it doesn't need the dependency semaphores, it should set
206 // this field to 0.
207 //
208 EFI_PHYSICAL_ADDRESS ApLocation;
209 } ACPI_CPU_DATA;
210
211 #endif