UefiCpuPkg: Add CPUID definitions for AMD.
[mirror_edk2.git] / UefiCpuPkg / Include / Register / Amd / Cpuid.h
1 /** @file
2 CPUID leaf definitions.
3
4 Provides defines for CPUID leaf indexes. Data structures are provided for
5 registers returned by a CPUID leaf that contain one or more bit fields.
6 If a register returned is a single 32-bit value, then a data structure is
7 not provided for that register.
8
9 Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
10
11 This program and the accompanying materials are licensed and made available
12 under the terms and conditions of the BSD License which accompanies this
13 distribution. The full text of the license may be found at
14 http://opensource.org/licenses/bsd-license.php
15
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18
19 @par Specification Reference:
20 AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34
21
22 **/
23
24 #ifndef __AMD_CPUID_H__
25 #define __AMD_CPUID_H__
26
27 /**
28 CPUID Signature Information
29
30 @param EAX CPUID_SIGNATURE (0x00)
31
32 @retval EAX Returns the highest value the CPUID instruction recognizes for
33 returning basic processor information. The value is returned is
34 processor specific.
35 @retval EBX First 4 characters of a vendor identification string.
36 @retval ECX Last 4 characters of a vendor identification string.
37 @retval EDX Middle 4 characters of a vendor identification string.
38
39 **/
40
41 ///
42 /// @{ CPUID signature values returned by AMD processors
43 ///
44 #define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX SIGNATURE_32 ('A', 'u', 't', 'h')
45 #define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX SIGNATURE_32 ('e', 'n', 't', 'i')
46 #define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX SIGNATURE_32 ('c', 'A', 'M', 'D')
47 ///
48 /// @}
49 ///
50
51
52 /**
53 CPUID Extended Processor Signature and Features
54
55 @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)
56
57 @retval EAX Extended Family, Model, Stepping Identifiers
58 described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX.
59 @retval EBX Brand Identifier
60 described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX.
61 @retval ECX Extended Feature Identifiers
62 described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX.
63 @retval EDX Extended Feature Identifiers
64 described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX.
65 **/
66
67 /**
68 CPUID Extended Processor Signature and Features EAX for CPUID leaf
69 #CPUID_EXTENDED_CPU_SIG.
70 **/
71 typedef union {
72 ///
73 /// Individual bit fields
74 ///
75 struct {
76 ///
77 /// [Bits 3:0] Stepping.
78 ///
79 UINT32 Stepping:4;
80 ///
81 /// [Bits 7:4] Base Model.
82 ///
83 UINT32 BaseModel:4;
84 ///
85 /// [Bits 11:8] Base Family.
86 ///
87 UINT32 BaseFamily:4;
88 ///
89 /// [Bit 15:12] Reserved.
90 ///
91 UINT32 Reserved1:4;
92 ///
93 /// [Bits 19:16] Extended Model.
94 ///
95 UINT32 ExtModel:4;
96 ///
97 /// [Bits 27:20] Extended Family.
98 ///
99 UINT32 ExtFamily:8;
100 ///
101 /// [Bit 31:28] Reserved.
102 ///
103 UINT32 Reserved2:4;
104 } Bits;
105 ///
106 /// All bit fields as a 32-bit value
107 ///
108 UINT32 Uint32;
109 } CPUID_AMD_EXTENDED_CPU_SIG_EAX;
110
111 /**
112 CPUID Extended Processor Signature and Features EBX for CPUID leaf
113 #CPUID_EXTENDED_CPU_SIG.
114 **/
115 typedef union {
116 ///
117 /// Individual bit fields
118 ///
119 struct {
120 ///
121 /// [Bits 27:0] Reserved.
122 ///
123 UINT32 Reserved:28;
124 ///
125 /// [Bit 31:28] Package Type.
126 ///
127 UINT32 PkgType:4;
128 } Bits;
129 ///
130 /// All bit fields as a 32-bit value
131 ///
132 UINT32 Uint32;
133 } CPUID_AMD_EXTENDED_CPU_SIG_EBX;
134
135 /**
136 CPUID Extended Processor Signature and Features ECX for CPUID leaf
137 #CPUID_EXTENDED_CPU_SIG.
138 **/
139 typedef union {
140 ///
141 /// Individual bit fields
142 ///
143 struct {
144 ///
145 /// [Bit 0] LAHF/SAHF available in 64-bit mode.
146 ///
147 UINT32 LAHF_SAHF:1;
148 ///
149 /// [Bit 1] Core multi-processing legacy mode.
150 ///
151 UINT32 CmpLegacy:1;
152 ///
153 /// [Bit 2] Secure Virtual Mode feature.
154 ///
155 UINT32 SVM:1;
156 ///
157 /// [Bit 3] Extended APIC register space.
158 ///
159 UINT32 ExtApicSpace:1;
160 ///
161 /// [Bit 4] LOCK MOV CR0 means MOV CR8.
162 ///
163 UINT32 AltMovCr8:1;
164 ///
165 /// [Bit 5] LZCNT instruction support.
166 ///
167 UINT32 LZCNT:1;
168 ///
169 /// [Bit 6] SSE4A instruction support.
170 ///
171 UINT32 SSE4A:1;
172 ///
173 /// [Bit 7] Misaligned SSE Mode.
174 ///
175 UINT32 MisAlignSse:1;
176 ///
177 /// [Bit 8] ThreeDNow Prefetch instructions.
178 ///
179 UINT32 PREFETCHW:1;
180 ///
181 /// [Bit 9] OS Visible Work-around support.
182 ///
183 UINT32 OSVW:1;
184 ///
185 /// [Bit 10] Instruction Based Sampling.
186 ///
187 UINT32 IBS:1;
188 ///
189 /// [Bit 11] Extended Operation Support.
190 ///
191 UINT32 XOP:1;
192 ///
193 /// [Bit 12] SKINIT and STGI support.
194 ///
195 UINT32 SKINIT:1;
196 ///
197 /// [Bit 13] Watchdog Timer support.
198 ///
199 UINT32 WDT:1;
200 ///
201 /// [Bit 14] Reserved.
202 ///
203 UINT32 Reserved1:1;
204 ///
205 /// [Bit 15] Lightweight Profiling support.
206 ///
207 UINT32 LWP:1;
208 ///
209 /// [Bit 16] 4-Operand FMA instruction support.
210 ///
211 UINT32 FMA4:1;
212 ///
213 /// [Bit 17] Translation Cache Extension.
214 ///
215 UINT32 TCE:1;
216 ///
217 /// [Bit 21:18] Reserved.
218 ///
219 UINT32 Reserved2:4;
220 ///
221 /// [Bit 22] Topology Extensions support.
222 ///
223 UINT32 TopologyExtensions:1;
224 ///
225 /// [Bit 23] Core Performance Counter Extensions.
226 ///
227 UINT32 PerfCtrExtCore:1;
228 ///
229 /// [Bit 25:24] Reserved.
230 ///
231 UINT32 Reserved3:2;
232 ///
233 /// [Bit 26] Data Breakpoint Extension.
234 ///
235 UINT32 DataBreakpointExtension:1;
236 ///
237 /// [Bit 27] Performance Time-Stamp Counter.
238 ///
239 UINT32 PerfTsc:1;
240 ///
241 /// [Bit 28] L3 Performance Counter Extensions.
242 ///
243 UINT32 PerfCtrExtL3:1;
244 ///
245 /// [Bit 29] MWAITX and MONITORX capability.
246 ///
247 UINT32 MwaitExtended:1;
248 ///
249 /// [Bit 31:30] Reserved.
250 ///
251 UINT32 Reserved4:2;
252 } Bits;
253 ///
254 /// All bit fields as a 32-bit value
255 ///
256 UINT32 Uint32;
257 } CPUID_AMD_EXTENDED_CPU_SIG_ECX;
258
259 /**
260 CPUID Extended Processor Signature and Features EDX for CPUID leaf
261 #CPUID_EXTENDED_CPU_SIG.
262 **/
263 typedef union {
264 ///
265 /// Individual bit fields
266 ///
267 struct {
268 ///
269 /// [Bit 0] x87 floating point unit on-chip.
270 ///
271 UINT32 FPU:1;
272 ///
273 /// [Bit 1] Virtual-mode enhancements.
274 ///
275 UINT32 VME:1;
276 ///
277 /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE.
278 ///
279 UINT32 DE:1;
280 ///
281 /// [Bit 3] Page-size extensions (4 MB pages).
282 ///
283 UINT32 PSE:1;
284 ///
285 /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.
286 ///
287 UINT32 TSC:1;
288 ///
289 /// [Bit 5] MSRs, with RDMSR and WRMSR instructions.
290 ///
291 UINT32 MSR:1;
292 ///
293 /// [Bit 6] Physical-address extensions (PAE).
294 ///
295 UINT32 PAE:1;
296 ///
297 /// [Bit 7] Machine check exception, CR4.MCE.
298 ///
299 UINT32 MCE:1;
300 ///
301 /// [Bit 8] CMPXCHG8B instruction.
302 ///
303 UINT32 CMPXCHG8B:1;
304 ///
305 /// [Bit 9] APIC exists and is enabled.
306 ///
307 UINT32 APIC:1;
308 ///
309 /// [Bit 10] Reserved.
310 ///
311 UINT32 Reserved1:1;
312 ///
313 /// [Bit 11] SYSCALL and SYSRET instructions.
314 ///
315 UINT32 SYSCALL_SYSRET:1;
316 ///
317 /// [Bit 12] Memory-type range registers.
318 ///
319 UINT32 MTRR:1;
320 ///
321 /// [Bit 13] Page global extension, CR4.PGE.
322 ///
323 UINT32 PGE:1;
324 ///
325 /// [Bit 14] Machine check architecture, MCG_CAP.
326 ///
327 UINT32 MCA:1;
328 ///
329 /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.
330 ///
331 UINT32 CMOV:1;
332 ///
333 /// [Bit 16] Page attribute table.
334 ///
335 UINT32 PAT:1;
336 ///
337 /// [Bit 17] Page-size extensions.
338 ///
339 UINT32 PSE36 : 1;
340 ///
341 /// [Bit 19:18] Reserved.
342 ///
343 UINT32 Reserved2:2;
344 ///
345 /// [Bit 20] No-execute page protection.
346 ///
347 UINT32 NX:1;
348 ///
349 /// [Bit 21] Reserved.
350 ///
351 UINT32 Reserved3:1;
352 ///
353 /// [Bit 22] AMD Extensions to MMX instructions.
354 ///
355 UINT32 MmxExt:1;
356 ///
357 /// [Bit 23] MMX instructions.
358 ///
359 UINT32 MMX:1;
360 ///
361 /// [Bit 24] FXSAVE and FXRSTOR instructions.
362 ///
363 UINT32 FFSR:1;
364 ///
365 /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations.
366 ///
367 UINT32 FFXSR:1;
368 ///
369 /// [Bit 26] 1-GByte large page support.
370 ///
371 UINT32 Page1GB:1;
372 ///
373 /// [Bit 27] RDTSCP intructions.
374 ///
375 UINT32 RDTSCP:1;
376 ///
377 /// [Bit 28] Reserved.
378 ///
379 UINT32 Reserved4:1;
380 ///
381 /// [Bit 29] Long Mode.
382 ///
383 UINT32 LM:1;
384 ///
385 /// [Bit 30] 3DNow! instructions.
386 ///
387 UINT32 ThreeDNow:1;
388 ///
389 /// [Bit 31] AMD Extensions to 3DNow! instructions.
390 ///
391 UINT32 ThreeDNowExt:1;
392 } Bits;
393 ///
394 /// All bit fields as a 32-bit value
395 ///
396 UINT32 Uint32;
397 } CPUID_AMD_EXTENDED_CPU_SIG_EDX;
398
399
400 /**
401 CPUID Linear Physical Address Size
402
403 @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
404
405 @retval EAX Linear/Physical Address Size described by the type
406 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX.
407 @retval EBX Linear/Physical Address Size described by the type
408 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX.
409 @retval ECX Linear/Physical Address Size described by the type
410 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX.
411 @retval EDX Reserved.
412 **/
413
414 /**
415 CPUID Linear Physical Address Size EAX for CPUID leaf
416 #CPUID_VIR_PHY_ADDRESS_SIZE.
417 **/
418 typedef union {
419 ///
420 /// Individual bit fields
421 ///
422 struct {
423 ///
424 /// [Bits 7:0] Maximum physical byte address size in bits.
425 ///
426 UINT32 PhysicalAddressBits:8;
427 ///
428 /// [Bits 15:8] Maximum linear byte address size in bits.
429 ///
430 UINT32 LinearAddressBits:8;
431 ///
432 /// [Bits 23:16] Maximum guest physical byte address size in bits.
433 ///
434 UINT32 GuestPhysAddrSize:8;
435 ///
436 /// [Bit 31:24] Reserved.
437 ///
438 UINT32 Reserved:8;
439 } Bits;
440 ///
441 /// All bit fields as a 32-bit value
442 ///
443 UINT32 Uint32;
444 } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX;
445
446 /**
447 CPUID Linear Physical Address Size EBX for CPUID leaf
448 #CPUID_VIR_PHY_ADDRESS_SIZE.
449 **/
450 typedef union {
451 ///
452 /// Individual bit fields
453 ///
454 struct {
455 ///
456 /// [Bits 0] Clear Zero Instruction.
457 ///
458 UINT32 CLZERO:1;
459 ///
460 /// [Bits 1] Instructions retired count support.
461 ///
462 UINT32 IRPerf:1;
463 ///
464 /// [Bits 2] Restore error pointers for XSave instructions.
465 ///
466 UINT32 XSaveErPtr:1;
467 ///
468 /// [Bit 31:3] Reserved.
469 ///
470 UINT32 Reserved:29;
471 } Bits;
472 ///
473 /// All bit fields as a 32-bit value
474 ///
475 UINT32 Uint32;
476 } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX;
477
478 /**
479 CPUID Linear Physical Address Size ECX for CPUID leaf
480 #CPUID_VIR_PHY_ADDRESS_SIZE.
481 **/
482 typedef union {
483 ///
484 /// Individual bit fields
485 ///
486 struct {
487 ///
488 /// [Bits 7:0] Number of threads - 1.
489 ///
490 UINT32 NC:8;
491 ///
492 /// [Bit 11:8] Reserved.
493 ///
494 UINT32 Reserved1:4;
495 ///
496 /// [Bits 15:12] APIC ID size.
497 ///
498 UINT32 ApicIdCoreIdSize:4;
499 ///
500 /// [Bits 17:16] Performance time-stamp counter size.
501 ///
502 UINT32 PerfTscSize:2;
503 ///
504 /// [Bit 31:18] Reserved.
505 ///
506 UINT32 Reserved2:14;
507 } Bits;
508 ///
509 /// All bit fields as a 32-bit value
510 ///
511 UINT32 Uint32;
512 } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX;
513
514
515 /**
516 CPUID AMD Processor Topology
517
518 @param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E)
519
520 @retval EAX Extended APIC ID described by the type
521 CPUID_AMD_PROCESSOR_TOPOLOGY_EAX.
522 @retval EBX Core Indentifiers described by the type
523 CPUID_AMD_PROCESSOR_TOPOLOGY_EBX.
524 @retval ECX Node Indentifiers described by the type
525 CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.
526 @retval EDX Reserved.
527 **/
528 #define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E
529
530 /**
531 CPUID AMD Processor Topology EAX for CPUID leaf
532 #CPUID_AMD_PROCESSOR_TOPOLOGY.
533 **/
534 typedef union {
535 ///
536 /// Individual bit fields
537 ///
538 struct {
539 ///
540 /// [Bit 31:0] Extended APIC Id.
541 ///
542 UINT32 ExtendedApicId;
543 } Bits;
544 ///
545 /// All bit fields as a 32-bit value
546 ///
547 UINT32 Uint32;
548 } CPUID_AMD_PROCESSOR_TOPOLOGY_EAX;
549
550 /**
551 CPUID AMD Processor Topology EBX for CPUID leaf
552 #CPUID_AMD_PROCESSOR_TOPOLOGY.
553 **/
554 typedef union {
555 ///
556 /// Individual bit fields
557 ///
558 struct {
559 ///
560 /// [Bits 7:0] Core Id.
561 ///
562 UINT32 CoreId:8;
563 ///
564 /// [Bits 15:8] Threads per core.
565 ///
566 UINT32 ThreadsPerCore:8;
567 ///
568 /// [Bit 31:16] Reserved.
569 ///
570 UINT32 Reserved:16;
571 } Bits;
572 ///
573 /// All bit fields as a 32-bit value
574 ///
575 UINT32 Uint32;
576 } CPUID_AMD_PROCESSOR_TOPOLOGY_EBX;
577
578 /**
579 CPUID AMD Processor Topology ECX for CPUID leaf
580 #CPUID_AMD_PROCESSOR_TOPOLOGY.
581 **/
582 typedef union {
583 ///
584 /// Individual bit fields
585 ///
586 struct {
587 ///
588 /// [Bits 7:0] Node Id.
589 ///
590 UINT32 NodeId:8;
591 ///
592 /// [Bits 10:8] Nodes per processor.
593 ///
594 UINT32 NodesPerProcessor:3;
595 ///
596 /// [Bit 31:11] Reserved.
597 ///
598 UINT32 Reserved:21;
599 } Bits;
600 ///
601 /// All bit fields as a 32-bit value
602 ///
603 UINT32 Uint32;
604 } CPUID_AMD_PROCESSOR_TOPOLOGY_ECX;
605
606
607 /**
608 CPUID Memory Encryption Information
609
610 @param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F)
611
612 @retval EAX Returns the memory encryption feature support status.
613 @retval EBX If memory encryption feature is present then return
614 the page table bit number used to enable memory encryption support
615 and reducing of physical address space in bits.
616 @retval ECX Returns number of encrypted guest supported simultaneously.
617 @retval EDX Returns minimum SEV enabled and SEV disabled ASID.
618
619 <b>Example usage</b>
620 @code
621 UINT32 Eax;
622 UINT32 Ebx;
623 UINT32 Ecx;
624 UINT32 Edx;
625
626 AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx);
627 @endcode
628 **/
629
630 #define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F
631
632 /**
633 CPUID Memory Encryption support information EAX for CPUID leaf
634 #CPUID_MEMORY_ENCRYPTION_INFO.
635 **/
636 typedef union {
637 ///
638 /// Individual bit fields
639 ///
640 struct {
641 ///
642 /// [Bit 0] Secure Memory Encryption (Sme) Support
643 ///
644 UINT32 SmeBit:1;
645
646 ///
647 /// [Bit 1] Secure Encrypted Virtualization (Sev) Support
648 ///
649 UINT32 SevBit:1;
650
651 ///
652 /// [Bit 2] Page flush MSR support
653 ///
654 UINT32 PageFlushMsrBit:1;
655
656 ///
657 /// [Bit 3] Encrypted state support
658 ///
659 UINT32 SevEsBit:1;
660
661 ///
662 /// [Bit 31:4] Reserved
663 ///
664 UINT32 ReservedBits:28;
665 } Bits;
666 ///
667 /// All bit fields as a 32-bit value
668 ///
669 UINT32 Uint32;
670 } CPUID_MEMORY_ENCRYPTION_INFO_EAX;
671
672 /**
673 CPUID Memory Encryption support information EBX for CPUID leaf
674 #CPUID_MEMORY_ENCRYPTION_INFO.
675 **/
676 typedef union {
677 ///
678 /// Individual bit fields
679 ///
680 struct {
681 ///
682 /// [Bit 5:0] Page table bit number used to enable memory encryption
683 ///
684 UINT32 PtePosBits:6;
685
686 ///
687 /// [Bit 11:6] Reduction of system physical address space bits when
688 /// memory encryption is enabled
689 ///
690 UINT32 ReducedPhysBits:5;
691
692 ///
693 /// [Bit 31:12] Reserved
694 ///
695 UINT32 ReservedBits:21;
696 } Bits;
697 ///
698 /// All bit fields as a 32-bit value
699 ///
700 UINT32 Uint32;
701 } CPUID_MEMORY_ENCRYPTION_INFO_EBX;
702
703 /**
704 CPUID Memory Encryption support information ECX for CPUID leaf
705 #CPUID_MEMORY_ENCRYPTION_INFO.
706 **/
707 typedef union {
708 ///
709 /// Individual bit fields
710 ///
711 struct {
712 ///
713 /// [Bit 31:0] Number of encrypted guest supported simultaneously
714 ///
715 UINT32 NumGuests;
716 } Bits;
717 ///
718 /// All bit fields as a 32-bit value
719 ///
720 UINT32 Uint32;
721 } CPUID_MEMORY_ENCRYPTION_INFO_ECX;
722
723 /**
724 CPUID Memory Encryption support information EDX for CPUID leaf
725 #CPUID_MEMORY_ENCRYPTION_INFO.
726 **/
727 typedef union {
728 ///
729 /// Individual bit fields
730 ///
731 struct {
732 ///
733 /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID
734 ///
735 UINT32 MinAsid;
736 } Bits;
737 ///
738 /// All bit fields as a 32-bit value
739 ///
740 UINT32 Uint32;
741 } CPUID_MEMORY_ENCRYPTION_INFO_EDX;
742
743 #endif