2 Architectural MSR Definitions.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1.
22 @par Specification Reference:
23 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
24 December 2015, Appendix A VMX Capability Reporting Facility, Section A.1.
26 @par Specification Reference:
27 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
28 December 2015, Appendix A VMX Capability Reporting Facility, Section A.6.
32 #ifndef __ARCHITECTURAL_MSR_H__
33 #define __ARCHITECTURAL_MSR_H__
36 See Section 35.20, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
38 @param ECX MSR_IA32_P5_MC_ADDR (0x00000000)
39 @param EAX Lower 32-bits of MSR value.
40 @param EDX Upper 32-bits of MSR value.
46 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);
47 AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);
49 @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.
51 #define MSR_IA32_P5_MC_ADDR 0x00000000
55 See Section 35.20, "MSRs in Pentium Processors.". DF_DM = 05_01H.
57 @param ECX MSR_IA32_P5_MC_TYPE (0x00000001)
58 @param EAX Lower 32-bits of MSR value.
59 @param EDX Upper 32-bits of MSR value.
65 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);
66 AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);
68 @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.
70 #define MSR_IA32_P5_MC_TYPE 0x00000001
74 See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced
75 at Display Family / Display Model 0F_03H.
77 @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)
78 @param EAX Lower 32-bits of MSR value.
79 @param EDX Upper 32-bits of MSR value.
85 Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);
86 AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);
88 @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.
90 #define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
94 See Section 17.14, "Time-Stamp Counter.". Introduced at Display Family /
97 @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)
98 @param EAX Lower 32-bits of MSR value.
99 @param EDX Upper 32-bits of MSR value.
105 Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);
106 AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);
108 @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.
110 #define MSR_IA32_TIME_STAMP_COUNTER 0x00000010
114 Platform ID (RO) The operating system can use this MSR to determine "slot"
115 information for the processor and the proper microcode update to load.
116 Introduced at Display Family / Display Model 06_01H.
118 @param ECX MSR_IA32_PLATFORM_ID (0x00000017)
119 @param EAX Lower 32-bits of MSR value.
120 Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
121 @param EDX Upper 32-bits of MSR value.
122 Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
126 MSR_IA32_PLATFORM_ID_REGISTER Msr;
128 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
130 @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
132 #define MSR_IA32_PLATFORM_ID 0x00000017
135 MSR information returned for MSR index #MSR_IA32_PLATFORM_ID
139 /// Individual bit fields
145 /// [Bits 52:50] Platform Id (RO) Contains information concerning the
146 /// intended platform for the processor.
149 /// 0 0 0 Processor Flag 0.
150 /// 0 0 1 Processor Flag 1
151 /// 0 1 0 Processor Flag 2
152 /// 0 1 1 Processor Flag 3
153 /// 1 0 0 Processor Flag 4
154 /// 1 0 1 Processor Flag 5
155 /// 1 1 0 Processor Flag 6
156 /// 1 1 1 Processor Flag 7
162 /// All bit fields as a 64-bit value
165 } MSR_IA32_PLATFORM_ID_REGISTER
;
171 @param ECX MSR_IA32_APIC_BASE (0x0000001B)
172 @param EAX Lower 32-bits of MSR value.
173 Described by the type MSR_IA32_APIC_BASE_REGISTER.
174 @param EDX Upper 32-bits of MSR value.
175 Described by the type MSR_IA32_APIC_BASE_REGISTER.
179 MSR_IA32_APIC_BASE_REGISTER Msr;
181 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
182 AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);
184 @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.
186 #define MSR_IA32_APIC_BASE 0x0000001B
189 MSR information returned for MSR index #MSR_IA32_APIC_BASE
193 /// Individual bit fields
198 /// [Bit 8] BSP flag (R/W).
203 /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display
208 /// [Bit 11] APIC Global Enable (R/W).
212 /// [Bits 31:12] APIC Base (R/W).
216 /// [Bits 63:32] APIC Base (R/W).
218 UINT32 ApicBaseHi
:32;
221 /// All bit fields as a 64-bit value
224 } MSR_IA32_APIC_BASE_REGISTER
;
228 Control Features in Intel 64 Processor (R/W). If any one enumeration
229 condition for defined bit field holds.
231 @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A)
232 @param EAX Lower 32-bits of MSR value.
233 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
234 @param EDX Upper 32-bits of MSR value.
235 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
239 MSR_IA32_FEATURE_CONTROL_REGISTER Msr;
241 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
242 AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);
244 @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
246 #define MSR_IA32_FEATURE_CONTROL 0x0000003A
249 MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL
253 /// Individual bit fields
257 /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from
258 /// being written, writes to this bit will result in GP(0). Note: Once the
259 /// Lock bit is set, the contents of this register cannot be modified.
260 /// Therefore the lock bit must be set after configuring support for Intel
261 /// Virtualization Technology and prior to transferring control to an
262 /// option ROM or the OS. Hence, once the Lock bit is set, the entire
263 /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD
264 /// is not deasserted. If any one enumeration condition for defined bit
265 /// field position greater than bit 0 holds.
269 /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a
270 /// system executive to use VMX in conjunction with SMX to support
271 /// Intel(R) Trusted Execution Technology. BIOS must set this bit only
272 /// when the CPUID function 1 returns VMX feature flag and SMX feature
273 /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&
274 /// CPUID.01H:ECX[6] = 1.
276 UINT32 EnableVmxInsideSmx
:1;
278 /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX
279 /// for system executive that do not require SMX. BIOS must set this bit
280 /// only when the CPUID function 1 returns VMX feature flag set (ECX bit
281 /// 5). If CPUID.01H:ECX[5] = 1.
283 UINT32 EnableVmxOutsideSmx
:1;
286 /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit
287 /// in the field represents an enable control for a corresponding SENTER
288 /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If
289 /// CPUID.01H:ECX[6] = 1.
291 UINT32 SenterLocalFunctionEnables
:7;
293 /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable
294 /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit
295 /// 6] is set. If CPUID.01H:ECX[6] = 1.
297 UINT32 SenterGlobalEnable
:1;
300 /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX
301 /// leaf functions. This bit is supported only if CPUID.1:ECX.[bit 6] is
302 /// set. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.
307 /// [Bit 20] LMCE On (R/WL): When set, system software can program the
308 /// MSRs associated with LMCE to configure delivery of some machine check
309 /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.
316 /// All bit fields as a 32-bit value
320 /// All bit fields as a 64-bit value
323 } MSR_IA32_FEATURE_CONTROL_REGISTER
;
327 Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,
328 ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for
329 a logical processor. Reset value is Zero. A write to IA32_TSC will modify
330 the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does
331 not affect the internal invariant TSC hardware.
333 @param ECX MSR_IA32_TSC_ADJUST (0x0000003B)
334 @param EAX Lower 32-bits of MSR value.
335 @param EDX Upper 32-bits of MSR value.
341 Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);
342 AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);
344 @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.
346 #define MSR_IA32_TSC_ADJUST 0x0000003B
350 BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a
351 microcode update to be loaded into the processor. See Section 9.11.6,
352 "Microcode Update Loader." A processor may prevent writing to this MSR when
353 loading guest states on VM entries or saving guest states on VM exits.
354 Introduced at Display Family / Display Model 06_01H.
356 @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079)
357 @param EAX Lower 32-bits of MSR value.
358 @param EDX Upper 32-bits of MSR value.
365 AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);
367 @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.
369 #define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
373 BIOS Update Signature (RO) Returns the microcode update signature following
374 the execution of CPUID.01H. A processor may prevent writing to this MSR when
375 loading guest states on VM entries or saving guest states on VM exits.
376 Introduced at Display Family / Display Model 06_01H.
378 @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B)
379 @param EAX Lower 32-bits of MSR value.
380 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
381 @param EDX Upper 32-bits of MSR value.
382 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
386 MSR_IA32_BIOS_SIGN_ID_REGISTER Msr;
388 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);
390 @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.
392 #define MSR_IA32_BIOS_SIGN_ID 0x0000008B
395 MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID
399 /// Individual bit fields
404 /// [Bits 63:32] Microcode update signature. This field contains the
405 /// signature of the currently loaded microcode update when read following
406 /// the execution of the CPUID instruction, function 1. It is required
407 /// that this register field be pre-loaded with zero prior to executing
408 /// the CPUID, function 1. If the field remains equal to zero, then there
409 /// is no microcode update loaded. Another nonzero value will be the
412 UINT32 MicrocodeUpdateSignature
:32;
415 /// All bit fields as a 64-bit value
418 } MSR_IA32_BIOS_SIGN_ID_REGISTER
;
422 SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =
425 @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)
426 @param EAX Lower 32-bits of MSR value.
427 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
428 @param EDX Upper 32-bits of MSR value.
429 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
433 MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr;
435 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
436 AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);
438 @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.
440 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
443 MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL
447 /// Individual bit fields
451 /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this
452 /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment
453 /// (see Section 34.15.6), the dual-monitor treatment cannot be activated
454 /// if the bit is 0. This bit is cleared when the logical processor is
460 /// [Bit 2] Determines whether executions of VMXOFF unblock SMIs under the
461 /// default treatment of SMIs and SMM. Executions of VMXOFF unblock SMIs
462 /// unless bit 2 is 1 (the value of bit 0 is irrelevant).
467 /// [Bits 31:12] MSEG Base (R/W).
473 /// All bit fields as a 32-bit value
477 /// All bit fields as a 64-bit value
480 } MSR_IA32_SMM_MONITOR_CTL_REGISTER
;
483 MSEG header that is located at the physical address specified by the MsegBase
484 field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.
487 UINT32 MsegHeaderRevision
;
488 UINT32 MonitorFeatures
;
490 UINT32 GdtrBaseOffset
;
496 // Pad header so total size is 2KB
498 UINT8 Reserved
[SIZE_2KB
- 8 * sizeof (UINT32
)];
503 Base address of the logical processor's SMRAM image (RO, SMM only). If
506 @param ECX MSR_IA32_SMBASE (0x0000009E)
507 @param EAX Lower 32-bits of MSR value.
508 @param EDX Upper 32-bits of MSR value.
514 Msr = AsmReadMsr64 (MSR_IA32_SMBASE);
516 @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.
518 #define MSR_IA32_SMBASE 0x0000009E
522 General Performance Counters (R/W).
523 MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.
525 @param ECX MSR_IA32_PMCn
526 @param EAX Lower 32-bits of MSR value.
527 @param EDX Upper 32-bits of MSR value.
533 Msr = AsmReadMsr64 (MSR_IA32_PMC0);
534 AsmWriteMsr64 (MSR_IA32_PMC0, Msr);
536 @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.
537 MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.
538 MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.
539 MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.
540 MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.
541 MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.
542 MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.
543 MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.
546 #define MSR_IA32_PMC0 0x000000C1
547 #define MSR_IA32_PMC1 0x000000C2
548 #define MSR_IA32_PMC2 0x000000C3
549 #define MSR_IA32_PMC3 0x000000C4
550 #define MSR_IA32_PMC4 0x000000C5
551 #define MSR_IA32_PMC5 0x000000C6
552 #define MSR_IA32_PMC6 0x000000C7
553 #define MSR_IA32_PMC7 0x000000C8
558 TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.
559 C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative
560 to TSC freq.) when the logical processor is in C0. Cleared upon overflow /
561 wrap-around of IA32_APERF.
563 @param ECX MSR_IA32_MPERF (0x000000E7)
564 @param EAX Lower 32-bits of MSR value.
565 @param EDX Upper 32-bits of MSR value.
571 Msr = AsmReadMsr64 (MSR_IA32_MPERF);
572 AsmWriteMsr64 (MSR_IA32_MPERF, Msr);
574 @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.
576 #define MSR_IA32_MPERF 0x000000E7
580 Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =
581 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at
582 the coordinated clock frequency, when the logical processor is in C0.
583 Cleared upon overflow / wrap-around of IA32_MPERF.
585 @param ECX MSR_IA32_APERF (0x000000E8)
586 @param EAX Lower 32-bits of MSR value.
587 @param EDX Upper 32-bits of MSR value.
593 Msr = AsmReadMsr64 (MSR_IA32_APERF);
594 AsmWriteMsr64 (MSR_IA32_APERF, Msr);
596 @note MSR_IA32_APERF is defined as IA32_APERF in SDM.
598 #define MSR_IA32_APERF 0x000000E8
602 MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".
603 Introduced at Display Family / Display Model 06_01H.
605 @param ECX MSR_IA32_MTRRCAP (0x000000FE)
606 @param EAX Lower 32-bits of MSR value.
607 Described by the type MSR_IA32_MTRRCAP_REGISTER.
608 @param EDX Upper 32-bits of MSR value.
609 Described by the type MSR_IA32_MTRRCAP_REGISTER.
613 MSR_IA32_MTRRCAP_REGISTER Msr;
615 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);
617 @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.
619 #define MSR_IA32_MTRRCAP 0x000000FE
622 MSR information returned for MSR index #MSR_IA32_MTRRCAP
626 /// Individual bit fields
630 /// [Bits 7:0] VCNT: The number of variable memory type ranges in the
635 /// [Bit 8] Fixed range MTRRs are supported when set.
640 /// [Bit 10] WC Supported when set.
644 /// [Bit 11] SMRR Supported when set.
651 /// All bit fields as a 32-bit value
655 /// All bit fields as a 64-bit value
658 } MSR_IA32_MTRRCAP_REGISTER
;
662 SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
664 @param ECX MSR_IA32_SYSENTER_CS (0x00000174)
665 @param EAX Lower 32-bits of MSR value.
666 Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
667 @param EDX Upper 32-bits of MSR value.
668 Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
672 MSR_IA32_SYSENTER_CS_REGISTER Msr;
674 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);
675 AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);
677 @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.
679 #define MSR_IA32_SYSENTER_CS 0x00000174
682 MSR information returned for MSR index #MSR_IA32_SYSENTER_CS
686 /// Individual bit fields
690 /// [Bits 15:0] CS Selector.
697 /// All bit fields as a 32-bit value
701 /// All bit fields as a 64-bit value
704 } MSR_IA32_SYSENTER_CS_REGISTER
;
708 SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
710 @param ECX MSR_IA32_SYSENTER_ESP (0x00000175)
711 @param EAX Lower 32-bits of MSR value.
712 @param EDX Upper 32-bits of MSR value.
718 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);
719 AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);
721 @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.
723 #define MSR_IA32_SYSENTER_ESP 0x00000175
727 SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
729 @param ECX MSR_IA32_SYSENTER_EIP (0x00000176)
730 @param EAX Lower 32-bits of MSR value.
731 @param EDX Upper 32-bits of MSR value.
737 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);
738 AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);
740 @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.
742 #define MSR_IA32_SYSENTER_EIP 0x00000176
746 Global Machine Check Capability (RO). Introduced at Display Family / Display
749 @param ECX MSR_IA32_MCG_CAP (0x00000179)
750 @param EAX Lower 32-bits of MSR value.
751 Described by the type MSR_IA32_MCG_CAP_REGISTER.
752 @param EDX Upper 32-bits of MSR value.
753 Described by the type MSR_IA32_MCG_CAP_REGISTER.
757 MSR_IA32_MCG_CAP_REGISTER Msr;
759 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
761 @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
763 #define MSR_IA32_MCG_CAP 0x00000179
766 MSR information returned for MSR index #MSR_IA32_MCG_CAP
770 /// Individual bit fields
774 /// [Bits 7:0] Count: Number of reporting banks.
778 /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.
782 /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present
783 /// if this bit is set.
787 /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.
788 /// Introduced at Display Family / Display Model 06_01H.
792 /// [Bit 11] MCG_TES_P: Threshold-based error status register are present
793 /// if this bit is set.
798 /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state
799 /// registers present.
801 UINT32 MCG_EXT_CNT
:8;
803 /// [Bit 24] MCG_SER_P: The processor supports software error recovery if
809 /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform
810 /// firmware to be invoked when an error is detected so that it may
811 /// provide additional platform specific information in an ACPI format
812 /// "Generic Error Data Entry" that augments the data included in machine
813 /// check bank registers. Introduced at Display Family / Display Model
818 /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended
819 /// state in IA32_MCG_STATUS and associated MSR necessary to configure
820 /// Local Machine Check Exception (LMCE). Introduced at Display Family /
821 /// Display Model 06_3EH.
828 /// All bit fields as a 32-bit value
832 /// All bit fields as a 64-bit value
835 } MSR_IA32_MCG_CAP_REGISTER
;
839 Global Machine Check Status (R/W0). Introduced at Display Family / Display
842 @param ECX MSR_IA32_MCG_STATUS (0x0000017A)
843 @param EAX Lower 32-bits of MSR value.
844 Described by the type MSR_IA32_MCG_STATUS_REGISTER.
845 @param EDX Upper 32-bits of MSR value.
846 Described by the type MSR_IA32_MCG_STATUS_REGISTER.
850 MSR_IA32_MCG_STATUS_REGISTER Msr;
852 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);
853 AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);
855 @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.
857 #define MSR_IA32_MCG_STATUS 0x0000017A
860 MSR information returned for MSR index #MSR_IA32_MCG_STATUS
864 /// Individual bit fields
868 /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display
873 /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display
878 /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family
879 /// / Display Model 06_01H.
883 /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.
890 /// All bit fields as a 32-bit value
894 /// All bit fields as a 64-bit value
897 } MSR_IA32_MCG_STATUS_REGISTER
;
901 Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.
903 @param ECX MSR_IA32_MCG_CTL (0x0000017B)
904 @param EAX Lower 32-bits of MSR value.
905 @param EDX Upper 32-bits of MSR value.
911 Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);
912 AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);
914 @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.
916 #define MSR_IA32_MCG_CTL 0x0000017B
920 Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.
922 @param ECX MSR_IA32_PERFEVTSELn
923 @param EAX Lower 32-bits of MSR value.
924 Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
925 @param EDX Upper 32-bits of MSR value.
926 Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
930 MSR_IA32_PERFEVTSEL_REGISTER Msr;
932 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);
933 AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);
935 @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.
936 MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.
937 MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.
938 MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
941 #define MSR_IA32_PERFEVTSEL0 0x00000186
942 #define MSR_IA32_PERFEVTSEL1 0x00000187
943 #define MSR_IA32_PERFEVTSEL2 0x00000188
944 #define MSR_IA32_PERFEVTSEL3 0x00000189
948 MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to
949 #MSR_IA32_PERFEVTSEL3
953 /// Individual bit fields
957 /// [Bits 7:0] Event Select: Selects a performance event logic unit.
959 UINT32 EventSelect
:8;
961 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
962 /// detect on the selected event logic.
966 /// [Bit 16] USR: Counts while in privilege level is not ring 0.
970 /// [Bit 17] OS: Counts while in privilege level is ring 0.
974 /// [Bit 18] Edge: Enables edge detection if set.
978 /// [Bit 19] PC: enables pin control.
982 /// [Bit 20] INT: enables interrupt on counter overflow.
986 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
987 /// event conditions occurring across all logical processors sharing a
988 /// processor core. When set to 0, the counter only increments the
989 /// associated event conditions occurring in the logical processor which
990 /// programmed the MSR.
994 /// [Bit 22] EN: enables the corresponding performance counter to commence
995 /// counting when this bit is set.
999 /// [Bit 23] INV: invert the CMASK.
1003 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
1004 /// performance counter increments each cycle if the event count is
1005 /// greater than or equal to the CMASK.
1011 /// All bit fields as a 32-bit value
1015 /// All bit fields as a 64-bit value
1018 } MSR_IA32_PERFEVTSEL_REGISTER
;
1022 Current performance state(P-State) operating point (RO). Introduced at
1023 Display Family / Display Model 0F_03H.
1025 @param ECX MSR_IA32_PERF_STATUS (0x00000198)
1026 @param EAX Lower 32-bits of MSR value.
1027 Described by the type MSR_IA32_PERF_STATUS_REGISTER.
1028 @param EDX Upper 32-bits of MSR value.
1029 Described by the type MSR_IA32_PERF_STATUS_REGISTER.
1031 <b>Example usage</b>
1033 MSR_IA32_PERF_STATUS_REGISTER Msr;
1035 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);
1037 @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.
1039 #define MSR_IA32_PERF_STATUS 0x00000198
1042 MSR information returned for MSR index #MSR_IA32_PERF_STATUS
1046 /// Individual bit fields
1050 /// [Bits 15:0] Current performance State Value.
1053 UINT32 Reserved1
:16;
1054 UINT32 Reserved2
:32;
1057 /// All bit fields as a 32-bit value
1061 /// All bit fields as a 64-bit value
1064 } MSR_IA32_PERF_STATUS_REGISTER
;
1068 (R/W). Introduced at Display Family / Display Model 0F_03H.
1070 @param ECX MSR_IA32_PERF_CTL (0x00000199)
1071 @param EAX Lower 32-bits of MSR value.
1072 Described by the type MSR_IA32_PERF_CTL_REGISTER.
1073 @param EDX Upper 32-bits of MSR value.
1074 Described by the type MSR_IA32_PERF_CTL_REGISTER.
1076 <b>Example usage</b>
1078 MSR_IA32_PERF_CTL_REGISTER Msr;
1080 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);
1081 AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);
1083 @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.
1085 #define MSR_IA32_PERF_CTL 0x00000199
1088 MSR information returned for MSR index #MSR_IA32_PERF_CTL
1092 /// Individual bit fields
1096 /// [Bits 15:0] Target performance State Value.
1098 UINT32 TargetState
:16;
1099 UINT32 Reserved1
:16;
1101 /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH
1105 UINT32 Reserved2
:31;
1108 /// All bit fields as a 64-bit value
1111 } MSR_IA32_PERF_CTL_REGISTER
;
1115 Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled
1116 Clock Modulation.". Introduced at Display Family / Display Model 0F_0H.
1118 @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)
1119 @param EAX Lower 32-bits of MSR value.
1120 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
1121 @param EDX Upper 32-bits of MSR value.
1122 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
1124 <b>Example usage</b>
1126 MSR_IA32_CLOCK_MODULATION_REGISTER Msr;
1128 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);
1129 AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);
1131 @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.
1133 #define MSR_IA32_CLOCK_MODULATION 0x0000019A
1136 MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION
1140 /// Individual bit fields
1144 /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If
1145 /// CPUID.06H:EAX[5] = 1.
1147 UINT32 ExtendedOnDemandClockModulationDutyCycle
:1;
1149 /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded
1150 /// values for target duty cycle modulation.
1152 UINT32 OnDemandClockModulationDutyCycle
:3;
1154 /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.
1156 UINT32 OnDemandClockModulationEnable
:1;
1157 UINT32 Reserved1
:27;
1158 UINT32 Reserved2
:32;
1161 /// All bit fields as a 32-bit value
1165 /// All bit fields as a 64-bit value
1168 } MSR_IA32_CLOCK_MODULATION_REGISTER
;
1172 Thermal Interrupt Control (R/W) Enables and disables the generation of an
1173 interrupt on temperature transitions detected with the processor's thermal
1174 sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".
1175 Introduced at Display Family / Display Model 0F_0H.
1177 @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)
1178 @param EAX Lower 32-bits of MSR value.
1179 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
1180 @param EDX Upper 32-bits of MSR value.
1181 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
1183 <b>Example usage</b>
1185 MSR_IA32_THERM_INTERRUPT_REGISTER Msr;
1187 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);
1188 AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);
1190 @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.
1192 #define MSR_IA32_THERM_INTERRUPT 0x0000019B
1195 MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT
1199 /// Individual bit fields
1203 /// [Bit 0] High-Temperature Interrupt Enable.
1205 UINT32 HighTempEnable
:1;
1207 /// [Bit 1] Low-Temperature Interrupt Enable.
1209 UINT32 LowTempEnable
:1;
1211 /// [Bit 2] PROCHOT# Interrupt Enable.
1213 UINT32 PROCHOT_Enable
:1;
1215 /// [Bit 3] FORCEPR# Interrupt Enable.
1217 UINT32 FORCEPR_Enable
:1;
1219 /// [Bit 4] Critical Temperature Interrupt Enable.
1221 UINT32 CriticalTempEnable
:1;
1224 /// [Bits 14:8] Threshold #1 Value.
1226 UINT32 Threshold1
:7;
1228 /// [Bit 15] Threshold #1 Interrupt Enable.
1230 UINT32 Threshold1Enable
:1;
1232 /// [Bits 22:16] Threshold #2 Value.
1234 UINT32 Threshold2
:7;
1236 /// [Bit 23] Threshold #2 Interrupt Enable.
1238 UINT32 Threshold2Enable
:1;
1240 /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.
1242 UINT32 PowerLimitNotificationEnable
:1;
1244 UINT32 Reserved3
:32;
1247 /// All bit fields as a 32-bit value
1251 /// All bit fields as a 64-bit value
1254 } MSR_IA32_THERM_INTERRUPT_REGISTER
;
1258 Thermal Status Information (RO) Contains status information about the
1259 processor's thermal sensor and automatic thermal monitoring facilities. See
1260 Section 14.7.2, "Thermal Monitor". Introduced at Display Family / Display
1263 @param ECX MSR_IA32_THERM_STATUS (0x0000019C)
1264 @param EAX Lower 32-bits of MSR value.
1265 Described by the type MSR_IA32_THERM_STATUS_REGISTER.
1266 @param EDX Upper 32-bits of MSR value.
1267 Described by the type MSR_IA32_THERM_STATUS_REGISTER.
1269 <b>Example usage</b>
1271 MSR_IA32_THERM_STATUS_REGISTER Msr;
1273 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);
1275 @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.
1277 #define MSR_IA32_THERM_STATUS 0x0000019C
1280 MSR information returned for MSR index #MSR_IA32_THERM_STATUS
1284 /// Individual bit fields
1288 /// [Bit 0] Thermal Status (RO):.
1290 UINT32 ThermalStatus
:1;
1292 /// [Bit 1] Thermal Status Log (R/W):.
1294 UINT32 ThermalStatusLog
:1;
1296 /// [Bit 2] PROCHOT # or FORCEPR# event (RO).
1298 UINT32 PROCHOT_FORCEPR_Event
:1;
1300 /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0).
1302 UINT32 PROCHOT_FORCEPR_Log
:1;
1304 /// [Bit 4] Critical Temperature Status (RO).
1306 UINT32 CriticalTempStatus
:1;
1308 /// [Bit 5] Critical Temperature Status log (R/WC0).
1310 UINT32 CriticalTempStatusLog
:1;
1312 /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.
1314 UINT32 ThermalThreshold1Status
:1;
1316 /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.
1318 UINT32 ThermalThreshold1Log
:1;
1320 /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.
1322 UINT32 ThermalThreshold2Status
:1;
1324 /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.
1326 UINT32 ThermalThreshold2Log
:1;
1328 /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.
1330 UINT32 PowerLimitStatus
:1;
1332 /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.
1334 UINT32 PowerLimitLog
:1;
1336 /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.
1338 UINT32 CurrentLimitStatus
:1;
1340 /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
1342 UINT32 CurrentLimitLog
:1;
1344 /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.
1346 UINT32 CrossDomainLimitStatus
:1;
1348 /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
1350 UINT32 CrossDomainLimitLog
:1;
1352 /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.
1354 UINT32 DigitalReadout
:7;
1357 /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =
1360 UINT32 ResolutionInDegreesCelsius
:4;
1362 /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.
1364 UINT32 ReadingValid
:1;
1365 UINT32 Reserved2
:32;
1368 /// All bit fields as a 32-bit value
1372 /// All bit fields as a 64-bit value
1375 } MSR_IA32_THERM_STATUS_REGISTER
;
1379 Enable Misc. Processor Features (R/W) Allows a variety of processor
1380 functions to be enabled and disabled.
1382 @param ECX MSR_IA32_MISC_ENABLE (0x000001A0)
1383 @param EAX Lower 32-bits of MSR value.
1384 Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
1385 @param EDX Upper 32-bits of MSR value.
1386 Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
1388 <b>Example usage</b>
1390 MSR_IA32_MISC_ENABLE_REGISTER Msr;
1392 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
1393 AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);
1395 @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
1397 #define MSR_IA32_MISC_ENABLE 0x000001A0
1400 MSR information returned for MSR index #MSR_IA32_MISC_ENABLE
1404 /// Individual bit fields
1408 /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for
1409 /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings
1410 /// are disabled. Introduced at Display Family / Display Model 0F_0H.
1412 UINT32 FastStrings
:1;
1415 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
1416 /// this bit enables the thermal control circuit (TCC) portion of the
1417 /// Intel Thermal Monitor feature. This allows the processor to
1418 /// automatically reduce power consumption in response to TCC activation.
1419 /// 0 = Disabled. Note: In some products clearing this bit might be
1420 /// ignored in critical thermal conditions, and TM1, TM2 and adaptive
1421 /// thermal throttling will still be activated. Introduced at Display
1422 /// Family / Display Model 0F_0H.
1424 UINT32 AutomaticThermalControlCircuit
:1;
1427 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance
1428 /// monitoring enabled 0 = Performance monitoring disabled. Introduced at
1429 /// Display Family / Display Model 0F_0H.
1431 UINT32 PerformanceMonitoring
:1;
1434 /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't
1435 /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at
1436 /// Display Family / Display Model 0F_0H.
1440 /// [Bit 12] Precise Event Based Sampling (PEBS) Unavailable (RO) 1 =
1441 /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display
1442 /// Family / Display Model 06_0FH.
1447 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced
1448 /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep
1449 /// Technology enabled. If CPUID.01H: ECX[7] =1.
1454 /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the
1455 /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This
1456 /// indicates that MONITOR/MWAIT are not supported. Software attempts to
1457 /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit
1458 /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit
1459 /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit
1460 /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it
1461 /// in the default state. Writing this bit when the SSE3 feature flag is
1462 /// set to 0 may generate a #GP exception. Introduced at Display Family /
1463 /// Display Model 0F_03H.
1468 /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H
1469 /// returns a maximum value in EAX[7:0] of 3. BIOS should contain a setup
1470 /// question that allows users to specify when the installed OS does not
1471 /// support CPUID functions greater than 3. Before setting this bit, BIOS
1472 /// must execute the CPUID.0H and examine the maximum value returned in
1473 /// EAX[7:0]. If the maximum value is greater than 3, the bit is
1474 /// supported. Otherwise, the bit is not supported. Writing to this bit
1475 /// when the maximum value is greater than 3 may generate a #GP exception.
1476 /// Setting this bit may cause unexpected behavior in software that
1477 /// depends on the availability of CPUID leaves greater than 3. Introduced
1478 /// at Display Family / Display Model 0F_03H.
1480 UINT32 LimitCpuidMaxval
:1;
1482 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
1483 /// disabled. xTPR messages are optional messages that allow the processor
1484 /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.
1486 UINT32 xTPR_Message_Disable
:1;
1490 /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit
1491 /// feature (XD Bit) is disabled and the XD Bit extended feature flag will
1492 /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the
1493 /// Execute Disable Bit feature (if available) allows the OS to enable PAE
1494 /// paging and take advantage of data only pages. BIOS must not alter the
1495 /// contents of this bit location, if XD bit is not supported. Writing
1496 /// this bit to 1 when the XD Bit extended feature flag is set to 0 may
1497 /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.
1500 UINT32 Reserved9
:29;
1503 /// All bit fields as a 64-bit value
1506 } MSR_IA32_MISC_ENABLE_REGISTER
;
1510 Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.
1512 @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)
1513 @param EAX Lower 32-bits of MSR value.
1514 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
1515 @param EDX Upper 32-bits of MSR value.
1516 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
1518 <b>Example usage</b>
1520 MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr;
1522 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);
1523 AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);
1525 @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
1527 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0
1530 MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS
1534 /// Individual bit fields
1538 /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest
1539 /// performance. 15 indicates preference to maximize energy saving.
1541 UINT32 PowerPolicyPreference
:4;
1542 UINT32 Reserved1
:28;
1543 UINT32 Reserved2
:32;
1546 /// All bit fields as a 32-bit value
1550 /// All bit fields as a 64-bit value
1553 } MSR_IA32_ENERGY_PERF_BIAS_REGISTER
;
1557 Package Thermal Status Information (RO) Contains status information about
1558 the package's thermal sensor. See Section 14.8, "Package Level Thermal
1559 Management.". If CPUID.06H: EAX[6] = 1.
1561 @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)
1562 @param EAX Lower 32-bits of MSR value.
1563 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
1564 @param EDX Upper 32-bits of MSR value.
1565 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
1567 <b>Example usage</b>
1569 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr;
1571 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);
1573 @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.
1575 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1
1578 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS
1582 /// Individual bit fields
1586 /// [Bit 0] Pkg Thermal Status (RO):.
1588 UINT32 ThermalStatus
:1;
1590 /// [Bit 1] Pkg Thermal Status Log (R/W):.
1592 UINT32 ThermalStatusLog
:1;
1594 /// [Bit 2] Pkg PROCHOT # event (RO).
1596 UINT32 PROCHOT_Event
:1;
1598 /// [Bit 3] Pkg PROCHOT # log (R/WC0).
1600 UINT32 PROCHOT_Log
:1;
1602 /// [Bit 4] Pkg Critical Temperature Status (RO).
1604 UINT32 CriticalTempStatus
:1;
1606 /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).
1608 UINT32 CriticalTempStatusLog
:1;
1610 /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).
1612 UINT32 ThermalThreshold1Status
:1;
1614 /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).
1616 UINT32 ThermalThreshold1Log
:1;
1618 /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).
1620 UINT32 ThermalThreshold2Status
:1;
1622 /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).
1624 UINT32 ThermalThreshold2Log
:1;
1626 /// [Bit 10] Pkg Power Limitation Status (RO).
1628 UINT32 PowerLimitStatus
:1;
1630 /// [Bit 11] Pkg Power Limitation log (R/WC0).
1632 UINT32 PowerLimitLog
:1;
1635 /// [Bits 22:16] Pkg Digital Readout (RO).
1637 UINT32 DigitalReadout
:7;
1639 UINT32 Reserved3
:32;
1642 /// All bit fields as a 32-bit value
1646 /// All bit fields as a 64-bit value
1649 } MSR_IA32_PACKAGE_THERM_STATUS_REGISTER
;
1653 Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of
1654 an interrupt on temperature transitions detected with the package's thermal
1655 sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:
1658 @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)
1659 @param EAX Lower 32-bits of MSR value.
1660 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
1661 @param EDX Upper 32-bits of MSR value.
1662 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
1664 <b>Example usage</b>
1666 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr;
1668 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);
1669 AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);
1671 @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.
1673 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2
1676 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT
1680 /// Individual bit fields
1684 /// [Bit 0] Pkg High-Temperature Interrupt Enable.
1686 UINT32 HighTempEnable
:1;
1688 /// [Bit 1] Pkg Low-Temperature Interrupt Enable.
1690 UINT32 LowTempEnable
:1;
1692 /// [Bit 2] Pkg PROCHOT# Interrupt Enable.
1694 UINT32 PROCHOT_Enable
:1;
1697 /// [Bit 4] Pkg Overheat Interrupt Enable.
1699 UINT32 OverheatEnable
:1;
1702 /// [Bits 14:8] Pkg Threshold #1 Value.
1704 UINT32 Threshold1
:7;
1706 /// [Bit 15] Pkg Threshold #1 Interrupt Enable.
1708 UINT32 Threshold1Enable
:1;
1710 /// [Bits 22:16] Pkg Threshold #2 Value.
1712 UINT32 Threshold2
:7;
1714 /// [Bit 23] Pkg Threshold #2 Interrupt Enable.
1716 UINT32 Threshold2Enable
:1;
1718 /// [Bit 24] Pkg Power Limit Notification Enable.
1720 UINT32 PowerLimitNotificationEnable
:1;
1722 UINT32 Reserved4
:32;
1725 /// All bit fields as a 32-bit value
1729 /// All bit fields as a 64-bit value
1732 } MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER
;
1736 Trace/Profile Resource Control (R/W). Introduced at Display Family / Display
1739 @param ECX MSR_IA32_DEBUGCTL (0x000001D9)
1740 @param EAX Lower 32-bits of MSR value.
1741 Described by the type MSR_IA32_DEBUGCTL_REGISTER.
1742 @param EDX Upper 32-bits of MSR value.
1743 Described by the type MSR_IA32_DEBUGCTL_REGISTER.
1745 <b>Example usage</b>
1747 MSR_IA32_DEBUGCTL_REGISTER Msr;
1749 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);
1750 AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);
1752 @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.
1754 #define MSR_IA32_DEBUGCTL 0x000001D9
1757 MSR information returned for MSR index #MSR_IA32_DEBUGCTL
1761 /// Individual bit fields
1765 /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a
1766 /// running trace of the most recent branches taken by the processor in
1767 /// the LBR stack. Introduced at Display Family / Display Model 06_01H.
1771 /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat
1772 /// EFLAGS.TF as single-step on branches instead of single-step on
1773 /// instructions. Introduced at Display Family / Display Model 06_01H.
1778 /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be
1779 /// sent. Introduced at Display Family / Display Model 06_0EH.
1783 /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to
1784 /// be logged in a BTS buffer. Introduced at Display Family / Display
1789 /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular
1790 /// fashion. When this bit is set, an interrupt is generated by the BTS
1791 /// facility when the BTS buffer is full. Introduced at Display Family /
1792 /// Display Model 06_0EH.
1796 /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.
1797 /// Introduced at Display Family / Display Model 06_0FH.
1799 UINT32 BTS_OFF_OS
:1;
1801 /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.
1802 /// Introduced at Display Family / Display Model 06_0FH.
1804 UINT32 BTS_OFF_USR
:1;
1806 /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a
1807 /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
1809 UINT32 FREEZE_LBRS_ON_PMI
:1;
1811 /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the
1812 /// global counter control MSR are frozen (address 38FH) on a PMI request.
1813 /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
1815 UINT32 FREEZE_PERFMON_ON_PMI
:1;
1817 /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to
1818 /// receive and generate PMI on behalf of the uncore. Introduced at
1819 /// Display Family / Display Model 06_1AH.
1821 UINT32 ENABLE_UNCORE_PMI
:1;
1823 /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace
1824 /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.
1826 UINT32 FREEZE_WHILE_SMM
:1;
1828 /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If
1829 /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).
1832 UINT32 Reserved2
:16;
1833 UINT32 Reserved3
:32;
1836 /// All bit fields as a 32-bit value
1840 /// All bit fields as a 64-bit value
1843 } MSR_IA32_DEBUGCTL_REGISTER
;
1847 SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.
1848 If IA32_MTRRCAP.SMRR[11] = 1.
1850 @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2)
1851 @param EAX Lower 32-bits of MSR value.
1852 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
1853 @param EDX Upper 32-bits of MSR value.
1854 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
1856 <b>Example usage</b>
1858 MSR_IA32_SMRR_PHYSBASE_REGISTER Msr;
1860 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);
1861 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);
1863 @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.
1865 #define MSR_IA32_SMRR_PHYSBASE 0x000001F2
1868 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE
1872 /// Individual bit fields
1876 /// [Bits 7:0] Type. Specifies memory type of the range.
1881 /// [Bits 31:12] PhysBase. SMRR physical Base Address.
1884 UINT32 Reserved2
:32;
1887 /// All bit fields as a 32-bit value
1891 /// All bit fields as a 64-bit value
1894 } MSR_IA32_SMRR_PHYSBASE_REGISTER
;
1898 SMRR Range Mask. (Writeable only in SMM) Range Mask of SMM memory range. If
1899 IA32_MTRRCAP[SMRR] = 1.
1901 @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)
1902 @param EAX Lower 32-bits of MSR value.
1903 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
1904 @param EDX Upper 32-bits of MSR value.
1905 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
1907 <b>Example usage</b>
1909 MSR_IA32_SMRR_PHYSMASK_REGISTER Msr;
1911 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);
1912 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);
1914 @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.
1916 #define MSR_IA32_SMRR_PHYSMASK 0x000001F3
1919 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK
1923 /// Individual bit fields
1926 UINT32 Reserved1
:11;
1928 /// [Bit 11] Valid Enable range mask.
1932 /// [Bits 31:12] PhysMask SMRR address range mask.
1935 UINT32 Reserved2
:32;
1938 /// All bit fields as a 32-bit value
1942 /// All bit fields as a 64-bit value
1945 } MSR_IA32_SMRR_PHYSMASK_REGISTER
;
1949 DCA Capability (R). If CPUID.01H: ECX[18] = 1.
1951 @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)
1952 @param EAX Lower 32-bits of MSR value.
1953 @param EDX Upper 32-bits of MSR value.
1955 <b>Example usage</b>
1959 Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);
1961 @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.
1963 #define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8
1967 If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.
1969 @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9)
1970 @param EAX Lower 32-bits of MSR value.
1971 @param EDX Upper 32-bits of MSR value.
1973 <b>Example usage</b>
1977 Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);
1978 AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);
1980 @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.
1982 #define MSR_IA32_CPU_DCA_CAP 0x000001F9
1986 DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.
1988 @param ECX MSR_IA32_DCA_0_CAP (0x000001FA)
1989 @param EAX Lower 32-bits of MSR value.
1990 Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
1991 @param EDX Upper 32-bits of MSR value.
1992 Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
1994 <b>Example usage</b>
1996 MSR_IA32_DCA_0_CAP_REGISTER Msr;
1998 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);
1999 AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);
2001 @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.
2003 #define MSR_IA32_DCA_0_CAP 0x000001FA
2006 MSR information returned for MSR index #MSR_IA32_DCA_0_CAP
2010 /// Individual bit fields
2014 /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no
2015 /// defeatures are set.
2017 UINT32 DCA_ACTIVE
:1;
2019 /// [Bits 2:1] TRANSACTION.
2021 UINT32 TRANSACTION
:2;
2023 /// [Bits 6:3] DCA_TYPE.
2027 /// [Bits 10:7] DCA_QUEUE_SIZE.
2029 UINT32 DCA_QUEUE_SIZE
:4;
2032 /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW
2038 /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.
2043 /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).
2047 UINT32 Reserved5
:32;
2050 /// All bit fields as a 32-bit value
2054 /// All bit fields as a 64-bit value
2057 } MSR_IA32_DCA_0_CAP_REGISTER
;
2061 MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".
2062 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
2064 @param ECX MSR_IA32_MTRR_PHYSBASEn
2065 @param EAX Lower 32-bits of MSR value.
2066 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
2067 @param EDX Upper 32-bits of MSR value.
2068 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
2070 <b>Example usage</b>
2072 MSR_IA32_MTRR_PHYSBASE_REGISTER Msr;
2074 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
2075 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);
2077 @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM.
2078 MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM.
2079 MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM.
2080 MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM.
2081 MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM.
2082 MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM.
2083 MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM.
2084 MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM.
2085 MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM.
2086 MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.
2089 #define MSR_IA32_MTRR_PHYSBASE0 0x00000200
2090 #define MSR_IA32_MTRR_PHYSBASE1 0x00000202
2091 #define MSR_IA32_MTRR_PHYSBASE2 0x00000204
2092 #define MSR_IA32_MTRR_PHYSBASE3 0x00000206
2093 #define MSR_IA32_MTRR_PHYSBASE4 0x00000208
2094 #define MSR_IA32_MTRR_PHYSBASE5 0x0000020A
2095 #define MSR_IA32_MTRR_PHYSBASE6 0x0000020C
2096 #define MSR_IA32_MTRR_PHYSBASE7 0x0000020E
2097 #define MSR_IA32_MTRR_PHYSBASE8 0x00000210
2098 #define MSR_IA32_MTRR_PHYSBASE9 0x00000212
2102 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to
2103 #MSR_IA32_MTRR_PHYSBASE9
2107 /// Individual bit fields
2111 /// [Bits 7:0] Type. Specifies memory type of the range.
2116 /// [Bits 31:12] PhysBase. MTRR physical Base Address.
2120 /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.
2121 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
2122 /// maximum physical address range supported by the processor. It is
2123 /// reported by CPUID leaf function 80000008H. If CPUID does not support
2124 /// leaf 80000008H, the processor supports 36-bit physical address size,
2125 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
2127 UINT32 PhysBaseHi
:32;
2130 /// All bit fields as a 64-bit value
2133 } MSR_IA32_MTRR_PHYSBASE_REGISTER
;
2137 MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".
2138 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
2140 @param ECX MSR_IA32_MTRR_PHYSMASKn
2141 @param EAX Lower 32-bits of MSR value.
2142 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
2143 @param EDX Upper 32-bits of MSR value.
2144 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
2146 <b>Example usage</b>
2148 MSR_IA32_MTRR_PHYSMASK_REGISTER Msr;
2150 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
2151 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);
2153 @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM.
2154 MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM.
2155 MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM.
2156 MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM.
2157 MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM.
2158 MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM.
2159 MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM.
2160 MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM.
2161 MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM.
2162 MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.
2165 #define MSR_IA32_MTRR_PHYSMASK0 0x00000201
2166 #define MSR_IA32_MTRR_PHYSMASK1 0x00000203
2167 #define MSR_IA32_MTRR_PHYSMASK2 0x00000205
2168 #define MSR_IA32_MTRR_PHYSMASK3 0x00000207
2169 #define MSR_IA32_MTRR_PHYSMASK4 0x00000209
2170 #define MSR_IA32_MTRR_PHYSMASK5 0x0000020B
2171 #define MSR_IA32_MTRR_PHYSMASK6 0x0000020D
2172 #define MSR_IA32_MTRR_PHYSMASK7 0x0000020F
2173 #define MSR_IA32_MTRR_PHYSMASK8 0x00000211
2174 #define MSR_IA32_MTRR_PHYSMASK9 0x00000213
2178 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to
2179 #MSR_IA32_MTRR_PHYSMASK9
2183 /// Individual bit fields
2186 UINT32 Reserved1
:11;
2188 /// [Bit 11] Valid Enable range mask.
2192 /// [Bits 31:12] PhysMask. MTRR address range mask.
2196 /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.
2197 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
2198 /// maximum physical address range supported by the processor. It is
2199 /// reported by CPUID leaf function 80000008H. If CPUID does not support
2200 /// leaf 80000008H, the processor supports 36-bit physical address size,
2201 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
2203 UINT32 PhysMaskHi
:32;
2206 /// All bit fields as a 64-bit value
2209 } MSR_IA32_MTRR_PHYSMASK_REGISTER
;
2213 MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.
2215 @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250)
2216 @param EAX Lower 32-bits of MSR value.
2217 @param EDX Upper 32-bits of MSR value.
2219 <b>Example usage</b>
2223 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);
2224 AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);
2226 @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.
2228 #define MSR_IA32_MTRR_FIX64K_00000 0x00000250
2232 MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.
2234 @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258)
2235 @param EAX Lower 32-bits of MSR value.
2236 @param EDX Upper 32-bits of MSR value.
2238 <b>Example usage</b>
2242 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);
2243 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);
2245 @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.
2247 #define MSR_IA32_MTRR_FIX16K_80000 0x00000258
2251 MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.
2253 @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)
2254 @param EAX Lower 32-bits of MSR value.
2255 @param EDX Upper 32-bits of MSR value.
2257 <b>Example usage</b>
2261 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);
2262 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);
2264 @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.
2266 #define MSR_IA32_MTRR_FIX16K_A0000 0x00000259
2270 See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.
2272 @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)
2273 @param EAX Lower 32-bits of MSR value.
2274 @param EDX Upper 32-bits of MSR value.
2276 <b>Example usage</b>
2280 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);
2281 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);
2283 @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.
2285 #define MSR_IA32_MTRR_FIX4K_C0000 0x00000268
2289 MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.
2291 @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)
2292 @param EAX Lower 32-bits of MSR value.
2293 @param EDX Upper 32-bits of MSR value.
2295 <b>Example usage</b>
2299 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);
2300 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);
2302 @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.
2304 #define MSR_IA32_MTRR_FIX4K_C8000 0x00000269
2308 MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.
2310 @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)
2311 @param EAX Lower 32-bits of MSR value.
2312 @param EDX Upper 32-bits of MSR value.
2314 <b>Example usage</b>
2318 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);
2319 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);
2321 @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.
2323 #define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
2327 MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.
2329 @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)
2330 @param EAX Lower 32-bits of MSR value.
2331 @param EDX Upper 32-bits of MSR value.
2333 <b>Example usage</b>
2337 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);
2338 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);
2340 @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.
2342 #define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
2346 MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.
2348 @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)
2349 @param EAX Lower 32-bits of MSR value.
2350 @param EDX Upper 32-bits of MSR value.
2352 <b>Example usage</b>
2356 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);
2357 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);
2359 @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.
2361 #define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
2365 MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.
2367 @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)
2368 @param EAX Lower 32-bits of MSR value.
2369 @param EDX Upper 32-bits of MSR value.
2371 <b>Example usage</b>
2375 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);
2376 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);
2378 @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.
2380 #define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
2384 MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.
2386 @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)
2387 @param EAX Lower 32-bits of MSR value.
2388 @param EDX Upper 32-bits of MSR value.
2390 <b>Example usage</b>
2394 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);
2395 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);
2397 @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.
2399 #define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
2403 MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.
2405 @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)
2406 @param EAX Lower 32-bits of MSR value.
2407 @param EDX Upper 32-bits of MSR value.
2409 <b>Example usage</b>
2413 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);
2414 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);
2416 @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.
2418 #define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
2422 IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.
2424 @param ECX MSR_IA32_PAT (0x00000277)
2425 @param EAX Lower 32-bits of MSR value.
2426 Described by the type MSR_IA32_PAT_REGISTER.
2427 @param EDX Upper 32-bits of MSR value.
2428 Described by the type MSR_IA32_PAT_REGISTER.
2430 <b>Example usage</b>
2432 MSR_IA32_PAT_REGISTER Msr;
2434 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);
2435 AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);
2437 @note MSR_IA32_PAT is defined as IA32_PAT in SDM.
2439 #define MSR_IA32_PAT 0x00000277
2442 MSR information returned for MSR index #MSR_IA32_PAT
2446 /// Individual bit fields
2455 /// [Bits 10:8] PA1.
2460 /// [Bits 18:16] PA2.
2465 /// [Bits 26:24] PA3.
2470 /// [Bits 34:32] PA4.
2475 /// [Bits 42:40] PA5.
2480 /// [Bits 50:48] PA6.
2485 /// [Bits 58:56] PA7.
2491 /// All bit fields as a 64-bit value
2494 } MSR_IA32_PAT_REGISTER
;
2498 Provides the programming interface to use corrected MC error signaling
2499 capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.
2501 @param ECX MSR_IA32_MCn_CTL2
2502 @param EAX Lower 32-bits of MSR value.
2503 Described by the type MSR_IA32_MC_CTL2_REGISTER.
2504 @param EDX Upper 32-bits of MSR value.
2505 Described by the type MSR_IA32_MC_CTL2_REGISTER.
2507 <b>Example usage</b>
2509 MSR_IA32_MC_CTL2_REGISTER Msr;
2511 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
2512 AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);
2514 @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM.
2515 MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM.
2516 MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM.
2517 MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM.
2518 MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.
2519 MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM.
2520 MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM.
2521 MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM.
2522 MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM.
2523 MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM.
2524 MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM.
2525 MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM.
2526 MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM.
2527 MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM.
2528 MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM.
2529 MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM.
2530 MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM.
2531 MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM.
2532 MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM.
2533 MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM.
2534 MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM.
2535 MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM.
2536 MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM.
2537 MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM.
2538 MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM.
2539 MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM.
2540 MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM.
2541 MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM.
2542 MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM.
2543 MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM.
2544 MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM.
2545 MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.
2548 #define MSR_IA32_MC0_CTL2 0x00000280
2549 #define MSR_IA32_MC1_CTL2 0x00000281
2550 #define MSR_IA32_MC2_CTL2 0x00000282
2551 #define MSR_IA32_MC3_CTL2 0x00000283
2552 #define MSR_IA32_MC4_CTL2 0x00000284
2553 #define MSR_IA32_MC5_CTL2 0x00000285
2554 #define MSR_IA32_MC6_CTL2 0x00000286
2555 #define MSR_IA32_MC7_CTL2 0x00000287
2556 #define MSR_IA32_MC8_CTL2 0x00000288
2557 #define MSR_IA32_MC9_CTL2 0x00000289
2558 #define MSR_IA32_MC10_CTL2 0x0000028A
2559 #define MSR_IA32_MC11_CTL2 0x0000028B
2560 #define MSR_IA32_MC12_CTL2 0x0000028C
2561 #define MSR_IA32_MC13_CTL2 0x0000028D
2562 #define MSR_IA32_MC14_CTL2 0x0000028E
2563 #define MSR_IA32_MC15_CTL2 0x0000028F
2564 #define MSR_IA32_MC16_CTL2 0x00000290
2565 #define MSR_IA32_MC17_CTL2 0x00000291
2566 #define MSR_IA32_MC18_CTL2 0x00000292
2567 #define MSR_IA32_MC19_CTL2 0x00000293
2568 #define MSR_IA32_MC20_CTL2 0x00000294
2569 #define MSR_IA32_MC21_CTL2 0x00000295
2570 #define MSR_IA32_MC22_CTL2 0x00000296
2571 #define MSR_IA32_MC23_CTL2 0x00000297
2572 #define MSR_IA32_MC24_CTL2 0x00000298
2573 #define MSR_IA32_MC25_CTL2 0x00000299
2574 #define MSR_IA32_MC26_CTL2 0x0000029A
2575 #define MSR_IA32_MC27_CTL2 0x0000029B
2576 #define MSR_IA32_MC28_CTL2 0x0000029C
2577 #define MSR_IA32_MC29_CTL2 0x0000029D
2578 #define MSR_IA32_MC30_CTL2 0x0000029E
2579 #define MSR_IA32_MC31_CTL2 0x0000029F
2583 MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2
2584 to #MSR_IA32_MC31_CTL2
2588 /// Individual bit fields
2592 /// [Bits 14:0] Corrected error count threshold.
2594 UINT32 CorrectedErrorCountThreshold
:15;
2595 UINT32 Reserved1
:15;
2597 /// [Bit 30] CMCI_EN.
2601 UINT32 Reserved3
:32;
2604 /// All bit fields as a 32-bit value
2608 /// All bit fields as a 64-bit value
2611 } MSR_IA32_MC_CTL2_REGISTER
;
2615 MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.
2617 @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF)
2618 @param EAX Lower 32-bits of MSR value.
2619 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
2620 @param EDX Upper 32-bits of MSR value.
2621 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
2623 <b>Example usage</b>
2625 MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr;
2627 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
2628 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);
2630 @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.
2632 #define MSR_IA32_MTRR_DEF_TYPE 0x000002FF
2635 MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE
2639 /// Individual bit fields
2643 /// [Bits 2:0] Default Memory Type.
2648 /// [Bit 10] Fixed Range MTRR Enable.
2652 /// [Bit 11] MTRR Enable.
2655 UINT32 Reserved2
:20;
2656 UINT32 Reserved3
:32;
2659 /// All bit fields as a 32-bit value
2663 /// All bit fields as a 64-bit value
2666 } MSR_IA32_MTRR_DEF_TYPE_REGISTER
;
2670 Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If
2671 CPUID.0AH: EDX[4:0] > 0.
2673 @param ECX MSR_IA32_FIXED_CTR0 (0x00000309)
2674 @param EAX Lower 32-bits of MSR value.
2675 @param EDX Upper 32-bits of MSR value.
2677 <b>Example usage</b>
2681 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);
2682 AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);
2684 @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.
2686 #define MSR_IA32_FIXED_CTR0 0x00000309
2690 Fixed-Function Performance Counter 1 0 (R/W): Counts CPU_CLK_Unhalted.Core.
2691 If CPUID.0AH: EDX[4:0] > 1.
2693 @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)
2694 @param EAX Lower 32-bits of MSR value.
2695 @param EDX Upper 32-bits of MSR value.
2697 <b>Example usage</b>
2701 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);
2702 AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);
2704 @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.
2706 #define MSR_IA32_FIXED_CTR1 0x0000030A
2710 Fixed-Function Performance Counter 0 0 (R/W): Counts CPU_CLK_Unhalted.Ref.
2711 If CPUID.0AH: EDX[4:0] > 2.
2713 @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)
2714 @param EAX Lower 32-bits of MSR value.
2715 @param EDX Upper 32-bits of MSR value.
2717 <b>Example usage</b>
2721 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);
2722 AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);
2724 @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.
2726 #define MSR_IA32_FIXED_CTR2 0x0000030B
2730 RO. If CPUID.01H: ECX[15] = 1.
2732 @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345)
2733 @param EAX Lower 32-bits of MSR value.
2734 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
2735 @param EDX Upper 32-bits of MSR value.
2736 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
2738 <b>Example usage</b>
2740 MSR_IA32_PERF_CAPABILITIES_REGISTER Msr;
2742 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);
2743 AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);
2745 @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.
2747 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
2750 MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES
2754 /// Individual bit fields
2758 /// [Bits 5:0] LBR format.
2762 /// [Bit 6] PEBS Trap.
2766 /// [Bit 7] PEBSSaveArchRegs.
2768 UINT32 PEBS_ARCH_REG
:1;
2770 /// [Bits 11:8] PEBS Record Format.
2772 UINT32 PEBS_REC_FMT
:4;
2774 /// [Bit 12] 1: Freeze while SMM is supported.
2776 UINT32 SMM_FREEZE
:1;
2778 /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.
2781 UINT32 Reserved1
:18;
2782 UINT32 Reserved2
:32;
2785 /// All bit fields as a 32-bit value
2789 /// All bit fields as a 64-bit value
2792 } MSR_IA32_PERF_CAPABILITIES_REGISTER
;
2796 Fixed-Function Performance Counter Control (R/W) Counter increments while
2797 the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with
2798 the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]
2801 @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D)
2802 @param EAX Lower 32-bits of MSR value.
2803 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
2804 @param EDX Upper 32-bits of MSR value.
2805 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
2807 <b>Example usage</b>
2809 MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr;
2811 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);
2812 AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);
2814 @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.
2816 #define MSR_IA32_FIXED_CTR_CTRL 0x0000038D
2819 MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL
2823 /// Individual bit fields
2827 /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.
2831 /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.
2835 /// [Bit 2] AnyThread: When set to 1, it enables counting the associated
2836 /// event conditions occurring across all logical processors sharing a
2837 /// processor core. When set to 0, the counter only increments the
2838 /// associated event conditions occurring in the logical processor which
2839 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2841 UINT32 AnyThread0
:1;
2843 /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.
2847 /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.
2851 /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.
2855 /// [Bit 6] AnyThread: When set to 1, it enables counting the associated
2856 /// event conditions occurring across all logical processors sharing a
2857 /// processor core. When set to 0, the counter only increments the
2858 /// associated event conditions occurring in the logical processor which
2859 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2861 UINT32 AnyThread1
:1;
2863 /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.
2867 /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.
2871 /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.
2875 /// [Bit 10] AnyThread: When set to 1, it enables counting the associated
2876 /// event conditions occurring across all logical processors sharing a
2877 /// processor core. When set to 0, the counter only increments the
2878 /// associated event conditions occurring in the logical processor which
2879 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2881 UINT32 AnyThread2
:1;
2883 /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.
2886 UINT32 Reserved1
:20;
2887 UINT32 Reserved2
:32;
2890 /// All bit fields as a 32-bit value
2894 /// All bit fields as a 64-bit value
2897 } MSR_IA32_FIXED_CTR_CTRL_REGISTER
;
2901 Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.
2903 @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)
2904 @param EAX Lower 32-bits of MSR value.
2905 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
2906 @param EDX Upper 32-bits of MSR value.
2907 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
2909 <b>Example usage</b>
2911 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
2913 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);
2915 @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
2917 #define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E
2920 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS
2924 /// Individual bit fields
2928 /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:
2933 /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:
2938 /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:
2943 /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:
2947 UINT32 Reserved1
:28;
2949 /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If
2950 /// CPUID.0AH: EAX[7:0] > 1.
2952 UINT32 Ovf_FixedCtr0
:1;
2954 /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If
2955 /// CPUID.0AH: EAX[7:0] > 1.
2957 UINT32 Ovf_FixedCtr1
:1;
2959 /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If
2960 /// CPUID.0AH: EAX[7:0] > 1.
2962 UINT32 Ovf_FixedCtr2
:1;
2963 UINT32 Reserved2
:20;
2965 /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory
2966 /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
2967 /// && IA32_RTIT_CTL.ToPA = 1.
2969 UINT32 Trace_ToPA_PMI
:1;
2972 /// [Bit 58] LBR_Frz: LBRs are frozen due to -
2973 /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If
2974 /// CPUID.0AH: EAX[7:0] > 3.
2978 /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due
2979 /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU
2980 /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.
2984 /// [Bit 60] ASCI: Data in the performance counters in the core PMU may
2985 /// include contributions from the direct or indirect operation intel SGX
2986 /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.
2990 /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:
2993 UINT32 Ovf_Uncore
:1;
2995 /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:
3000 /// [Bit 63] CondChgd: status bits of this register has changed. If
3001 /// CPUID.0AH: EAX[7:0] > 0.
3006 /// All bit fields as a 64-bit value
3009 } MSR_IA32_PERF_GLOBAL_STATUS_REGISTER
;
3013 Global Performance Counter Control (R/W) Counter increments while the result
3014 of ANDing respective enable bit in this MSR with the corresponding OS or USR
3015 bits in the general-purpose or fixed counter control MSR is true. If
3016 CPUID.0AH: EAX[7:0] > 0.
3018 @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)
3019 @param EAX Lower 32-bits of MSR value.
3020 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
3021 @param EDX Upper 32-bits of MSR value.
3022 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
3024 <b>Example usage</b>
3026 MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;
3028 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);
3029 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
3031 @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.
3033 #define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F
3036 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL
3040 /// Individual bit fields
3044 /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.
3045 /// Enable bitmask. Only the first n-1 bits are valid.
3046 /// Bits n..31 are reserved.
3050 /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.
3051 /// Enable bitmask. Only the first n-1 bits are valid.
3052 /// Bits 31:n are reserved.
3054 UINT32 EN_FIXED_CTRn
:32;
3057 /// All bit fields as a 64-bit value
3060 } MSR_IA32_PERF_GLOBAL_CTRL_REGISTER
;
3064 Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >
3065 0 && CPUID.0AH: EAX[7:0] <= 3.
3067 @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
3068 @param EAX Lower 32-bits of MSR value.
3069 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
3070 @param EDX Upper 32-bits of MSR value.
3071 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
3073 <b>Example usage</b>
3075 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
3077 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);
3078 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
3080 @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.
3082 #define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
3085 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL
3089 /// Individual bit fields
3093 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
3094 /// Clear bitmask. Only the first n-1 bits are valid.
3095 /// Bits 31:n are reserved.
3099 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
3100 /// If CPUID.0AH: EDX[4:0] > n.
3101 /// Clear bitmask. Only the first n-1 bits are valid.
3102 /// Bits 22:n are reserved.
3104 UINT32 Ovf_FIXED_CTRn
:23;
3106 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
3107 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.
3109 UINT32 Trace_ToPA_PMI
:1;
3112 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
3113 /// Display Model 06_2EH.
3115 UINT32 Ovf_Uncore
:1;
3117 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
3121 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
3126 /// All bit fields as a 64-bit value
3129 } MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
;
3133 Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:
3136 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
3137 @param EAX Lower 32-bits of MSR value.
3138 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
3139 @param EDX Upper 32-bits of MSR value.
3140 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
3142 <b>Example usage</b>
3144 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;
3146 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);
3147 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
3149 @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
3151 #define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
3154 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET
3158 /// Individual bit fields
3162 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
3163 /// Clear bitmask. Only the first n-1 bits are valid.
3164 /// Bits 31:n are reserved.
3168 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
3169 /// If CPUID.0AH: EDX[4:0] > n.
3170 /// Clear bitmask. Only the first n-1 bits are valid.
3171 /// Bits 22:n are reserved.
3173 UINT32 Ovf_FIXED_CTRn
:23;
3175 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
3176 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.
3178 UINT32 Trace_ToPA_PMI
:1;
3181 /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
3185 /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
3189 /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.
3193 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
3194 /// Display Model 06_2EH.
3196 UINT32 Ovf_Uncore
:1;
3198 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
3202 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
3207 /// All bit fields as a 64-bit value
3210 } MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
;
3214 Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:
3217 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
3218 @param EAX Lower 32-bits of MSR value.
3219 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
3220 @param EDX Upper 32-bits of MSR value.
3221 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
3223 <b>Example usage</b>
3225 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;
3227 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);
3228 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
3230 @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
3232 #define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
3235 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET
3239 /// Individual bit fields
3243 /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.
3244 /// Set bitmask. Only the first n-1 bits are valid.
3245 /// Bits 31:n are reserved.
3249 /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.
3250 /// If CPUID.0AH: EAX[7:0] > n.
3251 /// Set bitmask. Only the first n-1 bits are valid.
3252 /// Bits 22:n are reserved.
3254 UINT32 Ovf_FIXED_CTRn
:23;
3256 /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.
3258 UINT32 Trace_ToPA_PMI
:1;
3261 /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
3265 /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
3269 /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.
3273 /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.
3275 UINT32 Ovf_Uncore
:1;
3277 /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.
3283 /// All bit fields as a 64-bit value
3286 } MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
;
3290 Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >
3293 @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)
3294 @param EAX Lower 32-bits of MSR value.
3295 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
3296 @param EDX Upper 32-bits of MSR value.
3297 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
3299 <b>Example usage</b>
3301 MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr;
3303 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);
3305 @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.
3307 #define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392
3310 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE
3314 /// Individual bit fields
3318 /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n.
3319 /// Status bitmask. Only the first n-1 bits are valid.
3320 /// Bits 31:n are reserved.
3322 UINT32 IA32_PERFEVTSELn
:32;
3324 /// [Bits 62:32] IA32_FIXED_CTRn in use.
3325 /// If CPUID.0AH: EAX[7:0] > n.
3326 /// Status bitmask. Only the first n-1 bits are valid.
3327 /// Bits 30:n are reserved.
3329 UINT32 IA32_FIXED_CTRn
:31;
3331 /// [Bit 63] PMI in use.
3336 /// All bit fields as a 64-bit value
3339 } MSR_IA32_PERF_GLOBAL_INUSE_REGISTER
;
3345 @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1)
3346 @param EAX Lower 32-bits of MSR value.
3347 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
3348 @param EDX Upper 32-bits of MSR value.
3349 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
3351 <b>Example usage</b>
3353 MSR_IA32_PEBS_ENABLE_REGISTER Msr;
3355 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);
3356 AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);
3358 @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.
3360 #define MSR_IA32_PEBS_ENABLE 0x000003F1
3363 MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE
3367 /// Individual bit fields
3371 /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /
3372 /// Display Model 06_0FH.
3376 /// [Bits 3:1] Reserved or Model specific.
3379 UINT32 Reserved2
:28;
3381 /// [Bits 35:32] Reserved or Model specific.
3384 UINT32 Reserved4
:28;
3387 /// All bit fields as a 64-bit value
3390 } MSR_IA32_PEBS_ENABLE_REGISTER
;
3394 MCn_CTL. If IA32_MCG_CAP.CNT > n.
3396 @param ECX MSR_IA32_MCn_CTL
3397 @param EAX Lower 32-bits of MSR value.
3398 @param EDX Upper 32-bits of MSR value.
3400 <b>Example usage</b>
3404 Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
3405 AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);
3407 @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM.
3408 MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM.
3409 MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM.
3410 MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM.
3411 MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.
3412 MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM.
3413 MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM.
3414 MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM.
3415 MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM.
3416 MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM.
3417 MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM.
3418 MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM.
3419 MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM.
3420 MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM.
3421 MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM.
3422 MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM.
3423 MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM.
3424 MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM.
3425 MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM.
3426 MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM.
3427 MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM.
3428 MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM.
3429 MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM.
3430 MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM.
3431 MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM.
3432 MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM.
3433 MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM.
3434 MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM.
3435 MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.
3438 #define MSR_IA32_MC0_CTL 0x00000400
3439 #define MSR_IA32_MC1_CTL 0x00000404
3440 #define MSR_IA32_MC2_CTL 0x00000408
3441 #define MSR_IA32_MC3_CTL 0x0000040C
3442 #define MSR_IA32_MC4_CTL 0x00000410
3443 #define MSR_IA32_MC5_CTL 0x00000414
3444 #define MSR_IA32_MC6_CTL 0x00000418
3445 #define MSR_IA32_MC7_CTL 0x0000041C
3446 #define MSR_IA32_MC8_CTL 0x00000420
3447 #define MSR_IA32_MC9_CTL 0x00000424
3448 #define MSR_IA32_MC10_CTL 0x00000428
3449 #define MSR_IA32_MC11_CTL 0x0000042C
3450 #define MSR_IA32_MC12_CTL 0x00000430
3451 #define MSR_IA32_MC13_CTL 0x00000434
3452 #define MSR_IA32_MC14_CTL 0x00000438
3453 #define MSR_IA32_MC15_CTL 0x0000043C
3454 #define MSR_IA32_MC16_CTL 0x00000440
3455 #define MSR_IA32_MC17_CTL 0x00000444
3456 #define MSR_IA32_MC18_CTL 0x00000448
3457 #define MSR_IA32_MC19_CTL 0x0000044C
3458 #define MSR_IA32_MC20_CTL 0x00000450
3459 #define MSR_IA32_MC21_CTL 0x00000454
3460 #define MSR_IA32_MC22_CTL 0x00000458
3461 #define MSR_IA32_MC23_CTL 0x0000045C
3462 #define MSR_IA32_MC24_CTL 0x00000460
3463 #define MSR_IA32_MC25_CTL 0x00000464
3464 #define MSR_IA32_MC26_CTL 0x00000468
3465 #define MSR_IA32_MC27_CTL 0x0000046C
3466 #define MSR_IA32_MC28_CTL 0x00000470
3471 MCn_STATUS. If IA32_MCG_CAP.CNT > n.
3473 @param ECX MSR_IA32_MCn_STATUS
3474 @param EAX Lower 32-bits of MSR value.
3475 @param EDX Upper 32-bits of MSR value.
3477 <b>Example usage</b>
3481 Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
3482 AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);
3484 @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM.
3485 MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM.
3486 MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM.
3487 MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM.
3488 MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM.
3489 MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM.
3490 MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM.
3491 MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM.
3492 MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM.
3493 MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM.
3494 MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM.
3495 MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM.
3496 MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM.
3497 MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM.
3498 MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM.
3499 MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM.
3500 MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM.
3501 MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM.
3502 MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM.
3503 MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM.
3504 MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM.
3505 MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM.
3506 MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM.
3507 MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM.
3508 MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM.
3509 MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM.
3510 MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM.
3511 MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM.
3512 MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.
3515 #define MSR_IA32_MC0_STATUS 0x00000401
3516 #define MSR_IA32_MC1_STATUS 0x00000405
3517 #define MSR_IA32_MC2_STATUS 0x00000409
3518 #define MSR_IA32_MC3_STATUS 0x0000040D
3519 #define MSR_IA32_MC4_STATUS 0x00000411
3520 #define MSR_IA32_MC5_STATUS 0x00000415
3521 #define MSR_IA32_MC6_STATUS 0x00000419
3522 #define MSR_IA32_MC7_STATUS 0x0000041D
3523 #define MSR_IA32_MC8_STATUS 0x00000421
3524 #define MSR_IA32_MC9_STATUS 0x00000425
3525 #define MSR_IA32_MC10_STATUS 0x00000429
3526 #define MSR_IA32_MC11_STATUS 0x0000042D
3527 #define MSR_IA32_MC12_STATUS 0x00000431
3528 #define MSR_IA32_MC13_STATUS 0x00000435
3529 #define MSR_IA32_MC14_STATUS 0x00000439
3530 #define MSR_IA32_MC15_STATUS 0x0000043D
3531 #define MSR_IA32_MC16_STATUS 0x00000441
3532 #define MSR_IA32_MC17_STATUS 0x00000445
3533 #define MSR_IA32_MC18_STATUS 0x00000449
3534 #define MSR_IA32_MC19_STATUS 0x0000044D
3535 #define MSR_IA32_MC20_STATUS 0x00000451
3536 #define MSR_IA32_MC21_STATUS 0x00000455
3537 #define MSR_IA32_MC22_STATUS 0x00000459
3538 #define MSR_IA32_MC23_STATUS 0x0000045D
3539 #define MSR_IA32_MC24_STATUS 0x00000461
3540 #define MSR_IA32_MC25_STATUS 0x00000465
3541 #define MSR_IA32_MC26_STATUS 0x00000469
3542 #define MSR_IA32_MC27_STATUS 0x0000046D
3543 #define MSR_IA32_MC28_STATUS 0x00000471
3548 MCn_ADDR. If IA32_MCG_CAP.CNT > n.
3550 @param ECX MSR_IA32_MCn_ADDR
3551 @param EAX Lower 32-bits of MSR value.
3552 @param EDX Upper 32-bits of MSR value.
3554 <b>Example usage</b>
3558 Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
3559 AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);
3561 @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM.
3562 MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM.
3563 MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM.
3564 MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM.
3565 MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM.
3566 MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM.
3567 MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM.
3568 MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM.
3569 MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM.
3570 MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM.
3571 MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM.
3572 MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM.
3573 MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM.
3574 MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM.
3575 MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM.
3576 MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM.
3577 MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM.
3578 MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM.
3579 MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM.
3580 MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM.
3581 MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM.
3582 MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM.
3583 MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM.
3584 MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM.
3585 MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM.
3586 MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM.
3587 MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM.
3588 MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM.
3589 MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.
3592 #define MSR_IA32_MC0_ADDR 0x00000402
3593 #define MSR_IA32_MC1_ADDR 0x00000406
3594 #define MSR_IA32_MC2_ADDR 0x0000040A
3595 #define MSR_IA32_MC3_ADDR 0x0000040E
3596 #define MSR_IA32_MC4_ADDR 0x00000412
3597 #define MSR_IA32_MC5_ADDR 0x00000416
3598 #define MSR_IA32_MC6_ADDR 0x0000041A
3599 #define MSR_IA32_MC7_ADDR 0x0000041E
3600 #define MSR_IA32_MC8_ADDR 0x00000422
3601 #define MSR_IA32_MC9_ADDR 0x00000426
3602 #define MSR_IA32_MC10_ADDR 0x0000042A
3603 #define MSR_IA32_MC11_ADDR 0x0000042E
3604 #define MSR_IA32_MC12_ADDR 0x00000432
3605 #define MSR_IA32_MC13_ADDR 0x00000436
3606 #define MSR_IA32_MC14_ADDR 0x0000043A
3607 #define MSR_IA32_MC15_ADDR 0x0000043E
3608 #define MSR_IA32_MC16_ADDR 0x00000442
3609 #define MSR_IA32_MC17_ADDR 0x00000446
3610 #define MSR_IA32_MC18_ADDR 0x0000044A
3611 #define MSR_IA32_MC19_ADDR 0x0000044E
3612 #define MSR_IA32_MC20_ADDR 0x00000452
3613 #define MSR_IA32_MC21_ADDR 0x00000456
3614 #define MSR_IA32_MC22_ADDR 0x0000045A
3615 #define MSR_IA32_MC23_ADDR 0x0000045E
3616 #define MSR_IA32_MC24_ADDR 0x00000462
3617 #define MSR_IA32_MC25_ADDR 0x00000466
3618 #define MSR_IA32_MC26_ADDR 0x0000046A
3619 #define MSR_IA32_MC27_ADDR 0x0000046E
3620 #define MSR_IA32_MC28_ADDR 0x00000472
3625 MCn_MISC. If IA32_MCG_CAP.CNT > n.
3627 @param ECX MSR_IA32_MCn_MISC
3628 @param EAX Lower 32-bits of MSR value.
3629 @param EDX Upper 32-bits of MSR value.
3631 <b>Example usage</b>
3635 Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
3636 AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);
3638 @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM.
3639 MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM.
3640 MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM.
3641 MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM.
3642 MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM.
3643 MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM.
3644 MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.
3645 MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM.
3646 MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM.
3647 MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM.
3648 MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM.
3649 MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM.
3650 MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM.
3651 MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM.
3652 MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM.
3653 MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM.
3654 MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM.
3655 MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM.
3656 MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM.
3657 MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM.
3658 MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM.
3659 MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM.
3660 MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM.
3661 MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM.
3662 MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM.
3663 MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM.
3664 MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM.
3665 MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM.
3666 MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.
3669 #define MSR_IA32_MC0_MISC 0x00000403
3670 #define MSR_IA32_MC1_MISC 0x00000407
3671 #define MSR_IA32_MC2_MISC 0x0000040B
3672 #define MSR_IA32_MC3_MISC 0x0000040F
3673 #define MSR_IA32_MC4_MISC 0x00000413
3674 #define MSR_IA32_MC5_MISC 0x00000417
3675 #define MSR_IA32_MC6_MISC 0x0000041B
3676 #define MSR_IA32_MC7_MISC 0x0000041F
3677 #define MSR_IA32_MC8_MISC 0x00000423
3678 #define MSR_IA32_MC9_MISC 0x00000427
3679 #define MSR_IA32_MC10_MISC 0x0000042B
3680 #define MSR_IA32_MC11_MISC 0x0000042F
3681 #define MSR_IA32_MC12_MISC 0x00000433
3682 #define MSR_IA32_MC13_MISC 0x00000437
3683 #define MSR_IA32_MC14_MISC 0x0000043B
3684 #define MSR_IA32_MC15_MISC 0x0000043F
3685 #define MSR_IA32_MC16_MISC 0x00000443
3686 #define MSR_IA32_MC17_MISC 0x00000447
3687 #define MSR_IA32_MC18_MISC 0x0000044B
3688 #define MSR_IA32_MC19_MISC 0x0000044F
3689 #define MSR_IA32_MC20_MISC 0x00000453
3690 #define MSR_IA32_MC21_MISC 0x00000457
3691 #define MSR_IA32_MC22_MISC 0x0000045B
3692 #define MSR_IA32_MC23_MISC 0x0000045F
3693 #define MSR_IA32_MC24_MISC 0x00000463
3694 #define MSR_IA32_MC25_MISC 0x00000467
3695 #define MSR_IA32_MC26_MISC 0x0000046B
3696 #define MSR_IA32_MC27_MISC 0x0000046F
3697 #define MSR_IA32_MC28_MISC 0x00000473
3702 Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic
3703 VMX Information.". If CPUID.01H:ECX.[5] = 1.
3705 @param ECX MSR_IA32_VMX_BASIC (0x00000480)
3706 @param EAX Lower 32-bits of MSR value.
3707 @param EDX Upper 32-bits of MSR value.
3709 <b>Example usage</b>
3711 MSR_IA32_VMX_BASIC_REGISTER Msr;
3713 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);
3715 @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.
3717 #define MSR_IA32_VMX_BASIC 0x00000480
3720 MSR information returned for MSR index #MSR_IA32_VMX_BASIC
3724 /// Individual bit fields
3728 /// [Bits 30:0] VMCS revision identifier used by the processor. Processors
3729 /// that use the same VMCS revision identifier use the same size for VMCS
3730 /// regions (see subsequent item on bits 44:32).
3732 /// @note Earlier versions of this manual specified that the VMCS revision
3733 /// identifier was a 32-bit field in bits 31:0 of this MSR. For all
3734 /// processors produced prior to this change, bit 31 of this MSR was read
3737 UINT32 VmcsRevisonId
:31;
3738 UINT32 MustBeZero
:1;
3740 /// [Bit 44:32] Reports the number of bytes that software should allocate
3741 /// for the VMXON region and any VMCS region. It is a value greater than
3742 /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).
3747 /// [Bit 48] Indicates the width of the physical addresses that may be used
3748 /// for the VMXON region, each VMCS, and data structures referenced by
3749 /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX
3750 /// transitions). If the bit is 0, these addresses are limited to the
3751 /// processor's physical-address width. If the bit is 1, these addresses
3752 /// are limited to 32 bits. This bit is always 0 for processors that
3753 /// support Intel 64 architecture.
3755 /// @note On processors that support Intel 64 architecture, the pointer
3756 /// must not set bits beyond the processor's physical address width.
3758 UINT32 VmcsAddressWidth
:1;
3760 /// [Bit 49] If bit 49 is read as 1, the logical processor supports the
3761 /// dual-monitor treatment of system-management interrupts and
3762 /// system-management mode. See Section 34.15 for details of this treatment.
3764 UINT32 DualMonitor
:1;
3766 /// [Bit 53:50] report the memory type that should be used for the VMCS,
3767 /// for data structures referenced by pointers in the VMCS (I/O bitmaps,
3768 /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG
3769 /// header. If software needs to access these data structures (e.g., to
3770 /// modify the contents of the MSR bitmaps), it can configure the paging
3771 /// structures to map them into the linear-address space. If it does so,
3772 /// it should establish mappings that use the memory type reported bits
3773 /// 53:50 in this MSR.
3775 /// As of this writing, all processors that support VMX operation indicate
3776 /// the write-back type.
3778 /// If software needs to access these data structures (e.g., to modify
3779 /// the contents of the MSR bitmaps), it can configure the paging
3780 /// structures to map them into the linear-address space. If it does so,
3781 /// it should establish mappings that use the memory type reported in this
3784 /// @note Alternatively, software may map any of these regions or
3785 /// structures with the UC memory type. (This may be necessary for the MSEG
3786 /// header.) Doing so is discouraged unless necessary as it will cause the
3787 /// performance of software accesses to those structures to suffer.
3790 UINT32 MemoryType
:4;
3792 /// [Bit 54] If bit 54 is read as 1, the logical processor reports
3793 /// information in the VM-exit instruction-information field on VM exits
3794 /// due to execution of the INS and OUTS instructions. This reporting is
3795 /// done only if this bit is read as 1.
3797 UINT32 InsOutsReporting
:1;
3799 /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may
3800 /// be cleared to 0. See Appendix A.2 for details. It also reports support
3801 /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,
3802 /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and
3803 /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,
3804 /// Appendix A.4, and Appendix A.5 for details.
3806 UINT32 VmxControls
:1;
3810 /// All bit fields as a 64-bit value
3813 } MSR_IA32_VMX_BASIC_REGISTER
;
3816 /// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType
3818 #define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00
3819 #define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06
3826 Capability Reporting Register of Pinbased VM-execution Controls (R/O) See
3827 Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.
3829 @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481)
3830 @param EAX Lower 32-bits of MSR value.
3831 @param EDX Upper 32-bits of MSR value.
3833 <b>Example usage</b>
3837 Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);
3839 @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.
3841 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
3845 Capability Reporting Register of Primary Processor-based VM-execution
3846 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
3847 Controls.". If CPUID.01H:ECX.[5] = 1.
3849 @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)
3850 @param EAX Lower 32-bits of MSR value.
3851 @param EDX Upper 32-bits of MSR value.
3853 <b>Example usage</b>
3857 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);
3859 @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.
3861 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
3865 Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,
3866 "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.
3868 @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483)
3869 @param EAX Lower 32-bits of MSR value.
3870 @param EDX Upper 32-bits of MSR value.
3872 <b>Example usage</b>
3876 Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);
3878 @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.
3880 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
3884 Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,
3885 "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.
3887 @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484)
3888 @param EAX Lower 32-bits of MSR value.
3889 @param EDX Upper 32-bits of MSR value.
3891 <b>Example usage</b>
3895 Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);
3897 @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.
3899 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
3903 Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,
3904 "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.
3906 @param ECX MSR_IA32_VMX_MISC (0x00000485)
3907 @param EAX Lower 32-bits of MSR value.
3908 @param EDX Upper 32-bits of MSR value.
3910 <b>Example usage</b>
3912 IA32_VMX_MISC_REGISTER Msr;
3914 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);
3916 @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.
3918 #define MSR_IA32_VMX_MISC 0x00000485
3921 MSR information returned for MSR index #IA32_VMX_MISC
3925 /// Individual bit fields
3929 /// [Bits 4:0] Reports a value X that specifies the relationship between the
3930 /// rate of the VMX-preemption timer and that of the timestamp counter (TSC).
3931 /// Specifically, the VMX-preemption timer (if it is active) counts down by
3932 /// 1 every time bit X in the TSC changes due to a TSC increment.
3934 UINT32 VmxTimerRatio
:5;
3936 /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA
3937 /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more
3938 /// details. This bit is read as 1 on any logical processor that supports
3939 /// the 1-setting of the "unrestricted guest" VM-execution control.
3941 UINT32 VmExitEferLma
:1;
3943 /// [Bit 6] reports (if set) the support for activity state 1 (HLT).
3945 UINT32 HltActivityStateSupported
:1;
3947 /// [Bit 7] reports (if set) the support for activity state 2 (shutdown).
3949 UINT32 ShutdownActivityStateSupported
:1;
3951 /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).
3953 UINT32 WaitForSipiActivityStateSupported
:1;
3956 /// [Bit 15] If read as 1, the RDMSR instruction can be used in system-
3957 /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).
3958 /// See Section 34.15.6.4.
3960 UINT32 SmBaseMsrSupported
:1;
3962 /// [Bits 24:16] Indicate the number of CR3-target values supported by the
3963 /// processor. This number is a value between 0 and 256, inclusive (bit 24
3964 /// is set if and only if bits 23:16 are clear).
3966 UINT32 NumberOfCr3TargetValues
:9;
3968 /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum
3969 /// number of MSRs that should appear in the VM-exit MSR-store list, the
3970 /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if
3971 /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the
3972 /// recommended maximum number of MSRs to be included in each list. If the
3973 /// limit is exceeded, undefined processor behavior may result (including a
3974 /// machine check during the VMX transition).
3976 UINT32 MsrStoreListMaximum
:3;
3978 /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set
3979 /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1
3980 /// (see Section 34.14.4).
3982 UINT32 BlockSmiSupported
:1;
3984 /// [Bit 29] read as 1, software can use VMWRITE to write to any supported
3985 /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit
3986 /// information fields.
3988 UINT32 VmWriteSupported
:1;
3991 /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the
3994 UINT32 MsegRevisionIdentifier
:32;
3997 /// All bit fields as a 64-bit value
4000 } IA32_VMX_MISC_REGISTER
;
4004 Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,
4005 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
4007 @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486)
4008 @param EAX Lower 32-bits of MSR value.
4009 @param EDX Upper 32-bits of MSR value.
4011 <b>Example usage</b>
4015 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);
4017 @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.
4019 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
4023 Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,
4024 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
4026 @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487)
4027 @param EAX Lower 32-bits of MSR value.
4028 @param EDX Upper 32-bits of MSR value.
4030 <b>Example usage</b>
4034 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);
4036 @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.
4038 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
4042 Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,
4043 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
4045 @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488)
4046 @param EAX Lower 32-bits of MSR value.
4047 @param EDX Upper 32-bits of MSR value.
4049 <b>Example usage</b>
4053 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);
4055 @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.
4057 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
4061 Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,
4062 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
4064 @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489)
4065 @param EAX Lower 32-bits of MSR value.
4066 @param EDX Upper 32-bits of MSR value.
4068 <b>Example usage</b>
4072 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);
4074 @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.
4076 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
4080 Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix
4081 A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.
4083 @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A)
4084 @param EAX Lower 32-bits of MSR value.
4085 @param EDX Upper 32-bits of MSR value.
4087 <b>Example usage</b>
4091 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);
4093 @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.
4095 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048A
4099 Capability Reporting Register of Secondary Processor-based VM-execution
4100 Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution
4101 Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).
4103 @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)
4104 @param EAX Lower 32-bits of MSR value.
4105 @param EDX Upper 32-bits of MSR value.
4107 <b>Example usage</b>
4111 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);
4113 @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.
4115 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B
4119 Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,
4120 "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C
4121 TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).
4123 @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)
4124 @param EAX Lower 32-bits of MSR value.
4125 @param EDX Upper 32-bits of MSR value.
4127 <b>Example usage</b>
4131 Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);
4133 @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.
4135 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C
4139 Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)
4140 See Appendix A.3.1, "Pin-Based VMExecution Controls.". If (
4141 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4143 @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)
4144 @param EAX Lower 32-bits of MSR value.
4145 @param EDX Upper 32-bits of MSR value.
4147 <b>Example usage</b>
4151 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);
4153 @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.
4155 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D
4159 Capability Reporting Register of Primary Processor-based VM-execution Flex
4160 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
4161 Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4163 @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)
4164 @param EAX Lower 32-bits of MSR value.
4165 @param EDX Upper 32-bits of MSR value.
4167 <b>Example usage</b>
4171 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);
4173 @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.
4175 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E
4179 Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix
4180 A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4182 @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)
4183 @param EAX Lower 32-bits of MSR value.
4184 @param EDX Upper 32-bits of MSR value.
4186 <b>Example usage</b>
4190 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);
4192 @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.
4194 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F
4198 Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix
4199 A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4201 @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)
4202 @param EAX Lower 32-bits of MSR value.
4203 @param EDX Upper 32-bits of MSR value.
4205 <b>Example usage</b>
4209 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);
4211 @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.
4213 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
4217 Capability Reporting Register of VMfunction Controls (R/O). If(
4218 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4220 @param ECX MSR_IA32_VMX_VMFUNC (0x00000491)
4221 @param EAX Lower 32-bits of MSR value.
4222 @param EDX Upper 32-bits of MSR value.
4224 <b>Example usage</b>
4228 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);
4230 @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.
4232 #define MSR_IA32_VMX_VMFUNC 0x00000491
4236 Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&
4237 IA32_PERF_CAPABILITIES[ 13] = 1.
4239 @param ECX MSR_IA32_A_PMCn
4240 @param EAX Lower 32-bits of MSR value.
4241 @param EDX Upper 32-bits of MSR value.
4243 <b>Example usage</b>
4247 Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
4248 AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);
4250 @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM.
4251 MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM.
4252 MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM.
4253 MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM.
4254 MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM.
4255 MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM.
4256 MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM.
4257 MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.
4260 #define MSR_IA32_A_PMC0 0x000004C1
4261 #define MSR_IA32_A_PMC1 0x000004C2
4262 #define MSR_IA32_A_PMC2 0x000004C3
4263 #define MSR_IA32_A_PMC3 0x000004C4
4264 #define MSR_IA32_A_PMC4 0x000004C5
4265 #define MSR_IA32_A_PMC5 0x000004C6
4266 #define MSR_IA32_A_PMC6 0x000004C7
4267 #define MSR_IA32_A_PMC7 0x000004C8
4272 (R/W). If IA32_MCG_CAP.LMCE_P =1.
4274 @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0)
4275 @param EAX Lower 32-bits of MSR value.
4276 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
4277 @param EDX Upper 32-bits of MSR value.
4278 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
4280 <b>Example usage</b>
4282 MSR_IA32_MCG_EXT_CTL_REGISTER Msr;
4284 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);
4285 AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);
4287 @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.
4289 #define MSR_IA32_MCG_EXT_CTL 0x000004D0
4292 MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL
4296 /// Individual bit fields
4300 /// [Bit 0] LMCE_EN.
4303 UINT32 Reserved1
:31;
4304 UINT32 Reserved2
:32;
4307 /// All bit fields as a 32-bit value
4311 /// All bit fields as a 64-bit value
4314 } MSR_IA32_MCG_EXT_CTL_REGISTER
;
4318 Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,
4319 ECX=0H): EBX[2] = 1.
4321 @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500)
4322 @param EAX Lower 32-bits of MSR value.
4323 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
4324 @param EDX Upper 32-bits of MSR value.
4325 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
4327 <b>Example usage</b>
4329 MSR_IA32_SGX_SVN_STATUS_REGISTER Msr;
4331 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);
4333 @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.
4335 #define MSR_IA32_SGX_SVN_STATUS 0x00000500
4338 MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS
4342 /// Individual bit fields
4346 /// [Bit 0] Lock. See Section 42.12.3, "Interactions with Authenticated
4347 /// Code Modules (ACMs)".
4350 UINT32 Reserved1
:15;
4352 /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.12.3, "Interactions with
4353 /// Authenticated Code Modules (ACMs)".
4355 UINT32 SGX_SVN_SINIT
:8;
4357 UINT32 Reserved3
:32;
4360 /// All bit fields as a 32-bit value
4364 /// All bit fields as a 64-bit value
4367 } MSR_IA32_SGX_SVN_STATUS_REGISTER
;
4371 Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
4372 && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)
4375 @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)
4376 @param EAX Lower 32-bits of MSR value.
4377 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
4378 @param EDX Upper 32-bits of MSR value.
4379 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
4381 <b>Example usage</b>
4383 MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr;
4385 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
4386 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);
4388 @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.
4390 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
4393 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE
4397 /// Individual bit fields
4402 /// [Bits 31:7] Base physical address.
4406 /// [Bits 63:32] Base physical address.
4411 /// All bit fields as a 64-bit value
4414 } MSR_IA32_RTIT_OUTPUT_BASE_REGISTER
;
4418 Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,
4419 ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)
4420 (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).
4422 @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)
4423 @param EAX Lower 32-bits of MSR value.
4424 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
4425 @param EDX Upper 32-bits of MSR value.
4426 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
4428 <b>Example usage</b>
4430 MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr;
4432 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);
4433 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);
4435 @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.
4437 #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561
4440 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS
4444 /// Individual bit fields
4449 /// [Bits 31:7] MaskOrTableOffset.
4451 UINT32 MaskOrTableOffset
:25;
4453 /// [Bits 63:32] Output Offset.
4455 UINT32 OutputOffset
:32;
4458 /// All bit fields as a 64-bit value
4461 } MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER
;
4465 Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4467 @param ECX MSR_IA32_RTIT_CTL (0x00000570)
4468 @param EAX Lower 32-bits of MSR value.
4469 Described by the type MSR_IA32_RTIT_CTL_REGISTER.
4470 @param EDX Upper 32-bits of MSR value.
4471 Described by the type MSR_IA32_RTIT_CTL_REGISTER.
4473 <b>Example usage</b>
4475 MSR_IA32_RTIT_CTL_REGISTER Msr;
4477 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
4478 AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);
4480 @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.
4482 #define MSR_IA32_RTIT_CTL 0x00000570
4485 MSR information returned for MSR index #MSR_IA32_RTIT_CTL
4489 /// Individual bit fields
4493 /// [Bit 0] TraceEn.
4497 /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4510 /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).
4514 /// [Bit 7] CR3 filter.
4522 /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
4530 /// [Bit 11] DisRETC.
4535 /// [Bit 13] BranchEn.
4539 /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
4544 /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4549 /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4554 /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).
4558 /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).
4562 /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).
4566 /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).
4569 UINT32 Reserved6
:16;
4572 /// All bit fields as a 64-bit value
4575 } MSR_IA32_RTIT_CTL_REGISTER
;
4579 Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4581 @param ECX MSR_IA32_RTIT_STATUS (0x00000571)
4582 @param EAX Lower 32-bits of MSR value.
4583 Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
4584 @param EDX Upper 32-bits of MSR value.
4585 Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
4587 <b>Example usage</b>
4589 MSR_IA32_RTIT_STATUS_REGISTER Msr;
4591 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);
4592 AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);
4594 @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.
4596 #define MSR_IA32_RTIT_STATUS 0x00000571
4599 MSR information returned for MSR index #MSR_IA32_RTIT_STATUS
4603 /// Individual bit fields
4607 /// [Bit 0] FilterEn, (writes ignored).
4608 /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).
4612 /// [Bit 1] ContexEn, (writes ignored).
4616 /// [Bit 2] TriggerEn, (writes ignored).
4625 /// [Bit 5] Stopped.
4628 UINT32 Reserved2
:26;
4630 /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).
4632 UINT32 PacketByteCnt
:17;
4633 UINT32 Reserved3
:15;
4636 /// All bit fields as a 64-bit value
4639 } MSR_IA32_RTIT_STATUS_REGISTER
;
4643 Trace Filter CR3 Match Register (R/W).
4644 If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4646 @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572)
4647 @param EAX Lower 32-bits of MSR value.
4648 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
4649 @param EDX Upper 32-bits of MSR value.
4650 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
4652 <b>Example usage</b>
4654 MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr;
4656 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);
4657 AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);
4659 @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.
4661 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572
4664 MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH
4668 /// Individual bit fields
4673 /// [Bits 31:5] CR3[63:5] value to match.
4677 /// [Bits 63:32] CR3[63:5] value to match.
4682 /// All bit fields as a 64-bit value
4685 } MSR_IA32_RTIT_CR3_MATCH_REGISTER
;
4689 Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
4691 @param ECX MSR_IA32_RTIT_ADDRn_A
4692 @param EAX Lower 32-bits of MSR value.
4693 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4694 @param EDX Upper 32-bits of MSR value.
4695 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4697 <b>Example usage</b>
4699 MSR_IA32_RTIT_ADDR_REGISTER Msr;
4701 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);
4702 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);
4704 @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM.
4705 MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM.
4706 MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM.
4707 MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.
4710 #define MSR_IA32_RTIT_ADDR0_A 0x00000580
4711 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
4712 #define MSR_IA32_RTIT_ADDR2_A 0x00000584
4713 #define MSR_IA32_RTIT_ADDR3_A 0x00000586
4718 Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
4720 @param ECX MSR_IA32_RTIT_ADDRn_B
4721 @param EAX Lower 32-bits of MSR value.
4722 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4723 @param EDX Upper 32-bits of MSR value.
4724 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4726 <b>Example usage</b>
4728 MSR_IA32_RTIT_ADDR_REGISTER Msr;
4730 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);
4731 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);
4733 @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM.
4734 MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM.
4735 MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM.
4736 MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.
4739 #define MSR_IA32_RTIT_ADDR0_B 0x00000581
4740 #define MSR_IA32_RTIT_ADDR1_B 0x00000583
4741 #define MSR_IA32_RTIT_ADDR2_B 0x00000585
4742 #define MSR_IA32_RTIT_ADDR3_B 0x00000587
4747 MSR information returned for MSR indexes
4748 #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and
4749 #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B
4753 /// Individual bit fields
4757 /// [Bits 31:0] Virtual Address.
4759 UINT32 VirtualAddress
:32;
4761 /// [Bits 47:32] Virtual Address.
4763 UINT32 VirtualAddressHi
:16;
4765 /// [Bits 63:48] SignExt_VA.
4767 UINT32 SignExt_VA
:16;
4770 /// All bit fields as a 64-bit value
4773 } MSR_IA32_RTIT_ADDR_REGISTER
;
4777 DS Save Area (R/W) Points to the linear address of the first byte of the DS
4778 buffer management area, which is used to manage the BTS and PEBS buffers.
4779 See Section 18.12.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]
4782 [Bits 31..0] The linear address of the first byte of the DS buffer
4783 management area, if not in IA-32e mode.
4785 [Bits 63..0] The linear address of the first byte of the DS buffer
4786 management area, if IA-32e mode is active.
4788 @param ECX MSR_IA32_DS_AREA (0x00000600)
4789 @param EAX Lower 32-bits of MSR value.
4790 Described by the type MSR_IA32_DS_AREA_REGISTER.
4791 @param EDX Upper 32-bits of MSR value.
4792 Described by the type MSR_IA32_DS_AREA_REGISTER.
4794 <b>Example usage</b>
4798 Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);
4799 AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);
4801 @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.
4803 #define MSR_IA32_DS_AREA 0x00000600
4807 TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =
4810 @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0)
4811 @param EAX Lower 32-bits of MSR value.
4812 @param EDX Upper 32-bits of MSR value.
4814 <b>Example usage</b>
4818 Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);
4819 AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);
4821 @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.
4823 #define MSR_IA32_TSC_DEADLINE 0x000006E0
4827 Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.
4829 @param ECX MSR_IA32_PM_ENABLE (0x00000770)
4830 @param EAX Lower 32-bits of MSR value.
4831 Described by the type MSR_IA32_PM_ENABLE_REGISTER.
4832 @param EDX Upper 32-bits of MSR value.
4833 Described by the type MSR_IA32_PM_ENABLE_REGISTER.
4835 <b>Example usage</b>
4837 MSR_IA32_PM_ENABLE_REGISTER Msr;
4839 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);
4840 AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);
4842 @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.
4844 #define MSR_IA32_PM_ENABLE 0x00000770
4847 MSR information returned for MSR index #MSR_IA32_PM_ENABLE
4851 /// Individual bit fields
4855 /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If
4856 /// CPUID.06H:EAX.[7] = 1.
4858 UINT32 HWP_ENABLE
:1;
4859 UINT32 Reserved1
:31;
4860 UINT32 Reserved2
:32;
4863 /// All bit fields as a 32-bit value
4867 /// All bit fields as a 64-bit value
4870 } MSR_IA32_PM_ENABLE_REGISTER
;
4874 HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.
4876 @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771)
4877 @param EAX Lower 32-bits of MSR value.
4878 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
4879 @param EDX Upper 32-bits of MSR value.
4880 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
4882 <b>Example usage</b>
4884 MSR_IA32_HWP_CAPABILITIES_REGISTER Msr;
4886 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);
4888 @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.
4890 #define MSR_IA32_HWP_CAPABILITIES 0x00000771
4893 MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES
4897 /// Individual bit fields
4901 /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance
4902 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4904 UINT32 Highest_Performance
:8;
4906 /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP
4907 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4909 UINT32 Guaranteed_Performance
:8;
4911 /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP
4912 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4914 UINT32 Most_Efficient_Performance
:8;
4916 /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance
4917 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4919 UINT32 Lowest_Performance
:8;
4923 /// All bit fields as a 32-bit value
4927 /// All bit fields as a 64-bit value
4930 } MSR_IA32_HWP_CAPABILITIES_REGISTER
;
4934 Power Management Control Hints for All Logical Processors in a Package
4935 (R/W). If CPUID.06H:EAX.[11] = 1.
4937 @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772)
4938 @param EAX Lower 32-bits of MSR value.
4939 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
4940 @param EDX Upper 32-bits of MSR value.
4941 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
4943 <b>Example usage</b>
4945 MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr;
4947 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);
4948 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);
4950 @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.
4952 #define MSR_IA32_HWP_REQUEST_PKG 0x00000772
4955 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG
4959 /// Individual bit fields
4963 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
4964 /// CPUID.06H:EAX.[11] = 1.
4966 UINT32 Minimum_Performance
:8;
4968 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
4969 /// CPUID.06H:EAX.[11] = 1.
4971 UINT32 Maximum_Performance
:8;
4973 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
4974 /// If CPUID.06H:EAX.[11] = 1.
4976 UINT32 Desired_Performance
:8;
4978 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
4979 /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.
4981 UINT32 Energy_Performance_Preference
:8;
4983 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
4984 /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.
4986 UINT32 Activity_Window
:10;
4990 /// All bit fields as a 64-bit value
4993 } MSR_IA32_HWP_REQUEST_PKG_REGISTER
;
4997 Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.
4999 @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773)
5000 @param EAX Lower 32-bits of MSR value.
5001 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
5002 @param EDX Upper 32-bits of MSR value.
5003 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
5005 <b>Example usage</b>
5007 MSR_IA32_HWP_INTERRUPT_REGISTER Msr;
5009 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);
5010 AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);
5012 @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.
5014 #define MSR_IA32_HWP_INTERRUPT 0x00000773
5017 MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT
5021 /// Individual bit fields
5025 /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP
5026 /// Notifications". If CPUID.06H:EAX.[8] = 1.
5028 UINT32 EN_Guaranteed_Performance_Change
:1;
5030 /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".
5031 /// If CPUID.06H:EAX.[8] = 1.
5033 UINT32 EN_Excursion_Minimum
:1;
5034 UINT32 Reserved1
:30;
5035 UINT32 Reserved2
:32;
5038 /// All bit fields as a 32-bit value
5042 /// All bit fields as a 64-bit value
5045 } MSR_IA32_HWP_INTERRUPT_REGISTER
;
5049 Power Management Control Hints to a Logical Processor (R/W). If
5050 CPUID.06H:EAX.[7] = 1.
5052 @param ECX MSR_IA32_HWP_REQUEST (0x00000774)
5053 @param EAX Lower 32-bits of MSR value.
5054 Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
5055 @param EDX Upper 32-bits of MSR value.
5056 Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
5058 <b>Example usage</b>
5060 MSR_IA32_HWP_REQUEST_REGISTER Msr;
5062 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);
5063 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);
5065 @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.
5067 #define MSR_IA32_HWP_REQUEST 0x00000774
5070 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST
5074 /// Individual bit fields
5078 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
5079 /// CPUID.06H:EAX.[7] = 1.
5081 UINT32 Minimum_Performance
:8;
5083 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
5084 /// CPUID.06H:EAX.[7] = 1.
5086 UINT32 Maximum_Performance
:8;
5088 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
5089 /// If CPUID.06H:EAX.[7] = 1.
5091 UINT32 Desired_Performance
:8;
5093 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
5094 /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.
5096 UINT32 Energy_Performance_Preference
:8;
5098 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
5099 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.
5101 UINT32 Activity_Window
:10;
5103 /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If
5104 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.
5106 UINT32 Package_Control
:1;
5110 /// All bit fields as a 64-bit value
5113 } MSR_IA32_HWP_REQUEST_REGISTER
;
5117 Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If
5118 CPUID.06H:EAX.[7] = 1.
5120 @param ECX MSR_IA32_HWP_STATUS (0x00000777)
5121 @param EAX Lower 32-bits of MSR value.
5122 Described by the type MSR_IA32_HWP_STATUS_REGISTER.
5123 @param EDX Upper 32-bits of MSR value.
5124 Described by the type MSR_IA32_HWP_STATUS_REGISTER.
5126 <b>Example usage</b>
5128 MSR_IA32_HWP_STATUS_REGISTER Msr;
5130 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);
5131 AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);
5133 @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.
5135 #define MSR_IA32_HWP_STATUS 0x00000777
5138 MSR information returned for MSR index #MSR_IA32_HWP_STATUS
5142 /// Individual bit fields
5146 /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,
5147 /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.
5149 UINT32 Guaranteed_Performance_Change
:1;
5152 /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP
5153 /// Feedback". If CPUID.06H:EAX.[7] = 1.
5155 UINT32 Excursion_To_Minimum
:1;
5156 UINT32 Reserved2
:29;
5157 UINT32 Reserved3
:32;
5160 /// All bit fields as a 32-bit value
5164 /// All bit fields as a 64-bit value
5167 } MSR_IA32_HWP_STATUS_REGISTER
;
5171 x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1
5172 && IA32_APIC_BASE.[10] = 1.
5174 @param ECX MSR_IA32_X2APIC_APICID (0x00000802)
5175 @param EAX Lower 32-bits of MSR value.
5176 @param EDX Upper 32-bits of MSR value.
5178 <b>Example usage</b>
5182 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);
5184 @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.
5186 #define MSR_IA32_X2APIC_APICID 0x00000802
5190 x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5191 IA32_APIC_BASE.[10] = 1.
5193 @param ECX MSR_IA32_X2APIC_VERSION (0x00000803)
5194 @param EAX Lower 32-bits of MSR value.
5195 @param EDX Upper 32-bits of MSR value.
5197 <b>Example usage</b>
5201 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);
5203 @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.
5205 #define MSR_IA32_X2APIC_VERSION 0x00000803
5209 x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5210 IA32_APIC_BASE.[10] = 1.
5212 @param ECX MSR_IA32_X2APIC_TPR (0x00000808)
5213 @param EAX Lower 32-bits of MSR value.
5214 @param EDX Upper 32-bits of MSR value.
5216 <b>Example usage</b>
5220 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);
5221 AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);
5223 @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.
5225 #define MSR_IA32_X2APIC_TPR 0x00000808
5229 x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5230 IA32_APIC_BASE.[10] = 1.
5232 @param ECX MSR_IA32_X2APIC_PPR (0x0000080A)
5233 @param EAX Lower 32-bits of MSR value.
5234 @param EDX Upper 32-bits of MSR value.
5236 <b>Example usage</b>
5240 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);
5242 @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.
5244 #define MSR_IA32_X2APIC_PPR 0x0000080A
5248 x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]
5251 @param ECX MSR_IA32_X2APIC_EOI (0x0000080B)
5252 @param EAX Lower 32-bits of MSR value.
5253 @param EDX Upper 32-bits of MSR value.
5255 <b>Example usage</b>
5260 AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);
5262 @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.
5264 #define MSR_IA32_X2APIC_EOI 0x0000080B
5268 x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5269 IA32_APIC_BASE.[10] = 1.
5271 @param ECX MSR_IA32_X2APIC_LDR (0x0000080D)
5272 @param EAX Lower 32-bits of MSR value.
5273 @param EDX Upper 32-bits of MSR value.
5275 <b>Example usage</b>
5279 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);
5281 @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.
5283 #define MSR_IA32_X2APIC_LDR 0x0000080D
5287 x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1
5288 && IA32_APIC_BASE.[10] = 1.
5290 @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F)
5291 @param EAX Lower 32-bits of MSR value.
5292 @param EDX Upper 32-bits of MSR value.
5294 <b>Example usage</b>
5298 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);
5299 AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);
5301 @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.
5303 #define MSR_IA32_X2APIC_SIVR 0x0000080F
5307 x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).
5308 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5310 @param ECX MSR_IA32_X2APIC_ISRn
5311 @param EAX Lower 32-bits of MSR value.
5312 @param EDX Upper 32-bits of MSR value.
5314 <b>Example usage</b>
5318 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);
5320 @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM.
5321 MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM.
5322 MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM.
5323 MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM.
5324 MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM.
5325 MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM.
5326 MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM.
5327 MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.
5330 #define MSR_IA32_X2APIC_ISR0 0x00000810
5331 #define MSR_IA32_X2APIC_ISR1 0x00000811
5332 #define MSR_IA32_X2APIC_ISR2 0x00000812
5333 #define MSR_IA32_X2APIC_ISR3 0x00000813
5334 #define MSR_IA32_X2APIC_ISR4 0x00000814
5335 #define MSR_IA32_X2APIC_ISR5 0x00000815
5336 #define MSR_IA32_X2APIC_ISR6 0x00000816
5337 #define MSR_IA32_X2APIC_ISR7 0x00000817
5342 x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).
5343 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5345 @param ECX MSR_IA32_X2APIC_TMRn
5346 @param EAX Lower 32-bits of MSR value.
5347 @param EDX Upper 32-bits of MSR value.
5349 <b>Example usage</b>
5353 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);
5355 @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM.
5356 MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM.
5357 MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM.
5358 MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM.
5359 MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM.
5360 MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM.
5361 MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM.
5362 MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.
5365 #define MSR_IA32_X2APIC_TMR0 0x00000818
5366 #define MSR_IA32_X2APIC_TMR1 0x00000819
5367 #define MSR_IA32_X2APIC_TMR2 0x0000081A
5368 #define MSR_IA32_X2APIC_TMR3 0x0000081B
5369 #define MSR_IA32_X2APIC_TMR4 0x0000081C
5370 #define MSR_IA32_X2APIC_TMR5 0x0000081D
5371 #define MSR_IA32_X2APIC_TMR6 0x0000081E
5372 #define MSR_IA32_X2APIC_TMR7 0x0000081F
5377 x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).
5378 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5380 @param ECX MSR_IA32_X2APIC_IRRn
5381 @param EAX Lower 32-bits of MSR value.
5382 @param EDX Upper 32-bits of MSR value.
5384 <b>Example usage</b>
5388 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);
5390 @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM.
5391 MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM.
5392 MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM.
5393 MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM.
5394 MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM.
5395 MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM.
5396 MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM.
5397 MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.
5400 #define MSR_IA32_X2APIC_IRR0 0x00000820
5401 #define MSR_IA32_X2APIC_IRR1 0x00000821
5402 #define MSR_IA32_X2APIC_IRR2 0x00000822
5403 #define MSR_IA32_X2APIC_IRR3 0x00000823
5404 #define MSR_IA32_X2APIC_IRR4 0x00000824
5405 #define MSR_IA32_X2APIC_IRR5 0x00000825
5406 #define MSR_IA32_X2APIC_IRR6 0x00000826
5407 #define MSR_IA32_X2APIC_IRR7 0x00000827
5412 x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5413 IA32_APIC_BASE.[10] = 1.
5415 @param ECX MSR_IA32_X2APIC_ESR (0x00000828)
5416 @param EAX Lower 32-bits of MSR value.
5417 @param EDX Upper 32-bits of MSR value.
5419 <b>Example usage</b>
5423 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);
5424 AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);
5426 @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.
5428 #define MSR_IA32_X2APIC_ESR 0x00000828
5432 x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If
5433 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5435 @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)
5436 @param EAX Lower 32-bits of MSR value.
5437 @param EDX Upper 32-bits of MSR value.
5439 <b>Example usage</b>
5443 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);
5444 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);
5446 @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.
5448 #define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F
5452 x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5453 IA32_APIC_BASE.[10] = 1.
5455 @param ECX MSR_IA32_X2APIC_ICR (0x00000830)
5456 @param EAX Lower 32-bits of MSR value.
5457 @param EDX Upper 32-bits of MSR value.
5459 <b>Example usage</b>
5463 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);
5464 AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);
5466 @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.
5468 #define MSR_IA32_X2APIC_ICR 0x00000830
5472 x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5473 IA32_APIC_BASE.[10] = 1.
5475 @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832)
5476 @param EAX Lower 32-bits of MSR value.
5477 @param EDX Upper 32-bits of MSR value.
5479 <b>Example usage</b>
5483 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);
5484 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);
5486 @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.
5488 #define MSR_IA32_X2APIC_LVT_TIMER 0x00000832
5492 x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =
5493 1 && IA32_APIC_BASE.[10] = 1.
5495 @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)
5496 @param EAX Lower 32-bits of MSR value.
5497 @param EDX Upper 32-bits of MSR value.
5499 <b>Example usage</b>
5503 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);
5504 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);
5506 @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.
5508 #define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833
5512 x2APIC LVT Performance Monitor Interrupt Register (R/W). If
5513 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5515 @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834)
5516 @param EAX Lower 32-bits of MSR value.
5517 @param EDX Upper 32-bits of MSR value.
5519 <b>Example usage</b>
5523 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);
5524 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);
5526 @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.
5528 #define MSR_IA32_X2APIC_LVT_PMI 0x00000834
5532 x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5533 IA32_APIC_BASE.[10] = 1.
5535 @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)
5536 @param EAX Lower 32-bits of MSR value.
5537 @param EDX Upper 32-bits of MSR value.
5539 <b>Example usage</b>
5543 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);
5544 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);
5546 @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.
5548 #define MSR_IA32_X2APIC_LVT_LINT0 0x00000835
5552 x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5553 IA32_APIC_BASE.[10] = 1.
5555 @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)
5556 @param EAX Lower 32-bits of MSR value.
5557 @param EDX Upper 32-bits of MSR value.
5559 <b>Example usage</b>
5563 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);
5564 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);
5566 @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.
5568 #define MSR_IA32_X2APIC_LVT_LINT1 0x00000836
5572 x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5573 IA32_APIC_BASE.[10] = 1.
5575 @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837)
5576 @param EAX Lower 32-bits of MSR value.
5577 @param EDX Upper 32-bits of MSR value.
5579 <b>Example usage</b>
5583 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);
5584 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);
5586 @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.
5588 #define MSR_IA32_X2APIC_LVT_ERROR 0x00000837
5592 x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5593 IA32_APIC_BASE.[10] = 1.
5595 @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838)
5596 @param EAX Lower 32-bits of MSR value.
5597 @param EDX Upper 32-bits of MSR value.
5599 <b>Example usage</b>
5603 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);
5604 AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);
5606 @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.
5608 #define MSR_IA32_X2APIC_INIT_COUNT 0x00000838
5612 x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5613 IA32_APIC_BASE.[10] = 1.
5615 @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839)
5616 @param EAX Lower 32-bits of MSR value.
5617 @param EDX Upper 32-bits of MSR value.
5619 <b>Example usage</b>
5623 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);
5625 @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.
5627 #define MSR_IA32_X2APIC_CUR_COUNT 0x00000839
5631 x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5632 IA32_APIC_BASE.[10] = 1.
5634 @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E)
5635 @param EAX Lower 32-bits of MSR value.
5636 @param EDX Upper 32-bits of MSR value.
5638 <b>Example usage</b>
5642 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);
5643 AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);
5645 @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.
5647 #define MSR_IA32_X2APIC_DIV_CONF 0x0000083E
5651 x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&
5652 IA32_APIC_BASE.[10] = 1.
5654 @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F)
5655 @param EAX Lower 32-bits of MSR value.
5656 @param EDX Upper 32-bits of MSR value.
5658 <b>Example usage</b>
5663 AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);
5665 @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.
5667 #define MSR_IA32_X2APIC_SELF_IPI 0x0000083F
5671 Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.
5673 @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80)
5674 @param EAX Lower 32-bits of MSR value.
5675 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
5676 @param EDX Upper 32-bits of MSR value.
5677 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
5679 <b>Example usage</b>
5681 MSR_IA32_DEBUG_INTERFACE_REGISTER Msr;
5683 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);
5684 AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);
5686 @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.
5688 #define MSR_IA32_DEBUG_INTERFACE 0x00000C80
5691 MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE
5695 /// Individual bit fields
5699 /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.
5700 /// Default is 0. If CPUID.01H:ECX.[11] = 1.
5703 UINT32 Reserved1
:29;
5705 /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The
5706 /// lock bit is set automatically on the first SMI assertion even if not
5707 /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.
5711 /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to
5712 /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.
5714 UINT32 DebugOccurred
:1;
5715 UINT32 Reserved2
:32;
5718 /// All bit fields as a 32-bit value
5722 /// All bit fields as a 64-bit value
5725 } MSR_IA32_DEBUG_INTERFACE_REGISTER
;
5729 L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).
5731 @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81)
5732 @param EAX Lower 32-bits of MSR value.
5733 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
5734 @param EDX Upper 32-bits of MSR value.
5735 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
5737 <b>Example usage</b>
5739 MSR_IA32_L3_QOS_CFG_REGISTER Msr;
5741 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);
5742 AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);
5744 @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.
5746 #define MSR_IA32_L3_QOS_CFG 0x00000C81
5749 MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG
5753 /// Individual bit fields
5757 /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate
5758 /// in Code and Data Prioritization (CDP) mode.
5761 UINT32 Reserved1
:31;
5762 UINT32 Reserved2
:32;
5765 /// All bit fields as a 32-bit value
5769 /// All bit fields as a 64-bit value
5772 } MSR_IA32_L3_QOS_CFG_REGISTER
;
5776 Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]
5779 @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D)
5780 @param EAX Lower 32-bits of MSR value.
5781 Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
5782 @param EDX Upper 32-bits of MSR value.
5783 Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
5785 <b>Example usage</b>
5787 MSR_IA32_QM_EVTSEL_REGISTER Msr;
5789 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);
5790 AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);
5792 @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
5794 #define MSR_IA32_QM_EVTSEL 0x00000C8D
5797 MSR information returned for MSR index #MSR_IA32_QM_EVTSEL
5801 /// Individual bit fields
5805 /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via
5811 /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to
5812 /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (
5813 /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
5815 UINT32 ResourceMonitoringID
:32;
5818 /// All bit fields as a 64-bit value
5821 } MSR_IA32_QM_EVTSEL_REGISTER
;
5825 Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1
5828 @param ECX MSR_IA32_QM_CTR (0x00000C8E)
5829 @param EAX Lower 32-bits of MSR value.
5830 Described by the type MSR_IA32_QM_CTR_REGISTER.
5831 @param EDX Upper 32-bits of MSR value.
5832 Described by the type MSR_IA32_QM_CTR_REGISTER.
5834 <b>Example usage</b>
5836 MSR_IA32_QM_CTR_REGISTER Msr;
5838 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);
5840 @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.
5842 #define MSR_IA32_QM_CTR 0x00000C8E
5845 MSR information returned for MSR index #MSR_IA32_QM_CTR
5849 /// Individual bit fields
5853 /// [Bits 31:0] Resource Monitored Data.
5855 UINT32 ResourceMonitoredData
:32;
5857 /// [Bits 61:32] Resource Monitored Data.
5859 UINT32 ResourceMonitoredDataHi
:30;
5861 /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not
5862 /// available or not monitored for this resource or RMID.
5864 UINT32 Unavailable
:1;
5866 /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was
5867 /// written to IA32_PQR_QM_EVTSEL.
5872 /// All bit fields as a 64-bit value
5875 } MSR_IA32_QM_CTR_REGISTER
;
5879 Resource Association Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] =
5882 @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)
5883 @param EAX Lower 32-bits of MSR value.
5884 Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
5885 @param EDX Upper 32-bits of MSR value.
5886 Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
5888 <b>Example usage</b>
5890 MSR_IA32_PQR_ASSOC_REGISTER Msr;
5892 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);
5893 AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);
5895 @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
5897 #define MSR_IA32_PQR_ASSOC 0x00000C8F
5900 MSR information returned for MSR index #MSR_IA32_PQR_ASSOC
5904 /// Individual bit fields
5908 /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware
5909 /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`
5910 /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
5912 UINT32 ResourceMonitoringID
:32;
5914 /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on
5915 /// writes); returns the current COS when read. If ( CPUID.(EAX=07H,
5916 /// ECX=0):EBX.[15] = 1 ).
5921 /// All bit fields as a 64-bit value
5924 } MSR_IA32_PQR_ASSOC_REGISTER
;
5928 Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,
5929 ECX=0H):EBX[14] = 1).
5931 @param ECX MSR_IA32_BNDCFGS (0x00000D90)
5932 @param EAX Lower 32-bits of MSR value.
5933 Described by the type MSR_IA32_BNDCFGS_REGISTER.
5934 @param EDX Upper 32-bits of MSR value.
5935 Described by the type MSR_IA32_BNDCFGS_REGISTER.
5937 <b>Example usage</b>
5939 MSR_IA32_BNDCFGS_REGISTER Msr;
5941 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);
5942 AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);
5944 @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.
5946 #define MSR_IA32_BNDCFGS 0x00000D90
5949 MSR information returned for MSR index #MSR_IA32_BNDCFGS
5953 /// Individual bit fields
5957 /// [Bit 0] EN: Enable Intel MPX in supervisor mode.
5961 /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch
5962 /// instructions in the absence of the BND prefix.
5964 UINT32 BNDPRESERVE
:1;
5967 /// [Bits 31:12] Base Address of Bound Directory.
5971 /// [Bits 63:32] Base Address of Bound Directory.
5976 /// All bit fields as a 64-bit value
5979 } MSR_IA32_BNDCFGS_REGISTER
;
5983 Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.
5985 @param ECX MSR_IA32_XSS (0x00000DA0)
5986 @param EAX Lower 32-bits of MSR value.
5987 Described by the type MSR_IA32_XSS_REGISTER.
5988 @param EDX Upper 32-bits of MSR value.
5989 Described by the type MSR_IA32_XSS_REGISTER.
5991 <b>Example usage</b>
5993 MSR_IA32_XSS_REGISTER Msr;
5995 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);
5996 AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);
5998 @note MSR_IA32_XSS is defined as IA32_XSS in SDM.
6000 #define MSR_IA32_XSS 0x00000DA0
6003 MSR information returned for MSR index #MSR_IA32_XSS
6007 /// Individual bit fields
6012 /// [Bit 8] Trace Packet Configuration State (R/W).
6014 UINT32 TracePacketConfigurationState
:1;
6015 UINT32 Reserved2
:23;
6016 UINT32 Reserved3
:32;
6019 /// All bit fields as a 32-bit value
6023 /// All bit fields as a 64-bit value
6026 } MSR_IA32_XSS_REGISTER
;
6030 Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.
6032 @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0)
6033 @param EAX Lower 32-bits of MSR value.
6034 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
6035 @param EDX Upper 32-bits of MSR value.
6036 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
6038 <b>Example usage</b>
6040 MSR_IA32_PKG_HDC_CTL_REGISTER Msr;
6042 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);
6043 AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);
6045 @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.
6047 #define MSR_IA32_PKG_HDC_CTL 0x00000DB0
6050 MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL
6054 /// Individual bit fields
6058 /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled
6059 /// logical processors in the package. See Section 14.5.2, "Package level
6060 /// Enabling HDC". If CPUID.06H:EAX.[13] = 1.
6062 UINT32 HDC_Pkg_Enable
:1;
6063 UINT32 Reserved1
:31;
6064 UINT32 Reserved2
:32;
6067 /// All bit fields as a 32-bit value
6071 /// All bit fields as a 64-bit value
6074 } MSR_IA32_PKG_HDC_CTL_REGISTER
;
6078 Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.
6080 @param ECX MSR_IA32_PM_CTL1 (0x00000DB1)
6081 @param EAX Lower 32-bits of MSR value.
6082 Described by the type MSR_IA32_PM_CTL1_REGISTER.
6083 @param EDX Upper 32-bits of MSR value.
6084 Described by the type MSR_IA32_PM_CTL1_REGISTER.
6086 <b>Example usage</b>
6088 MSR_IA32_PM_CTL1_REGISTER Msr;
6090 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);
6091 AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);
6093 @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.
6095 #define MSR_IA32_PM_CTL1 0x00000DB1
6098 MSR information returned for MSR index #MSR_IA32_PM_CTL1
6102 /// Individual bit fields
6106 /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for
6107 /// package level HDC control. See Section 14.5.3.
6108 /// If CPUID.06H:EAX.[13] = 1.
6110 UINT32 HDC_Allow_Block
:1;
6111 UINT32 Reserved1
:31;
6112 UINT32 Reserved2
:32;
6115 /// All bit fields as a 32-bit value
6119 /// All bit fields as a 64-bit value
6122 } MSR_IA32_PM_CTL1_REGISTER
;
6126 Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.
6127 Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical
6128 processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.
6130 @param ECX MSR_IA32_THREAD_STALL (0x00000DB2)
6131 @param EAX Lower 32-bits of MSR value.
6132 @param EDX Upper 32-bits of MSR value.
6134 <b>Example usage</b>
6138 Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);
6140 @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.
6142 #define MSR_IA32_THREAD_STALL 0x00000DB2
6146 Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]
6147 CPUID.80000001H:EDX.[2 9]).
6149 @param ECX MSR_IA32_EFER (0xC0000080)
6150 @param EAX Lower 32-bits of MSR value.
6151 Described by the type MSR_IA32_EFER_REGISTER.
6152 @param EDX Upper 32-bits of MSR value.
6153 Described by the type MSR_IA32_EFER_REGISTER.
6155 <b>Example usage</b>
6157 MSR_IA32_EFER_REGISTER Msr;
6159 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
6160 AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);
6162 @note MSR_IA32_EFER is defined as IA32_EFER in SDM.
6164 #define MSR_IA32_EFER 0xC0000080
6167 MSR information returned for MSR index #MSR_IA32_EFER
6171 /// Individual bit fields
6175 /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET
6176 /// instructions in 64-bit mode.
6181 /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode
6187 /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode
6188 /// is active when set.
6192 /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).
6195 UINT32 Reserved3
:20;
6196 UINT32 Reserved4
:32;
6199 /// All bit fields as a 32-bit value
6203 /// All bit fields as a 64-bit value
6206 } MSR_IA32_EFER_REGISTER
;
6210 System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
6212 @param ECX MSR_IA32_STAR (0xC0000081)
6213 @param EAX Lower 32-bits of MSR value.
6214 @param EDX Upper 32-bits of MSR value.
6216 <b>Example usage</b>
6220 Msr = AsmReadMsr64 (MSR_IA32_STAR);
6221 AsmWriteMsr64 (MSR_IA32_STAR, Msr);
6223 @note MSR_IA32_STAR is defined as IA32_STAR in SDM.
6225 #define MSR_IA32_STAR 0xC0000081
6229 IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
6231 @param ECX MSR_IA32_LSTAR (0xC0000082)
6232 @param EAX Lower 32-bits of MSR value.
6233 @param EDX Upper 32-bits of MSR value.
6235 <b>Example usage</b>
6239 Msr = AsmReadMsr64 (MSR_IA32_LSTAR);
6240 AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);
6242 @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.
6244 #define MSR_IA32_LSTAR 0xC0000082
6248 System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.
6250 @param ECX MSR_IA32_FMASK (0xC0000084)
6251 @param EAX Lower 32-bits of MSR value.
6252 @param EDX Upper 32-bits of MSR value.
6254 <b>Example usage</b>
6258 Msr = AsmReadMsr64 (MSR_IA32_FMASK);
6259 AsmWriteMsr64 (MSR_IA32_FMASK, Msr);
6261 @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.
6263 #define MSR_IA32_FMASK 0xC0000084
6267 Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.
6269 @param ECX MSR_IA32_FS_BASE (0xC0000100)
6270 @param EAX Lower 32-bits of MSR value.
6271 @param EDX Upper 32-bits of MSR value.
6273 <b>Example usage</b>
6277 Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);
6278 AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);
6280 @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.
6282 #define MSR_IA32_FS_BASE 0xC0000100
6286 Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
6288 @param ECX MSR_IA32_GS_BASE (0xC0000101)
6289 @param EAX Lower 32-bits of MSR value.
6290 @param EDX Upper 32-bits of MSR value.
6292 <b>Example usage</b>
6296 Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);
6297 AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);
6299 @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.
6301 #define MSR_IA32_GS_BASE 0xC0000101
6305 Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
6307 @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102)
6308 @param EAX Lower 32-bits of MSR value.
6309 @param EDX Upper 32-bits of MSR value.
6311 <b>Example usage</b>
6315 Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);
6316 AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);
6318 @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.
6320 #define MSR_IA32_KERNEL_GS_BASE 0xC0000102
6324 Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.
6326 @param ECX MSR_IA32_TSC_AUX (0xC0000103)
6327 @param EAX Lower 32-bits of MSR value.
6328 Described by the type MSR_IA32_TSC_AUX_REGISTER.
6329 @param EDX Upper 32-bits of MSR value.
6330 Described by the type MSR_IA32_TSC_AUX_REGISTER.
6332 <b>Example usage</b>
6334 MSR_IA32_TSC_AUX_REGISTER Msr;
6336 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);
6337 AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);
6339 @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.
6341 #define MSR_IA32_TSC_AUX 0xC0000103
6344 MSR information returned for MSR index #MSR_IA32_TSC_AUX
6348 /// Individual bit fields
6352 /// [Bits 31:0] AUX: Auxiliary signature of TSC.
6358 /// All bit fields as a 32-bit value
6362 /// All bit fields as a 64-bit value
6365 } MSR_IA32_TSC_AUX_REGISTER
;