2 CPUID leaf definitions.
4 Provides defines for CPUID leaf indexes. Data structures are provided for
5 registers returned by a CPUID leaf that contain one or more bit fields.
6 If a register returned is a single 32-bit value, then a data structure is
7 not provided for that register.
9 Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,
14 November 2018, CPUID instruction.
22 CPUID Signature Information
24 @param EAX CPUID_SIGNATURE (0x00)
26 @retval EAX Returns the highest value the CPUID instruction recognizes for
27 returning basic processor information. The value is returned is
29 @retval EBX First 4 characters of a vendor identification string.
30 @retval ECX Last 4 characters of a vendor identification string.
31 @retval EDX Middle 4 characters of a vendor identification string.
40 AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
43 #define CPUID_SIGNATURE 0x00
46 /// @{ CPUID signature values returned by Intel processors
48 #define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u')
49 #define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I')
50 #define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l')
57 CPUID Version Information
59 @param EAX CPUID_VERSION_INFO (0x01)
61 @retval EAX Returns Model, Family, Stepping Information described by the
62 type CPUID_VERSION_INFO_EAX.
63 @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by
64 the type CPUID_VERSION_INFO_EBX.
65 @retval ECX CPU Feature Information described by the type
66 CPUID_VERSION_INFO_ECX.
67 @retval EDX CPU Feature Information described by the type
68 CPUID_VERSION_INFO_EDX.
72 CPUID_VERSION_INFO_EAX Eax;
73 CPUID_VERSION_INFO_EBX Ebx;
74 CPUID_VERSION_INFO_ECX Ecx;
75 CPUID_VERSION_INFO_EDX Edx;
77 AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
80 #define CPUID_VERSION_INFO 0x01
83 CPUID Version Information returned in EAX for CPUID leaf
88 /// Individual bit fields
91 UINT32 SteppingId
:4; ///< [Bits 3:0] Stepping ID
92 UINT32 Model
:4; ///< [Bits 7:4] Model
93 UINT32 FamilyId
:4; ///< [Bits 11:8] Family
94 UINT32 ProcessorType
:2; ///< [Bits 13:12] Processor Type
95 UINT32 Reserved1
:2; ///< [Bits 15:14] Reserved
96 UINT32 ExtendedModelId
:4; ///< [Bits 19:16] Extended Model ID
97 UINT32 ExtendedFamilyId
:8; ///< [Bits 27:20] Extended Family ID
98 UINT32 Reserved2
:4; ///< Reserved
101 /// All bit fields as a 32-bit value
104 } CPUID_VERSION_INFO_EAX
;
107 /// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType
109 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00
110 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01
111 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02
117 CPUID Version Information returned in EBX for CPUID leaf
122 /// Individual bit fields
126 /// [Bits 7:0] Provides an entry into a brand string table that contains
127 /// brand strings for IA-32 processors.
131 /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH
132 /// and CLFLUSHOPT instructions in 8-byte increments. This field was
133 /// introduced in the Pentium 4 processor.
135 UINT32 CacheLineSize
:8;
137 /// [Bits 23:16] Maximum number of addressable IDs for logical processors
138 /// in this physical package.
141 /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is
142 /// the number of unique initial APICIDs reserved for addressing different
143 /// logical processors in a physical package. This field is only valid if
144 /// CPUID.1.EDX.HTT[bit 28]= 1.
146 UINT32 MaximumAddressableIdsForLogicalProcessors
:8;
148 /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the
149 /// processor during power up. This field was introduced in the Pentium 4
152 UINT32 InitialLocalApicId
:8;
155 /// All bit fields as a 32-bit value
158 } CPUID_VERSION_INFO_EBX
;
161 CPUID Version Information returned in ECX for CPUID leaf
166 /// Individual bit fields
170 /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the
171 /// processor supports this technology
175 /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ
176 /// instruction. Carryless Multiplication
180 /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports
181 /// DS area using 64-bit layout.
185 /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports
190 /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor
191 /// supports the extensions to the Debug Store feature to allow for branch
192 /// message storage qualified by CPL
196 /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the
197 /// processor supports this technology.
201 /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor
202 /// supports this technology
206 /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates
207 /// that the processor supports this technology
211 /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor
212 /// supports this technology
216 /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming
217 /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction
218 /// extensions are not present in the processor.
222 /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode
223 /// can be set to either adaptive mode or shared mode. A value of 0 indicates
224 /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR
225 /// Bit 24 (L1 Data Cache Context Mode) for details
229 /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE
230 /// MSR for silicon debug
234 /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple
235 /// Add) extensions using YMM state.
239 /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature
244 /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor
245 /// supports changing IA32_MISC_ENABLE[Bit 23].
247 UINT32 xTPR_Update_Control
:1;
249 /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the
250 /// processor supports the performance and debug feature indication MSR
251 /// IA32_PERF_CAPABILITIES.
256 /// [Bit 17] Process-context identifiers. A value of 1 indicates that the
257 /// processor supports PCIDs and that software may set CR4.PCIDE to 1.
261 /// [Bit 18] A value of 1 indicates the processor supports the ability to
262 /// prefetch data from a memory mapped device. Direct Cache Access.
266 /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.
270 /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.
274 /// [Bit 21] A value of 1 indicates that the processor supports x2APIC
279 /// [Bit 22] A value of 1 indicates that the processor supports MOVBE
284 /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT
289 /// [Bit 24] A value of 1 indicates that the processor's local APIC timer
290 /// supports one-shot operation using a TSC deadline value.
292 UINT32 TSC_Deadline
:1;
294 /// [Bit 25] A value of 1 indicates that the processor supports the AESNI
295 /// instruction extensions.
299 /// [Bit 26] A value of 1 indicates that the processor supports the
300 /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV
301 /// instructions, and XCR0.
305 /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]
306 /// to enable XSETBV/XGETBV instructions to access XCR0 and to support
307 /// processor extended state management using XSAVE/XRSTOR.
311 /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction
316 /// [Bit 29] A value of 1 indicates that processor supports 16-bit
317 /// floating-point conversion instructions.
321 /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.
325 /// [Bit 31] Always returns 0.
330 /// All bit fields as a 32-bit value
333 } CPUID_VERSION_INFO_ECX
;
336 CPUID Version Information returned in EDX for CPUID leaf
341 /// Individual bit fields
345 /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.
349 /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,
350 /// including CR4.VME for controlling the feature, CR4.PVI for protected
351 /// mode virtual interrupts, software interrupt indirection, expansion of
352 /// the TSS with the software indirection bitmap, and EFLAGS.VIF and
353 /// EFLAGS.VIP flags.
357 /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including
358 /// CR4.DE for controlling the feature, and optional trapping of accesses to
363 /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,
364 /// including CR4.PSE for controlling the feature, the defined dirty bit in
365 /// PDE (Page Directory Entries), optional reserved bit trapping in CR3,
370 /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,
371 /// including CR4.TSD for controlling privilege.
375 /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The
376 /// RDMSR and WRMSR instructions are supported. Some of the MSRs are
377 /// implementation dependent.
381 /// [Bit 6] Physical Address Extension. Physical addresses greater than 32
382 /// bits are supported: extended page table entry formats, an extra level in
383 /// the page translation tables is defined, 2-MByte pages are supported
384 /// instead of 4 Mbyte pages if PAE bit is 1.
388 /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine
389 /// Checks, including CR4.MCE for controlling the feature. This feature does
390 /// not define the model-specific implementations of machine-check error
391 /// logging, reporting, and processor shutdowns. Machine Check exception
392 /// handlers may have to depend on processor version to do model specific
393 /// processing of the exception, or test for the presence of the Machine
398 /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)
399 /// instruction is supported (implicitly locked and atomic).
403 /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable
404 /// Interrupt Controller (APIC), responding to memory mapped commands in the
405 /// physical address range FFFE0000H to FFFE0FFFH (by default - some
406 /// processors permit the APIC to be relocated).
411 /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT
412 /// and associated MSRs are supported.
416 /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap
417 /// MSR contains feature bits that describe what memory types are supported,
418 /// how many variable MTRRs are supported, and whether fixed MTRRs are
423 /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure
424 /// entries that map a page, indicating TLB entries that are common to
425 /// different processes and need not be flushed. The CR4.PGE bit controls
430 /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine
431 /// Check Architecture of reporting machine errors is supported. The MCG_CAP
432 /// MSR contains feature bits describing how many banks of error reporting
433 /// MSRs are supported.
437 /// [Bit 15] Conditional Move Instructions. The conditional move instruction
438 /// CMOV is supported. In addition, if x87 FPU is present as indicated by the
439 /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.
443 /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This
444 /// feature augments the Memory Type Range Registers (MTRRs), allowing an
445 /// operating system to specify attributes of memory accessed through a
446 /// linear address on a 4KB granularity.
450 /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical
451 /// memory beyond 4 GBytes are supported with 32-bit paging. This feature
452 /// indicates that upper bits of the physical address of a 4-MByte page are
453 /// encoded in bits 20:13 of the page-directory entry. Such physical
454 /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.
458 /// [Bit 18] Processor Serial Number. The processor supports the 96-bit
459 /// processor identification number feature and the feature is enabled.
463 /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.
468 /// [Bit 21] Debug Store. The processor supports the ability to write debug
469 /// information into a memory resident buffer. This feature is used by the
470 /// branch trace store (BTS) and precise event-based sampling (PEBS)
475 /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The
476 /// processor implements internal MSRs that allow processor temperature to
477 /// be monitored and processor performance to be modulated in predefined
478 /// duty cycles under software control.
482 /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX
487 /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR
488 /// instructions are supported for fast save and restore of the floating
489 /// point context. Presence of this bit also indicates that CR4.OSFXSR is
490 /// available for an operating system to indicate that it supports the
491 /// FXSAVE and FXRSTOR instructions.
495 /// [Bit 25] SSE. The processor supports the SSE extensions.
499 /// [Bit 26] SSE2. The processor supports the SSE2 extensions.
503 /// [Bit 27] Self Snoop. The processor supports the management of
504 /// conflicting memory types by performing a snoop of its own cache
505 /// structure for transactions issued to the bus.
509 /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT
510 /// indicates there is only a single logical processor in the package and
511 /// software should assume only a single APIC ID is reserved. A value of 1
512 /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of
513 /// addressable IDs for logical processors in this package) is valid for the
518 /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor
519 /// automatic thermal control circuitry (TCC).
524 /// [Bit 31] Pending Break Enable. The processor supports the use of the
525 /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is
526 /// asserted) to signal the processor that an interrupt is pending and that
527 /// the processor should return to normal operation to handle the interrupt.
528 /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.
533 /// All bit fields as a 32-bit value
536 } CPUID_VERSION_INFO_EDX
;
540 CPUID Cache and TLB Information
542 @param EAX CPUID_CACHE_INFO (0x02)
544 @retval EAX Cache and TLB Information described by the type
545 CPUID_CACHE_INFO_CACHE_TLB.
546 CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns
547 0x01 and must be ignored. Only valid if
548 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
549 @retval EBX Cache and TLB Information described by the type
550 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
551 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
552 @retval ECX Cache and TLB Information described by the type
553 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
554 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
555 @retval EDX Cache and TLB Information described by the type
556 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
557 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
561 CPUID_CACHE_INFO_CACHE_TLB Eax;
562 CPUID_CACHE_INFO_CACHE_TLB Ebx;
563 CPUID_CACHE_INFO_CACHE_TLB Ecx;
564 CPUID_CACHE_INFO_CACHE_TLB Edx;
566 AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
569 <b>Cache Descriptor values</b>
571 <tr><th>Value </th><th> Type </th><th> Description </th></tr>
572 <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr>
573 <tr><td> 0x01 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr>
574 <tr><td> 0x02 </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr>
575 <tr><td> 0x03 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr>
576 <tr><td> 0x04 </td><td> TLB </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr>
577 <tr><td> 0x05 </td><td> TLB </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr>
578 <tr><td> 0x06 </td><td> Cache </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative,
579 32 byte line size</td></tr>
580 <tr><td> 0x08 </td><td> Cache </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative,
581 32 byte line size</td></tr>
582 <tr><td> 0x09 </td><td> Cache </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative,
583 64 byte line size</td></tr>
584 <tr><td> 0x0A </td><td> Cache </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr>
585 <tr><td> 0x0B </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr>
586 <tr><td> 0x0C </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr>
587 <tr><td> 0x0D </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr>
588 <tr><td> 0x0E </td><td> Cache </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr>
589 <tr><td> 0x1D </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr>
590 <tr><td> 0x21 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr>
591 <tr><td> 0x22 </td><td> Cache </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size,
592 2 lines per sector</td></tr>
593 <tr><td> 0x23 </td><td> Cache </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size,
594 2 lines per sector</td></tr>
595 <tr><td> 0x24 </td><td> Cache </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr>
596 <tr><td> 0x25 </td><td> Cache </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size,
597 2 lines per sector</td></tr>
598 <tr><td> 0x29 </td><td> Cache </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size,
599 2 lines per sector</td></tr>
600 <tr><td> 0x2C </td><td> Cache </td><td> 1st-level data cache: 32 KBytes, 8-way set associative,
601 64 byte line size</td></tr>
602 <tr><td> 0x30 </td><td> Cache </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative,
603 64 byte line size</td></tr>
604 <tr><td> 0x40 </td><td> Cache </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache,
605 no 3rd-level cache</td></tr>
606 <tr><td> 0x41 </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr>
607 <tr><td> 0x42 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr>
608 <tr><td> 0x43 </td><td> Cache </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr>
609 <tr><td> 0x44 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr>
610 <tr><td> 0x45 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr>
611 <tr><td> 0x46 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr>
612 <tr><td> 0x47 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr>
613 <tr><td> 0x48 </td><td> Cache </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr>
614 <tr><td> 0x49 </td><td> Cache </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size
615 (Intel Xeon processor MP, Family 0FH, Model 06H)<BR>
616 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
617 <tr><td> 0x4A </td><td> Cache </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr>
618 <tr><td> 0x4B </td><td> Cache </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr>
619 <tr><td> 0x4C </td><td> Cache </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr>
620 <tr><td> 0x4D </td><td> Cache </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr>
621 <tr><td> 0x4E </td><td> Cache </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr>
622 <tr><td> 0x4F </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr>
623 <tr><td> 0x50 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr>
624 <tr><td> 0x51 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr>
625 <tr><td> 0x52 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr>
626 <tr><td> 0x55 </td><td> TLB </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr>
627 <tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>
628 <tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>
629 <tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>
630 <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>
631 <tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>
632 <tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>
633 <tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>
634 <tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>
635 <tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>
636 <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 2 MByte or 4 MByte pages, 4-way set associative,
637 32 entries and a separate array with 1 GByte pages, 4-way set associative,
639 <tr><td> 0x64 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 512 entries</td></tr>
640 <tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>
641 <tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>
642 <tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>
643 <tr><td> 0x6A </td><td> Cache </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr>
644 <tr><td> 0x6B </td><td> Cache </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr>
645 <tr><td> 0x6C </td><td> Cache </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr>
646 <tr><td> 0x6D </td><td> Cache </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr>
647 <tr><td> 0x70 </td><td> Cache </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr>
648 <tr><td> 0x71 </td><td> Cache </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr>
649 <tr><td> 0x72 </td><td> Cache </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr>
650 <tr><td> 0x76 </td><td> TLB </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr>
651 <tr><td> 0x78 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr>
652 <tr><td> 0x79 </td><td> Cache </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size,
653 2 lines per sector</td></tr>
654 <tr><td> 0x7A </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size,
655 2 lines per sector</td></tr>
656 <tr><td> 0x7B </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size,
657 2 lines per sector</td></tr>
658 <tr><td> 0x7C </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size,
659 2 lines per sector</td></tr>
660 <tr><td> 0x7D </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr>
661 <tr><td> 0x7F </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr>
662 <tr><td> 0x80 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr>
663 <tr><td> 0x82 </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr>
664 <tr><td> 0x83 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr>
665 <tr><td> 0x84 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr>
666 <tr><td> 0x85 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr>
667 <tr><td> 0x86 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
668 <tr><td> 0x87 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
669 <tr><td> 0xA0 </td><td> DTLB </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr>
670 <tr><td> 0xB0 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
671 <tr><td> 0xB1 </td><td> TLB </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr>
672 <tr><td> 0xB2 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr>
673 <tr><td> 0xB3 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
674 <tr><td> 0xB4 </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr>
675 <tr><td> 0xB5 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr>
676 <tr><td> 0xB6 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative,
677 128 entries</td></tr>
678 <tr><td> 0xBA </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr>
679 <tr><td> 0xC0 </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr>
680 <tr><td> 0xC1 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative,
681 1024 entries</td></tr>
682 <tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>
683 <tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,
684 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>
685 <tr><td> 0xC4 </td><td> DTLB </td><td> DTLB: 2M/4M Byte pages, 4-way associative, 32 entries</td></tr>
686 <tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>
687 <tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
688 <tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>
689 <tr><td> 0xD2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr>
690 <tr><td> 0xD6 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
691 <tr><td> 0xD7 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr>
692 <tr><td> 0xD8 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr>
693 <tr><td> 0xDC </td><td> Cache </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr>
694 <tr><td> 0xDD </td><td> Cache </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr>
695 <tr><td> 0xDE </td><td> Cache </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr>
696 <tr><td> 0xE2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr>
697 <tr><td> 0xE3 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
698 <tr><td> 0xE4 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr>
699 <tr><td> 0xEA </td><td> Cache </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr>
700 <tr><td> 0xEB </td><td> Cache </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr>
701 <tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr>
702 <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr>
703 <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr>
704 <tr><td> 0xFE </td><td> General </td><td> CPUID leaf 2 does not report TLB descriptor information; use CPUID
705 leaf 18H to query TLB and other address translation parameters.</td></tr>
706 <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information,
707 use CPUID leaf 4 to query cache parameters</td></tr>
710 #define CPUID_CACHE_INFO 0x02
713 CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID
714 leaf #CPUID_CACHE_INFO.
718 /// Individual bit fields
723 /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.
724 /// if 1, then none of the cache descriptor bytes in the register are valid.
729 /// Array of Cache and TLB descriptor bytes
731 UINT8 CacheDescriptor
[4];
733 /// All bit fields as a 32-bit value
736 } CPUID_CACHE_INFO_CACHE_TLB
;
740 CPUID Processor Serial Number
742 Processor serial number (PSN) is not supported in the Pentium 4 processor
743 or later. On all models, use the PSN flag (returned using CPUID) to check
744 for PSN support before accessing the feature.
746 @param EAX CPUID_SERIAL_NUMBER (0x03)
748 @retval EAX Reserved.
749 @retval EBX Reserved.
750 @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in
751 Pentium III processor only; otherwise, the value in this
752 register is reserved.)
753 @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in
754 Pentium III processor only; otherwise, the value in this
755 register is reserved.)
762 AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);
765 #define CPUID_SERIAL_NUMBER 0x03
769 CPUID Cache Parameters
771 @param EAX CPUID_CACHE_PARAMS (0x04)
772 @param ECX Cache Level. Valid values start at 0. Software can enumerate
773 the deterministic cache parameters for each level of the cache
774 hierarchy starting with an index value of 0, until the
775 parameters report the value associated with the CacheType
776 field in CPUID_CACHE_PARAMS_EAX is 0.
778 @retval EAX Returns cache type information described by the type
779 CPUID_CACHE_PARAMS_EAX.
780 @retval EBX Returns cache line and associativity information described by
781 the type CPUID_CACHE_PARAMS_EBX.
782 @retval ECX Returns the number of sets in the cache.
783 @retval EDX Returns cache WINVD/INVD behavior described by the type
784 CPUID_CACHE_PARAMS_EDX.
789 CPUID_CACHE_PARAMS_EAX Eax;
790 CPUID_CACHE_PARAMS_EBX Ebx;
792 CPUID_CACHE_PARAMS_EDX Edx;
797 CPUID_CACHE_PARAMS, CacheLevel,
798 &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32
801 } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
804 #define CPUID_CACHE_PARAMS 0x04
807 CPUID Cache Parameters Information returned in EAX for CPUID leaf
812 /// Individual bit fields
816 /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,
817 /// then there is no information for the requested cache level.
821 /// [Bits 7:5] Cache level (Starts at 1).
825 /// [Bit 8] Self Initializing cache level (does not need SW initialization).
827 UINT32 SelfInitializingCache
:1;
829 /// [Bit 9] Fully Associative cache.
831 UINT32 FullyAssociativeCache
:1;
833 /// [Bits 13:10] Reserved.
837 /// [Bits 25:14] Maximum number of addressable IDs for logical processors
838 /// sharing this cache.
840 /// Add one to the return value to get the result.
841 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14])
842 /// is the number of unique initial APIC IDs reserved for addressing
843 /// different logical processors sharing this cache.
845 UINT32 MaximumAddressableIdsForLogicalProcessors
:12;
847 /// [Bits 31:26] Maximum number of addressable IDs for processor cores in
848 /// the physical package.
850 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26])
851 /// is the number of unique Core_IDs reserved for addressing different
852 /// processor cores in a physical package. Core ID is a subset of bits of
853 /// the initial APIC ID.
854 /// The returned value is constant for valid initial values in ECX. Valid
855 /// ECX values start from 0.
857 UINT32 MaximumAddressableIdsForProcessorCores
:6;
860 /// All bit fields as a 32-bit value
863 } CPUID_CACHE_PARAMS_EAX
;
866 /// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType
868 #define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00
869 #define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01
870 #define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02
871 #define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03
877 CPUID Cache Parameters Information returned in EBX for CPUID leaf
882 /// Individual bit fields
886 /// [Bits 11:0] System Coherency Line Size. Add one to the return value to
891 /// [Bits 21:12] Physical Line Partitions. Add one to the return value to
894 UINT32 LinePartitions
:10;
896 /// [Bits 31:22] Ways of associativity. Add one to the return value to get
902 /// All bit fields as a 32-bit value
905 } CPUID_CACHE_PARAMS_EBX
;
908 CPUID Cache Parameters Information returned in EDX for CPUID leaf
913 /// Individual bit fields
917 /// [Bit 0] Write-Back Invalidate/Invalidate.
918 /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level
919 /// caches for threads sharing this cache.
920 /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of
921 /// non-originating threads sharing this cache.
925 /// [Bit 1] Cache Inclusiveness.
926 /// 0 = Cache is not inclusive of lower cache levels.
927 /// 1 = Cache is inclusive of lower cache levels.
929 UINT32 CacheInclusiveness
:1;
931 /// [Bit 2] Complex Cache Indexing.
932 /// 0 = Direct mapped cache.
933 /// 1 = A complex function is used to index the cache, potentially using all
936 UINT32 ComplexCacheIndexing
:1;
940 /// All bit fields as a 32-bit value
943 } CPUID_CACHE_PARAMS_EDX
;
947 CPUID MONITOR/MWAIT Information
949 @param EAX CPUID_MONITOR_MWAIT (0x05)
951 @retval EAX Smallest monitor-line size in bytes described by the type
952 CPUID_MONITOR_MWAIT_EAX.
953 @retval EBX Largest monitor-line size in bytes described by the type
954 CPUID_MONITOR_MWAIT_EBX.
955 @retval ECX Enumeration of Monitor-Mwait extensions support described by
956 the type CPUID_MONITOR_MWAIT_ECX.
957 @retval EDX Sub C-states supported described by the type
958 CPUID_MONITOR_MWAIT_EDX.
962 CPUID_MONITOR_MWAIT_EAX Eax;
963 CPUID_MONITOR_MWAIT_EBX Ebx;
964 CPUID_MONITOR_MWAIT_ECX Ecx;
965 CPUID_MONITOR_MWAIT_EDX Edx;
967 AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
970 #define CPUID_MONITOR_MWAIT 0x05
973 CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf
974 #CPUID_MONITOR_MWAIT.
978 /// Individual bit fields
982 /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's
983 /// monitor granularity).
985 UINT32 SmallestMonitorLineSize
:16;
989 /// All bit fields as a 32-bit value
992 } CPUID_MONITOR_MWAIT_EAX
;
995 CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf
996 #CPUID_MONITOR_MWAIT.
1000 /// Individual bit fields
1004 /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's
1005 /// monitor granularity).
1007 UINT32 LargestMonitorLineSize
:16;
1011 /// All bit fields as a 32-bit value
1014 } CPUID_MONITOR_MWAIT_EBX
;
1017 CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf
1018 #CPUID_MONITOR_MWAIT.
1022 /// Individual bit fields
1026 /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,
1027 /// and EDX are valid.
1029 UINT32 ExtensionsSupported
:1;
1031 /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when
1032 /// interrupts disabled.
1034 UINT32 InterruptAsBreak
:1;
1038 /// All bit fields as a 32-bit value
1041 } CPUID_MONITOR_MWAIT_ECX
;
1044 CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf
1045 #CPUID_MONITOR_MWAIT.
1048 The definition of C0 through C7 states for MWAIT extension are
1049 processor-specific C-states, not ACPI C-states.
1053 /// Individual bit fields
1057 /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.
1061 /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.
1065 /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.
1069 /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.
1073 /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.
1077 /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.
1081 /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.
1085 /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.
1090 /// All bit fields as a 32-bit value
1093 } CPUID_MONITOR_MWAIT_EDX
;
1097 CPUID Thermal and Power Management
1099 @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06)
1101 @retval EAX Thermal and power management features described by the type
1102 CPUID_THERMAL_POWER_MANAGEMENT_EAX.
1103 @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor
1104 described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX.
1105 @retval ECX Performance features described by the type
1106 CPUID_THERMAL_POWER_MANAGEMENT_ECX.
1107 @retval EDX Reserved.
1109 <b>Example usage</b>
1111 CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;
1112 CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;
1113 CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;
1115 AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
1118 #define CPUID_THERMAL_POWER_MANAGEMENT 0x06
1121 CPUID Thermal and Power Management Information returned in EAX for CPUID leaf
1122 #CPUID_THERMAL_POWER_MANAGEMENT.
1126 /// Individual bit fields
1130 /// [Bit 0] Digital temperature sensor is supported if set.
1132 UINT32 DigitalTemperatureSensor
:1;
1134 /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).
1136 UINT32 TurboBoostTechnology
:1;
1138 /// [Bit 2] APIC-Timer-always-running feature is supported if set.
1143 /// [Bit 4] Power limit notification controls are supported if set.
1147 /// [Bit 5] Clock modulation duty cycle extension is supported if set.
1151 /// [Bit 6] Package thermal management is supported if set.
1155 /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,
1156 /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
1160 /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.
1162 UINT32 HWP_Notification
:1;
1164 /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.
1166 UINT32 HWP_Activity_Window
:1;
1168 /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.
1170 UINT32 HWP_Energy_Performance_Preference
:1;
1172 /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.
1174 UINT32 HWP_Package_Level_Request
:1;
1177 /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,
1178 /// IA32_THREAD_STALL MSRs are supported if set.
1182 /// [Bit 14] Intel Turbo Boost Max Technology 3.0 available.
1184 UINT32 TurboBoostMaxTechnology30
:1;
1186 /// [Bit 15] HWP Capabilities.
1187 /// Highest Performance change is supported if set.
1189 UINT32 HWPCapabilities
:1;
1191 /// [Bit 16] HWP PECI override is supported if set.
1193 UINT32 HWPPECIOverride
:1;
1195 /// [Bit 17] Flexible HWP is supported if set.
1197 UINT32 FlexibleHWP
:1;
1199 /// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.
1201 UINT32 FastAccessMode
:1;
1204 /// [Bit 20] Ignoring Idle Logical Processor HWP request is supported if set.
1206 UINT32 IgnoringIdleLogicalProcessorHWPRequest
:1;
1207 UINT32 Reserved5
:11;
1210 /// All bit fields as a 32-bit value
1213 } CPUID_THERMAL_POWER_MANAGEMENT_EAX
;
1216 CPUID Thermal and Power Management Information returned in EBX for CPUID leaf
1217 #CPUID_THERMAL_POWER_MANAGEMENT.
1221 /// Individual bit fields
1225 /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.
1227 UINT32 InterruptThresholds
:4;
1231 /// All bit fields as a 32-bit value
1234 } CPUID_THERMAL_POWER_MANAGEMENT_EBX
;
1237 CPUID Thermal and Power Management Information returned in ECX for CPUID leaf
1238 #CPUID_THERMAL_POWER_MANAGEMENT.
1242 /// Individual bit fields
1246 /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF
1247 /// and IA32_APERF). The capability to provide a measure of delivered
1248 /// processor performance (since last reset of the counters), as a percentage
1249 /// of the expected processor performance when running at the TSC frequency.
1251 UINT32 HardwareCoordinationFeedback
:1;
1254 /// [Bit 3] If this bit is set, then the processor supports performance-energy
1255 /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS
1258 UINT32 PerformanceEnergyBias
:1;
1259 UINT32 Reserved2
:28;
1262 /// All bit fields as a 32-bit value
1265 } CPUID_THERMAL_POWER_MANAGEMENT_ECX
;
1269 CPUID Structured Extended Feature Flags Enumeration
1271 @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)
1272 @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00).
1275 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
1276 index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.
1278 @retval EAX The maximum input value for ECX to retrieve sub-leaf information.
1279 @retval EBX Structured Extended Feature Flags described by the type
1280 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX.
1281 @retval EBX Structured Extended Feature Flags described by the type
1282 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX.
1283 @retval EDX Reserved.
1285 <b>Example usage</b>
1288 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
1289 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;
1293 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
1294 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
1295 &Eax, NULL, NULL, NULL
1297 for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {
1299 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
1301 NULL, &Ebx.Uint32, &Ecx.Uint32, NULL
1306 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07
1309 /// CPUID Structured Extended Feature Flags Enumeration sub-leaf
1311 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00
1314 CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf
1315 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
1316 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
1320 /// Individual bit fields
1324 /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
1328 /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.
1330 UINT32 IA32_TSC_ADJUST
:1;
1332 /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT
1333 /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".
1337 /// [Bit 3] If 1 indicates the processor supports the first group of advanced
1338 /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)
1342 /// [Bit 4] Hardware Lock Elision
1346 /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.
1350 /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.
1352 UINT32 FDP_EXCPTN_ONLY
:1;
1354 /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.
1358 /// [Bit 8] If 1 indicates the processor supports the second group of
1359 /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,
1360 /// SARX, SHLX, SHRX)
1364 /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.
1366 UINT32 EnhancedRepMovsbStosb
:1;
1368 /// [Bit 10] If 1, supports INVPCID instruction for system software that
1369 /// manages process-context identifiers.
1373 /// [Bit 11] Restricted Transactional Memory
1377 /// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
1378 /// Monitoring capability if 1.
1382 /// [Bit 13] Deprecates FPU CS and FPU DS values if 1.
1384 UINT32 DeprecateFpuCsDs
:1;
1386 /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.
1390 /// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
1391 /// Allocation capability if 1.
1395 /// [Bit 16] AVX512F.
1399 /// [Bit 17] AVX512DQ.
1403 /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.
1407 /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX
1412 /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC
1413 /// instructions) if 1.
1417 /// [Bit 21] AVX512_IFMA.
1419 UINT32 AVX512_IFMA
:1;
1422 /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.
1424 UINT32 CLFLUSHOPT
:1;
1426 /// [Bit 24] If 1 indicates the processor supports the CLWB instruction.
1430 /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace
1433 UINT32 IntelProcessorTrace
:1;
1435 /// [Bit 26] AVX512PF. (Intel Xeon Phi only.).
1439 /// [Bit 27] AVX512ER. (Intel Xeon Phi only.).
1443 /// [Bit 28] AVX512CD.
1447 /// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R)
1448 /// SHA Extensions) if 1.
1452 /// [Bit 30] AVX512BW.
1456 /// [Bit 31] AVX512VL.
1461 /// All bit fields as a 32-bit value
1464 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
;
1467 CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf
1468 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
1469 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
1473 /// Individual bit fields
1477 /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.
1478 /// (Intel Xeon Phi only.)
1480 UINT32 PREFETCHWT1
:1;
1482 /// [Bit 1] AVX512_VBMI.
1484 UINT32 AVX512_VBMI
:1;
1486 /// [Bit 2] Supports user-mode instruction prevention if 1.
1490 /// [Bit 3] Supports protection keys for user-mode pages if 1.
1494 /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the
1495 /// RDPKRU/WRPKRU instructions).
1500 /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).
1502 UINT32 AVX512_VPOPCNTDQ
:1;
1505 /// [Bits 16] Supports 5-level paging if 1.
1507 UINT32 FiveLevelPage
:1;
1509 /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions
1514 /// [Bit 22] RDPID and IA32_TSC_AUX are available if 1.
1519 /// [Bit 30] Supports SGX Launch Configuration if 1.
1525 /// All bit fields as a 32-bit value
1528 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
;
1531 CPUID Structured Extended Feature Flags Enumeration in EDX for CPUID leaf
1532 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
1533 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
1537 /// Individual bit fields
1541 /// [Bit 1:0] Reserved.
1545 /// [Bit 2] AVX512_4VNNIW. (Intel Xeon Phi only.)
1547 UINT32 AVX512_4VNNIW
:1;
1549 /// [Bit 3] AVX512_4FMAPS. (Intel Xeon Phi only.)
1551 UINT32 AVX512_4FMAPS
:1;
1553 /// [Bit 25:4] Reserved.
1555 UINT32 Reserved2
:22;
1557 /// [Bit 26] Enumerates support for indirect branch restricted speculation
1558 /// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors
1559 /// that set this bit support the IA32_SPEC_CTRL MSR and the IA32_PRED_CMD
1560 /// MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS) and
1561 /// IA32_PRED_CMD[0] (IBPB).
1563 UINT32 EnumeratesSupportForIBRSAndIBPB
:1;
1565 /// [Bit 27] Enumerates support for single thread indirect branch
1566 /// predictors (STIBP). Processors that set this bit support the
1567 /// IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[1]
1570 UINT32 EnumeratesSupportForSTIBP
:1;
1572 /// [Bit 28] Enumerates support for L1D_FLUSH. Processors that set this bit
1573 /// support the IA32_FLUSH_CMD MSR. They allow software to set
1574 /// IA32_FLUSH_CMD[0] (L1D_FLUSH).
1576 UINT32 EnumeratesSupportForL1D_FLUSH
:1;
1578 /// [Bit 29] Enumerates support for the IA32_ARCH_CAPABILITIES MSR.
1580 UINT32 EnumeratesSupportForCapability
:1;
1582 /// [Bit 30] Reserved.
1586 /// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD).
1587 /// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow
1588 /// software to set IA32_SPEC_CTRL[2] (SSBD).
1590 UINT32 EnumeratesSupportForSSBD
:1;
1593 /// All bit fields as a 32-bit value
1596 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX
;
1599 CPUID Direct Cache Access Information
1601 @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09)
1603 @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).
1604 @retval EBX Reserved.
1605 @retval ECX Reserved.
1606 @retval EDX Reserved.
1608 <b>Example usage</b>
1612 AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);
1615 #define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09
1619 CPUID Architectural Performance Monitoring
1621 @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A)
1623 @retval EAX Architectural Performance Monitoring information described by
1624 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX.
1625 @retval EBX Architectural Performance Monitoring information described by
1626 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX.
1627 @retval ECX Reserved.
1628 @retval EDX Architectural Performance Monitoring information described by
1629 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX.
1631 <b>Example usage</b>
1633 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;
1634 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;
1635 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;
1637 AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);
1640 #define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A
1643 CPUID Architectural Performance Monitoring EAX for CPUID leaf
1644 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1648 /// Individual bit fields
1652 /// [Bit 7:0] Version ID of architectural performance monitoring.
1654 UINT32 ArchPerfMonVerID
:8;
1656 /// [Bits 15:8] Number of general-purpose performance monitoring counter
1657 /// per logical processor.
1659 /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous
1660 /// block of MSR address space. Each performance event select register is
1661 /// paired with a corresponding performance counter in the 0C1H address
1664 UINT32 PerformanceMonitorCounters
:8;
1666 /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.
1668 /// The bit width of an IA32_PMCx MSR. This the number of valid bits for
1669 /// read operation. On write operations, the lower-order 32 bits of the MSR
1670 /// may be written with any value, and the high-order bits are sign-extended
1671 /// from the value of bit 31.
1673 UINT32 PerformanceMonitorCounterWidth
:8;
1675 /// [Bits 31:24] Length of EBX bit vector to enumerate architectural
1676 /// performance monitoring events.
1678 UINT32 EbxBitVectorLength
:8;
1681 /// All bit fields as a 32-bit value
1684 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX
;
1687 CPUID Architectural Performance Monitoring EBX for CPUID leaf
1688 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1692 /// Individual bit fields
1696 /// [Bit 0] Core cycle event not available if 1.
1698 UINT32 UnhaltedCoreCycles
:1;
1700 /// [Bit 1] Instruction retired event not available if 1.
1702 UINT32 InstructionsRetired
:1;
1704 /// [Bit 2] Reference cycles event not available if 1.
1706 UINT32 UnhaltedReferenceCycles
:1;
1708 /// [Bit 3] Last-level cache reference event not available if 1.
1710 UINT32 LastLevelCacheReferences
:1;
1712 /// [Bit 4] Last-level cache misses event not available if 1.
1714 UINT32 LastLevelCacheMisses
:1;
1716 /// [Bit 5] Branch instruction retired event not available if 1.
1718 UINT32 BranchInstructionsRetired
:1;
1720 /// [Bit 6] Branch mispredict retired event not available if 1.
1722 UINT32 AllBranchMispredictRetired
:1;
1726 /// All bit fields as a 32-bit value
1729 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
;
1732 CPUID Architectural Performance Monitoring EDX for CPUID leaf
1733 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1737 /// Individual bit fields
1741 /// [Bits 4:0] Number of fixed-function performance counters
1742 /// (if Version ID > 1).
1744 UINT32 FixedFunctionPerformanceCounters
:5;
1746 /// [Bits 12:5] Bit width of fixed-function performance counters
1747 /// (if Version ID > 1).
1749 UINT32 FixedFunctionPerformanceCounterWidth
:8;
1752 /// [Bits 15] AnyThread deprecation.
1754 UINT32 AnyThreadDeprecation
:1;
1755 UINT32 Reserved2
:16;
1758 /// All bit fields as a 32-bit value
1761 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX
;
1765 CPUID Extended Topology Information
1768 CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first
1769 checking for the existence of Leaf 1FH before using leaf 0BH.
1770 Most of Leaf 0BH output depends on the initial value in ECX. The EDX output
1771 of leaf 0BH is always valid and does not vary with input value in ECX. Output
1772 value in ECX[7:0] always equals input value in ECX[7:0].
1773 Sub-leaf index 0 enumerates SMT level. Each subsequent higher sub-leaf index
1774 enumerates a higher-level topological entity in hierarchical order.
1775 For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and
1777 If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],
1778 other input values with ECX > n also return 0 in ECX[15:8].
1780 @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B)
1781 @param ECX Level number
1783 @retval EAX Extended topology information described by the type
1784 CPUID_EXTENDED_TOPOLOGY_EAX.
1785 @retval EBX Extended topology information described by the type
1786 CPUID_EXTENDED_TOPOLOGY_EBX.
1787 @retval ECX Extended topology information described by the type
1788 CPUID_EXTENDED_TOPOLOGY_ECX.
1789 @retval EDX x2APIC ID the current logical processor.
1791 <b>Example usage</b>
1793 CPUID_EXTENDED_TOPOLOGY_EAX Eax;
1794 CPUID_EXTENDED_TOPOLOGY_EBX Ebx;
1795 CPUID_EXTENDED_TOPOLOGY_ECX Ecx;
1802 CPUID_EXTENDED_TOPOLOGY, LevelNumber,
1803 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx
1806 } while (Eax.Bits.ApicIdShift != 0);
1809 #define CPUID_EXTENDED_TOPOLOGY 0x0B
1812 CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1816 /// Individual bit fields
1820 /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique
1821 /// topology ID of the next level type. All logical processors with the
1822 /// same next level ID share current level.
1825 /// Software should use this field (EAX[4:0]) to enumerate processor
1826 /// topology of the system.
1828 UINT32 ApicIdShift
:5;
1832 /// All bit fields as a 32-bit value
1835 } CPUID_EXTENDED_TOPOLOGY_EAX
;
1838 CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1842 /// Individual bit fields
1846 /// [Bits 15:0] Number of logical processors at this level type. The number
1847 /// reflects configuration as shipped by Intel.
1850 /// Software must not use EBX[15:0] to enumerate processor topology of the
1851 /// system. This value in this field (EBX[15:0]) is only intended for
1852 /// display/diagnostic purposes. The actual number of logical processors
1853 /// available to BIOS/OS/Applications may be different from the value of
1854 /// EBX[15:0], depending on software and platform hardware configurations.
1856 UINT32 LogicalProcessors
:16;
1860 /// All bit fields as a 32-bit value
1863 } CPUID_EXTENDED_TOPOLOGY_EBX
;
1866 CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1870 /// Individual bit fields
1874 /// [Bits 7:0] Level number. Same value in ECX input.
1876 UINT32 LevelNumber
:8;
1878 /// [Bits 15:8] Level type.
1881 /// The value of the "level type" field is not related to level numbers in
1882 /// any way, higher "level type" values do not mean higher levels.
1888 /// All bit fields as a 32-bit value
1891 } CPUID_EXTENDED_TOPOLOGY_ECX
;
1894 /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
1896 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00
1897 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01
1898 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02
1905 CPUID Extended State Information
1907 @param EAX CPUID_EXTENDED_STATE (0x0D)
1908 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00).
1909 CPUID_EXTENDED_STATE_SUB_LEAF (0x01).
1910 CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).
1911 Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.
1913 #define CPUID_EXTENDED_STATE 0x0D
1916 CPUID Extended State Information Main Leaf
1918 @param EAX CPUID_EXTENDED_STATE (0x0D)
1919 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)
1921 @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n]
1922 can be set to 1 only if EAX[n] is 1. The format of the extended
1923 state main leaf is described by the type
1924 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX.
1925 @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
1926 area) required by enabled features in XCR0. May be different than
1927 ECX if some features at the end of the XSAVE save area are not
1929 @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
1930 area) of the XSAVE/XRSTOR save area required by all supported
1931 features in the processor, i.e., all the valid bit fields in XCR0.
1932 @retval EDX Reports the supported bits of the upper 32 bits of XCR0.
1933 XCR0[n+32] can be set to 1 only if EDX[n] is 1.
1935 <b>Example usage</b>
1937 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;
1943 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,
1944 &Eax.Uint32, &Ebx, &Ecx, &Edx
1948 #define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00
1951 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
1952 sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF.
1956 /// Individual bit fields
1960 /// [Bit 0] x87 state.
1964 /// [Bit 1] SSE state.
1968 /// [Bit 2] AVX state.
1972 /// [Bits 4:3] MPX state.
1976 /// [Bits 7:5] AVX-512 state.
1980 /// [Bit 8] Used for IA32_XSS.
1984 /// [Bit 9] PKRU state.
1989 /// [Bit 13] Used for IA32_XSS, part 2.
1991 UINT32 IA32_XSS_2
:1;
1992 UINT32 Reserved2
:18;
1995 /// All bit fields as a 32-bit value
1998 } CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
;
2001 CPUID Extended State Information Sub Leaf
2003 @param EAX CPUID_EXTENDED_STATE (0x0D)
2004 @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01)
2006 @retval EAX The format of the extended state sub-leaf is described by the
2007 type CPUID_EXTENDED_STATE_SUB_LEAF_EAX.
2008 @retval EBX The size in bytes of the XSAVE area containing all states
2009 enabled by XCRO | IA32_XSS.
2010 @retval ECX The format of the extended state sub-leaf is described by the
2011 type CPUID_EXTENDED_STATE_SUB_LEAF_ECX.
2012 @retval EDX Reports the supported bits of the upper 32 bits of the
2013 IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.
2015 <b>Example usage</b>
2017 CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;
2019 CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;
2023 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,
2024 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx
2028 #define CPUID_EXTENDED_STATE_SUB_LEAF 0x01
2031 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
2032 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
2036 /// Individual bit fields
2040 /// [Bit 0] XSAVEOPT is available.
2044 /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.
2048 /// [Bit 2] Supports XGETBV with ECX = 1 if set.
2052 /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.
2058 /// All bit fields as a 32-bit value
2061 } CPUID_EXTENDED_STATE_SUB_LEAF_EAX
;
2064 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
2065 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
2069 /// Individual bit fields
2073 /// [Bits 7:0] Used for XCR0.
2077 /// [Bit 8] PT STate.
2081 /// [Bit 9] Used for XCR0.
2086 /// [Bit 13] HWP state.
2089 UINT32 Reserved8
:18;
2092 /// All bit fields as a 32-bit value
2095 } CPUID_EXTENDED_STATE_SUB_LEAF_ECX
;
2098 CPUID Extended State Information Size and Offset Sub Leaf
2101 Leaf 0DH output depends on the initial value in ECX.
2102 Each sub-leaf index (starting at position 2) is supported if it corresponds to
2103 a supported bit in either the XCR0 register or the IA32_XSS MSR.
2104 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
2105 n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1
2106 returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0
2107 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].
2109 @param EAX CPUID_EXTENDED_STATE (0x0D)
2110 @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based
2111 on supported bits in XCR0 or IA32_XSS_MSR.
2113 @retval EAX The size in bytes (from the offset specified in EBX) of the save
2114 area for an extended state feature associated with a valid
2116 @retval EBX The offset in bytes of this extended state component's save area
2117 from the beginning of the XSAVE/XRSTOR area. This field reports
2118 0 if the sub-leaf index, n, does not map to a valid bit in the
2120 @retval ECX The format of the extended state components's save area as
2121 described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX.
2122 This field reports 0 if the sub-leaf index, n, is invalid.
2123 @retval EDX This field reports 0 if the sub-leaf index, n, is invalid;
2124 otherwise it is reserved.
2126 <b>Example usage</b>
2130 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;
2134 for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {
2136 CPUID_EXTENDED_STATE, SubLeaf,
2137 &Eax, &Ebx, &Ecx.Uint32, &Edx
2142 #define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02
2145 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
2146 sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET.
2150 /// Individual bit fields
2154 /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is
2155 /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported
2160 /// [Bit 1] is set if, when the compacted format of an XSAVE area is used,
2161 /// this extended state component located on the next 64-byte boundary
2162 /// following the preceding state component (otherwise, it is located
2163 /// immediately following the preceding state component).
2169 /// All bit fields as a 32-bit value
2172 } CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX
;
2176 CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
2178 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
2179 @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00).
2180 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).
2183 #define CPUID_INTEL_RDT_MONITORING 0x0F
2186 CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
2187 Enumeration Sub-leaf
2189 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
2190 @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00)
2192 @retval EAX Reserved.
2193 @retval EBX Maximum range (zero-based) of RMID within this physical
2194 processor of all types.
2195 @retval ECX Reserved.
2196 @retval EDX L3 Cache Intel RDT Monitoring Information Enumeration described by
2197 the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX.
2199 <b>Example usage</b>
2202 CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
2205 CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,
2206 NULL, &Ebx, NULL, &Edx.Uint32
2210 #define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00
2213 CPUID Intel RDT Monitoring Information EDX for CPUID leaf
2214 #CPUID_INTEL_RDT_MONITORING, sub-leaf
2215 #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF.
2219 /// Individual bit fields
2224 /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.
2226 UINT32 L3CacheRDT_M
:1;
2227 UINT32 Reserved2
:30;
2230 /// All bit fields as a 32-bit value
2233 } CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX
;
2236 CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf
2238 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
2239 @param ECX CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01)
2241 @retval EAX Reserved.
2242 @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).
2243 @retval ECX Maximum range (zero-based) of RMID of this resource type.
2244 @retval EDX L3 Cache Intel RDT Monitoring Capability information described by the
2245 type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX.
2247 <b>Example usage</b>
2251 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;
2254 CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,
2255 NULL, &Ebx, &Ecx, &Edx.Uint32
2259 #define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01
2262 CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf
2263 #CPUID_INTEL_RDT_MONITORING, sub-leaf
2264 #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF.
2268 /// Individual bit fields
2272 /// [Bit 0] Supports L3 occupancy monitoring if 1.
2274 UINT32 L3CacheOccupancyMonitoring
:1;
2276 /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1.
2278 UINT32 L3CacheTotalBandwidthMonitoring
:1;
2280 /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1.
2282 UINT32 L3CacheLocalBandwidthMonitoring
:1;
2286 /// All bit fields as a 32-bit value
2289 } CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX
;
2293 CPUID Intel Resource Director Technology (Intel RDT) Allocation Information
2295 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10).
2296 @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).
2297 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01).
2298 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).
2300 #define CPUID_INTEL_RDT_ALLOCATION 0x10
2303 Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf
2305 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
2306 @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).
2308 @retval EAX Reserved.
2309 @retval EBX L3 and L2 Cache Allocation Technology information described by
2310 the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX.
2311 @retval ECX Reserved.
2312 @retval EDX Reserved.
2314 <b>Example usage</b>
2316 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;
2319 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,
2320 NULL, &Ebx.Uint32, NULL, NULL
2324 #define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00
2327 CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf
2328 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2329 #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF.
2333 /// Individual bit fields
2338 /// [Bit 1] Supports L3 Cache Allocation Technology if 1.
2340 UINT32 L3CacheAllocation
:1;
2342 /// [Bit 2] Supports L2 Cache Allocation Technology if 1.
2344 UINT32 L2CacheAllocation
:1;
2346 /// [Bit 3] Supports Memory Bandwidth Allocation if 1.
2348 UINT32 MemoryBandwidth
:1;
2349 UINT32 Reserved3
:28;
2352 /// All bit fields as a 32-bit value
2355 } CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX
;
2359 L3 Cache Allocation Technology Enumeration Sub-leaf
2361 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
2362 @param ECX CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01)
2364 @retval EAX RESID L3 Cache Allocation Technology information described by
2365 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX.
2366 @retval EBX Bit-granular map of isolation/contention of allocation units.
2367 @retval ECX RESID L3 Cache Allocation Technology information described by
2368 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX.
2369 @retval EDX RESID L3 Cache Allocation Technology information described by
2370 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX.
2372 <b>Example usage</b>
2374 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;
2376 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;
2377 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;
2380 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,
2381 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32
2385 #define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01
2388 CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf
2389 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2390 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
2394 /// Individual bit fields
2398 /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
2399 /// using minus-one notation.
2401 UINT32 CapacityLength
:5;
2405 /// All bit fields as a 32-bit value
2408 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX
;
2411 CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf
2412 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2413 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
2417 /// Individual bit fields
2422 /// [Bit 2] Code and Data Prioritization Technology supported if 1.
2424 UINT32 CodeDataPrioritization
:1;
2425 UINT32 Reserved2
:29;
2428 /// All bit fields as a 32-bit value
2431 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX
;
2434 CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf
2435 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2436 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
2440 /// Individual bit fields
2444 /// [Bits 15:0] Highest COS number supported for this ResID.
2446 UINT32 HighestCosNumber
:16;
2450 /// All bit fields as a 32-bit value
2453 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX
;
2456 L2 Cache Allocation Technology Enumeration Sub-leaf
2458 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
2459 @param ECX CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02)
2461 @retval EAX RESID L2 Cache Allocation Technology information described by
2462 the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX.
2463 @retval EBX Bit-granular map of isolation/contention of allocation units.
2464 @retval ECX Reserved.
2465 @retval EDX RESID L2 Cache Allocation Technology information described by
2466 the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX.
2468 <b>Example usage</b>
2470 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;
2472 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;
2475 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,
2476 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
2480 #define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02
2483 CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf
2484 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2485 #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.
2489 /// Individual bit fields
2493 /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
2494 /// using minus-one notation.
2496 UINT32 CapacityLength
:5;
2500 /// All bit fields as a 32-bit value
2503 } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX
;
2506 CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf
2507 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2508 #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.
2512 /// Individual bit fields
2516 /// [Bits 15:0] Highest COS number supported for this ResID.
2518 UINT32 HighestCosNumber
:16;
2522 /// All bit fields as a 32-bit value
2525 } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX
;
2528 Memory Bandwidth Allocation Enumeration Sub-leaf
2530 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
2531 @param ECX CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF (0x03)
2533 @retval EAX RESID memory bandwidth Allocation Technology information
2534 described by the type
2535 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX.
2536 @retval EBX Reserved.
2537 @retval ECX RESID memory bandwidth Allocation Technology information
2538 described by the type
2539 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX.
2540 @retval EDX RESID memory bandwidth Allocation Technology information
2541 described by the type
2542 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX.
2544 <b>Example usage</b>
2546 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX Eax;
2548 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX Ecx;
2549 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx;
2553 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,
2554 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
2558 #define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03
2561 CPUID memory bandwidth Allocation Technology Information EAX for CPUID leaf
2562 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2563 #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.
2567 /// Individual bit fields
2571 /// [Bits 11:0] Reports the maximum MBA throttling value supported for
2572 /// the corresponding ResID using minus-one notation.
2574 UINT32 MaximumMBAThrottling
:12;
2578 /// All bit fields as a 32-bit value
2581 } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX
;
2584 CPUID memory bandwidth Allocation Technology Information ECX for CPUID leaf
2585 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2586 #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.
2590 /// Individual bit fields
2594 /// [Bits 1:0] Reserved.
2598 /// [Bits 3] Reports whether the response of the delay values is linear.
2601 UINT32 Reserved2
:29;
2604 /// All bit fields as a 32-bit value
2607 } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX
;
2610 CPUID memory bandwidth Allocation Technology Information EDX for CPUID leaf
2611 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2612 #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.
2616 /// Individual bit fields
2620 /// [Bits 15:0] Highest COS number supported for this ResID.
2622 UINT32 HighestCosNumber
:16;
2626 /// All bit fields as a 32-bit value
2629 } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX
;
2632 Intel SGX resource capability and configuration.
2633 See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves".
2635 If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying
2636 CPUID with EAX=12H on Intel SGX resource capability and configuration.
2638 @param EAX CPUID_INTEL_SGX (0x12)
2639 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00).
2640 CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01).
2641 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02).
2642 Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0])
2643 until the sub-leaf type is invalid.
2646 #define CPUID_INTEL_SGX 0x12
2649 Sub-Leaf 0 Enumeration of Intel SGX Capabilities.
2650 Enumerates Intel SGX capability, including enclave instruction opcode support.
2652 @param EAX CPUID_INTEL_SGX (0x12)
2653 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00)
2655 @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
2656 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX.
2657 @retval EBX MISCSELECT: Reports the bit vector of supported extended features
2658 that can be written to the MISC region of the SSA.
2659 @retval ECX Reserved.
2660 @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
2661 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX.
2663 <b>Example usage</b>
2665 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;
2667 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;
2670 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,
2671 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
2675 #define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00
2678 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,
2679 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
2683 /// Individual bit fields
2687 /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.
2691 /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.
2696 /// [Bit 5] If 1, indicates Intel SGX supports ENCLV instruction leaves
2697 /// EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT.
2701 /// [Bit 6] If 1, indicates Intel SGX supports ENCLS instruction leaves ETRACKC,
2702 /// ERDINFO, ELDBC, and ELDUC.
2705 UINT32 Reserved2
:25;
2708 /// All bit fields as a 32-bit value
2711 } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX
;
2714 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX,
2715 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
2719 /// Individual bit fields
2723 /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes
2724 /// when not in 64-bit mode.
2726 UINT32 MaxEnclaveSize_Not64
:8;
2728 /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes
2729 /// when operating in 64-bit mode.
2731 UINT32 MaxEnclaveSize_64
:8;
2735 /// All bit fields as a 32-bit value
2738 } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX
;
2742 Sub-Leaf 1 Enumeration of Intel SGX Capabilities.
2743 Enumerates Intel SGX capability of processor state configuration and enclave
2744 configuration in the SECS structure.
2746 @param EAX CPUID_INTEL_SGX (0x12)
2747 @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01)
2749 @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can
2750 set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE
2751 only if EAX[n] is 1, where n < 32.
2752 @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can
2753 set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE
2754 only if EBX[n] is 1, where n < 32.
2755 @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can
2756 set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE
2757 only if ECX[n] is 1, where n < 32.
2758 @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can
2759 set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE
2760 only if EDX[n] is 1, where n < 32.
2762 <b>Example usage</b>
2770 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,
2771 &Eax, &Ebx, &Ecx, &Edx
2775 #define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01
2779 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.
2780 Enumerates available EPC resources.
2782 @param EAX CPUID_INTEL_SGX (0x12)
2783 @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02)
2785 @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2786 Resources is described by the type
2787 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX.
2788 @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2789 Resources is described by the type
2790 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX.
2791 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2792 Resources is described by the type
2793 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX.
2794 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2795 Resources is described by the type
2796 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX.
2798 <b>Example usage</b>
2800 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;
2801 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;
2802 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;
2803 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;
2806 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF,
2807 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
2811 #define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02
2814 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID
2815 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2819 /// Individual bit fields
2823 /// [Bit 3:0] Sub-leaf-type encoding.
2824 /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0.
2825 /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC)
2826 /// in EBX:EAX and EDX:ECX.
2827 /// All other encoding are reserved.
2829 UINT32 SubLeafType
:4;
2832 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of
2833 /// the base of the EPC section.
2835 UINT32 LowAddressOfEpcSection
:20;
2838 /// All bit fields as a 32-bit value
2841 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX
;
2844 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID
2845 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2849 /// Individual bit fields
2853 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of
2854 /// the base of the EPC section.
2856 UINT32 HighAddressOfEpcSection
:20;
2860 /// All bit fields as a 32-bit value
2863 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX
;
2866 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID
2867 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2871 /// Individual bit fields
2875 /// [Bit 3:0] The EPC section encoding.
2876 /// 0000b: Not valid.
2877 /// 0001b: The EPC section is confidentiality, integrity and replay protected.
2878 /// All other encoding are reserved.
2880 UINT32 EpcSection
:4;
2883 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the
2884 /// corresponding EPC section within the Processor Reserved Memory.
2886 UINT32 LowSizeOfEpcSection
:20;
2889 /// All bit fields as a 32-bit value
2892 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX
;
2895 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID
2896 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2900 /// Individual bit fields
2904 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the
2905 /// corresponding EPC section within the Processor Reserved Memory.
2907 UINT32 HighSizeOfEpcSection
:20;
2911 /// All bit fields as a 32-bit value
2914 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX
;
2918 CPUID Intel Processor Trace Information
2920 @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14)
2921 @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00).
2922 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).
2925 #define CPUID_INTEL_PROCESSOR_TRACE 0x14
2928 CPUID Intel Processor Trace Information Main Leaf
2930 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
2931 @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00)
2933 @retval EAX Reports the maximum sub-leaf supported in leaf 14H.
2934 @retval EBX Returns Intel processor trace information described by the
2935 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX.
2936 @retval ECX Returns Intel processor trace information described by the
2937 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX.
2938 @retval EDX Reserved.
2940 <b>Example usage</b>
2943 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;
2944 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
2947 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
2948 &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL
2952 #define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00
2955 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2956 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
2960 /// Individual bit fields
2964 /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,
2965 /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.
2969 /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate
2972 UINT32 ConfigurablePsb
:1;
2974 /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering,
2975 /// and preservation of Intel PT MSRs across warm reset.
2977 UINT32 IpTraceStopFiltering
:1;
2979 /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of
2980 /// COFI-based packets.
2984 /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set
2985 /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE
2986 /// can generate packets.
2990 /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set
2991 /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet
2994 UINT32 PowerEventTrace
:1;
2998 /// All bit fields as a 32-bit value
3001 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
;
3004 CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
3005 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
3009 /// Individual bit fields
3013 /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence
3014 /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and
3015 /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
3019 /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to
3020 /// the maximum allowed by the MaskOrTableOffset field of
3021 /// IA32_RTIT_OUTPUT_MASK_PTRS.
3025 /// [Bit 2] If 1, indicates support of Single-Range Output scheme.
3027 UINT32 SingleRangeOutput
:1;
3029 /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem.
3031 UINT32 TraceTransportSubsystem
:1;
3034 /// [Bit 31] If 1, generated packets which contain IP payloads have LIP
3035 /// values, which include the CS base component.
3040 /// All bit fields as a 32-bit value
3043 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX
;
3047 CPUID Intel Processor Trace Information Sub-leaf
3049 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
3050 @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01)
3052 @retval EAX Returns Intel processor trace information described by the
3053 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX.
3054 @retval EBX Returns Intel processor trace information described by the
3055 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX.
3056 @retval ECX Reserved.
3057 @retval EDX Reserved.
3059 <b>Example usage</b>
3061 UINT32 MaximumSubLeaf;
3063 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;
3064 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;
3067 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
3068 &MaximumSubLeaf, NULL, NULL, NULL
3071 for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {
3073 CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,
3074 &Eax.Uint32, &Ebx.Uint32, NULL, NULL
3079 #define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01
3082 CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
3083 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
3087 /// Individual bit fields
3091 /// [Bits 2:0] Number of configurable Address Ranges for filtering.
3093 UINT32 ConfigurableAddressRanges
:3;
3096 /// [Bits 31:16] Bitmap of supported MTC period encodings
3098 UINT32 MtcPeriodEncodings
:16;
3102 /// All bit fields as a 32-bit value
3105 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX
;
3108 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
3109 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
3113 /// Individual bit fields
3117 /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.
3119 UINT32 CycleThresholdEncodings
:16;
3121 /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.
3123 UINT32 PsbFrequencyEncodings
:16;
3127 /// All bit fields as a 32-bit value
3130 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX
;
3134 CPUID Time Stamp Counter and Nominal Core Crystal Clock Information
3137 If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.
3138 EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core
3139 crystal clock frequency.
3140 If ECX is 0, the nominal core crystal clock frequency is not enumerated.
3141 "TSC frequency" = "core crystal clock frequency" * EBX/EAX.
3142 The core crystal clock may differ from the reference clock, bus clock, or core
3145 @param EAX CPUID_TIME_STAMP_COUNTER (0x15)
3147 @retval EAX An unsigned integer which is the denominator of the
3148 TSC/"core crystal clock" ratio
3149 @retval EBX An unsigned integer which is the numerator of the
3150 TSC/"core crystal clock" ratio.
3151 @retval ECX An unsigned integer which is the nominal frequency
3152 of the core crystal clock in Hz.
3153 @retval EDX Reserved.
3155 <b>Example usage</b>
3161 AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);
3164 #define CPUID_TIME_STAMP_COUNTER 0x15
3168 CPUID Processor Frequency Information
3171 Data is returned from this interface in accordance with the processor's
3172 specification and does not reflect actual values. Suitable use of this data
3173 includes the display of processor information in like manner to the processor
3174 brand string and for determining the appropriate range to use when displaying
3175 processor information e.g. frequency history graphs. The returned information
3176 should not be used for any other purpose as the returned information does not
3177 accurately correlate to information / counters returned by other processor
3178 interfaces. While a processor may support the Processor Frequency Information
3179 leaf, fields that return a value of zero are not supported.
3181 @param EAX CPUID_TIME_STAMP_COUNTER (0x16)
3183 @retval EAX Returns processor base frequency information described by the
3184 type CPUID_PROCESSOR_FREQUENCY_EAX.
3185 @retval EBX Returns maximum frequency information described by the type
3186 CPUID_PROCESSOR_FREQUENCY_EBX.
3187 @retval ECX Returns bus frequency information described by the type
3188 CPUID_PROCESSOR_FREQUENCY_ECX.
3189 @retval EDX Reserved.
3191 <b>Example usage</b>
3193 CPUID_PROCESSOR_FREQUENCY_EAX Eax;
3194 CPUID_PROCESSOR_FREQUENCY_EBX Ebx;
3195 CPUID_PROCESSOR_FREQUENCY_ECX Ecx;
3197 AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
3200 #define CPUID_PROCESSOR_FREQUENCY 0x16
3203 CPUID Processor Frequency Information EAX for CPUID leaf
3204 #CPUID_PROCESSOR_FREQUENCY.
3208 /// Individual bit fields
3212 /// [Bits 15:0] Processor Base Frequency (in MHz).
3214 UINT32 ProcessorBaseFrequency
:16;
3218 /// All bit fields as a 32-bit value
3221 } CPUID_PROCESSOR_FREQUENCY_EAX
;
3224 CPUID Processor Frequency Information EBX for CPUID leaf
3225 #CPUID_PROCESSOR_FREQUENCY.
3229 /// Individual bit fields
3233 /// [Bits 15:0] Maximum Frequency (in MHz).
3235 UINT32 MaximumFrequency
:16;
3239 /// All bit fields as a 32-bit value
3242 } CPUID_PROCESSOR_FREQUENCY_EBX
;
3245 CPUID Processor Frequency Information ECX for CPUID leaf
3246 #CPUID_PROCESSOR_FREQUENCY.
3250 /// Individual bit fields
3254 /// [Bits 15:0] Bus (Reference) Frequency (in MHz).
3256 UINT32 BusFrequency
:16;
3260 /// All bit fields as a 32-bit value
3263 } CPUID_PROCESSOR_FREQUENCY_ECX
;
3267 CPUID SoC Vendor Information
3269 @param EAX CPUID_SOC_VENDOR (0x17)
3270 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
3271 CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
3272 CPUID_SOC_VENDOR_BRAND_STRING1 (0x02)
3273 CPUID_SOC_VENDOR_BRAND_STRING1 (0x03)
3276 Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String
3277 is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC
3278 Vendor Brand String is constructed by concatenating in ascending order of
3279 EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.
3282 #define CPUID_SOC_VENDOR 0x17
3285 CPUID SoC Vendor Information
3287 @param EAX CPUID_SOC_VENDOR (0x17)
3288 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
3290 @retval EAX MaxSOCID_Index. Reports the maximum input value of supported
3291 sub-leaf in leaf 17H.
3292 @retval EBX Returns SoC Vendor information described by the type
3293 CPUID_SOC_VENDOR_MAIN_LEAF_EBX.
3294 @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC
3296 @retval EDX Stepping ID. A unique number within an SOC project that an SOC
3299 <b>Example usage</b>
3302 CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;
3307 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,
3308 &Eax, &Ebx.Uint32, &Ecx, &Edx
3312 #define CPUID_SOC_VENDOR_MAIN_LEAF 0x00
3315 CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf
3316 #CPUID_SOC_VENDOR_MAIN_LEAF.
3320 /// Individual bit fields
3324 /// [Bits 15:0] SOC Vendor ID.
3326 UINT32 SocVendorId
:16;
3328 /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry
3329 /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is
3330 /// assigned by Intel.
3332 UINT32 IsVendorScheme
:1;
3336 /// All bit fields as a 32-bit value
3339 } CPUID_SOC_VENDOR_MAIN_LEAF_EBX
;
3342 CPUID SoC Vendor Information
3344 @param EAX CPUID_SOC_VENDOR (0x17)
3345 @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
3347 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
3348 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3349 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
3350 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3351 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
3352 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3353 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
3354 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3356 <b>Example usage</b>
3358 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
3359 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
3360 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
3361 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
3364 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,
3365 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
3369 #define CPUID_SOC_VENDOR_BRAND_STRING1 0x01
3372 CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,
3373 #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3.
3377 /// 4 UTF-8 characters of Soc Vendor Brand String
3379 CHAR8 BrandString
[4];
3381 /// All fields as a 32-bit value
3384 } CPUID_SOC_VENDOR_BRAND_STRING_DATA
;
3387 CPUID SoC Vendor Information
3389 @param EAX CPUID_SOC_VENDOR (0x17)
3390 @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02)
3392 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
3393 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3394 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
3395 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3396 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
3397 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3398 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
3399 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3401 <b>Example usage</b>
3403 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
3404 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
3405 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
3406 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
3409 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,
3410 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
3414 #define CPUID_SOC_VENDOR_BRAND_STRING2 0x02
3417 CPUID SoC Vendor Information
3419 @param EAX CPUID_SOC_VENDOR (0x17)
3420 @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03)
3422 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
3423 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3424 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
3425 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3426 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
3427 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3428 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
3429 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3431 <b>Example usage</b>
3433 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
3434 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
3435 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
3436 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
3439 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,
3440 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
3444 #define CPUID_SOC_VENDOR_BRAND_STRING3 0x03
3447 CPUID Deterministic Address Translation Parameters
3450 Each sub-leaf enumerates a different address translation structure.
3451 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
3452 index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX. A
3453 sub-leaf index is also invalid if EDX[4:0] returns 0.
3454 Valid sub-leaves do not need to be contiguous or in any particular order. A
3455 valid sub-leaf may be in a higher input ECX value than an invalid sub-leaf or
3456 than a valid sub-leaf of a higher or lower-level structure.
3457 * Some unified TLBs will allow a single TLB entry to satisfy data read/write
3458 and instruction fetches. Others will require separate entries (e.g., one
3459 loaded on data read/write and another loaded on an instruction fetch).
3460 Please see the Intel 64 and IA-32 Architectures Optimization Reference Manual
3461 for details of a particular product.
3462 ** Add one to the return value to get the result.
3464 @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18)
3465 @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00)
3466 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_SUB_LEAF (0x*)
3469 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18
3472 CPUID Deterministic Address Translation Parameters
3474 @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18)
3475 @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00)
3477 @retval EAX Reports the maximum input value of supported sub-leaf in leaf 18H.
3478 @retval EBX Returns Deterministic Address Translation Parameters described by
3479 the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX.
3480 @retval ECX Number of Sets.
3481 @retval EDX Returns Deterministic Address Translation Parameters described by
3482 the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.
3484 <b>Example usage</b>
3487 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX Ebx;
3489 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX Edx;
3492 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS,
3493 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF,
3494 &Eax, &Ebx.Uint32, &Ecx, &Edx.Uint32
3498 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00
3501 CPUID Deterministic Address Translation Parameters EBX for CPUID leafs.
3505 /// Individual bit fields
3509 /// [Bits 0] 4K page size entries supported by this structure.
3513 /// [Bits 1] 2MB page size entries supported by this structure.
3517 /// [Bits 2] 4MB page size entries supported by this structure.
3521 /// [Bits 3] 1 GB page size entries supported by this structure.
3525 /// [Bits 7:4] Reserved.
3529 /// [Bits 10:8] Partitioning (0: Soft partitioning between the logical
3530 /// processors sharing this structure)
3532 UINT32 Partitioning
:3;
3534 /// [Bits 15:11] Reserved.
3538 /// [Bits 31:16] W = Ways of associativity.
3543 /// All bit fields as a 32-bit value
3546 } CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX
;
3549 CPUID Deterministic Address Translation Parameters EDX for CPUID leafs.
3553 /// Individual bit fields
3557 /// [Bits 4:0] Translation cache type field.
3559 UINT32 TranslationCacheType
:5;
3561 /// [Bits 7:5] Translation cache level (starts at 1).
3563 UINT32 TranslationCacheLevel
:3;
3565 /// [Bits 8] Fully associative structure.
3567 UINT32 FullyAssociative
:1;
3569 /// [Bits 13:9] Reserved.
3573 /// [Bits 25:14] Maximum number of addressable IDs for logical
3574 /// processors sharing this translation cache.
3576 UINT32 MaximumNum
:12;
3578 /// [Bits 31:26] Reserved.
3583 /// All bit fields as a 32-bit value
3586 } CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX
;
3589 /// @{ Define value for CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.TranslationCacheType
3591 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INVALID 0x00
3592 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_DATA_TLB 0x01
3593 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INSTRUCTION_TLB 0x02
3594 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_UNIFIED_TLB 0x03
3601 CPUID V2 Extended Topology Enumeration Leaf
3604 CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking
3605 for the existence of Leaf 1FH and using this if available.
3606 Most of Leaf 1FH output depends on the initial value in ECX. The EDX output of leaf
3607 1FH is always valid and does not vary with input value in ECX. Output value in ECX[7:0]
3608 always equals input value in ECX[7:0]. Sub-leaf index 0 enumerates SMT level. Each
3609 subsequent higher sub-leaf index enumerates a higher-level topological entity in
3610 hierarchical order. For sub-leaves that return an invalid level-type of 0 in ECX[15:8];
3611 EAX and EBX will return 0. If an input value n in ECX returns the invalid level-type of
3612 0 in ECX[15:8], other input values with ECX > n also return 0 in ECX[15:8].
3614 Software should use this field (EAX[4:0]) to enumerate processor topology of the system.
3615 Software must not use EBX[15:0] to enumerate processor topology of the system. This value
3616 in this field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual
3617 number of logical processors available to BIOS/OS/Applications may be different from the
3618 value of EBX[15:0], depending on software and platform hardware configurations.
3620 @param EAX CPUID_V2_EXTENDED_TOPOLOGY (0x1F)
3621 @param ECX Level number
3624 #define CPUID_V2_EXTENDED_TOPOLOGY 0x1F
3627 /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
3628 /// The value of the "level type" field is not related to level numbers in
3629 /// any way, higher "level type" values do not mean higher levels.
3631 #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03
3632 #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04
3633 #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05
3639 CPUID Extended Function
3641 @param EAX CPUID_EXTENDED_FUNCTION (0x80000000)
3643 @retval EAX Maximum Input Value for Extended Function CPUID Information.
3644 @retval EBX Reserved.
3645 @retval ECX Reserved.
3646 @retval EDX Reserved.
3648 <b>Example usage</b>
3652 AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
3655 #define CPUID_EXTENDED_FUNCTION 0x80000000
3659 CPUID Extended Processor Signature and Feature Bits
3661 @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)
3663 @retval EAX CPUID_EXTENDED_CPU_SIG.
3664 @retval EBX Reserved.
3665 @retval ECX Extended Processor Signature and Feature Bits information
3666 described by the type CPUID_EXTENDED_CPU_SIG_ECX.
3667 @retval EDX Extended Processor Signature and Feature Bits information
3668 described by the type CPUID_EXTENDED_CPU_SIG_EDX.
3670 <b>Example usage</b>
3673 CPUID_EXTENDED_CPU_SIG_ECX Ecx;
3674 CPUID_EXTENDED_CPU_SIG_EDX Edx;
3676 AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);
3679 #define CPUID_EXTENDED_CPU_SIG 0x80000001
3682 CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf
3683 #CPUID_EXTENDED_CPU_SIG.
3687 /// Individual bit fields
3691 /// [Bit 0] LAHF/SAHF available in 64-bit mode.
3701 /// [Bit 8] PREFETCHW.
3704 UINT32 Reserved3
:23;
3707 /// All bit fields as a 32-bit value
3710 } CPUID_EXTENDED_CPU_SIG_ECX
;
3713 CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf
3714 #CPUID_EXTENDED_CPU_SIG.
3718 /// Individual bit fields
3721 UINT32 Reserved1
:11;
3723 /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.
3725 UINT32 SYSCALL_SYSRET
:1;
3728 /// [Bit 20] Execute Disable Bit available.
3733 /// [Bit 26] 1-GByte pages are available if 1.
3737 /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.
3742 /// [Bit 29] Intel(R) 64 Architecture available if 1.
3748 /// All bit fields as a 32-bit value
3751 } CPUID_EXTENDED_CPU_SIG_EDX
;
3755 CPUID Processor Brand String
3757 @param EAX CPUID_BRAND_STRING1 (0x80000002)
3759 @retval EAX Processor Brand String in type CPUID_BRAND_STRING_DATA.
3760 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3761 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3762 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3764 <b>Example usage</b>
3766 CPUID_BRAND_STRING_DATA Eax;
3767 CPUID_BRAND_STRING_DATA Ebx;
3768 CPUID_BRAND_STRING_DATA Ecx;
3769 CPUID_BRAND_STRING_DATA Edx;
3771 AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
3774 #define CPUID_BRAND_STRING1 0x80000002
3777 CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,
3778 #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3.
3782 /// 4 ASCII characters of Processor Brand String
3784 CHAR8 BrandString
[4];
3786 /// All fields as a 32-bit value
3789 } CPUID_BRAND_STRING_DATA
;
3792 CPUID Processor Brand String
3794 @param EAX CPUID_BRAND_STRING2 (0x80000003)
3796 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3797 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3798 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3799 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3801 <b>Example usage</b>
3803 CPUID_BRAND_STRING_DATA Eax;
3804 CPUID_BRAND_STRING_DATA Ebx;
3805 CPUID_BRAND_STRING_DATA Ecx;
3806 CPUID_BRAND_STRING_DATA Edx;
3808 AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
3811 #define CPUID_BRAND_STRING2 0x80000003
3814 CPUID Processor Brand String
3816 @param EAX CPUID_BRAND_STRING3 (0x80000004)
3818 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3819 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3820 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3821 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3823 <b>Example usage</b>
3825 CPUID_BRAND_STRING_DATA Eax;
3826 CPUID_BRAND_STRING_DATA Ebx;
3827 CPUID_BRAND_STRING_DATA Ecx;
3828 CPUID_BRAND_STRING_DATA Edx;
3830 AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
3833 #define CPUID_BRAND_STRING3 0x80000004
3837 CPUID Extended Cache information
3839 @param EAX CPUID_EXTENDED_CACHE_INFO (0x80000006)
3841 @retval EAX Reserved.
3842 @retval EBX Reserved.
3843 @retval ECX Extended cache information described by the type
3844 CPUID_EXTENDED_CACHE_INFO_ECX.
3845 @retval EDX Reserved.
3847 <b>Example usage</b>
3849 CPUID_EXTENDED_CACHE_INFO_ECX Ecx;
3851 AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);
3854 #define CPUID_EXTENDED_CACHE_INFO 0x80000006
3857 CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.
3861 /// Individual bit fields
3865 /// [Bits 7:0] Cache line size in bytes.
3867 UINT32 CacheLineSize
:8;
3870 /// [Bits 15:12] L2 Associativity field. Supported values are in the range
3871 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to
3872 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL
3874 UINT32 L2Associativity
:4;
3876 /// [Bits 31:16] Cache size in 1K units.
3878 UINT32 CacheSize
:16;
3881 /// All bit fields as a 32-bit value
3884 } CPUID_EXTENDED_CACHE_INFO_ECX
;
3887 /// @{ Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity
3889 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED 0x00
3890 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED 0x01
3891 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY 0x02
3892 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04
3893 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06
3894 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08
3895 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_32_WAY 0x0A
3896 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_48_WAY 0x0B
3897 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_64_WAY 0x0C
3898 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_96_WAY 0x0D
3899 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_128_WAY 0x0E
3900 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F
3906 CPUID Extended Time Stamp Counter information
3908 @param EAX CPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007)
3910 @retval EAX Reserved.
3911 @retval EBX Reserved.
3912 @retval ECX Reserved.
3913 @retval EDX Extended time stamp counter (TSC) information described by the
3914 type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX.
3916 <b>Example usage</b>
3918 CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;
3920 AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);
3923 #define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007
3926 CPUID Extended Time Stamp Counter information EDX for CPUID leaf
3927 #CPUID_EXTENDED_TIME_STAMP_COUNTER.
3931 /// Individual bit fields
3936 /// [Bit 8] Invariant TSC available if 1.
3938 UINT32 InvariantTsc
:1;
3939 UINT32 Reserved2
:23;
3942 /// All bit fields as a 32-bit value
3945 } CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX
;
3949 CPUID Linear Physical Address Size
3951 @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
3953 @retval EAX Linear/Physical Address Size described by the type
3954 CPUID_VIR_PHY_ADDRESS_SIZE_EAX.
3955 @retval EBX Reserved.
3956 @retval ECX Reserved.
3957 @retval EDX Reserved.
3959 <b>Example usage</b>
3961 CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;
3963 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);
3966 #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
3969 CPUID Linear Physical Address Size EAX for CPUID leaf
3970 #CPUID_VIR_PHY_ADDRESS_SIZE.
3974 /// Individual bit fields
3978 /// [Bits 7:0] Number of physical address bits.
3981 /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address
3982 /// number supported should come from this field.
3984 UINT32 PhysicalAddressBits
:8;
3986 /// [Bits 15:8] Number of linear address bits.
3988 UINT32 LinearAddressBits
:8;
3992 /// All bit fields as a 32-bit value
3995 } CPUID_VIR_PHY_ADDRESS_SIZE_EAX
;
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