2 CPUID leaf definitions.
\r
4 Provides defines for CPUID leaf indexes. Data structures are provided for
\r
5 registers returned by a CPUID leaf that contain one or more bit fields.
\r
6 If a register returned is a single 32-bit value, then a data structure is
\r
7 not provided for that register.
\r
9 Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
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10 This program and the accompanying materials are licensed and made available under
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11 the terms and conditions of the BSD License which accompanies this distribution.
\r
12 The full text of the license may be found at
\r
13 http://opensource.org/licenses/bsd-license.php
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15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
\r
18 @par Specification Reference:
\r
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,
\r
20 November 2018, CPUID instruction.
\r
28 CPUID Signature Information
\r
30 @param EAX CPUID_SIGNATURE (0x00)
\r
32 @retval EAX Returns the highest value the CPUID instruction recognizes for
\r
33 returning basic processor information. The value is returned is
\r
35 @retval EBX First 4 characters of a vendor identification string.
\r
36 @retval ECX Last 4 characters of a vendor identification string.
\r
37 @retval EDX Middle 4 characters of a vendor identification string.
\r
39 <b>Example usage</b>
\r
46 AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
\r
49 #define CPUID_SIGNATURE 0x00
\r
52 /// @{ CPUID signature values returned by Intel processors
\r
54 #define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u')
\r
55 #define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I')
\r
56 #define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l')
\r
63 CPUID Version Information
\r
65 @param EAX CPUID_VERSION_INFO (0x01)
\r
67 @retval EAX Returns Model, Family, Stepping Information described by the
\r
68 type CPUID_VERSION_INFO_EAX.
\r
69 @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by
\r
70 the type CPUID_VERSION_INFO_EBX.
\r
71 @retval ECX CPU Feature Information described by the type
\r
72 CPUID_VERSION_INFO_ECX.
\r
73 @retval EDX CPU Feature Information described by the type
\r
74 CPUID_VERSION_INFO_EDX.
\r
76 <b>Example usage</b>
\r
78 CPUID_VERSION_INFO_EAX Eax;
\r
79 CPUID_VERSION_INFO_EBX Ebx;
\r
80 CPUID_VERSION_INFO_ECX Ecx;
\r
81 CPUID_VERSION_INFO_EDX Edx;
\r
83 AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
\r
86 #define CPUID_VERSION_INFO 0x01
\r
89 CPUID Version Information returned in EAX for CPUID leaf
\r
90 #CPUID_VERSION_INFO.
\r
94 /// Individual bit fields
\r
97 UINT32 SteppingId:4; ///< [Bits 3:0] Stepping ID
\r
98 UINT32 Model:4; ///< [Bits 7:4] Model
\r
99 UINT32 FamilyId:4; ///< [Bits 11:8] Family
\r
100 UINT32 ProcessorType:2; ///< [Bits 13:12] Processor Type
\r
101 UINT32 Reserved1:2; ///< [Bits 15:14] Reserved
\r
102 UINT32 ExtendedModelId:4; ///< [Bits 19:16] Extended Model ID
\r
103 UINT32 ExtendedFamilyId:8; ///< [Bits 27:20] Extended Family ID
\r
104 UINT32 Reserved2:4; ///< Reserved
\r
107 /// All bit fields as a 32-bit value
\r
110 } CPUID_VERSION_INFO_EAX;
\r
113 /// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType
\r
115 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00
\r
116 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01
\r
117 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02
\r
123 CPUID Version Information returned in EBX for CPUID leaf
\r
124 #CPUID_VERSION_INFO.
\r
128 /// Individual bit fields
\r
132 /// [Bits 7:0] Provides an entry into a brand string table that contains
\r
133 /// brand strings for IA-32 processors.
\r
135 UINT32 BrandIndex:8;
\r
137 /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH
\r
138 /// and CLFLUSHOPT instructions in 8-byte increments. This field was
\r
139 /// introduced in the Pentium 4 processor.
\r
141 UINT32 CacheLineSize:8;
\r
143 /// [Bits 23:16] Maximum number of addressable IDs for logical processors
\r
144 /// in this physical package.
\r
147 /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is
\r
148 /// the number of unique initial APICIDs reserved for addressing different
\r
149 /// logical processors in a physical package. This field is only valid if
\r
150 /// CPUID.1.EDX.HTT[bit 28]= 1.
\r
152 UINT32 MaximumAddressableIdsForLogicalProcessors:8;
\r
154 /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the
\r
155 /// processor during power up. This field was introduced in the Pentium 4
\r
158 UINT32 InitialLocalApicId:8;
\r
161 /// All bit fields as a 32-bit value
\r
164 } CPUID_VERSION_INFO_EBX;
\r
167 CPUID Version Information returned in ECX for CPUID leaf
\r
168 #CPUID_VERSION_INFO.
\r
172 /// Individual bit fields
\r
176 /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the
\r
177 /// processor supports this technology
\r
181 /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ
\r
182 /// instruction. Carryless Multiplication
\r
184 UINT32 PCLMULQDQ:1;
\r
186 /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports
\r
187 /// DS area using 64-bit layout.
\r
191 /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports
\r
196 /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor
\r
197 /// supports the extensions to the Debug Store feature to allow for branch
\r
198 /// message storage qualified by CPL
\r
202 /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the
\r
203 /// processor supports this technology.
\r
207 /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor
\r
208 /// supports this technology
\r
212 /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates
\r
213 /// that the processor supports this technology
\r
217 /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor
\r
218 /// supports this technology
\r
222 /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming
\r
223 /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction
\r
224 /// extensions are not present in the processor.
\r
228 /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode
\r
229 /// can be set to either adaptive mode or shared mode. A value of 0 indicates
\r
230 /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR
\r
231 /// Bit 24 (L1 Data Cache Context Mode) for details
\r
235 /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE
\r
236 /// MSR for silicon debug
\r
240 /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple
\r
241 /// Add) extensions using YMM state.
\r
245 /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature
\r
248 UINT32 CMPXCHG16B:1;
\r
250 /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor
\r
251 /// supports changing IA32_MISC_ENABLE[Bit 23].
\r
253 UINT32 xTPR_Update_Control:1;
\r
255 /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the
\r
256 /// processor supports the performance and debug feature indication MSR
\r
257 /// IA32_PERF_CAPABILITIES.
\r
262 /// [Bit 17] Process-context identifiers. A value of 1 indicates that the
\r
263 /// processor supports PCIDs and that software may set CR4.PCIDE to 1.
\r
267 /// [Bit 18] A value of 1 indicates the processor supports the ability to
\r
268 /// prefetch data from a memory mapped device. Direct Cache Access.
\r
272 /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.
\r
276 /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.
\r
280 /// [Bit 21] A value of 1 indicates that the processor supports x2APIC
\r
285 /// [Bit 22] A value of 1 indicates that the processor supports MOVBE
\r
290 /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT
\r
295 /// [Bit 24] A value of 1 indicates that the processor's local APIC timer
\r
296 /// supports one-shot operation using a TSC deadline value.
\r
298 UINT32 TSC_Deadline:1;
\r
300 /// [Bit 25] A value of 1 indicates that the processor supports the AESNI
\r
301 /// instruction extensions.
\r
305 /// [Bit 26] A value of 1 indicates that the processor supports the
\r
306 /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV
\r
307 /// instructions, and XCR0.
\r
311 /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]
\r
312 /// to enable XSETBV/XGETBV instructions to access XCR0 and to support
\r
313 /// processor extended state management using XSAVE/XRSTOR.
\r
317 /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction
\r
322 /// [Bit 29] A value of 1 indicates that processor supports 16-bit
\r
323 /// floating-point conversion instructions.
\r
327 /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.
\r
331 /// [Bit 31] Always returns 0.
\r
336 /// All bit fields as a 32-bit value
\r
339 } CPUID_VERSION_INFO_ECX;
\r
342 CPUID Version Information returned in EDX for CPUID leaf
\r
343 #CPUID_VERSION_INFO.
\r
347 /// Individual bit fields
\r
351 /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.
\r
355 /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,
\r
356 /// including CR4.VME for controlling the feature, CR4.PVI for protected
\r
357 /// mode virtual interrupts, software interrupt indirection, expansion of
\r
358 /// the TSS with the software indirection bitmap, and EFLAGS.VIF and
\r
359 /// EFLAGS.VIP flags.
\r
363 /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including
\r
364 /// CR4.DE for controlling the feature, and optional trapping of accesses to
\r
369 /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,
\r
370 /// including CR4.PSE for controlling the feature, the defined dirty bit in
\r
371 /// PDE (Page Directory Entries), optional reserved bit trapping in CR3,
\r
372 /// PDEs, and PTEs.
\r
376 /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,
\r
377 /// including CR4.TSD for controlling privilege.
\r
381 /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The
\r
382 /// RDMSR and WRMSR instructions are supported. Some of the MSRs are
\r
383 /// implementation dependent.
\r
387 /// [Bit 6] Physical Address Extension. Physical addresses greater than 32
\r
388 /// bits are supported: extended page table entry formats, an extra level in
\r
389 /// the page translation tables is defined, 2-MByte pages are supported
\r
390 /// instead of 4 Mbyte pages if PAE bit is 1.
\r
394 /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine
\r
395 /// Checks, including CR4.MCE for controlling the feature. This feature does
\r
396 /// not define the model-specific implementations of machine-check error
\r
397 /// logging, reporting, and processor shutdowns. Machine Check exception
\r
398 /// handlers may have to depend on processor version to do model specific
\r
399 /// processing of the exception, or test for the presence of the Machine
\r
404 /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)
\r
405 /// instruction is supported (implicitly locked and atomic).
\r
409 /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable
\r
410 /// Interrupt Controller (APIC), responding to memory mapped commands in the
\r
411 /// physical address range FFFE0000H to FFFE0FFFH (by default - some
\r
412 /// processors permit the APIC to be relocated).
\r
415 UINT32 Reserved1:1;
\r
417 /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT
\r
418 /// and associated MSRs are supported.
\r
422 /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap
\r
423 /// MSR contains feature bits that describe what memory types are supported,
\r
424 /// how many variable MTRRs are supported, and whether fixed MTRRs are
\r
429 /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure
\r
430 /// entries that map a page, indicating TLB entries that are common to
\r
431 /// different processes and need not be flushed. The CR4.PGE bit controls
\r
436 /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine
\r
437 /// Check Architecture of reporting machine errors is supported. The MCG_CAP
\r
438 /// MSR contains feature bits describing how many banks of error reporting
\r
439 /// MSRs are supported.
\r
443 /// [Bit 15] Conditional Move Instructions. The conditional move instruction
\r
444 /// CMOV is supported. In addition, if x87 FPU is present as indicated by the
\r
445 /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.
\r
449 /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This
\r
450 /// feature augments the Memory Type Range Registers (MTRRs), allowing an
\r
451 /// operating system to specify attributes of memory accessed through a
\r
452 /// linear address on a 4KB granularity.
\r
456 /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical
\r
457 /// memory beyond 4 GBytes are supported with 32-bit paging. This feature
\r
458 /// indicates that upper bits of the physical address of a 4-MByte page are
\r
459 /// encoded in bits 20:13 of the page-directory entry. Such physical
\r
460 /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.
\r
464 /// [Bit 18] Processor Serial Number. The processor supports the 96-bit
\r
465 /// processor identification number feature and the feature is enabled.
\r
469 /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.
\r
472 UINT32 Reserved2:1;
\r
474 /// [Bit 21] Debug Store. The processor supports the ability to write debug
\r
475 /// information into a memory resident buffer. This feature is used by the
\r
476 /// branch trace store (BTS) and precise event-based sampling (PEBS)
\r
481 /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The
\r
482 /// processor implements internal MSRs that allow processor temperature to
\r
483 /// be monitored and processor performance to be modulated in predefined
\r
484 /// duty cycles under software control.
\r
488 /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX
\r
493 /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR
\r
494 /// instructions are supported for fast save and restore of the floating
\r
495 /// point context. Presence of this bit also indicates that CR4.OSFXSR is
\r
496 /// available for an operating system to indicate that it supports the
\r
497 /// FXSAVE and FXRSTOR instructions.
\r
501 /// [Bit 25] SSE. The processor supports the SSE extensions.
\r
505 /// [Bit 26] SSE2. The processor supports the SSE2 extensions.
\r
509 /// [Bit 27] Self Snoop. The processor supports the management of
\r
510 /// conflicting memory types by performing a snoop of its own cache
\r
511 /// structure for transactions issued to the bus.
\r
515 /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT
\r
516 /// indicates there is only a single logical processor in the package and
\r
517 /// software should assume only a single APIC ID is reserved. A value of 1
\r
518 /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of
\r
519 /// addressable IDs for logical processors in this package) is valid for the
\r
524 /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor
\r
525 /// automatic thermal control circuitry (TCC).
\r
528 UINT32 Reserved3:1;
\r
530 /// [Bit 31] Pending Break Enable. The processor supports the use of the
\r
531 /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is
\r
532 /// asserted) to signal the processor that an interrupt is pending and that
\r
533 /// the processor should return to normal operation to handle the interrupt.
\r
534 /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.
\r
539 /// All bit fields as a 32-bit value
\r
542 } CPUID_VERSION_INFO_EDX;
\r
546 CPUID Cache and TLB Information
\r
548 @param EAX CPUID_CACHE_INFO (0x02)
\r
550 @retval EAX Cache and TLB Information described by the type
\r
551 CPUID_CACHE_INFO_CACHE_TLB.
\r
552 CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns
\r
553 0x01 and must be ignored. Only valid if
\r
554 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
\r
555 @retval EBX Cache and TLB Information described by the type
\r
556 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
\r
557 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
\r
558 @retval ECX Cache and TLB Information described by the type
\r
559 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
\r
560 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
\r
561 @retval EDX Cache and TLB Information described by the type
\r
562 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
\r
563 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
\r
565 <b>Example usage</b>
\r
567 CPUID_CACHE_INFO_CACHE_TLB Eax;
\r
568 CPUID_CACHE_INFO_CACHE_TLB Ebx;
\r
569 CPUID_CACHE_INFO_CACHE_TLB Ecx;
\r
570 CPUID_CACHE_INFO_CACHE_TLB Edx;
\r
572 AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
\r
575 <b>Cache Descriptor values</b>
\r
577 <tr><th>Value </th><th> Type </th><th> Description </th></tr>
\r
578 <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr>
\r
579 <tr><td> 0x01 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr>
\r
580 <tr><td> 0x02 </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr>
\r
581 <tr><td> 0x03 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr>
\r
582 <tr><td> 0x04 </td><td> TLB </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr>
\r
583 <tr><td> 0x05 </td><td> TLB </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr>
\r
584 <tr><td> 0x06 </td><td> Cache </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative,
\r
585 32 byte line size</td></tr>
\r
586 <tr><td> 0x08 </td><td> Cache </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative,
\r
587 32 byte line size</td></tr>
\r
588 <tr><td> 0x09 </td><td> Cache </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative,
\r
589 64 byte line size</td></tr>
\r
590 <tr><td> 0x0A </td><td> Cache </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr>
\r
591 <tr><td> 0x0B </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr>
\r
592 <tr><td> 0x0C </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr>
\r
593 <tr><td> 0x0D </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr>
\r
594 <tr><td> 0x0E </td><td> Cache </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr>
\r
595 <tr><td> 0x1D </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr>
\r
596 <tr><td> 0x21 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr>
\r
597 <tr><td> 0x22 </td><td> Cache </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size,
\r
598 2 lines per sector</td></tr>
\r
599 <tr><td> 0x23 </td><td> Cache </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size,
\r
600 2 lines per sector</td></tr>
\r
601 <tr><td> 0x24 </td><td> Cache </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr>
\r
602 <tr><td> 0x25 </td><td> Cache </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size,
\r
603 2 lines per sector</td></tr>
\r
604 <tr><td> 0x29 </td><td> Cache </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size,
\r
605 2 lines per sector</td></tr>
\r
606 <tr><td> 0x2C </td><td> Cache </td><td> 1st-level data cache: 32 KBytes, 8-way set associative,
\r
607 64 byte line size</td></tr>
\r
608 <tr><td> 0x30 </td><td> Cache </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative,
\r
609 64 byte line size</td></tr>
\r
610 <tr><td> 0x40 </td><td> Cache </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache,
\r
611 no 3rd-level cache</td></tr>
\r
612 <tr><td> 0x41 </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr>
\r
613 <tr><td> 0x42 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr>
\r
614 <tr><td> 0x43 </td><td> Cache </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr>
\r
615 <tr><td> 0x44 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr>
\r
616 <tr><td> 0x45 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr>
\r
617 <tr><td> 0x46 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr>
\r
618 <tr><td> 0x47 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr>
\r
619 <tr><td> 0x48 </td><td> Cache </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr>
\r
620 <tr><td> 0x49 </td><td> Cache </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size
\r
621 (Intel Xeon processor MP, Family 0FH, Model 06H)<BR>
\r
622 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
\r
623 <tr><td> 0x4A </td><td> Cache </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr>
\r
624 <tr><td> 0x4B </td><td> Cache </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr>
\r
625 <tr><td> 0x4C </td><td> Cache </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr>
\r
626 <tr><td> 0x4D </td><td> Cache </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr>
\r
627 <tr><td> 0x4E </td><td> Cache </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr>
\r
628 <tr><td> 0x4F </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr>
\r
629 <tr><td> 0x50 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr>
\r
630 <tr><td> 0x51 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr>
\r
631 <tr><td> 0x52 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr>
\r
632 <tr><td> 0x55 </td><td> TLB </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr>
\r
633 <tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>
\r
634 <tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>
\r
635 <tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>
\r
636 <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>
\r
637 <tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>
\r
638 <tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>
\r
639 <tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>
\r
640 <tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>
\r
641 <tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>
\r
642 <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 2 MByte or 4 MByte pages, 4-way set associative,
\r
643 32 entries and a separate array with 1 GByte pages, 4-way set associative,
\r
644 4 entries</td></tr>
\r
645 <tr><td> 0x64 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 512 entries</td></tr>
\r
646 <tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>
\r
647 <tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>
\r
648 <tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>
\r
649 <tr><td> 0x6A </td><td> Cache </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr>
\r
650 <tr><td> 0x6B </td><td> Cache </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr>
\r
651 <tr><td> 0x6C </td><td> Cache </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr>
\r
652 <tr><td> 0x6D </td><td> Cache </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr>
\r
653 <tr><td> 0x70 </td><td> Cache </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr>
\r
654 <tr><td> 0x71 </td><td> Cache </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr>
\r
655 <tr><td> 0x72 </td><td> Cache </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr>
\r
656 <tr><td> 0x76 </td><td> TLB </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr>
\r
657 <tr><td> 0x78 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr>
\r
658 <tr><td> 0x79 </td><td> Cache </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size,
\r
659 2 lines per sector</td></tr>
\r
660 <tr><td> 0x7A </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size,
\r
661 2 lines per sector</td></tr>
\r
662 <tr><td> 0x7B </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size,
\r
663 2 lines per sector</td></tr>
\r
664 <tr><td> 0x7C </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size,
\r
665 2 lines per sector</td></tr>
\r
666 <tr><td> 0x7D </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr>
\r
667 <tr><td> 0x7F </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr>
\r
668 <tr><td> 0x80 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr>
\r
669 <tr><td> 0x82 </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr>
\r
670 <tr><td> 0x83 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr>
\r
671 <tr><td> 0x84 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr>
\r
672 <tr><td> 0x85 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr>
\r
673 <tr><td> 0x86 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
\r
674 <tr><td> 0x87 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
\r
675 <tr><td> 0xA0 </td><td> DTLB </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr>
\r
676 <tr><td> 0xB0 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
\r
677 <tr><td> 0xB1 </td><td> TLB </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr>
\r
678 <tr><td> 0xB2 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr>
\r
679 <tr><td> 0xB3 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
\r
680 <tr><td> 0xB4 </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr>
\r
681 <tr><td> 0xB5 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr>
\r
682 <tr><td> 0xB6 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative,
\r
683 128 entries</td></tr>
\r
684 <tr><td> 0xBA </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr>
\r
685 <tr><td> 0xC0 </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr>
\r
686 <tr><td> 0xC1 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative,
\r
687 1024 entries</td></tr>
\r
688 <tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>
\r
689 <tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,
\r
690 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>
\r
691 <tr><td> 0xC4 </td><td> DTLB </td><td> DTLB: 2M/4M Byte pages, 4-way associative, 32 entries</td></tr>
\r
692 <tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>
\r
693 <tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
\r
694 <tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>
\r
695 <tr><td> 0xD2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr>
\r
696 <tr><td> 0xD6 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
\r
697 <tr><td> 0xD7 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr>
\r
698 <tr><td> 0xD8 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr>
\r
699 <tr><td> 0xDC </td><td> Cache </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr>
\r
700 <tr><td> 0xDD </td><td> Cache </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr>
\r
701 <tr><td> 0xDE </td><td> Cache </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr>
\r
702 <tr><td> 0xE2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr>
\r
703 <tr><td> 0xE3 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
\r
704 <tr><td> 0xE4 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr>
\r
705 <tr><td> 0xEA </td><td> Cache </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr>
\r
706 <tr><td> 0xEB </td><td> Cache </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr>
\r
707 <tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr>
\r
708 <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr>
\r
709 <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr>
\r
710 <tr><td> 0xFE </td><td> General </td><td> CPUID leaf 2 does not report TLB descriptor information; use CPUID
\r
711 leaf 18H to query TLB and other address translation parameters.</td></tr>
\r
712 <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information,
\r
713 use CPUID leaf 4 to query cache parameters</td></tr>
\r
716 #define CPUID_CACHE_INFO 0x02
\r
719 CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID
\r
720 leaf #CPUID_CACHE_INFO.
\r
724 /// Individual bit fields
\r
727 UINT32 Reserved:31;
\r
729 /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.
\r
730 /// if 1, then none of the cache descriptor bytes in the register are valid.
\r
735 /// Array of Cache and TLB descriptor bytes
\r
737 UINT8 CacheDescriptor[4];
\r
739 /// All bit fields as a 32-bit value
\r
742 } CPUID_CACHE_INFO_CACHE_TLB;
\r
746 CPUID Processor Serial Number
\r
748 Processor serial number (PSN) is not supported in the Pentium 4 processor
\r
749 or later. On all models, use the PSN flag (returned using CPUID) to check
\r
750 for PSN support before accessing the feature.
\r
752 @param EAX CPUID_SERIAL_NUMBER (0x03)
\r
754 @retval EAX Reserved.
\r
755 @retval EBX Reserved.
\r
756 @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in
\r
757 Pentium III processor only; otherwise, the value in this
\r
758 register is reserved.)
\r
759 @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in
\r
760 Pentium III processor only; otherwise, the value in this
\r
761 register is reserved.)
\r
763 <b>Example usage</b>
\r
768 AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);
\r
771 #define CPUID_SERIAL_NUMBER 0x03
\r
775 CPUID Cache Parameters
\r
777 @param EAX CPUID_CACHE_PARAMS (0x04)
\r
778 @param ECX Cache Level. Valid values start at 0. Software can enumerate
\r
779 the deterministic cache parameters for each level of the cache
\r
780 hierarchy starting with an index value of 0, until the
\r
781 parameters report the value associated with the CacheType
\r
782 field in CPUID_CACHE_PARAMS_EAX is 0.
\r
784 @retval EAX Returns cache type information described by the type
\r
785 CPUID_CACHE_PARAMS_EAX.
\r
786 @retval EBX Returns cache line and associativity information described by
\r
787 the type CPUID_CACHE_PARAMS_EBX.
\r
788 @retval ECX Returns the number of sets in the cache.
\r
789 @retval EDX Returns cache WINVD/INVD behavior described by the type
\r
790 CPUID_CACHE_PARAMS_EDX.
\r
792 <b>Example usage</b>
\r
795 CPUID_CACHE_PARAMS_EAX Eax;
\r
796 CPUID_CACHE_PARAMS_EBX Ebx;
\r
798 CPUID_CACHE_PARAMS_EDX Edx;
\r
803 CPUID_CACHE_PARAMS, CacheLevel,
\r
804 &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32
\r
807 } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
\r
810 #define CPUID_CACHE_PARAMS 0x04
\r
813 CPUID Cache Parameters Information returned in EAX for CPUID leaf
\r
814 #CPUID_CACHE_PARAMS.
\r
818 /// Individual bit fields
\r
822 /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,
\r
823 /// then there is no information for the requested cache level.
\r
825 UINT32 CacheType:5;
\r
827 /// [Bits 7:5] Cache level (Starts at 1).
\r
829 UINT32 CacheLevel:3;
\r
831 /// [Bit 8] Self Initializing cache level (does not need SW initialization).
\r
833 UINT32 SelfInitializingCache:1;
\r
835 /// [Bit 9] Fully Associative cache.
\r
837 UINT32 FullyAssociativeCache:1;
\r
839 /// [Bits 13:10] Reserved.
\r
843 /// [Bits 25:14] Maximum number of addressable IDs for logical processors
\r
844 /// sharing this cache.
\r
846 /// Add one to the return value to get the result.
\r
847 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14])
\r
848 /// is the number of unique initial APIC IDs reserved for addressing
\r
849 /// different logical processors sharing this cache.
\r
851 UINT32 MaximumAddressableIdsForLogicalProcessors:12;
\r
853 /// [Bits 31:26] Maximum number of addressable IDs for processor cores in
\r
854 /// the physical package.
\r
856 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26])
\r
857 /// is the number of unique Core_IDs reserved for addressing different
\r
858 /// processor cores in a physical package. Core ID is a subset of bits of
\r
859 /// the initial APIC ID.
\r
860 /// The returned value is constant for valid initial values in ECX. Valid
\r
861 /// ECX values start from 0.
\r
863 UINT32 MaximumAddressableIdsForProcessorCores:6;
\r
866 /// All bit fields as a 32-bit value
\r
869 } CPUID_CACHE_PARAMS_EAX;
\r
872 /// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType
\r
874 #define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00
\r
875 #define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01
\r
876 #define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02
\r
877 #define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03
\r
883 CPUID Cache Parameters Information returned in EBX for CPUID leaf
\r
884 #CPUID_CACHE_PARAMS.
\r
888 /// Individual bit fields
\r
892 /// [Bits 11:0] System Coherency Line Size. Add one to the return value to
\r
893 /// get the result.
\r
895 UINT32 LineSize:12;
\r
897 /// [Bits 21:12] Physical Line Partitions. Add one to the return value to
\r
898 /// get the result.
\r
900 UINT32 LinePartitions:10;
\r
902 /// [Bits 31:22] Ways of associativity. Add one to the return value to get
\r
908 /// All bit fields as a 32-bit value
\r
911 } CPUID_CACHE_PARAMS_EBX;
\r
914 CPUID Cache Parameters Information returned in EDX for CPUID leaf
\r
915 #CPUID_CACHE_PARAMS.
\r
919 /// Individual bit fields
\r
923 /// [Bit 0] Write-Back Invalidate/Invalidate.
\r
924 /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level
\r
925 /// caches for threads sharing this cache.
\r
926 /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of
\r
927 /// non-originating threads sharing this cache.
\r
929 UINT32 Invalidate:1;
\r
931 /// [Bit 1] Cache Inclusiveness.
\r
932 /// 0 = Cache is not inclusive of lower cache levels.
\r
933 /// 1 = Cache is inclusive of lower cache levels.
\r
935 UINT32 CacheInclusiveness:1;
\r
937 /// [Bit 2] Complex Cache Indexing.
\r
938 /// 0 = Direct mapped cache.
\r
939 /// 1 = A complex function is used to index the cache, potentially using all
\r
942 UINT32 ComplexCacheIndexing:1;
\r
943 UINT32 Reserved:29;
\r
946 /// All bit fields as a 32-bit value
\r
949 } CPUID_CACHE_PARAMS_EDX;
\r
953 CPUID MONITOR/MWAIT Information
\r
955 @param EAX CPUID_MONITOR_MWAIT (0x05)
\r
957 @retval EAX Smallest monitor-line size in bytes described by the type
\r
958 CPUID_MONITOR_MWAIT_EAX.
\r
959 @retval EBX Largest monitor-line size in bytes described by the type
\r
960 CPUID_MONITOR_MWAIT_EBX.
\r
961 @retval ECX Enumeration of Monitor-Mwait extensions support described by
\r
962 the type CPUID_MONITOR_MWAIT_ECX.
\r
963 @retval EDX Sub C-states supported described by the type
\r
964 CPUID_MONITOR_MWAIT_EDX.
\r
966 <b>Example usage</b>
\r
968 CPUID_MONITOR_MWAIT_EAX Eax;
\r
969 CPUID_MONITOR_MWAIT_EBX Ebx;
\r
970 CPUID_MONITOR_MWAIT_ECX Ecx;
\r
971 CPUID_MONITOR_MWAIT_EDX Edx;
\r
973 AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
\r
976 #define CPUID_MONITOR_MWAIT 0x05
\r
979 CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf
\r
980 #CPUID_MONITOR_MWAIT.
\r
984 /// Individual bit fields
\r
988 /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's
\r
989 /// monitor granularity).
\r
991 UINT32 SmallestMonitorLineSize:16;
\r
992 UINT32 Reserved:16;
\r
995 /// All bit fields as a 32-bit value
\r
998 } CPUID_MONITOR_MWAIT_EAX;
\r
1001 CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf
\r
1002 #CPUID_MONITOR_MWAIT.
\r
1006 /// Individual bit fields
\r
1010 /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's
\r
1011 /// monitor granularity).
\r
1013 UINT32 LargestMonitorLineSize:16;
\r
1014 UINT32 Reserved:16;
\r
1017 /// All bit fields as a 32-bit value
\r
1020 } CPUID_MONITOR_MWAIT_EBX;
\r
1023 CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf
\r
1024 #CPUID_MONITOR_MWAIT.
\r
1028 /// Individual bit fields
\r
1032 /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,
\r
1033 /// and EDX are valid.
\r
1035 UINT32 ExtensionsSupported:1;
\r
1037 /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when
\r
1038 /// interrupts disabled.
\r
1040 UINT32 InterruptAsBreak:1;
\r
1041 UINT32 Reserved:30;
\r
1044 /// All bit fields as a 32-bit value
\r
1047 } CPUID_MONITOR_MWAIT_ECX;
\r
1050 CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf
\r
1051 #CPUID_MONITOR_MWAIT.
\r
1054 The definition of C0 through C7 states for MWAIT extension are
\r
1055 processor-specific C-states, not ACPI C-states.
\r
1059 /// Individual bit fields
\r
1063 /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.
\r
1065 UINT32 C0States:4;
\r
1067 /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.
\r
1069 UINT32 C1States:4;
\r
1071 /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.
\r
1073 UINT32 C2States:4;
\r
1075 /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.
\r
1077 UINT32 C3States:4;
\r
1079 /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.
\r
1081 UINT32 C4States:4;
\r
1083 /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.
\r
1085 UINT32 C5States:4;
\r
1087 /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.
\r
1089 UINT32 C6States:4;
\r
1091 /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.
\r
1093 UINT32 C7States:4;
\r
1096 /// All bit fields as a 32-bit value
\r
1099 } CPUID_MONITOR_MWAIT_EDX;
\r
1103 CPUID Thermal and Power Management
\r
1105 @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06)
\r
1107 @retval EAX Thermal and power management features described by the type
\r
1108 CPUID_THERMAL_POWER_MANAGEMENT_EAX.
\r
1109 @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor
\r
1110 described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX.
\r
1111 @retval ECX Performance features described by the type
\r
1112 CPUID_THERMAL_POWER_MANAGEMENT_ECX.
\r
1113 @retval EDX Reserved.
\r
1115 <b>Example usage</b>
\r
1117 CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;
\r
1118 CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;
\r
1119 CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;
\r
1121 AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
\r
1124 #define CPUID_THERMAL_POWER_MANAGEMENT 0x06
\r
1127 CPUID Thermal and Power Management Information returned in EAX for CPUID leaf
\r
1128 #CPUID_THERMAL_POWER_MANAGEMENT.
\r
1132 /// Individual bit fields
\r
1136 /// [Bit 0] Digital temperature sensor is supported if set.
\r
1138 UINT32 DigitalTemperatureSensor:1;
\r
1140 /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).
\r
1142 UINT32 TurboBoostTechnology:1;
\r
1144 /// [Bit 2] APIC-Timer-always-running feature is supported if set.
\r
1147 UINT32 Reserved1:1;
\r
1149 /// [Bit 4] Power limit notification controls are supported if set.
\r
1153 /// [Bit 5] Clock modulation duty cycle extension is supported if set.
\r
1157 /// [Bit 6] Package thermal management is supported if set.
\r
1161 /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,
\r
1162 /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
\r
1166 /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.
\r
1168 UINT32 HWP_Notification:1;
\r
1170 /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.
\r
1172 UINT32 HWP_Activity_Window:1;
\r
1174 /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.
\r
1176 UINT32 HWP_Energy_Performance_Preference:1;
\r
1178 /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.
\r
1180 UINT32 HWP_Package_Level_Request:1;
\r
1181 UINT32 Reserved2:1;
\r
1183 /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,
\r
1184 /// IA32_THREAD_STALL MSRs are supported if set.
\r
1188 /// [Bit 14] Intel Turbo Boost Max Technology 3.0 available.
\r
1190 UINT32 TurboBoostMaxTechnology30:1;
\r
1192 /// [Bit 15] HWP Capabilities.
\r
1193 /// Highest Performance change is supported if set.
\r
1195 UINT32 HWPCapabilities:1;
\r
1197 /// [Bit 16] HWP PECI override is supported if set.
\r
1199 UINT32 HWPPECIOverride:1;
\r
1201 /// [Bit 17] Flexible HWP is supported if set.
\r
1203 UINT32 FlexibleHWP:1;
\r
1205 /// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.
\r
1207 UINT32 FastAccessMode:1;
\r
1208 UINT32 Reserved4:1;
\r
1210 /// [Bit 20] Ignoring Idle Logical Processor HWP request is supported if set.
\r
1212 UINT32 IgnoringIdleLogicalProcessorHWPRequest:1;
\r
1213 UINT32 Reserved5:11;
\r
1216 /// All bit fields as a 32-bit value
\r
1219 } CPUID_THERMAL_POWER_MANAGEMENT_EAX;
\r
1222 CPUID Thermal and Power Management Information returned in EBX for CPUID leaf
\r
1223 #CPUID_THERMAL_POWER_MANAGEMENT.
\r
1227 /// Individual bit fields
\r
1231 /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.
\r
1233 UINT32 InterruptThresholds:4;
\r
1234 UINT32 Reserved:28;
\r
1237 /// All bit fields as a 32-bit value
\r
1240 } CPUID_THERMAL_POWER_MANAGEMENT_EBX;
\r
1243 CPUID Thermal and Power Management Information returned in ECX for CPUID leaf
\r
1244 #CPUID_THERMAL_POWER_MANAGEMENT.
\r
1248 /// Individual bit fields
\r
1252 /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF
\r
1253 /// and IA32_APERF). The capability to provide a measure of delivered
\r
1254 /// processor performance (since last reset of the counters), as a percentage
\r
1255 /// of the expected processor performance when running at the TSC frequency.
\r
1257 UINT32 HardwareCoordinationFeedback:1;
\r
1258 UINT32 Reserved1:2;
\r
1260 /// [Bit 3] If this bit is set, then the processor supports performance-energy
\r
1261 /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS
\r
1264 UINT32 PerformanceEnergyBias:1;
\r
1265 UINT32 Reserved2:28;
\r
1268 /// All bit fields as a 32-bit value
\r
1271 } CPUID_THERMAL_POWER_MANAGEMENT_ECX;
\r
1275 CPUID Structured Extended Feature Flags Enumeration
\r
1277 @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)
\r
1278 @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00).
\r
1281 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
\r
1282 index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.
\r
1284 @retval EAX The maximum input value for ECX to retrieve sub-leaf information.
\r
1285 @retval EBX Structured Extended Feature Flags described by the type
\r
1286 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX.
\r
1287 @retval EBX Structured Extended Feature Flags described by the type
\r
1288 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX.
\r
1289 @retval EDX Reserved.
\r
1291 <b>Example usage</b>
\r
1294 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
\r
1295 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;
\r
1299 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
\r
1300 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
\r
1301 &Eax, NULL, NULL, NULL
\r
1303 for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {
\r
1305 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
\r
1307 NULL, &Ebx.Uint32, &Ecx.Uint32, NULL
\r
1312 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07
\r
1315 /// CPUID Structured Extended Feature Flags Enumeration sub-leaf
\r
1317 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00
\r
1320 CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf
\r
1321 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
\r
1322 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
\r
1326 /// Individual bit fields
\r
1330 /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
\r
1332 UINT32 FSGSBASE:1;
\r
1334 /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.
\r
1336 UINT32 IA32_TSC_ADJUST:1;
\r
1338 /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT
\r
1339 /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".
\r
1343 /// [Bit 3] If 1 indicates the processor supports the first group of advanced
\r
1344 /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)
\r
1348 /// [Bit 4] Hardware Lock Elision
\r
1352 /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.
\r
1356 /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.
\r
1358 UINT32 FDP_EXCPTN_ONLY:1;
\r
1360 /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.
\r
1364 /// [Bit 8] If 1 indicates the processor supports the second group of
\r
1365 /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,
\r
1366 /// SARX, SHLX, SHRX)
\r
1370 /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.
\r
1372 UINT32 EnhancedRepMovsbStosb:1;
\r
1374 /// [Bit 10] If 1, supports INVPCID instruction for system software that
\r
1375 /// manages process-context identifiers.
\r
1379 /// [Bit 11] Restricted Transactional Memory
\r
1383 /// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
\r
1384 /// Monitoring capability if 1.
\r
1388 /// [Bit 13] Deprecates FPU CS and FPU DS values if 1.
\r
1390 UINT32 DeprecateFpuCsDs:1;
\r
1392 /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.
\r
1396 /// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
\r
1397 /// Allocation capability if 1.
\r
1401 /// [Bit 16] AVX512F.
\r
1405 /// [Bit 17] AVX512DQ.
\r
1407 UINT32 AVX512DQ:1;
\r
1409 /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.
\r
1413 /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX
\r
1418 /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC
\r
1419 /// instructions) if 1.
\r
1423 /// [Bit 21] AVX512_IFMA.
\r
1425 UINT32 AVX512_IFMA:1;
\r
1426 UINT32 Reserved6:1;
\r
1428 /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.
\r
1430 UINT32 CLFLUSHOPT:1;
\r
1432 /// [Bit 24] If 1 indicates the processor supports the CLWB instruction.
\r
1436 /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace
\r
1439 UINT32 IntelProcessorTrace:1;
\r
1441 /// [Bit 26] AVX512PF. (Intel Xeon Phi only.).
\r
1443 UINT32 AVX512PF:1;
\r
1445 /// [Bit 27] AVX512ER. (Intel Xeon Phi only.).
\r
1447 UINT32 AVX512ER:1;
\r
1449 /// [Bit 28] AVX512CD.
\r
1451 UINT32 AVX512CD:1;
\r
1453 /// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R)
\r
1454 /// SHA Extensions) if 1.
\r
1458 /// [Bit 30] AVX512BW.
\r
1460 UINT32 AVX512BW:1;
\r
1462 /// [Bit 31] AVX512VL.
\r
1464 UINT32 AVX512VL:1;
\r
1467 /// All bit fields as a 32-bit value
\r
1470 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX;
\r
1473 CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf
\r
1474 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
\r
1475 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
\r
1479 /// Individual bit fields
\r
1483 /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.
\r
1484 /// (Intel Xeon Phi only.)
\r
1486 UINT32 PREFETCHWT1:1;
\r
1488 /// [Bit 1] AVX512_VBMI.
\r
1490 UINT32 AVX512_VBMI:1;
\r
1492 /// [Bit 2] Supports user-mode instruction prevention if 1.
\r
1496 /// [Bit 3] Supports protection keys for user-mode pages if 1.
\r
1500 /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the
\r
1501 /// RDPKRU/WRPKRU instructions).
\r
1504 UINT32 Reserved5:9;
\r
1506 /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).
\r
1508 UINT32 AVX512_VPOPCNTDQ:1;
\r
1509 UINT32 Reserved7:1;
\r
1511 /// [Bits 16] Supports 5-level paging if 1.
\r
1513 UINT32 FiveLevelPage:1;
\r
1515 /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions
\r
1516 /// in 64-bit mode.
\r
1520 /// [Bit 22] RDPID and IA32_TSC_AUX are available if 1.
\r
1523 UINT32 Reserved3:7;
\r
1525 /// [Bit 30] Supports SGX Launch Configuration if 1.
\r
1528 UINT32 Reserved4:1;
\r
1531 /// All bit fields as a 32-bit value
\r
1534 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX;
\r
1537 CPUID Structured Extended Feature Flags Enumeration in EDX for CPUID leaf
\r
1538 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
\r
1539 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
\r
1543 /// Individual bit fields
\r
1547 /// [Bit 1:0] Reserved.
\r
1549 UINT32 Reserved1:2;
\r
1551 /// [Bit 2] AVX512_4VNNIW. (Intel Xeon Phi only.)
\r
1553 UINT32 AVX512_4VNNIW:1;
\r
1555 /// [Bit 3] AVX512_4FMAPS. (Intel Xeon Phi only.)
\r
1557 UINT32 AVX512_4FMAPS:1;
\r
1559 /// [Bit 25:4] Reserved.
\r
1561 UINT32 Reserved2:22;
\r
1563 /// [Bit 26] Enumerates support for indirect branch restricted speculation
\r
1564 /// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors
\r
1565 /// that set this bit support the IA32_SPEC_CTRL MSR and the IA32_PRED_CMD
\r
1566 /// MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS) and
\r
1567 /// IA32_PRED_CMD[0] (IBPB).
\r
1569 UINT32 EnumeratesSupportForIBRSAndIBPB:1;
\r
1571 /// [Bit 27] Enumerates support for single thread indirect branch
\r
1572 /// predictors (STIBP). Processors that set this bit support the
\r
1573 /// IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[1]
\r
1576 UINT32 EnumeratesSupportForSTIBP:1;
\r
1578 /// [Bit 28] Enumerates support for L1D_FLUSH. Processors that set this bit
\r
1579 /// support the IA32_FLUSH_CMD MSR. They allow software to set
\r
1580 /// IA32_FLUSH_CMD[0] (L1D_FLUSH).
\r
1582 UINT32 EnumeratesSupportForL1D_FLUSH:1;
\r
1584 /// [Bit 29] Enumerates support for the IA32_ARCH_CAPABILITIES MSR.
\r
1586 UINT32 EnumeratesSupportForCapability:1;
\r
1588 /// [Bit 30] Reserved.
\r
1590 UINT32 Reserved3:1;
\r
1592 /// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD).
\r
1593 /// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow
\r
1594 /// software to set IA32_SPEC_CTRL[2] (SSBD).
\r
1596 UINT32 EnumeratesSupportForSSBD:1;
\r
1599 /// All bit fields as a 32-bit value
\r
1602 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX;
\r
1605 CPUID Direct Cache Access Information
\r
1607 @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09)
\r
1609 @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).
\r
1610 @retval EBX Reserved.
\r
1611 @retval ECX Reserved.
\r
1612 @retval EDX Reserved.
\r
1614 <b>Example usage</b>
\r
1618 AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);
\r
1621 #define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09
\r
1625 CPUID Architectural Performance Monitoring
\r
1627 @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A)
\r
1629 @retval EAX Architectural Performance Monitoring information described by
\r
1630 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX.
\r
1631 @retval EBX Architectural Performance Monitoring information described by
\r
1632 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX.
\r
1633 @retval ECX Reserved.
\r
1634 @retval EDX Architectural Performance Monitoring information described by
\r
1635 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX.
\r
1637 <b>Example usage</b>
\r
1639 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;
\r
1640 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;
\r
1641 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;
\r
1643 AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);
\r
1646 #define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A
\r
1649 CPUID Architectural Performance Monitoring EAX for CPUID leaf
\r
1650 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
\r
1654 /// Individual bit fields
\r
1658 /// [Bit 7:0] Version ID of architectural performance monitoring.
\r
1660 UINT32 ArchPerfMonVerID:8;
\r
1662 /// [Bits 15:8] Number of general-purpose performance monitoring counter
\r
1663 /// per logical processor.
\r
1665 /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous
\r
1666 /// block of MSR address space. Each performance event select register is
\r
1667 /// paired with a corresponding performance counter in the 0C1H address
\r
1670 UINT32 PerformanceMonitorCounters:8;
\r
1672 /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.
\r
1674 /// The bit width of an IA32_PMCx MSR. This the number of valid bits for
\r
1675 /// read operation. On write operations, the lower-order 32 bits of the MSR
\r
1676 /// may be written with any value, and the high-order bits are sign-extended
\r
1677 /// from the value of bit 31.
\r
1679 UINT32 PerformanceMonitorCounterWidth:8;
\r
1681 /// [Bits 31:24] Length of EBX bit vector to enumerate architectural
\r
1682 /// performance monitoring events.
\r
1684 UINT32 EbxBitVectorLength:8;
\r
1687 /// All bit fields as a 32-bit value
\r
1690 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX;
\r
1693 CPUID Architectural Performance Monitoring EBX for CPUID leaf
\r
1694 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
\r
1698 /// Individual bit fields
\r
1702 /// [Bit 0] Core cycle event not available if 1.
\r
1704 UINT32 UnhaltedCoreCycles:1;
\r
1706 /// [Bit 1] Instruction retired event not available if 1.
\r
1708 UINT32 InstructionsRetired:1;
\r
1710 /// [Bit 2] Reference cycles event not available if 1.
\r
1712 UINT32 UnhaltedReferenceCycles:1;
\r
1714 /// [Bit 3] Last-level cache reference event not available if 1.
\r
1716 UINT32 LastLevelCacheReferences:1;
\r
1718 /// [Bit 4] Last-level cache misses event not available if 1.
\r
1720 UINT32 LastLevelCacheMisses:1;
\r
1722 /// [Bit 5] Branch instruction retired event not available if 1.
\r
1724 UINT32 BranchInstructionsRetired:1;
\r
1726 /// [Bit 6] Branch mispredict retired event not available if 1.
\r
1728 UINT32 AllBranchMispredictRetired:1;
\r
1729 UINT32 Reserved:25;
\r
1732 /// All bit fields as a 32-bit value
\r
1735 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX;
\r
1738 CPUID Architectural Performance Monitoring EDX for CPUID leaf
\r
1739 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
\r
1743 /// Individual bit fields
\r
1747 /// [Bits 4:0] Number of fixed-function performance counters
\r
1748 /// (if Version ID > 1).
\r
1750 UINT32 FixedFunctionPerformanceCounters:5;
\r
1752 /// [Bits 12:5] Bit width of fixed-function performance counters
\r
1753 /// (if Version ID > 1).
\r
1755 UINT32 FixedFunctionPerformanceCounterWidth:8;
\r
1756 UINT32 Reserved1:2;
\r
1758 /// [Bits 15] AnyThread deprecation.
\r
1760 UINT32 AnyThreadDeprecation:1;
\r
1761 UINT32 Reserved2:16;
\r
1764 /// All bit fields as a 32-bit value
\r
1767 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX;
\r
1771 CPUID Extended Topology Information
\r
1774 CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first
\r
1775 checking for the existence of Leaf 1FH before using leaf 0BH.
\r
1776 Most of Leaf 0BH output depends on the initial value in ECX. The EDX output
\r
1777 of leaf 0BH is always valid and does not vary with input value in ECX. Output
\r
1778 value in ECX[7:0] always equals input value in ECX[7:0].
\r
1779 Sub-leaf index 0 enumerates SMT level. Each subsequent higher sub-leaf index
\r
1780 enumerates a higher-level topological entity in hierarchical order.
\r
1781 For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and
\r
1782 EBX will return 0.
\r
1783 If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],
\r
1784 other input values with ECX > n also return 0 in ECX[15:8].
\r
1786 @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B)
\r
1787 @param ECX Level number
\r
1789 @retval EAX Extended topology information described by the type
\r
1790 CPUID_EXTENDED_TOPOLOGY_EAX.
\r
1791 @retval EBX Extended topology information described by the type
\r
1792 CPUID_EXTENDED_TOPOLOGY_EBX.
\r
1793 @retval ECX Extended topology information described by the type
\r
1794 CPUID_EXTENDED_TOPOLOGY_ECX.
\r
1795 @retval EDX x2APIC ID the current logical processor.
\r
1797 <b>Example usage</b>
\r
1799 CPUID_EXTENDED_TOPOLOGY_EAX Eax;
\r
1800 CPUID_EXTENDED_TOPOLOGY_EBX Ebx;
\r
1801 CPUID_EXTENDED_TOPOLOGY_ECX Ecx;
\r
1803 UINT32 LevelNumber;
\r
1808 CPUID_EXTENDED_TOPOLOGY, LevelNumber,
\r
1809 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx
\r
1812 } while (Eax.Bits.ApicIdShift != 0);
\r
1815 #define CPUID_EXTENDED_TOPOLOGY 0x0B
\r
1818 CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
\r
1822 /// Individual bit fields
\r
1826 /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique
\r
1827 /// topology ID of the next level type. All logical processors with the
\r
1828 /// same next level ID share current level.
\r
1831 /// Software should use this field (EAX[4:0]) to enumerate processor
\r
1832 /// topology of the system.
\r
1834 UINT32 ApicIdShift:5;
\r
1835 UINT32 Reserved:27;
\r
1838 /// All bit fields as a 32-bit value
\r
1841 } CPUID_EXTENDED_TOPOLOGY_EAX;
\r
1844 CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
\r
1848 /// Individual bit fields
\r
1852 /// [Bits 15:0] Number of logical processors at this level type. The number
\r
1853 /// reflects configuration as shipped by Intel.
\r
1856 /// Software must not use EBX[15:0] to enumerate processor topology of the
\r
1857 /// system. This value in this field (EBX[15:0]) is only intended for
\r
1858 /// display/diagnostic purposes. The actual number of logical processors
\r
1859 /// available to BIOS/OS/Applications may be different from the value of
\r
1860 /// EBX[15:0], depending on software and platform hardware configurations.
\r
1862 UINT32 LogicalProcessors:16;
\r
1863 UINT32 Reserved:16;
\r
1866 /// All bit fields as a 32-bit value
\r
1869 } CPUID_EXTENDED_TOPOLOGY_EBX;
\r
1872 CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
\r
1876 /// Individual bit fields
\r
1880 /// [Bits 7:0] Level number. Same value in ECX input.
\r
1882 UINT32 LevelNumber:8;
\r
1884 /// [Bits 15:8] Level type.
\r
1887 /// The value of the "level type" field is not related to level numbers in
\r
1888 /// any way, higher "level type" values do not mean higher levels.
\r
1890 UINT32 LevelType:8;
\r
1891 UINT32 Reserved:16;
\r
1894 /// All bit fields as a 32-bit value
\r
1897 } CPUID_EXTENDED_TOPOLOGY_ECX;
\r
1900 /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
\r
1902 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00
\r
1903 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01
\r
1904 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02
\r
1911 CPUID Extended State Information
\r
1913 @param EAX CPUID_EXTENDED_STATE (0x0D)
\r
1914 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00).
\r
1915 CPUID_EXTENDED_STATE_SUB_LEAF (0x01).
\r
1916 CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).
\r
1917 Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.
\r
1919 #define CPUID_EXTENDED_STATE 0x0D
\r
1922 CPUID Extended State Information Main Leaf
\r
1924 @param EAX CPUID_EXTENDED_STATE (0x0D)
\r
1925 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)
\r
1927 @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n]
\r
1928 can be set to 1 only if EAX[n] is 1. The format of the extended
\r
1929 state main leaf is described by the type
\r
1930 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX.
\r
1931 @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
\r
1932 area) required by enabled features in XCR0. May be different than
\r
1933 ECX if some features at the end of the XSAVE save area are not
\r
1935 @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
\r
1936 area) of the XSAVE/XRSTOR save area required by all supported
\r
1937 features in the processor, i.e., all the valid bit fields in XCR0.
\r
1938 @retval EDX Reports the supported bits of the upper 32 bits of XCR0.
\r
1939 XCR0[n+32] can be set to 1 only if EDX[n] is 1.
\r
1941 <b>Example usage</b>
\r
1943 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;
\r
1949 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,
\r
1950 &Eax.Uint32, &Ebx, &Ecx, &Edx
\r
1954 #define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00
\r
1957 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
\r
1958 sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF.
\r
1962 /// Individual bit fields
\r
1966 /// [Bit 0] x87 state.
\r
1970 /// [Bit 1] SSE state.
\r
1974 /// [Bit 2] AVX state.
\r
1978 /// [Bits 4:3] MPX state.
\r
1982 /// [Bits 7:5] AVX-512 state.
\r
1986 /// [Bit 8] Used for IA32_XSS.
\r
1988 UINT32 IA32_XSS:1;
\r
1990 /// [Bit 9] PKRU state.
\r
1993 UINT32 Reserved1:3;
\r
1995 /// [Bit 13] Used for IA32_XSS, part 2.
\r
1997 UINT32 IA32_XSS_2:1;
\r
1998 UINT32 Reserved2:18;
\r
2001 /// All bit fields as a 32-bit value
\r
2004 } CPUID_EXTENDED_STATE_MAIN_LEAF_EAX;
\r
2007 CPUID Extended State Information Sub Leaf
\r
2009 @param EAX CPUID_EXTENDED_STATE (0x0D)
\r
2010 @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01)
\r
2012 @retval EAX The format of the extended state sub-leaf is described by the
\r
2013 type CPUID_EXTENDED_STATE_SUB_LEAF_EAX.
\r
2014 @retval EBX The size in bytes of the XSAVE area containing all states
\r
2015 enabled by XCRO | IA32_XSS.
\r
2016 @retval ECX The format of the extended state sub-leaf is described by the
\r
2017 type CPUID_EXTENDED_STATE_SUB_LEAF_ECX.
\r
2018 @retval EDX Reports the supported bits of the upper 32 bits of the
\r
2019 IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.
\r
2021 <b>Example usage</b>
\r
2023 CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;
\r
2025 CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;
\r
2029 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,
\r
2030 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx
\r
2034 #define CPUID_EXTENDED_STATE_SUB_LEAF 0x01
\r
2037 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
\r
2038 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
\r
2042 /// Individual bit fields
\r
2046 /// [Bit 0] XSAVEOPT is available.
\r
2048 UINT32 XSAVEOPT:1;
\r
2050 /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.
\r
2054 /// [Bit 2] Supports XGETBV with ECX = 1 if set.
\r
2058 /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.
\r
2061 UINT32 Reserved:28;
\r
2064 /// All bit fields as a 32-bit value
\r
2067 } CPUID_EXTENDED_STATE_SUB_LEAF_EAX;
\r
2070 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
\r
2071 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
\r
2075 /// Individual bit fields
\r
2079 /// [Bits 7:0] Used for XCR0.
\r
2083 /// [Bit 8] PT STate.
\r
2087 /// [Bit 9] Used for XCR0.
\r
2090 UINT32 Reserved1:3;
\r
2092 /// [Bit 13] HWP state.
\r
2094 UINT32 HWPState:1;
\r
2095 UINT32 Reserved8:18;
\r
2098 /// All bit fields as a 32-bit value
\r
2101 } CPUID_EXTENDED_STATE_SUB_LEAF_ECX;
\r
2104 CPUID Extended State Information Size and Offset Sub Leaf
\r
2107 Leaf 0DH output depends on the initial value in ECX.
\r
2108 Each sub-leaf index (starting at position 2) is supported if it corresponds to
\r
2109 a supported bit in either the XCR0 register or the IA32_XSS MSR.
\r
2110 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
\r
2111 n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1
\r
2112 returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0
\r
2113 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].
\r
2115 @param EAX CPUID_EXTENDED_STATE (0x0D)
\r
2116 @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based
\r
2117 on supported bits in XCR0 or IA32_XSS_MSR.
\r
2119 @retval EAX The size in bytes (from the offset specified in EBX) of the save
\r
2120 area for an extended state feature associated with a valid
\r
2121 sub-leaf index, n.
\r
2122 @retval EBX The offset in bytes of this extended state component's save area
\r
2123 from the beginning of the XSAVE/XRSTOR area. This field reports
\r
2124 0 if the sub-leaf index, n, does not map to a valid bit in the
\r
2126 @retval ECX The format of the extended state components's save area as
\r
2127 described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX.
\r
2128 This field reports 0 if the sub-leaf index, n, is invalid.
\r
2129 @retval EDX This field reports 0 if the sub-leaf index, n, is invalid;
\r
2130 otherwise it is reserved.
\r
2132 <b>Example usage</b>
\r
2136 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;
\r
2140 for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {
\r
2142 CPUID_EXTENDED_STATE, SubLeaf,
\r
2143 &Eax, &Ebx, &Ecx.Uint32, &Edx
\r
2148 #define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02
\r
2151 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
\r
2152 sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET.
\r
2156 /// Individual bit fields
\r
2160 /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is
\r
2161 /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported
\r
2166 /// [Bit 1] is set if, when the compacted format of an XSAVE area is used,
\r
2167 /// this extended state component located on the next 64-byte boundary
\r
2168 /// following the preceding state component (otherwise, it is located
\r
2169 /// immediately following the preceding state component).
\r
2171 UINT32 Compacted:1;
\r
2172 UINT32 Reserved:30;
\r
2175 /// All bit fields as a 32-bit value
\r
2178 } CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX;
\r
2182 CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
\r
2184 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
\r
2185 @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00).
\r
2186 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).
\r
2189 #define CPUID_INTEL_RDT_MONITORING 0x0F
\r
2192 CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
\r
2193 Enumeration Sub-leaf
\r
2195 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
\r
2196 @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00)
\r
2198 @retval EAX Reserved.
\r
2199 @retval EBX Maximum range (zero-based) of RMID within this physical
\r
2200 processor of all types.
\r
2201 @retval ECX Reserved.
\r
2202 @retval EDX L3 Cache Intel RDT Monitoring Information Enumeration described by
\r
2203 the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX.
\r
2205 <b>Example usage</b>
\r
2208 CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
\r
2211 CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,
\r
2212 NULL, &Ebx, NULL, &Edx.Uint32
\r
2216 #define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00
\r
2219 CPUID Intel RDT Monitoring Information EDX for CPUID leaf
\r
2220 #CPUID_INTEL_RDT_MONITORING, sub-leaf
\r
2221 #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF.
\r
2225 /// Individual bit fields
\r
2228 UINT32 Reserved1:1;
\r
2230 /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.
\r
2232 UINT32 L3CacheRDT_M:1;
\r
2233 UINT32 Reserved2:30;
\r
2236 /// All bit fields as a 32-bit value
\r
2239 } CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX;
\r
2242 CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf
\r
2244 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
\r
2245 @param ECX CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01)
\r
2247 @retval EAX Reserved.
\r
2248 @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).
\r
2249 @retval ECX Maximum range (zero-based) of RMID of this resource type.
\r
2250 @retval EDX L3 Cache Intel RDT Monitoring Capability information described by the
\r
2251 type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX.
\r
2253 <b>Example usage</b>
\r
2257 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;
\r
2260 CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,
\r
2261 NULL, &Ebx, &Ecx, &Edx.Uint32
\r
2265 #define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01
\r
2268 CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf
\r
2269 #CPUID_INTEL_RDT_MONITORING, sub-leaf
\r
2270 #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF.
\r
2274 /// Individual bit fields
\r
2278 /// [Bit 0] Supports L3 occupancy monitoring if 1.
\r
2280 UINT32 L3CacheOccupancyMonitoring:1;
\r
2282 /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1.
\r
2284 UINT32 L3CacheTotalBandwidthMonitoring:1;
\r
2286 /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1.
\r
2288 UINT32 L3CacheLocalBandwidthMonitoring:1;
\r
2289 UINT32 Reserved:29;
\r
2292 /// All bit fields as a 32-bit value
\r
2295 } CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX;
\r
2299 CPUID Intel Resource Director Technology (Intel RDT) Allocation Information
\r
2301 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10).
\r
2302 @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).
\r
2303 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01).
\r
2304 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).
\r
2306 #define CPUID_INTEL_RDT_ALLOCATION 0x10
\r
2309 Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf
\r
2311 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
\r
2312 @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).
\r
2314 @retval EAX Reserved.
\r
2315 @retval EBX L3 and L2 Cache Allocation Technology information described by
\r
2316 the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX.
\r
2317 @retval ECX Reserved.
\r
2318 @retval EDX Reserved.
\r
2320 <b>Example usage</b>
\r
2322 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;
\r
2325 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,
\r
2326 NULL, &Ebx.Uint32, NULL, NULL
\r
2330 #define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00
\r
2333 CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf
\r
2334 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
\r
2335 #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF.
\r
2339 /// Individual bit fields
\r
2342 UINT32 Reserved1:1;
\r
2344 /// [Bit 1] Supports L3 Cache Allocation Technology if 1.
\r
2346 UINT32 L3CacheAllocation:1;
\r
2348 /// [Bit 2] Supports L2 Cache Allocation Technology if 1.
\r
2350 UINT32 L2CacheAllocation:1;
\r
2352 /// [Bit 3] Supports Memory Bandwidth Allocation if 1.
\r
2354 UINT32 MemoryBandwidth:1;
\r
2355 UINT32 Reserved3:28;
\r
2358 /// All bit fields as a 32-bit value
\r
2361 } CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX;
\r
2365 L3 Cache Allocation Technology Enumeration Sub-leaf
\r
2367 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
\r
2368 @param ECX CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01)
\r
2370 @retval EAX RESID L3 Cache Allocation Technology information described by
\r
2371 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX.
\r
2372 @retval EBX Bit-granular map of isolation/contention of allocation units.
\r
2373 @retval ECX RESID L3 Cache Allocation Technology information described by
\r
2374 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX.
\r
2375 @retval EDX RESID L3 Cache Allocation Technology information described by
\r
2376 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX.
\r
2378 <b>Example usage</b>
\r
2380 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;
\r
2382 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;
\r
2383 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;
\r
2386 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,
\r
2387 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32
\r
2391 #define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01
\r
2394 CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf
\r
2395 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
\r
2396 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
\r
2400 /// Individual bit fields
\r
2404 /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
\r
2405 /// using minus-one notation.
\r
2407 UINT32 CapacityLength:5;
\r
2408 UINT32 Reserved:27;
\r
2411 /// All bit fields as a 32-bit value
\r
2414 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX;
\r
2417 CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf
\r
2418 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
\r
2419 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
\r
2423 /// Individual bit fields
\r
2426 UINT32 Reserved3:2;
\r
2428 /// [Bit 2] Code and Data Prioritization Technology supported if 1.
\r
2430 UINT32 CodeDataPrioritization:1;
\r
2431 UINT32 Reserved2:29;
\r
2434 /// All bit fields as a 32-bit value
\r
2437 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX;
\r
2440 CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf
\r
2441 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
\r
2442 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
\r
2446 /// Individual bit fields
\r
2450 /// [Bits 15:0] Highest COS number supported for this ResID.
\r
2452 UINT32 HighestCosNumber:16;
\r
2453 UINT32 Reserved:16;
\r
2456 /// All bit fields as a 32-bit value
\r
2459 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX;
\r
2462 L2 Cache Allocation Technology Enumeration Sub-leaf
\r
2464 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
\r
2465 @param ECX CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02)
\r
2467 @retval EAX RESID L2 Cache Allocation Technology information described by
\r
2468 the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX.
\r
2469 @retval EBX Bit-granular map of isolation/contention of allocation units.
\r
2470 @retval ECX Reserved.
\r
2471 @retval EDX RESID L2 Cache Allocation Technology information described by
\r
2472 the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX.
\r
2474 <b>Example usage</b>
\r
2476 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;
\r
2478 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;
\r
2481 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,
\r
2482 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
\r
2486 #define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02
\r
2489 CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf
\r
2490 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
\r
2491 #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.
\r
2495 /// Individual bit fields
\r
2499 /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
\r
2500 /// using minus-one notation.
\r
2502 UINT32 CapacityLength:5;
\r
2503 UINT32 Reserved:27;
\r
2506 /// All bit fields as a 32-bit value
\r
2509 } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX;
\r
2512 CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf
\r
2513 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
\r
2514 #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.
\r
2518 /// Individual bit fields
\r
2522 /// [Bits 15:0] Highest COS number supported for this ResID.
\r
2524 UINT32 HighestCosNumber:16;
\r
2525 UINT32 Reserved:16;
\r
2528 /// All bit fields as a 32-bit value
\r
2531 } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX;
\r
2534 Memory Bandwidth Allocation Enumeration Sub-leaf
\r
2536 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
\r
2537 @param ECX CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF (0x03)
\r
2539 @retval EAX RESID memory bandwidth Allocation Technology information
\r
2540 described by the type
\r
2541 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX.
\r
2542 @retval EBX Reserved.
\r
2543 @retval ECX RESID memory bandwidth Allocation Technology information
\r
2544 described by the type
\r
2545 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX.
\r
2546 @retval EDX RESID memory bandwidth Allocation Technology information
\r
2547 described by the type
\r
2548 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX.
\r
2550 <b>Example usage</b>
\r
2552 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX Eax;
\r
2554 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX Ecx;
\r
2555 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx;
\r
2559 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,
\r
2560 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
\r
2564 #define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03
\r
2567 CPUID memory bandwidth Allocation Technology Information EAX for CPUID leaf
\r
2568 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
\r
2569 #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.
\r
2573 /// Individual bit fields
\r
2577 /// [Bits 11:0] Reports the maximum MBA throttling value supported for
\r
2578 /// the corresponding ResID using minus-one notation.
\r
2580 UINT32 MaximumMBAThrottling:12;
\r
2581 UINT32 Reserved:20;
\r
2584 /// All bit fields as a 32-bit value
\r
2587 } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX;
\r
2590 CPUID memory bandwidth Allocation Technology Information ECX for CPUID leaf
\r
2591 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
\r
2592 #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.
\r
2596 /// Individual bit fields
\r
2600 /// [Bits 1:0] Reserved.
\r
2602 UINT32 Reserved1:2;
\r
2604 /// [Bits 3] Reports whether the response of the delay values is linear.
\r
2607 UINT32 Reserved2:29;
\r
2610 /// All bit fields as a 32-bit value
\r
2613 } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX;
\r
2616 CPUID memory bandwidth Allocation Technology Information EDX for CPUID leaf
\r
2617 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
\r
2618 #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.
\r
2622 /// Individual bit fields
\r
2626 /// [Bits 15:0] Highest COS number supported for this ResID.
\r
2628 UINT32 HighestCosNumber:16;
\r
2629 UINT32 Reserved:16;
\r
2632 /// All bit fields as a 32-bit value
\r
2635 } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX;
\r
2638 Intel SGX resource capability and configuration.
\r
2639 See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves".
\r
2641 If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying
\r
2642 CPUID with EAX=12H on Intel SGX resource capability and configuration.
\r
2644 @param EAX CPUID_INTEL_SGX (0x12)
\r
2645 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00).
\r
2646 CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01).
\r
2647 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02).
\r
2648 Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0])
\r
2649 until the sub-leaf type is invalid.
\r
2652 #define CPUID_INTEL_SGX 0x12
\r
2655 Sub-Leaf 0 Enumeration of Intel SGX Capabilities.
\r
2656 Enumerates Intel SGX capability, including enclave instruction opcode support.
\r
2658 @param EAX CPUID_INTEL_SGX (0x12)
\r
2659 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00)
\r
2661 @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
\r
2662 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX.
\r
2663 @retval EBX MISCSELECT: Reports the bit vector of supported extended features
\r
2664 that can be written to the MISC region of the SSA.
\r
2665 @retval ECX Reserved.
\r
2666 @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
\r
2667 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX.
\r
2669 <b>Example usage</b>
\r
2671 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;
\r
2673 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;
\r
2676 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,
\r
2677 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
\r
2681 #define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00
\r
2684 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,
\r
2685 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
\r
2689 /// Individual bit fields
\r
2693 /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.
\r
2697 /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.
\r
2700 UINT32 Reserved1:3;
\r
2702 /// [Bit 5] If 1, indicates Intel SGX supports ENCLV instruction leaves
\r
2703 /// EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT.
\r
2707 /// [Bit 6] If 1, indicates Intel SGX supports ENCLS instruction leaves ETRACKC,
\r
2708 /// ERDINFO, ELDBC, and ELDUC.
\r
2711 UINT32 Reserved2:25;
\r
2714 /// All bit fields as a 32-bit value
\r
2717 } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX;
\r
2720 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX,
\r
2721 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
\r
2725 /// Individual bit fields
\r
2729 /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes
\r
2730 /// when not in 64-bit mode.
\r
2732 UINT32 MaxEnclaveSize_Not64:8;
\r
2734 /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes
\r
2735 /// when operating in 64-bit mode.
\r
2737 UINT32 MaxEnclaveSize_64:8;
\r
2738 UINT32 Reserved:16;
\r
2741 /// All bit fields as a 32-bit value
\r
2744 } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX;
\r
2748 Sub-Leaf 1 Enumeration of Intel SGX Capabilities.
\r
2749 Enumerates Intel SGX capability of processor state configuration and enclave
\r
2750 configuration in the SECS structure.
\r
2752 @param EAX CPUID_INTEL_SGX (0x12)
\r
2753 @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01)
\r
2755 @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can
\r
2756 set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE
\r
2757 only if EAX[n] is 1, where n < 32.
\r
2758 @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can
\r
2759 set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE
\r
2760 only if EBX[n] is 1, where n < 32.
\r
2761 @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can
\r
2762 set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE
\r
2763 only if ECX[n] is 1, where n < 32.
\r
2764 @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can
\r
2765 set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE
\r
2766 only if EDX[n] is 1, where n < 32.
\r
2768 <b>Example usage</b>
\r
2776 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,
\r
2777 &Eax, &Ebx, &Ecx, &Edx
\r
2781 #define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01
\r
2785 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.
\r
2786 Enumerates available EPC resources.
\r
2788 @param EAX CPUID_INTEL_SGX (0x12)
\r
2789 @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02)
\r
2791 @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
\r
2792 Resources is described by the type
\r
2793 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX.
\r
2794 @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
\r
2795 Resources is described by the type
\r
2796 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX.
\r
2797 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
\r
2798 Resources is described by the type
\r
2799 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX.
\r
2800 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
\r
2801 Resources is described by the type
\r
2802 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX.
\r
2804 <b>Example usage</b>
\r
2806 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;
\r
2807 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;
\r
2808 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;
\r
2809 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;
\r
2812 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF,
\r
2813 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
\r
2817 #define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02
\r
2820 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID
\r
2821 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
\r
2825 /// Individual bit fields
\r
2829 /// [Bit 3:0] Sub-leaf-type encoding.
\r
2830 /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0.
\r
2831 /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC)
\r
2832 /// in EBX:EAX and EDX:ECX.
\r
2833 /// All other encoding are reserved.
\r
2835 UINT32 SubLeafType:4;
\r
2836 UINT32 Reserved:8;
\r
2838 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of
\r
2839 /// the base of the EPC section.
\r
2841 UINT32 LowAddressOfEpcSection:20;
\r
2844 /// All bit fields as a 32-bit value
\r
2847 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX;
\r
2850 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID
\r
2851 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
\r
2855 /// Individual bit fields
\r
2859 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of
\r
2860 /// the base of the EPC section.
\r
2862 UINT32 HighAddressOfEpcSection:20;
\r
2863 UINT32 Reserved:12;
\r
2866 /// All bit fields as a 32-bit value
\r
2869 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX;
\r
2872 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID
\r
2873 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
\r
2877 /// Individual bit fields
\r
2881 /// [Bit 3:0] The EPC section encoding.
\r
2882 /// 0000b: Not valid.
\r
2883 /// 0001b: The EPC section is confidentiality, integrity and replay protected.
\r
2884 /// All other encoding are reserved.
\r
2886 UINT32 EpcSection:4;
\r
2887 UINT32 Reserved:8;
\r
2889 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the
\r
2890 /// corresponding EPC section within the Processor Reserved Memory.
\r
2892 UINT32 LowSizeOfEpcSection:20;
\r
2895 /// All bit fields as a 32-bit value
\r
2898 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX;
\r
2901 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID
\r
2902 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
\r
2906 /// Individual bit fields
\r
2910 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the
\r
2911 /// corresponding EPC section within the Processor Reserved Memory.
\r
2913 UINT32 HighSizeOfEpcSection:20;
\r
2914 UINT32 Reserved:12;
\r
2917 /// All bit fields as a 32-bit value
\r
2920 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX;
\r
2924 CPUID Intel Processor Trace Information
\r
2926 @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14)
\r
2927 @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00).
\r
2928 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).
\r
2931 #define CPUID_INTEL_PROCESSOR_TRACE 0x14
\r
2934 CPUID Intel Processor Trace Information Main Leaf
\r
2936 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
\r
2937 @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00)
\r
2939 @retval EAX Reports the maximum sub-leaf supported in leaf 14H.
\r
2940 @retval EBX Returns Intel processor trace information described by the
\r
2941 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX.
\r
2942 @retval ECX Returns Intel processor trace information described by the
\r
2943 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX.
\r
2944 @retval EDX Reserved.
\r
2946 <b>Example usage</b>
\r
2949 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;
\r
2950 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
\r
2953 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
\r
2954 &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL
\r
2958 #define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00
\r
2961 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
\r
2962 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
\r
2966 /// Individual bit fields
\r
2970 /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,
\r
2971 /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.
\r
2973 UINT32 Cr3Filter:1;
\r
2975 /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate
\r
2978 UINT32 ConfigurablePsb:1;
\r
2980 /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering,
\r
2981 /// and preservation of Intel PT MSRs across warm reset.
\r
2983 UINT32 IpTraceStopFiltering:1;
\r
2985 /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of
\r
2986 /// COFI-based packets.
\r
2990 /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set
\r
2991 /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE
\r
2992 /// can generate packets.
\r
2996 /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set
\r
2997 /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet
\r
3000 UINT32 PowerEventTrace:1;
\r
3001 UINT32 Reserved:26;
\r
3004 /// All bit fields as a 32-bit value
\r
3007 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX;
\r
3010 CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
\r
3011 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
\r
3015 /// Individual bit fields
\r
3019 /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence
\r
3020 /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and
\r
3021 /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
\r
3025 /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to
\r
3026 /// the maximum allowed by the MaskOrTableOffset field of
\r
3027 /// IA32_RTIT_OUTPUT_MASK_PTRS.
\r
3031 /// [Bit 2] If 1, indicates support of Single-Range Output scheme.
\r
3033 UINT32 SingleRangeOutput:1;
\r
3035 /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem.
\r
3037 UINT32 TraceTransportSubsystem:1;
\r
3038 UINT32 Reserved:27;
\r
3040 /// [Bit 31] If 1, generated packets which contain IP payloads have LIP
\r
3041 /// values, which include the CS base component.
\r
3046 /// All bit fields as a 32-bit value
\r
3049 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX;
\r
3053 CPUID Intel Processor Trace Information Sub-leaf
\r
3055 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
\r
3056 @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01)
\r
3058 @retval EAX Returns Intel processor trace information described by the
\r
3059 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX.
\r
3060 @retval EBX Returns Intel processor trace information described by the
\r
3061 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX.
\r
3062 @retval ECX Reserved.
\r
3063 @retval EDX Reserved.
\r
3065 <b>Example usage</b>
\r
3067 UINT32 MaximumSubLeaf;
\r
3069 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;
\r
3070 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;
\r
3073 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
\r
3074 &MaximumSubLeaf, NULL, NULL, NULL
\r
3077 for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {
\r
3079 CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,
\r
3080 &Eax.Uint32, &Ebx.Uint32, NULL, NULL
\r
3085 #define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01
\r
3088 CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
\r
3089 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
\r
3093 /// Individual bit fields
\r
3097 /// [Bits 2:0] Number of configurable Address Ranges for filtering.
\r
3099 UINT32 ConfigurableAddressRanges:3;
\r
3100 UINT32 Reserved:13;
\r
3102 /// [Bits 31:16] Bitmap of supported MTC period encodings
\r
3104 UINT32 MtcPeriodEncodings:16;
\r
3108 /// All bit fields as a 32-bit value
\r
3111 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX;
\r
3114 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
\r
3115 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
\r
3119 /// Individual bit fields
\r
3123 /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.
\r
3125 UINT32 CycleThresholdEncodings:16;
\r
3127 /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.
\r
3129 UINT32 PsbFrequencyEncodings:16;
\r
3133 /// All bit fields as a 32-bit value
\r
3136 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX;
\r
3140 CPUID Time Stamp Counter and Nominal Core Crystal Clock Information
\r
3143 If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.
\r
3144 EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core
\r
3145 crystal clock frequency.
\r
3146 If ECX is 0, the nominal core crystal clock frequency is not enumerated.
\r
3147 "TSC frequency" = "core crystal clock frequency" * EBX/EAX.
\r
3148 The core crystal clock may differ from the reference clock, bus clock, or core
\r
3149 clock frequencies.
\r
3151 @param EAX CPUID_TIME_STAMP_COUNTER (0x15)
\r
3153 @retval EAX An unsigned integer which is the denominator of the
\r
3154 TSC/"core crystal clock" ratio
\r
3155 @retval EBX An unsigned integer which is the numerator of the
\r
3156 TSC/"core crystal clock" ratio.
\r
3157 @retval ECX An unsigned integer which is the nominal frequency
\r
3158 of the core crystal clock in Hz.
\r
3159 @retval EDX Reserved.
\r
3161 <b>Example usage</b>
\r
3167 AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);
\r
3170 #define CPUID_TIME_STAMP_COUNTER 0x15
\r
3174 CPUID Processor Frequency Information
\r
3177 Data is returned from this interface in accordance with the processor's
\r
3178 specification and does not reflect actual values. Suitable use of this data
\r
3179 includes the display of processor information in like manner to the processor
\r
3180 brand string and for determining the appropriate range to use when displaying
\r
3181 processor information e.g. frequency history graphs. The returned information
\r
3182 should not be used for any other purpose as the returned information does not
\r
3183 accurately correlate to information / counters returned by other processor
\r
3184 interfaces. While a processor may support the Processor Frequency Information
\r
3185 leaf, fields that return a value of zero are not supported.
\r
3187 @param EAX CPUID_TIME_STAMP_COUNTER (0x16)
\r
3189 @retval EAX Returns processor base frequency information described by the
\r
3190 type CPUID_PROCESSOR_FREQUENCY_EAX.
\r
3191 @retval EBX Returns maximum frequency information described by the type
\r
3192 CPUID_PROCESSOR_FREQUENCY_EBX.
\r
3193 @retval ECX Returns bus frequency information described by the type
\r
3194 CPUID_PROCESSOR_FREQUENCY_ECX.
\r
3195 @retval EDX Reserved.
\r
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