2 CPUID leaf definitions.
4 Provides defines for CPUID leaf indexes. Data structures are provided for
5 registers returned by a CPUID leaf that contain one or more bit fields.
6 If a register returned is a single 32-bit value, then a data structure is
7 not provided for that register.
9 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials are licensed and made available under
11 the terms and conditions of the BSD License which accompanies this distribution.
12 The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,
20 September 2016, CPUID instruction.
28 CPUID Signature Information
30 @param EAX CPUID_SIGNATURE (0x00)
32 @retval EAX Returns the highest value the CPUID instruction recognizes for
33 returning basic processor information. The value is returned is
35 @retval EBX First 4 characters of a vendor identification string.
36 @retval ECX Last 4 characters of a vendor identification string.
37 @retval EDX Middle 4 characters of a vendor identification string.
46 AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
49 #define CPUID_SIGNATURE 0x00
52 /// @{ CPUID signature values returned by Intel processors
54 #define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u')
55 #define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I')
56 #define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l')
63 CPUID Version Information
65 @param EAX CPUID_VERSION_INFO (0x01)
67 @retval EAX Returns Model, Family, Stepping Information described by the
68 type CPUID_VERSION_INFO_EAX.
69 @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by
70 the type CPUID_VERSION_INFO_EBX.
71 @retval ECX CPU Feature Information described by the type
72 CPUID_VERSION_INFO_ECX.
73 @retval EDX CPU Feature Information described by the type
74 CPUID_VERSION_INFO_EDX.
78 CPUID_VERSION_INFO_EAX Eax;
79 CPUID_VERSION_INFO_EBX Ebx;
80 CPUID_VERSION_INFO_ECX Ecx;
81 CPUID_VERSION_INFO_EDX Edx;
83 AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
86 #define CPUID_VERSION_INFO 0x01
89 CPUID Version Information returned in EAX for CPUID leaf
94 /// Individual bit fields
97 UINT32 SteppingId
:4; ///< [Bits 3:0] Stepping ID
98 UINT32 Model
:4; ///< [Bits 7:4] Model
99 UINT32 FamilyId
:4; ///< [Bits 11:8] Family
100 UINT32 ProcessorType
:2; ///< [Bits 13:12] Processor Type
101 UINT32 Reserved1
:2; ///< [Bits 15:14] Reserved
102 UINT32 ExtendedModelId
:4; ///< [Bits 19:16] Extended Model ID
103 UINT32 ExtendedFamilyId
:8; ///< [Bits 27:20] Extended Family ID
104 UINT32 Reserved2
:4; ///< Reserved
107 /// All bit fields as a 32-bit value
110 } CPUID_VERSION_INFO_EAX
;
113 /// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType
115 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00
116 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01
117 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02
123 CPUID Version Information returned in EBX for CPUID leaf
128 /// Individual bit fields
132 /// [Bits 7:0] Provides an entry into a brand string table that contains
133 /// brand strings for IA-32 processors.
137 /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH
138 /// and CLFLUSHOPT instructions in 8-byte increments. This field was
139 /// introduced in the Pentium 4 processor.
141 UINT32 CacheLineSize
:8;
143 /// [Bits 23:16] Maximum number of addressable IDs for logical processors
144 /// in this physical package.
147 /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is
148 /// the number of unique initial APICIDs reserved for addressing different
149 /// logical processors in a physical package. This field is only valid if
150 /// CPUID.1.EDX.HTT[bit 28]= 1.
152 UINT32 MaximumAddressableIdsForLogicalProcessors
:8;
154 /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the
155 /// processor during power up. This field was introduced in the Pentium 4
158 UINT32 InitialLocalApicId
:8;
161 /// All bit fields as a 32-bit value
164 } CPUID_VERSION_INFO_EBX
;
167 CPUID Version Information returned in ECX for CPUID leaf
172 /// Individual bit fields
176 /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the
177 /// processor supports this technology
181 /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ
182 /// instruction. Carryless Multiplication
186 /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports
187 /// DS area using 64-bit layout.
191 /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports
196 /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor
197 /// supports the extensions to the Debug Store feature to allow for branch
198 /// message storage qualified by CPL
202 /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the
203 /// processor supports this technology.
207 /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor
208 /// supports this technology
212 /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates
213 /// that the processor supports this technology
217 /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor
218 /// supports this technology
222 /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming
223 /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction
224 /// extensions are not present in the processor.
228 /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode
229 /// can be set to either adaptive mode or shared mode. A value of 0 indicates
230 /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR
231 /// Bit 24 (L1 Data Cache Context Mode) for details
235 /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE
236 /// MSR for silicon debug
240 /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple
241 /// Add) extensions using YMM state.
245 /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature
250 /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor
251 /// supports changing IA32_MISC_ENABLE[Bit 23].
253 UINT32 xTPR_Update_Control
:1;
255 /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the
256 /// processor supports the performance and debug feature indication MSR
257 /// IA32_PERF_CAPABILITIES.
262 /// [Bit 17] Process-context identifiers. A value of 1 indicates that the
263 /// processor supports PCIDs and that software may set CR4.PCIDE to 1.
267 /// [Bit 18] A value of 1 indicates the processor supports the ability to
268 /// prefetch data from a memory mapped device. Direct Cache Access.
272 /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.
276 /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.
280 /// [Bit 21] A value of 1 indicates that the processor supports x2APIC
285 /// [Bit 22] A value of 1 indicates that the processor supports MOVBE
290 /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT
295 /// [Bit 24] A value of 1 indicates that the processor's local APIC timer
296 /// supports one-shot operation using a TSC deadline value.
298 UINT32 TSC_Deadline
:1;
300 /// [Bit 25] A value of 1 indicates that the processor supports the AESNI
301 /// instruction extensions.
305 /// [Bit 26] A value of 1 indicates that the processor supports the
306 /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV
307 /// instructions, and XCR0.
311 /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]
312 /// to enable XSETBV/XGETBV instructions to access XCR0 and to support
313 /// processor extended state management using XSAVE/XRSTOR.
317 /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction
322 /// [Bit 29] A value of 1 indicates that processor supports 16-bit
323 /// floating-point conversion instructions.
327 /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.
331 /// [Bit 31] Always returns 0.
336 /// All bit fields as a 32-bit value
339 } CPUID_VERSION_INFO_ECX
;
342 CPUID Version Information returned in EDX for CPUID leaf
347 /// Individual bit fields
351 /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.
355 /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,
356 /// including CR4.VME for controlling the feature, CR4.PVI for protected
357 /// mode virtual interrupts, software interrupt indirection, expansion of
358 /// the TSS with the software indirection bitmap, and EFLAGS.VIF and
359 /// EFLAGS.VIP flags.
363 /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including
364 /// CR4.DE for controlling the feature, and optional trapping of accesses to
369 /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,
370 /// including CR4.PSE for controlling the feature, the defined dirty bit in
371 /// PDE (Page Directory Entries), optional reserved bit trapping in CR3,
376 /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,
377 /// including CR4.TSD for controlling privilege.
381 /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The
382 /// RDMSR and WRMSR instructions are supported. Some of the MSRs are
383 /// implementation dependent.
387 /// [Bit 6] Physical Address Extension. Physical addresses greater than 32
388 /// bits are supported: extended page table entry formats, an extra level in
389 /// the page translation tables is defined, 2-MByte pages are supported
390 /// instead of 4 Mbyte pages if PAE bit is 1.
394 /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine
395 /// Checks, including CR4.MCE for controlling the feature. This feature does
396 /// not define the model-specific implementations of machine-check error
397 /// logging, reporting, and processor shutdowns. Machine Check exception
398 /// handlers may have to depend on processor version to do model specific
399 /// processing of the exception, or test for the presence of the Machine
404 /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)
405 /// instruction is supported (implicitly locked and atomic).
409 /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable
410 /// Interrupt Controller (APIC), responding to memory mapped commands in the
411 /// physical address range FFFE0000H to FFFE0FFFH (by default - some
412 /// processors permit the APIC to be relocated).
417 /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT
418 /// and associated MSRs are supported.
422 /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap
423 /// MSR contains feature bits that describe what memory types are supported,
424 /// how many variable MTRRs are supported, and whether fixed MTRRs are
429 /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure
430 /// entries that map a page, indicating TLB entries that are common to
431 /// different processes and need not be flushed. The CR4.PGE bit controls
436 /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine
437 /// Check Architecture of reporting machine errors is supported. The MCG_CAP
438 /// MSR contains feature bits describing how many banks of error reporting
439 /// MSRs are supported.
443 /// [Bit 15] Conditional Move Instructions. The conditional move instruction
444 /// CMOV is supported. In addition, if x87 FPU is present as indicated by the
445 /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.
449 /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This
450 /// feature augments the Memory Type Range Registers (MTRRs), allowing an
451 /// operating system to specify attributes of memory accessed through a
452 /// linear address on a 4KB granularity.
456 /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical
457 /// memory beyond 4 GBytes are supported with 32-bit paging. This feature
458 /// indicates that upper bits of the physical address of a 4-MByte page are
459 /// encoded in bits 20:13 of the page-directory entry. Such physical
460 /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.
464 /// [Bit 18] Processor Serial Number. The processor supports the 96-bit
465 /// processor identification number feature and the feature is enabled.
469 /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.
474 /// [Bit 21] Debug Store. The processor supports the ability to write debug
475 /// information into a memory resident buffer. This feature is used by the
476 /// branch trace store (BTS) and precise event-based sampling (PEBS)
481 /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The
482 /// processor implements internal MSRs that allow processor temperature to
483 /// be monitored and processor performance to be modulated in predefined
484 /// duty cycles under software control.
488 /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX
493 /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR
494 /// instructions are supported for fast save and restore of the floating
495 /// point context. Presence of this bit also indicates that CR4.OSFXSR is
496 /// available for an operating system to indicate that it supports the
497 /// FXSAVE and FXRSTOR instructions.
501 /// [Bit 25] SSE. The processor supports the SSE extensions.
505 /// [Bit 26] SSE2. The processor supports the SSE2 extensions.
509 /// [Bit 27] Self Snoop. The processor supports the management of
510 /// conflicting memory types by performing a snoop of its own cache
511 /// structure for transactions issued to the bus.
515 /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT
516 /// indicates there is only a single logical processor in the package and
517 /// software should assume only a single APIC ID is reserved. A value of 1
518 /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of
519 /// addressable IDs for logical processors in this package) is valid for the
524 /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor
525 /// automatic thermal control circuitry (TCC).
530 /// [Bit 31] Pending Break Enable. The processor supports the use of the
531 /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is
532 /// asserted) to signal the processor that an interrupt is pending and that
533 /// the processor should return to normal operation to handle the interrupt.
534 /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.
539 /// All bit fields as a 32-bit value
542 } CPUID_VERSION_INFO_EDX
;
546 CPUID Cache and TLB Information
548 @param EAX CPUID_CACHE_INFO (0x02)
550 @retval EAX Cache and TLB Information described by the type
551 CPUID_CACHE_INFO_CACHE_TLB.
552 CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns
553 0x01 and must be ignored. Only valid if
554 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
555 @retval EBX Cache and TLB Information described by the type
556 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
557 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
558 @retval ECX Cache and TLB Information described by the type
559 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
560 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
561 @retval EDX Cache and TLB Information described by the type
562 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
563 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
567 CPUID_CACHE_INFO_CACHE_TLB Eax;
568 CPUID_CACHE_INFO_CACHE_TLB Ebx;
569 CPUID_CACHE_INFO_CACHE_TLB Ecx;
570 CPUID_CACHE_INFO_CACHE_TLB Edx;
572 AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
575 <b>Cache Descriptor values</b>
577 <tr><th>Value </th><th> Type </th><th> Description </th></tr>
578 <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr>
579 <tr><td> 0x01 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr>
580 <tr><td> 0x02 </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr>
581 <tr><td> 0x03 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr>
582 <tr><td> 0x04 </td><td> TLB </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr>
583 <tr><td> 0x05 </td><td> TLB </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr>
584 <tr><td> 0x06 </td><td> Cache </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative,
585 32 byte line size</td></tr>
586 <tr><td> 0x08 </td><td> Cache </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative,
587 32 byte line size</td></tr>
588 <tr><td> 0x09 </td><td> Cache </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative,
589 64 byte line size</td></tr>
590 <tr><td> 0x0A </td><td> Cache </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr>
591 <tr><td> 0x0B </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr>
592 <tr><td> 0x0C </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr>
593 <tr><td> 0x0D </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr>
594 <tr><td> 0x0E </td><td> Cache </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr>
595 <tr><td> 0x1D </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr>
596 <tr><td> 0x21 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr>
597 <tr><td> 0x22 </td><td> Cache </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size,
598 2 lines per sector</td></tr>
599 <tr><td> 0x23 </td><td> Cache </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size,
600 2 lines per sector</td></tr>
601 <tr><td> 0x24 </td><td> Cache </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr>
602 <tr><td> 0x25 </td><td> Cache </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size,
603 2 lines per sector</td></tr>
604 <tr><td> 0x29 </td><td> Cache </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size,
605 2 lines per sector</td></tr>
606 <tr><td> 0x2C </td><td> Cache </td><td> 1st-level data cache: 32 KBytes, 8-way set associative,
607 64 byte line size</td></tr>
608 <tr><td> 0x30 </td><td> Cache </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative,
609 64 byte line size</td></tr>
610 <tr><td> 0x40 </td><td> Cache </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache,
611 no 3rd-level cache</td></tr>
612 <tr><td> 0x41 </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr>
613 <tr><td> 0x42 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr>
614 <tr><td> 0x43 </td><td> Cache </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr>
615 <tr><td> 0x44 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr>
616 <tr><td> 0x45 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr>
617 <tr><td> 0x46 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr>
618 <tr><td> 0x47 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr>
619 <tr><td> 0x48 </td><td> Cache </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr>
620 <tr><td> 0x49 </td><td> Cache </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size
621 (Intel Xeon processor MP, Family 0FH, Model 06H)<BR>
622 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
623 <tr><td> 0x4A </td><td> Cache </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr>
624 <tr><td> 0x4B </td><td> Cache </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr>
625 <tr><td> 0x4C </td><td> Cache </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr>
626 <tr><td> 0x4D </td><td> Cache </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr>
627 <tr><td> 0x4E </td><td> Cache </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr>
628 <tr><td> 0x4F </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr>
629 <tr><td> 0x50 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr>
630 <tr><td> 0x51 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr>
631 <tr><td> 0x52 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr>
632 <tr><td> 0x55 </td><td> TLB </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr>
633 <tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>
634 <tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>
635 <tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>
636 <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>
637 <tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>
638 <tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>
639 <tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>
640 <tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>
641 <tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>
642 <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 2 MByte or 4 MByte pages, 4-way set associative,
643 32 entries and a separate array with 1 GByte pages, 4-way set associative,
645 <tr><td> 0x64 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 512 entries</td></tr>
646 <tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>
647 <tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>
648 <tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>
649 <tr><td> 0x6A </td><td> Cache </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr>
650 <tr><td> 0x6B </td><td> Cache </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr>
651 <tr><td> 0x6C </td><td> Cache </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr>
652 <tr><td> 0x6D </td><td> Cache </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr>
653 <tr><td> 0x70 </td><td> Cache </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr>
654 <tr><td> 0x71 </td><td> Cache </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr>
655 <tr><td> 0x72 </td><td> Cache </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr>
656 <tr><td> 0x76 </td><td> TLB </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr>
657 <tr><td> 0x78 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr>
658 <tr><td> 0x79 </td><td> Cache </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size,
659 2 lines per sector</td></tr>
660 <tr><td> 0x7A </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size,
661 2 lines per sector</td></tr>
662 <tr><td> 0x7B </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size,
663 2 lines per sector</td></tr>
664 <tr><td> 0x7C </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size,
665 2 lines per sector</td></tr>
666 <tr><td> 0x7D </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr>
667 <tr><td> 0x7F </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr>
668 <tr><td> 0x80 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr>
669 <tr><td> 0x82 </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr>
670 <tr><td> 0x83 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr>
671 <tr><td> 0x84 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr>
672 <tr><td> 0x85 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr>
673 <tr><td> 0x86 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
674 <tr><td> 0x87 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
675 <tr><td> 0xA0 </td><td> DTLB </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr>
676 <tr><td> 0xB0 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
677 <tr><td> 0xB1 </td><td> TLB </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr>
678 <tr><td> 0xB2 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr>
679 <tr><td> 0xB3 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
680 <tr><td> 0xB4 </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr>
681 <tr><td> 0xB5 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr>
682 <tr><td> 0xB6 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative,
683 128 entries</td></tr>
684 <tr><td> 0xBA </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr>
685 <tr><td> 0xC0 </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr>
686 <tr><td> 0xC1 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative,
687 1024 entries</td></tr>
688 <tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>
689 <tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,
690 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>
691 <tr><td> 0xC4 </td><td> DTLB </td><td> DTLB: 2M/4M Byte pages, 4-way associative, 32 entries</td></tr>
692 <tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>
693 <tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
694 <tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>
695 <tr><td> 0xD2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr>
696 <tr><td> 0xD6 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
697 <tr><td> 0xD7 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr>
698 <tr><td> 0xD8 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr>
699 <tr><td> 0xDC </td><td> Cache </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr>
700 <tr><td> 0xDD </td><td> Cache </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr>
701 <tr><td> 0xDE </td><td> Cache </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr>
702 <tr><td> 0xE2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr>
703 <tr><td> 0xE3 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
704 <tr><td> 0xE4 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr>
705 <tr><td> 0xEA </td><td> Cache </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr>
706 <tr><td> 0xEB </td><td> Cache </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr>
707 <tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr>
708 <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr>
709 <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr>
710 <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information,
711 use CPUID leaf 4 to query cache parameters</td></tr>
714 #define CPUID_CACHE_INFO 0x02
717 CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID
718 leaf #CPUID_CACHE_INFO.
722 /// Individual bit fields
727 /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.
728 /// if 1, then none of the cache descriptor bytes in the register are valid.
733 /// Array of Cache and TLB descriptor bytes
735 UINT8 CacheDescriptor
[4];
737 /// All bit fields as a 32-bit value
740 } CPUID_CACHE_INFO_CACHE_TLB
;
744 CPUID Processor Serial Number
746 Processor serial number (PSN) is not supported in the Pentium 4 processor
747 or later. On all models, use the PSN flag (returned using CPUID) to check
748 for PSN support before accessing the feature.
750 @param EAX CPUID_SERIAL_NUMBER (0x03)
752 @retval EAX Reserved.
753 @retval EBX Reserved.
754 @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in
755 Pentium III processor only; otherwise, the value in this
756 register is reserved.)
757 @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in
758 Pentium III processor only; otherwise, the value in this
759 register is reserved.)
766 AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);
769 #define CPUID_SERIAL_NUMBER 0x03
773 CPUID Cache Parameters
775 @param EAX CPUID_CACHE_PARAMS (0x04)
776 @param ECX Cache Level. Valid values start at 0. Software can enumerate
777 the deterministic cache parameters for each level of the cache
778 hierarchy starting with an index value of 0, until the
779 parameters report the value associated with the CacheType
780 field in CPUID_CACHE_PARAMS_EAX is 0.
782 @retval EAX Returns cache type information described by the type
783 CPUID_CACHE_PARAMS_EAX.
784 @retval EBX Returns cache line and associativity information described by
785 the type CPUID_CACHE_PARAMS_EBX.
786 @retval ECX Returns the number of sets in the cache.
787 @retval EDX Returns cache WINVD/INVD behavior described by the type
788 CPUID_CACHE_PARAMS_EDX.
793 CPUID_CACHE_PARAMS_EAX Eax;
794 CPUID_CACHE_PARAMS_EBX Ebx;
796 CPUID_CACHE_PARAMS_EDX Edx;
801 CPUID_CACHE_PARAMS, CacheLevel,
802 &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32
805 } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
808 #define CPUID_CACHE_PARAMS 0x04
811 CPUID Cache Parameters Information returned in EAX for CPUID leaf
816 /// Individual bit fields
820 /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,
821 /// then there is no information for the requested cache level.
825 /// [Bits 7:5] Cache level (Starts at 1).
829 /// [Bit 8] Self Initializing cache level (does not need SW initialization).
831 UINT32 SelfInitializingCache
:1;
833 /// [Bit 9] Fully Associative cache.
835 UINT32 FullyAssociativeCache
:1;
837 /// [Bits 13:10] Reserved.
841 /// [Bits 25:14] Maximum number of addressable IDs for logical processors
842 /// sharing this cache.
844 /// Add one to the return value to get the result.
845 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14])
846 /// is the number of unique initial APIC IDs reserved for addressing
847 /// different logical processors sharing this cache.
849 UINT32 MaximumAddressableIdsForLogicalProcessors
:12;
851 /// [Bits 31:26] Maximum number of addressable IDs for processor cores in
852 /// the physical package.
854 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26])
855 /// is the number of unique Core_IDs reserved for addressing different
856 /// processor cores in a physical package. Core ID is a subset of bits of
857 /// the initial APIC ID.
858 /// The returned value is constant for valid initial values in ECX. Valid
859 /// ECX values start from 0.
861 UINT32 MaximumAddressableIdsForProcessorCores
:6;
864 /// All bit fields as a 32-bit value
867 } CPUID_CACHE_PARAMS_EAX
;
870 /// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType
872 #define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00
873 #define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01
874 #define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02
875 #define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03
881 CPUID Cache Parameters Information returned in EBX for CPUID leaf
886 /// Individual bit fields
890 /// [Bits 11:0] System Coherency Line Size. Add one to the return value to
895 /// [Bits 21:12] Physical Line Partitions. Add one to the return value to
898 UINT32 LinePartitions
:10;
900 /// [Bits 31:22] Ways of associativity. Add one to the return value to get
906 /// All bit fields as a 32-bit value
909 } CPUID_CACHE_PARAMS_EBX
;
912 CPUID Cache Parameters Information returned in EDX for CPUID leaf
917 /// Individual bit fields
921 /// [Bit 0] Write-Back Invalidate/Invalidate.
922 /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level
923 /// caches for threads sharing this cache.
924 /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of
925 /// non-originating threads sharing this cache.
929 /// [Bit 1] Cache Inclusiveness.
930 /// 0 = Cache is not inclusive of lower cache levels.
931 /// 1 = Cache is inclusive of lower cache levels.
933 UINT32 CacheInclusiveness
:1;
935 /// [Bit 2] Complex Cache Indexing.
936 /// 0 = Direct mapped cache.
937 /// 1 = A complex function is used to index the cache, potentially using all
940 UINT32 ComplexCacheIndexing
:1;
944 /// All bit fields as a 32-bit value
947 } CPUID_CACHE_PARAMS_EDX
;
951 CPUID MONITOR/MWAIT Information
953 @param EAX CPUID_MONITOR_MWAIT (0x05)
955 @retval EAX Smallest monitor-line size in bytes described by the type
956 CPUID_MONITOR_MWAIT_EAX.
957 @retval EBX Largest monitor-line size in bytes described by the type
958 CPUID_MONITOR_MWAIT_EBX.
959 @retval ECX Enumeration of Monitor-Mwait extensions support described by
960 the type CPUID_MONITOR_MWAIT_ECX.
961 @retval EDX Sub C-states supported described by the type
962 CPUID_MONITOR_MWAIT_EDX.
966 CPUID_MONITOR_MWAIT_EAX Eax;
967 CPUID_MONITOR_MWAIT_EBX Ebx;
968 CPUID_MONITOR_MWAIT_ECX Ecx;
969 CPUID_MONITOR_MWAIT_EDX Edx;
971 AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
974 #define CPUID_MONITOR_MWAIT 0x05
977 CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf
978 #CPUID_MONITOR_MWAIT.
982 /// Individual bit fields
986 /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's
987 /// monitor granularity).
989 UINT32 SmallestMonitorLineSize
:16;
993 /// All bit fields as a 32-bit value
996 } CPUID_MONITOR_MWAIT_EAX
;
999 CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf
1000 #CPUID_MONITOR_MWAIT.
1004 /// Individual bit fields
1008 /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's
1009 /// monitor granularity).
1011 UINT32 LargestMonitorLineSize
:16;
1015 /// All bit fields as a 32-bit value
1018 } CPUID_MONITOR_MWAIT_EBX
;
1021 CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf
1022 #CPUID_MONITOR_MWAIT.
1026 /// Individual bit fields
1030 /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,
1031 /// and EDX are valid.
1033 UINT32 ExtensionsSupported
:1;
1035 /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when
1036 /// interrupts disabled.
1038 UINT32 InterruptAsBreak
:1;
1042 /// All bit fields as a 32-bit value
1045 } CPUID_MONITOR_MWAIT_ECX
;
1048 CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf
1049 #CPUID_MONITOR_MWAIT.
1052 The definition of C0 through C7 states for MWAIT extension are
1053 processor-specific C-states, not ACPI C-states.
1057 /// Individual bit fields
1061 /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.
1065 /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.
1069 /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.
1073 /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.
1077 /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.
1081 /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.
1085 /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.
1089 /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.
1094 /// All bit fields as a 32-bit value
1097 } CPUID_MONITOR_MWAIT_EDX
;
1101 CPUID Thermal and Power Management
1103 @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06)
1105 @retval EAX Thermal and power management features described by the type
1106 CPUID_THERMAL_POWER_MANAGEMENT_EAX.
1107 @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor
1108 described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX.
1109 @retval ECX Performance features described by the type
1110 CPUID_THERMAL_POWER_MANAGEMENT_ECX.
1111 @retval EDX Reserved.
1113 <b>Example usage</b>
1115 CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;
1116 CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;
1117 CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;
1119 AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
1122 #define CPUID_THERMAL_POWER_MANAGEMENT 0x06
1125 CPUID Thermal and Power Management Information returned in EAX for CPUID leaf
1126 #CPUID_THERMAL_POWER_MANAGEMENT.
1130 /// Individual bit fields
1134 /// [Bit 0] Digital temperature sensor is supported if set.
1136 UINT32 DigitalTemperatureSensor
:1;
1138 /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).
1140 UINT32 TurboBoostTechnology
:1;
1142 /// [Bit 2] APIC-Timer-always-running feature is supported if set.
1147 /// [Bit 4] Power limit notification controls are supported if set.
1151 /// [Bit 5] Clock modulation duty cycle extension is supported if set.
1155 /// [Bit 6] Package thermal management is supported if set.
1159 /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,
1160 /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
1164 /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.
1166 UINT32 HWP_Notification
:1;
1168 /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.
1170 UINT32 HWP_Activity_Window
:1;
1172 /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.
1174 UINT32 HWP_Energy_Performance_Preference
:1;
1176 /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.
1178 UINT32 HWP_Package_Level_Request
:1;
1181 /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,
1182 /// IA32_THREAD_STALL MSRs are supported if set.
1185 UINT32 Reserved3
:18;
1188 /// All bit fields as a 32-bit value
1191 } CPUID_THERMAL_POWER_MANAGEMENT_EAX
;
1194 CPUID Thermal and Power Management Information returned in EBX for CPUID leaf
1195 #CPUID_THERMAL_POWER_MANAGEMENT.
1199 /// Individual bit fields
1203 /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.
1205 UINT32 InterruptThresholds
:4;
1209 /// All bit fields as a 32-bit value
1212 } CPUID_THERMAL_POWER_MANAGEMENT_EBX
;
1215 CPUID Thermal and Power Management Information returned in ECX for CPUID leaf
1216 #CPUID_THERMAL_POWER_MANAGEMENT.
1220 /// Individual bit fields
1224 /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF
1225 /// and IA32_APERF). The capability to provide a measure of delivered
1226 /// processor performance (since last reset of the counters), as a percentage
1227 /// of the expected processor performance when running at the TSC frequency.
1229 UINT32 HardwareCoordinationFeedback
:1;
1232 /// [Bit 3] If this bit is set, then the processor supports performance-energy
1233 /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS
1236 UINT32 PerformanceEnergyBias
:1;
1237 UINT32 Reserved2
:28;
1240 /// All bit fields as a 32-bit value
1243 } CPUID_THERMAL_POWER_MANAGEMENT_ECX
;
1247 CPUID Structured Extended Feature Flags Enumeration
1249 @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)
1250 @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00).
1253 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
1254 index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.
1256 @retval EAX The maximum input value for ECX to retrieve sub-leaf information.
1257 @retval EBX Structured Extended Feature Flags described by the type
1258 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX.
1259 @retval EBX Structured Extended Feature Flags described by the type
1260 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX.
1261 @retval EDX Reserved.
1263 <b>Example usage</b>
1266 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
1267 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;
1271 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
1272 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
1273 &Eax, NULL, NULL, NULL
1275 for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {
1277 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
1279 NULL, &Ebx.Uint32, &Ecx.Uint32, NULL
1284 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07
1287 /// CPUID Structured Extended Feature Flags Enumeration sub-leaf
1289 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00
1292 CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf
1293 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
1294 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
1298 /// Individual bit fields
1302 /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
1306 /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.
1308 UINT32 IA32_TSC_ADJUST
:1;
1310 /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT
1311 /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".
1315 /// [Bit 3] If 1 indicates the processor supports the first group of advanced
1316 /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)
1320 /// [Bit 4] Hardware Lock Elision
1324 /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.
1328 /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.
1330 UINT32 FDP_EXCPTN_ONLY
:1;
1332 /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.
1336 /// [Bit 8] If 1 indicates the processor supports the second group of
1337 /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,
1338 /// SARX, SHLX, SHRX)
1342 /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.
1344 UINT32 EnhancedRepMovsbStosb
:1;
1346 /// [Bit 10] If 1, supports INVPCID instruction for system software that
1347 /// manages process-context identifiers.
1351 /// [Bit 11] Restricted Transactional Memory
1355 /// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
1356 /// Monitoring capability if 1.
1360 /// [Bit 13] Deprecates FPU CS and FPU DS values if 1.
1362 UINT32 DeprecateFpuCsDs
:1;
1364 /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.
1368 /// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
1369 /// Allocation capability if 1.
1374 /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.
1378 /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX
1383 /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC
1384 /// instructions) if 1.
1389 /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.
1391 UINT32 CLFLUSHOPT
:1;
1393 /// [Bit 24] If 1 indicates the processor supports the CLWB instruction.
1397 /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace
1400 UINT32 IntelProcessorTrace
:1;
1403 /// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R)
1404 /// SHA Extensions) if 1.
1410 /// All bit fields as a 32-bit value
1413 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
;
1416 CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf
1417 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
1418 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
1422 /// Individual bit fields
1426 /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.
1428 UINT32 PREFETCHWT1
:1;
1431 /// [Bit 2] Supports user-mode instruction prevention if 1.
1435 /// [Bit 3] Supports protection keys for user-mode pages if 1.
1439 /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the
1440 /// RDPKRU/WRPKRU instructions).
1443 UINT32 Reserved2
:12;
1445 /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions
1450 /// [Bit 22] Supports Read Processor ID if 1.
1455 /// [Bit 30] Supports SGX Launch Configuration if 1.
1461 /// All bit fields as a 32-bit value
1464 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
;
1468 CPUID Direct Cache Access Information
1470 @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09)
1472 @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).
1473 @retval EBX Reserved.
1474 @retval ECX Reserved.
1475 @retval EDX Reserved.
1477 <b>Example usage</b>
1481 AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);
1484 #define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09
1488 CPUID Architectural Performance Monitoring
1490 @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A)
1492 @retval EAX Architectural Performance Monitoring information described by
1493 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX.
1494 @retval EBX Architectural Performance Monitoring information described by
1495 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX.
1496 @retval ECX Reserved.
1497 @retval EDX Architectural Performance Monitoring information described by
1498 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX.
1500 <b>Example usage</b>
1502 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;
1503 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;
1504 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;
1506 AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);
1509 #define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A
1512 CPUID Architectural Performance Monitoring EAX for CPUID leaf
1513 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1517 /// Individual bit fields
1521 /// [Bit 7:0] Version ID of architectural performance monitoring.
1523 UINT32 ArchPerfMonVerID
:8;
1525 /// [Bits 15:8] Number of general-purpose performance monitoring counter
1526 /// per logical processor.
1528 /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous
1529 /// block of MSR address space. Each performance event select register is
1530 /// paired with a corresponding performance counter in the 0C1H address
1533 UINT32 PerformanceMonitorCounters
:8;
1535 /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.
1537 /// The bit width of an IA32_PMCx MSR. This the number of valid bits for
1538 /// read operation. On write operations, the lower-order 32 bits of the MSR
1539 /// may be written with any value, and the high-order bits are sign-extended
1540 /// from the value of bit 31.
1542 UINT32 PerformanceMonitorCounterWidth
:8;
1544 /// [Bits 31:24] Length of EBX bit vector to enumerate architectural
1545 /// performance monitoring events.
1547 UINT32 EbxBitVectorLength
:8;
1550 /// All bit fields as a 32-bit value
1553 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX
;
1556 CPUID Architectural Performance Monitoring EBX for CPUID leaf
1557 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1561 /// Individual bit fields
1565 /// [Bit 0] Core cycle event not available if 1.
1567 UINT32 UnhaltedCoreCycles
:1;
1569 /// [Bit 1] Instruction retired event not available if 1.
1571 UINT32 InstructionsRetired
:1;
1573 /// [Bit 2] Reference cycles event not available if 1.
1575 UINT32 UnhaltedReferenceCycles
:1;
1577 /// [Bit 3] Last-level cache reference event not available if 1.
1579 UINT32 LastLevelCacheReferences
:1;
1581 /// [Bit 4] Last-level cache misses event not available if 1.
1583 UINT32 LastLevelCacheMisses
:1;
1585 /// [Bit 5] Branch instruction retired event not available if 1.
1587 UINT32 BranchInstructionsRetired
:1;
1589 /// [Bit 6] Branch mispredict retired event not available if 1.
1591 UINT32 AllBranchMispredictRetired
:1;
1595 /// All bit fields as a 32-bit value
1598 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
;
1601 CPUID Architectural Performance Monitoring EDX for CPUID leaf
1602 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1606 /// Individual bit fields
1610 /// [Bits 4:0] Number of fixed-function performance counters
1611 /// (if Version ID > 1).
1613 UINT32 FixedFunctionPerformanceCounters
:5;
1615 /// [Bits 12:5] Bit width of fixed-function performance counters
1616 /// (if Version ID > 1).
1618 UINT32 FixedFunctionPerformanceCounterWidth
:8;
1622 /// All bit fields as a 32-bit value
1625 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX
;
1629 CPUID Extended Topology Information
1632 Most of Leaf 0BH output depends on the initial value in ECX. The EDX output
1633 of leaf 0BH is always valid and does not vary with input value in ECX. Output
1634 value in ECX[7:0] always equals input value in ECX[7:0]. For sub-leaves that
1635 return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0. If
1636 an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],
1637 other input values with ECX > n also return 0 in ECX[15:8].
1639 @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B)
1640 @param ECX Level number
1642 @retval EAX Extended topology information described by the type
1643 CPUID_EXTENDED_TOPOLOGY_EAX.
1644 @retval EBX Extended topology information described by the type
1645 CPUID_EXTENDED_TOPOLOGY_EBX.
1646 @retval ECX Extended topology information described by the type
1647 CPUID_EXTENDED_TOPOLOGY_ECX.
1648 @retval EDX x2APIC ID the current logical processor.
1650 <b>Example usage</b>
1652 CPUID_EXTENDED_TOPOLOGY_EAX Eax;
1653 CPUID_EXTENDED_TOPOLOGY_EBX Ebx;
1654 CPUID_EXTENDED_TOPOLOGY_ECX Ecx;
1661 CPUID_EXTENDED_TOPOLOGY, LevelNumber,
1662 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx
1665 } while (Eax.Bits.ApicIdShift != 0);
1668 #define CPUID_EXTENDED_TOPOLOGY 0x0B
1671 CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1675 /// Individual bit fields
1679 /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique
1680 /// topology ID of the next level type. All logical processors with the
1681 /// same next level ID share current level.
1684 /// Software should use this field (EAX[4:0]) to enumerate processor
1685 /// topology of the system.
1687 UINT32 ApicIdShift
:5;
1691 /// All bit fields as a 32-bit value
1694 } CPUID_EXTENDED_TOPOLOGY_EAX
;
1697 CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1701 /// Individual bit fields
1705 /// [Bits 15:0] Number of logical processors at this level type. The number
1706 /// reflects configuration as shipped by Intel.
1709 /// Software must not use EBX[15:0] to enumerate processor topology of the
1710 /// system. This value in this field (EBX[15:0]) is only intended for
1711 /// display/diagnostic purposes. The actual number of logical processors
1712 /// available to BIOS/OS/Applications may be different from the value of
1713 /// EBX[15:0], depending on software and platform hardware configurations.
1715 UINT32 LogicalProcessors
:16;
1719 /// All bit fields as a 32-bit value
1722 } CPUID_EXTENDED_TOPOLOGY_EBX
;
1725 CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1729 /// Individual bit fields
1733 /// [Bits 7:0] Level number. Same value in ECX input.
1735 UINT32 LevelNumber
:8;
1737 /// [Bits 15:8] Level type.
1740 /// The value of the "level type" field is not related to level numbers in
1741 /// any way, higher "level type" values do not mean higher levels.
1747 /// All bit fields as a 32-bit value
1750 } CPUID_EXTENDED_TOPOLOGY_ECX
;
1753 /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
1755 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00
1756 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01
1757 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02
1764 CPUID Extended State Information
1766 @param EAX CPUID_EXTENDED_STATE (0x0D)
1767 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00).
1768 CPUID_EXTENDED_STATE_SUB_LEAF (0x01).
1769 CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).
1770 Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.
1772 #define CPUID_EXTENDED_STATE 0x0D
1775 CPUID Extended State Information Main Leaf
1777 @param EAX CPUID_EXTENDED_STATE (0x0D)
1778 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)
1780 @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n]
1781 can be set to 1 only if EAX[n] is 1. The format of the extended
1782 state main leaf is described by the type
1783 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX.
1784 @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
1785 area) required by enabled features in XCR0. May be different than
1786 ECX if some features at the end of the XSAVE save area are not
1788 @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
1789 area) of the XSAVE/XRSTOR save area required by all supported
1790 features in the processor, i.e., all the valid bit fields in XCR0.
1791 @retval EDX Reports the supported bits of the upper 32 bits of XCR0.
1792 XCR0[n+32] can be set to 1 only if EDX[n] is 1.
1794 <b>Example usage</b>
1796 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;
1802 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,
1803 &Eax.Uint32, &Ebx, &Ecx, &Edx
1807 #define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00
1810 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
1811 sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF.
1815 /// Individual bit fields
1819 /// [Bit 0] x87 state.
1823 /// [Bit 1] SSE state.
1827 /// [Bit 2] AVX state.
1831 /// [Bits 4:3] MPX state.
1835 /// [Bits 7:5] AVX-512 state.
1839 /// [Bit 8] Used for IA32_XSS.
1843 /// [Bit 9] PKRU state.
1849 /// All bit fields as a 32-bit value
1852 } CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
;
1855 CPUID Extended State Information Sub Leaf
1857 @param EAX CPUID_EXTENDED_STATE (0x0D)
1858 @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01)
1860 @retval EAX The format of the extended state sub-leaf is described by the
1861 type CPUID_EXTENDED_STATE_SUB_LEAF_EAX.
1862 @retval EBX The size in bytes of the XSAVE area containing all states
1863 enabled by XCRO | IA32_XSS.
1864 @retval ECX The format of the extended state sub-leaf is described by the
1865 type CPUID_EXTENDED_STATE_SUB_LEAF_ECX.
1866 @retval EDX Reports the supported bits of the upper 32 bits of the
1867 IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.
1869 <b>Example usage</b>
1871 CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;
1873 CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;
1877 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,
1878 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx
1882 #define CPUID_EXTENDED_STATE_SUB_LEAF 0x01
1885 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
1886 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
1890 /// Individual bit fields
1894 /// [Bit 0] XSAVEOPT is available.
1898 /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.
1902 /// [Bit 2] Supports XGETBV with ECX = 1 if set.
1906 /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.
1912 /// All bit fields as a 32-bit value
1915 } CPUID_EXTENDED_STATE_SUB_LEAF_EAX
;
1918 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
1919 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
1923 /// Individual bit fields
1927 /// [Bits 7:0] Used for XCR0.
1931 /// [Bit 8] PT STate.
1935 /// [Bit 9] Used for XCR0.
1941 /// All bit fields as a 32-bit value
1944 } CPUID_EXTENDED_STATE_SUB_LEAF_ECX
;
1947 CPUID Extended State Information Size and Offset Sub Leaf
1950 Leaf 0DH output depends on the initial value in ECX.
1951 Each sub-leaf index (starting at position 2) is supported if it corresponds to
1952 a supported bit in either the XCR0 register or the IA32_XSS MSR.
1953 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
1954 n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1
1955 returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0
1956 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].
1958 @param EAX CPUID_EXTENDED_STATE (0x0D)
1959 @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based
1960 on supported bits in XCR0 or IA32_XSS_MSR.
1962 @retval EAX The size in bytes (from the offset specified in EBX) of the save
1963 area for an extended state feature associated with a valid
1965 @retval EBX The offset in bytes of this extended state component's save area
1966 from the beginning of the XSAVE/XRSTOR area. This field reports
1967 0 if the sub-leaf index, n, does not map to a valid bit in the
1969 @retval ECX The format of the extended state components's save area as
1970 described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX.
1971 This field reports 0 if the sub-leaf index, n, is invalid.
1972 @retval EDX This field reports 0 if the sub-leaf index, n, is invalid;
1973 otherwise it is reserved.
1975 <b>Example usage</b>
1979 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;
1983 for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {
1985 CPUID_EXTENDED_STATE, SubLeaf,
1986 &Eax, &Ebx, &Ecx.Uint32, &Edx
1991 #define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02
1994 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
1995 sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET.
1999 /// Individual bit fields
2003 /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is
2004 /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported
2009 /// [Bit 1] is set if, when the compacted format of an XSAVE area is used,
2010 /// this extended state component located on the next 64-byte boundary
2011 /// following the preceding state component (otherwise, it is located
2012 /// immediately following the preceding state component).
2018 /// All bit fields as a 32-bit value
2021 } CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX
;
2025 CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
2027 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
2028 @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00).
2029 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).
2032 #define CPUID_INTEL_RDT_MONITORING 0x0F
2035 CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
2036 Enumeration Sub-leaf
2038 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
2039 @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00)
2041 @retval EAX Reserved.
2042 @retval EBX Maximum range (zero-based) of RMID within this physical
2043 processor of all types.
2044 @retval ECX Reserved.
2045 @retval EDX L3 Cache Intel RDT Monitoring Information Enumeration described by
2046 the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX.
2048 <b>Example usage</b>
2051 CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
2054 CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,
2055 NULL, &Ebx, NULL, &Edx.Uint32
2059 #define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00
2062 CPUID Intel RDT Monitoring Information EDX for CPUID leaf
2063 #CPUID_INTEL_RDT_MONITORING, sub-leaf
2064 #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF.
2068 /// Individual bit fields
2073 /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.
2075 UINT32 L3CacheRDT_M
:1;
2076 UINT32 Reserved2
:30;
2079 /// All bit fields as a 32-bit value
2082 } CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX
;
2085 CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf
2087 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
2088 @param ECX CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01)
2090 @retval EAX Reserved.
2091 @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).
2092 @retval ECX Maximum range (zero-based) of RMID of this resource type.
2093 @retval EDX L3 Cache Intel RDT Monitoring Capability information described by the
2094 type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX.
2096 <b>Example usage</b>
2100 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;
2103 CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,
2104 NULL, &Ebx, &Ecx, &Edx.Uint32
2108 #define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01
2111 CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf
2112 #CPUID_INTEL_RDT_MONITORING, sub-leaf
2113 #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF.
2117 /// Individual bit fields
2121 /// [Bit 0] Supports L3 occupancy monitoring if 1.
2123 UINT32 L3CacheOccupancyMonitoring
:1;
2125 /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1.
2127 UINT32 L3CacheTotalBandwidthMonitoring
:1;
2129 /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1.
2131 UINT32 L3CacheLocalBandwidthMonitoring
:1;
2135 /// All bit fields as a 32-bit value
2138 } CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX
;
2142 CPUID Intel Resource Director Technology (Intel RDT) Allocation Information
2144 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10).
2145 @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).
2146 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01).
2147 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).
2149 #define CPUID_INTEL_RDT_ALLOCATION 0x10
2152 Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf
2154 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
2155 @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).
2157 @retval EAX Reserved.
2158 @retval EBX L3 and L2 Cache Allocation Technology information described by
2159 the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX.
2160 @retval ECX Reserved.
2161 @retval EDX Reserved.
2163 <b>Example usage</b>
2165 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;
2168 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,
2169 NULL, &Ebx.Uint32, NULL, NULL
2173 #define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00
2176 CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf
2177 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2178 #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF.
2182 /// Individual bit fields
2187 /// [Bit 1] Supports L3 Cache Allocation Technology if 1.
2189 UINT32 L3CacheAllocation
:1;
2191 /// [Bit 2] Supports L2 Cache Allocation Technology if 1.
2193 UINT32 L2CacheAllocation
:1;
2194 UINT32 Reserved2
:29;
2197 /// All bit fields as a 32-bit value
2200 } CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX
;
2204 L3 Cache Allocation Technology Enumeration Sub-leaf
2206 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
2207 @param ECX CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01)
2209 @retval EAX RESID L3 Cache Allocation Technology information described by
2210 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX.
2211 @retval EBX Bit-granular map of isolation/contention of allocation units.
2212 @retval ECX RESID L3 Cache Allocation Technology information described by
2213 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX.
2214 @retval EDX RESID L3 Cache Allocation Technology information described by
2215 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX.
2217 <b>Example usage</b>
2219 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;
2221 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;
2222 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;
2225 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,
2226 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32
2230 #define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01
2233 CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf
2234 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2235 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
2239 /// Individual bit fields
2243 /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
2244 /// using minus-one notation.
2246 UINT32 CapacityLength
:5;
2250 /// All bit fields as a 32-bit value
2253 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX
;
2256 CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf
2257 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2258 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
2262 /// Individual bit fields
2267 /// [Bit 1] Updates of COS should be infrequent if 1.
2269 UINT32 CosUpdatesInfrequent
:1;
2271 /// [Bit 2] Code and Data Prioritization Technology supported if 1.
2273 UINT32 CodeDataPrioritization
:1;
2274 UINT32 Reserved2
:29;
2277 /// All bit fields as a 32-bit value
2280 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX
;
2283 CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf
2284 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2285 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
2289 /// Individual bit fields
2293 /// [Bits 15:0] Highest COS number supported for this ResID.
2295 UINT32 HighestCosNumber
:16;
2299 /// All bit fields as a 32-bit value
2302 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX
;
2305 L2 Cache Allocation Technology Enumeration Sub-leaf
2307 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
2308 @param ECX CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02)
2310 @retval EAX RESID L2 Cache Allocation Technology information described by
2311 the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX.
2312 @retval EBX Bit-granular map of isolation/contention of allocation units.
2313 @retval ECX Reserved.
2314 @retval EDX RESID L2 Cache Allocation Technology information described by
2315 the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX.
2317 <b>Example usage</b>
2319 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;
2321 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;
2324 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,
2325 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
2329 #define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02
2332 CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf
2333 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2334 #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.
2338 /// Individual bit fields
2342 /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
2343 /// using minus-one notation.
2345 UINT32 CapacityLength
:5;
2349 /// All bit fields as a 32-bit value
2352 } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX
;
2355 CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf
2356 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2357 #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.
2361 /// Individual bit fields
2365 /// [Bits 15:0] Highest COS number supported for this ResID.
2367 UINT32 HighestCosNumber
:16;
2371 /// All bit fields as a 32-bit value
2374 } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX
;
2378 Intel SGX resource capability and configuration.
2379 See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves".
2381 If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying
2382 CPUID with EAX=12H on Intel SGX resource capability and configuration.
2384 @param EAX CPUID_INTEL_SGX (0x12)
2385 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00).
2386 CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01).
2387 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02).
2388 Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0])
2389 until the sub-leaf type is invalid.
2392 #define CPUID_INTEL_SGX 0x12
2395 Sub-Leaf 0 Enumeration of Intel SGX Capabilities.
2396 Enumerates Intel SGX capability, including enclave instruction opcode support.
2398 @param EAX CPUID_INTEL_SGX (0x12)
2399 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00)
2401 @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
2402 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX.
2403 @retval EBX MISCSELECT: Reports the bit vector of supported extended features
2404 that can be written to the MISC region of the SSA.
2405 @retval ECX Reserved.
2406 @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
2407 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX.
2409 <b>Example usage</b>
2411 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;
2413 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;
2416 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,
2417 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
2421 #define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00
2424 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,
2425 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
2429 /// Individual bit fields
2433 /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.
2437 /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.
2443 /// All bit fields as a 32-bit value
2446 } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX
;
2449 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX,
2450 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
2454 /// Individual bit fields
2458 /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes
2459 /// when not in 64-bit mode.
2461 UINT32 MaxEnclaveSize_Not64
:8;
2463 /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes
2464 /// when operating in 64-bit mode.
2466 UINT32 MaxEnclaveSize_64
:8;
2470 /// All bit fields as a 32-bit value
2473 } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX
;
2477 Sub-Leaf 1 Enumeration of Intel SGX Capabilities.
2478 Enumerates Intel SGX capability of processor state configuration and enclave
2479 configuration in the SECS structure.
2481 @param EAX CPUID_INTEL_SGX (0x12)
2482 @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01)
2484 @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can
2485 set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE
2486 only if EAX[n] is 1, where n < 32.
2487 @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can
2488 set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE
2489 only if EBX[n] is 1, where n < 32.
2490 @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can
2491 set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE
2492 only if ECX[n] is 1, where n < 32.
2493 @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can
2494 set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE
2495 only if EDX[n] is 1, where n < 32.
2497 <b>Example usage</b>
2505 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,
2506 &Eax, &Ebx, &Ecx, &Edx
2510 #define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01
2514 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.
2515 Enumerates available EPC resources.
2517 @param EAX CPUID_INTEL_SGX (0x12)
2518 @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02)
2520 @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2521 Resources is described by the type
2522 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX.
2523 @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2524 Resources is described by the type
2525 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX.
2526 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2527 Resources is described by the type
2528 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX.
2529 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2530 Resources is described by the type
2531 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX.
2533 <b>Example usage</b>
2535 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;
2536 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;
2537 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;
2538 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;
2541 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF,
2542 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
2546 #define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02
2549 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID
2550 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2554 /// Individual bit fields
2558 /// [Bit 3:0] Sub-leaf-type encoding.
2559 /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0.
2560 /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC)
2561 /// in EBX:EAX and EDX:ECX.
2562 /// All other encoding are reserved.
2564 UINT32 SubLeafType
:4;
2567 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of
2568 /// the base of the EPC section.
2570 UINT32 LowAddressOfEpcSection
:20;
2573 /// All bit fields as a 32-bit value
2576 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX
;
2579 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID
2580 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2584 /// Individual bit fields
2588 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of
2589 /// the base of the EPC section.
2591 UINT32 HighAddressOfEpcSection
:20;
2595 /// All bit fields as a 32-bit value
2598 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX
;
2601 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID
2602 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2606 /// Individual bit fields
2610 /// [Bit 3:0] The EPC section encoding.
2611 /// 0000b: Not valid.
2612 /// 0001b: The EPC section is confidentiality, integrity and replay protected.
2613 /// All other encoding are reserved.
2615 UINT32 EpcSection
:4;
2618 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the
2619 /// corresponding EPC section within the Processor Reserved Memory.
2621 UINT32 LowSizeOfEpcSection
:20;
2624 /// All bit fields as a 32-bit value
2627 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX
;
2630 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID
2631 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2635 /// Individual bit fields
2639 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the
2640 /// corresponding EPC section within the Processor Reserved Memory.
2642 UINT32 HighSizeOfEpcSection
:20;
2646 /// All bit fields as a 32-bit value
2649 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX
;
2653 CPUID Intel Processor Trace Information
2655 @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14)
2656 @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00).
2657 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).
2660 #define CPUID_INTEL_PROCESSOR_TRACE 0x14
2663 CPUID Intel Processor Trace Information Main Leaf
2665 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
2666 @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00)
2668 @retval EAX Reports the maximum sub-leaf supported in leaf 14H.
2669 @retval EBX Returns Intel processor trace information described by the
2670 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX.
2671 @retval ECX Returns Intel processor trace information described by the
2672 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX.
2673 @retval EDX Reserved.
2675 <b>Example usage</b>
2678 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;
2679 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
2682 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
2683 &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL
2687 #define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00
2690 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2691 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
2695 /// Individual bit fields
2699 /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,
2700 /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.
2704 /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate
2707 UINT32 ConfigurablePsb
:1;
2709 /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering,
2710 /// and preservation of Intel PT MSRs across warm reset.
2712 UINT32 IpTraceStopFiltering
:1;
2714 /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of
2715 /// COFI-based packets.
2719 /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set
2720 /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE
2721 /// can generate packets.
2725 /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set
2726 /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet
2729 UINT32 PowerEventTrace
:1;
2733 /// All bit fields as a 32-bit value
2736 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
;
2739 CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2740 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
2744 /// Individual bit fields
2748 /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence
2749 /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and
2750 /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
2754 /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to
2755 /// the maximum allowed by the MaskOrTableOffset field of
2756 /// IA32_RTIT_OUTPUT_MASK_PTRS.
2760 /// [Bit 2] If 1, indicates support of Single-Range Output scheme.
2762 UINT32 SingleRangeOutput
:1;
2764 /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem.
2766 UINT32 TraceTransportSubsystem
:1;
2769 /// [Bit 31] If 1, generated packets which contain IP payloads have LIP
2770 /// values, which include the CS base component.
2775 /// All bit fields as a 32-bit value
2778 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX
;
2782 CPUID Intel Processor Trace Information Sub-leaf
2784 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
2785 @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01)
2787 @retval EAX Returns Intel processor trace information described by the
2788 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX.
2789 @retval EBX Returns Intel processor trace information described by the
2790 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX.
2791 @retval ECX Reserved.
2792 @retval EDX Reserved.
2794 <b>Example usage</b>
2796 UINT32 MaximumSubLeaf;
2798 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;
2799 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;
2802 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
2803 &MaximumSubLeaf, NULL, NULL, NULL
2806 for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {
2808 CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,
2809 &Eax.Uint32, &Ebx.Uint32, NULL, NULL
2814 #define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01
2817 CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2818 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
2822 /// Individual bit fields
2826 /// [Bits 2:0] Number of configurable Address Ranges for filtering.
2828 UINT32 ConfigurableAddressRanges
:3;
2831 /// [Bits 31:16] Bitmap of supported MTC period encodings
2833 UINT32 MtcPeriodEncodings
:16;
2837 /// All bit fields as a 32-bit value
2840 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX
;
2843 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2844 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
2848 /// Individual bit fields
2852 /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.
2854 UINT32 CycleThresholdEncodings
:16;
2856 /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.
2858 UINT32 PsbFrequencyEncodings
:16;
2862 /// All bit fields as a 32-bit value
2865 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX
;
2869 CPUID Time Stamp Counter and Nominal Core Crystal Clock Information
2872 If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.
2873 EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core
2874 crystal clock frequency.
2875 If ECX is 0, the nominal core crystal clock frequency is not enumerated.
2876 "TSC frequency" = "core crystal clock frequency" * EBX/EAX.
2877 The core crystal clock may differ from the reference clock, bus clock, or core
2880 @param EAX CPUID_TIME_STAMP_COUNTER (0x15)
2882 @retval EAX An unsigned integer which is the denominator of the
2883 TSC/"core crystal clock" ratio
2884 @retval EBX An unsigned integer which is the numerator of the
2885 TSC/"core crystal clock" ratio.
2886 @retval ECX An unsigned integer which is the nominal frequency
2887 of the core crystal clock in Hz.
2888 @retval EDX Reserved.
2890 <b>Example usage</b>
2896 AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);
2899 #define CPUID_TIME_STAMP_COUNTER 0x15
2903 CPUID Processor Frequency Information
2906 Data is returned from this interface in accordance with the processor's
2907 specification and does not reflect actual values. Suitable use of this data
2908 includes the display of processor information in like manner to the processor
2909 brand string and for determining the appropriate range to use when displaying
2910 processor information e.g. frequency history graphs. The returned information
2911 should not be used for any other purpose as the returned information does not
2912 accurately correlate to information / counters returned by other processor
2913 interfaces. While a processor may support the Processor Frequency Information
2914 leaf, fields that return a value of zero are not supported.
2916 @param EAX CPUID_TIME_STAMP_COUNTER (0x16)
2918 @retval EAX Returns processor base frequency information described by the
2919 type CPUID_PROCESSOR_FREQUENCY_EAX.
2920 @retval EBX Returns maximum frequency information described by the type
2921 CPUID_PROCESSOR_FREQUENCY_EBX.
2922 @retval ECX Returns bus frequency information described by the type
2923 CPUID_PROCESSOR_FREQUENCY_ECX.
2924 @retval EDX Reserved.
2926 <b>Example usage</b>
2928 CPUID_PROCESSOR_FREQUENCY_EAX Eax;
2929 CPUID_PROCESSOR_FREQUENCY_EBX Ebx;
2930 CPUID_PROCESSOR_FREQUENCY_ECX Ecx;
2932 AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
2935 #define CPUID_PROCESSOR_FREQUENCY 0x16
2938 CPUID Processor Frequency Information EAX for CPUID leaf
2939 #CPUID_PROCESSOR_FREQUENCY.
2943 /// Individual bit fields
2947 /// [Bits 15:0] Processor Base Frequency (in MHz).
2949 UINT32 ProcessorBaseFrequency
:16;
2953 /// All bit fields as a 32-bit value
2956 } CPUID_PROCESSOR_FREQUENCY_EAX
;
2959 CPUID Processor Frequency Information EBX for CPUID leaf
2960 #CPUID_PROCESSOR_FREQUENCY.
2964 /// Individual bit fields
2968 /// [Bits 15:0] Maximum Frequency (in MHz).
2970 UINT32 MaximumFrequency
:16;
2974 /// All bit fields as a 32-bit value
2977 } CPUID_PROCESSOR_FREQUENCY_EBX
;
2980 CPUID Processor Frequency Information ECX for CPUID leaf
2981 #CPUID_PROCESSOR_FREQUENCY.
2985 /// Individual bit fields
2989 /// [Bits 15:0] Bus (Reference) Frequency (in MHz).
2991 UINT32 BusFrequency
:16;
2995 /// All bit fields as a 32-bit value
2998 } CPUID_PROCESSOR_FREQUENCY_ECX
;
3002 CPUID SoC Vendor Information
3004 @param EAX CPUID_SOC_VENDOR (0x17)
3005 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
3006 CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
3007 CPUID_SOC_VENDOR_BRAND_STRING1 (0x02)
3008 CPUID_SOC_VENDOR_BRAND_STRING1 (0x03)
3011 Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String
3012 is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC
3013 Vendor Brand String is constructed by concatenating in ascending order of
3014 EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.
3017 #define CPUID_SOC_VENDOR 0x17
3020 CPUID SoC Vendor Information
3022 @param EAX CPUID_SOC_VENDOR (0x17)
3023 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
3025 @retval EAX MaxSOCID_Index. Reports the maximum input value of supported
3026 sub-leaf in leaf 17H.
3027 @retval EBX Returns SoC Vendor information described by the type
3028 CPUID_SOC_VENDOR_MAIN_LEAF_EBX.
3029 @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC
3031 @retval EDX Stepping ID. A unique number within an SOC project that an SOC
3034 <b>Example usage</b>
3037 CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;
3042 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,
3043 &Eax, &Ebx.Uint32, &Ecx, &Edx
3047 #define CPUID_SOC_VENDOR_MAIN_LEAF 0x00
3050 CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf
3051 #CPUID_SOC_VENDOR_MAIN_LEAF.
3055 /// Individual bit fields
3059 /// [Bits 15:0] SOC Vendor ID.
3061 UINT32 SocVendorId
:16;
3063 /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry
3064 /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is
3065 /// assigned by Intel.
3067 UINT32 IsVendorScheme
:1;
3071 /// All bit fields as a 32-bit value
3074 } CPUID_SOC_VENDOR_MAIN_LEAF_EBX
;
3077 CPUID SoC Vendor Information
3079 @param EAX CPUID_SOC_VENDOR (0x17)
3080 @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
3082 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
3083 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3084 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
3085 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3086 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
3087 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3088 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
3089 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3091 <b>Example usage</b>
3093 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
3094 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
3095 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
3096 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
3099 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,
3100 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
3104 #define CPUID_SOC_VENDOR_BRAND_STRING1 0x01
3107 CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,
3108 #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3.
3112 /// 4 UTF-8 characters of Soc Vendor Brand String
3114 CHAR8 BrandString
[4];
3116 /// All fields as a 32-bit value
3119 } CPUID_SOC_VENDOR_BRAND_STRING_DATA
;
3122 CPUID SoC Vendor Information
3124 @param EAX CPUID_SOC_VENDOR (0x17)
3125 @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02)
3127 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
3128 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3129 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
3130 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3131 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
3132 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3133 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
3134 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3136 <b>Example usage</b>
3138 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
3139 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
3140 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
3141 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
3144 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,
3145 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
3149 #define CPUID_SOC_VENDOR_BRAND_STRING2 0x02
3152 CPUID SoC Vendor Information
3154 @param EAX CPUID_SOC_VENDOR (0x17)
3155 @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03)
3157 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
3158 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3159 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
3160 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3161 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
3162 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3163 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
3164 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3166 <b>Example usage</b>
3168 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
3169 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
3170 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
3171 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
3174 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,
3175 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
3179 #define CPUID_SOC_VENDOR_BRAND_STRING3 0x03
3183 CPUID Extended Function
3185 @param EAX CPUID_EXTENDED_FUNCTION (0x80000000)
3187 @retval EAX Maximum Input Value for Extended Function CPUID Information.
3188 @retval EBX Reserved.
3189 @retval ECX Reserved.
3190 @retval EDX Reserved.
3192 <b>Example usage</b>
3196 AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
3199 #define CPUID_EXTENDED_FUNCTION 0x80000000
3203 CPUID Extended Processor Signature and Feature Bits
3205 @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)
3207 @retval EAX CPUID_EXTENDED_CPU_SIG.
3208 @retval EBX Reserved.
3209 @retval ECX Extended Processor Signature and Feature Bits information
3210 described by the type CPUID_EXTENDED_CPU_SIG_ECX.
3211 @retval EDX Extended Processor Signature and Feature Bits information
3212 described by the type CPUID_EXTENDED_CPU_SIG_EDX.
3214 <b>Example usage</b>
3217 CPUID_EXTENDED_CPU_SIG_ECX Ecx;
3218 CPUID_EXTENDED_CPU_SIG_EDX Edx;
3220 AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);
3223 #define CPUID_EXTENDED_CPU_SIG 0x80000001
3226 CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf
3227 #CPUID_EXTENDED_CPU_SIG.
3231 /// Individual bit fields
3235 /// [Bit 0] LAHF/SAHF available in 64-bit mode.
3245 /// [Bit 8] PREFETCHW.
3248 UINT32 Reserved3
:23;
3251 /// All bit fields as a 32-bit value
3254 } CPUID_EXTENDED_CPU_SIG_ECX
;
3257 CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf
3258 #CPUID_EXTENDED_CPU_SIG.
3262 /// Individual bit fields
3265 UINT32 Reserved1
:11;
3267 /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.
3269 UINT32 SYSCALL_SYSRET
:1;
3272 /// [Bit 20] Execute Disable Bit available.
3277 /// [Bit 26] 1-GByte pages are available if 1.
3281 /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.
3286 /// [Bit 29] Intel(R) 64 Architecture available if 1.
3292 /// All bit fields as a 32-bit value
3295 } CPUID_EXTENDED_CPU_SIG_EDX
;
3299 CPUID Processor Brand String
3301 @param EAX CPUID_BRAND_STRING1 (0x80000002)
3303 @retval EAX Processor Brand String in type CPUID_BRAND_STRING_DATA.
3304 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3305 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3306 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3308 <b>Example usage</b>
3310 CPUID_BRAND_STRING_DATA Eax;
3311 CPUID_BRAND_STRING_DATA Ebx;
3312 CPUID_BRAND_STRING_DATA Ecx;
3313 CPUID_BRAND_STRING_DATA Edx;
3315 AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
3318 #define CPUID_BRAND_STRING1 0x80000002
3321 CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,
3322 #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3.
3326 /// 4 ASCII characters of Processor Brand String
3328 CHAR8 BrandString
[4];
3330 /// All fields as a 32-bit value
3333 } CPUID_BRAND_STRING_DATA
;
3336 CPUID Processor Brand String
3338 @param EAX CPUID_BRAND_STRING2 (0x80000003)
3340 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3341 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3342 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3343 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3345 <b>Example usage</b>
3347 CPUID_BRAND_STRING_DATA Eax;
3348 CPUID_BRAND_STRING_DATA Ebx;
3349 CPUID_BRAND_STRING_DATA Ecx;
3350 CPUID_BRAND_STRING_DATA Edx;
3352 AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
3355 #define CPUID_BRAND_STRING2 0x80000003
3358 CPUID Processor Brand String
3360 @param EAX CPUID_BRAND_STRING3 (0x80000004)
3362 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3363 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3364 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3365 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3367 <b>Example usage</b>
3369 CPUID_BRAND_STRING_DATA Eax;
3370 CPUID_BRAND_STRING_DATA Ebx;
3371 CPUID_BRAND_STRING_DATA Ecx;
3372 CPUID_BRAND_STRING_DATA Edx;
3374 AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
3377 #define CPUID_BRAND_STRING3 0x80000004
3381 CPUID Extended Cache information
3383 @param EAX CPUID_EXTENDED_CACHE_INFO (0x80000006)
3385 @retval EAX Reserved.
3386 @retval EBX Reserved.
3387 @retval ECX Extended cache information described by the type
3388 CPUID_EXTENDED_CACHE_INFO_ECX.
3389 @retval EDX Reserved.
3391 <b>Example usage</b>
3393 CPUID_EXTENDED_CACHE_INFO_ECX Ecx;
3395 AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);
3398 #define CPUID_EXTENDED_CACHE_INFO 0x80000006
3401 CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.
3405 /// Individual bit fields
3409 /// [Bits 7:0] Cache line size in bytes.
3411 UINT32 CacheLineSize
:8;
3414 /// [Bits 15:12] L2 Associativity field. Supported values are in the range
3415 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to
3416 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL
3418 UINT32 L2Associativity
:4;
3420 /// [Bits 31:16] Cache size in 1K units.
3422 UINT32 CacheSize
:16;
3425 /// All bit fields as a 32-bit value
3428 } CPUID_EXTENDED_CACHE_INFO_ECX
;
3431 /// @{ Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity
3433 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED 0x00
3434 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED 0x01
3435 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY 0x02
3436 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04
3437 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06
3438 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08
3439 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F
3445 CPUID Extended Time Stamp Counter information
3447 @param EAX CPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007)
3449 @retval EAX Reserved.
3450 @retval EBX Reserved.
3451 @retval ECX Reserved.
3452 @retval EDX Extended time stamp counter (TSC) information described by the
3453 type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX.
3455 <b>Example usage</b>
3457 CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;
3459 AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);
3462 #define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007
3465 CPUID Extended Time Stamp Counter information EDX for CPUID leaf
3466 #CPUID_EXTENDED_TIME_STAMP_COUNTER.
3470 /// Individual bit fields
3475 /// [Bit 8] Invariant TSC available if 1.
3477 UINT32 InvariantTsc
:1;
3478 UINT32 Reserved2
:23;
3481 /// All bit fields as a 32-bit value
3484 } CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX
;
3488 CPUID Linear Physical Address Size
3490 @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
3492 @retval EAX Linear/Physical Address Size described by the type
3493 CPUID_VIR_PHY_ADDRESS_SIZE_EAX.
3494 @retval EBX Reserved.
3495 @retval ECX Reserved.
3496 @retval EDX Reserved.
3498 <b>Example usage</b>
3500 CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;
3502 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);
3505 #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
3508 CPUID Linear Physical Address Size EAX for CPUID leaf
3509 #CPUID_VIR_PHY_ADDRESS_SIZE.
3513 /// Individual bit fields
3517 /// [Bits 7:0] Number of physical address bits.
3520 /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address
3521 /// number supported should come from this field.
3523 UINT32 PhysicalAddressBits
:8;
3525 /// [Bits 15:8] Number of linear address bits.
3527 UINT32 LinearAddressBits
:8;
3531 /// All bit fields as a 32-bit value
3534 } CPUID_VIR_PHY_ADDRESS_SIZE_EAX
;
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