2 CPUID leaf definitions.
4 Provides defines for CPUID leaf indexes. Data structures are provided for
5 registers returned by a CPUID leaf that contain one or more bit fields.
6 If a register returned is a single 32-bit value, then a data structure is
7 not provided for that register.
9 Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials are licensed and made available under
11 the terms and conditions of the BSD License which accompanies this distribution.
12 The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,
20 November 2018, CPUID instruction.
28 CPUID Signature Information
30 @param EAX CPUID_SIGNATURE (0x00)
32 @retval EAX Returns the highest value the CPUID instruction recognizes for
33 returning basic processor information. The value is returned is
35 @retval EBX First 4 characters of a vendor identification string.
36 @retval ECX Last 4 characters of a vendor identification string.
37 @retval EDX Middle 4 characters of a vendor identification string.
46 AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
49 #define CPUID_SIGNATURE 0x00
52 /// @{ CPUID signature values returned by Intel processors
54 #define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u')
55 #define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I')
56 #define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l')
63 CPUID Version Information
65 @param EAX CPUID_VERSION_INFO (0x01)
67 @retval EAX Returns Model, Family, Stepping Information described by the
68 type CPUID_VERSION_INFO_EAX.
69 @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by
70 the type CPUID_VERSION_INFO_EBX.
71 @retval ECX CPU Feature Information described by the type
72 CPUID_VERSION_INFO_ECX.
73 @retval EDX CPU Feature Information described by the type
74 CPUID_VERSION_INFO_EDX.
78 CPUID_VERSION_INFO_EAX Eax;
79 CPUID_VERSION_INFO_EBX Ebx;
80 CPUID_VERSION_INFO_ECX Ecx;
81 CPUID_VERSION_INFO_EDX Edx;
83 AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
86 #define CPUID_VERSION_INFO 0x01
89 CPUID Version Information returned in EAX for CPUID leaf
94 /// Individual bit fields
97 UINT32 SteppingId
:4; ///< [Bits 3:0] Stepping ID
98 UINT32 Model
:4; ///< [Bits 7:4] Model
99 UINT32 FamilyId
:4; ///< [Bits 11:8] Family
100 UINT32 ProcessorType
:2; ///< [Bits 13:12] Processor Type
101 UINT32 Reserved1
:2; ///< [Bits 15:14] Reserved
102 UINT32 ExtendedModelId
:4; ///< [Bits 19:16] Extended Model ID
103 UINT32 ExtendedFamilyId
:8; ///< [Bits 27:20] Extended Family ID
104 UINT32 Reserved2
:4; ///< Reserved
107 /// All bit fields as a 32-bit value
110 } CPUID_VERSION_INFO_EAX
;
113 /// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType
115 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00
116 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01
117 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02
123 CPUID Version Information returned in EBX for CPUID leaf
128 /// Individual bit fields
132 /// [Bits 7:0] Provides an entry into a brand string table that contains
133 /// brand strings for IA-32 processors.
137 /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH
138 /// and CLFLUSHOPT instructions in 8-byte increments. This field was
139 /// introduced in the Pentium 4 processor.
141 UINT32 CacheLineSize
:8;
143 /// [Bits 23:16] Maximum number of addressable IDs for logical processors
144 /// in this physical package.
147 /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is
148 /// the number of unique initial APICIDs reserved for addressing different
149 /// logical processors in a physical package. This field is only valid if
150 /// CPUID.1.EDX.HTT[bit 28]= 1.
152 UINT32 MaximumAddressableIdsForLogicalProcessors
:8;
154 /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the
155 /// processor during power up. This field was introduced in the Pentium 4
158 UINT32 InitialLocalApicId
:8;
161 /// All bit fields as a 32-bit value
164 } CPUID_VERSION_INFO_EBX
;
167 CPUID Version Information returned in ECX for CPUID leaf
172 /// Individual bit fields
176 /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the
177 /// processor supports this technology
181 /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ
182 /// instruction. Carryless Multiplication
186 /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports
187 /// DS area using 64-bit layout.
191 /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports
196 /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor
197 /// supports the extensions to the Debug Store feature to allow for branch
198 /// message storage qualified by CPL
202 /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the
203 /// processor supports this technology.
207 /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor
208 /// supports this technology
212 /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates
213 /// that the processor supports this technology
217 /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor
218 /// supports this technology
222 /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming
223 /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction
224 /// extensions are not present in the processor.
228 /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode
229 /// can be set to either adaptive mode or shared mode. A value of 0 indicates
230 /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR
231 /// Bit 24 (L1 Data Cache Context Mode) for details
235 /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE
236 /// MSR for silicon debug
240 /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple
241 /// Add) extensions using YMM state.
245 /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature
250 /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor
251 /// supports changing IA32_MISC_ENABLE[Bit 23].
253 UINT32 xTPR_Update_Control
:1;
255 /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the
256 /// processor supports the performance and debug feature indication MSR
257 /// IA32_PERF_CAPABILITIES.
262 /// [Bit 17] Process-context identifiers. A value of 1 indicates that the
263 /// processor supports PCIDs and that software may set CR4.PCIDE to 1.
267 /// [Bit 18] A value of 1 indicates the processor supports the ability to
268 /// prefetch data from a memory mapped device. Direct Cache Access.
272 /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.
276 /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.
280 /// [Bit 21] A value of 1 indicates that the processor supports x2APIC
285 /// [Bit 22] A value of 1 indicates that the processor supports MOVBE
290 /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT
295 /// [Bit 24] A value of 1 indicates that the processor's local APIC timer
296 /// supports one-shot operation using a TSC deadline value.
298 UINT32 TSC_Deadline
:1;
300 /// [Bit 25] A value of 1 indicates that the processor supports the AESNI
301 /// instruction extensions.
305 /// [Bit 26] A value of 1 indicates that the processor supports the
306 /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV
307 /// instructions, and XCR0.
311 /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]
312 /// to enable XSETBV/XGETBV instructions to access XCR0 and to support
313 /// processor extended state management using XSAVE/XRSTOR.
317 /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction
322 /// [Bit 29] A value of 1 indicates that processor supports 16-bit
323 /// floating-point conversion instructions.
327 /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.
331 /// [Bit 31] Always returns 0.
336 /// All bit fields as a 32-bit value
339 } CPUID_VERSION_INFO_ECX
;
342 CPUID Version Information returned in EDX for CPUID leaf
347 /// Individual bit fields
351 /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.
355 /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,
356 /// including CR4.VME for controlling the feature, CR4.PVI for protected
357 /// mode virtual interrupts, software interrupt indirection, expansion of
358 /// the TSS with the software indirection bitmap, and EFLAGS.VIF and
359 /// EFLAGS.VIP flags.
363 /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including
364 /// CR4.DE for controlling the feature, and optional trapping of accesses to
369 /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,
370 /// including CR4.PSE for controlling the feature, the defined dirty bit in
371 /// PDE (Page Directory Entries), optional reserved bit trapping in CR3,
376 /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,
377 /// including CR4.TSD for controlling privilege.
381 /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The
382 /// RDMSR and WRMSR instructions are supported. Some of the MSRs are
383 /// implementation dependent.
387 /// [Bit 6] Physical Address Extension. Physical addresses greater than 32
388 /// bits are supported: extended page table entry formats, an extra level in
389 /// the page translation tables is defined, 2-MByte pages are supported
390 /// instead of 4 Mbyte pages if PAE bit is 1.
394 /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine
395 /// Checks, including CR4.MCE for controlling the feature. This feature does
396 /// not define the model-specific implementations of machine-check error
397 /// logging, reporting, and processor shutdowns. Machine Check exception
398 /// handlers may have to depend on processor version to do model specific
399 /// processing of the exception, or test for the presence of the Machine
404 /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)
405 /// instruction is supported (implicitly locked and atomic).
409 /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable
410 /// Interrupt Controller (APIC), responding to memory mapped commands in the
411 /// physical address range FFFE0000H to FFFE0FFFH (by default - some
412 /// processors permit the APIC to be relocated).
417 /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT
418 /// and associated MSRs are supported.
422 /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap
423 /// MSR contains feature bits that describe what memory types are supported,
424 /// how many variable MTRRs are supported, and whether fixed MTRRs are
429 /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure
430 /// entries that map a page, indicating TLB entries that are common to
431 /// different processes and need not be flushed. The CR4.PGE bit controls
436 /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine
437 /// Check Architecture of reporting machine errors is supported. The MCG_CAP
438 /// MSR contains feature bits describing how many banks of error reporting
439 /// MSRs are supported.
443 /// [Bit 15] Conditional Move Instructions. The conditional move instruction
444 /// CMOV is supported. In addition, if x87 FPU is present as indicated by the
445 /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.
449 /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This
450 /// feature augments the Memory Type Range Registers (MTRRs), allowing an
451 /// operating system to specify attributes of memory accessed through a
452 /// linear address on a 4KB granularity.
456 /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical
457 /// memory beyond 4 GBytes are supported with 32-bit paging. This feature
458 /// indicates that upper bits of the physical address of a 4-MByte page are
459 /// encoded in bits 20:13 of the page-directory entry. Such physical
460 /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.
464 /// [Bit 18] Processor Serial Number. The processor supports the 96-bit
465 /// processor identification number feature and the feature is enabled.
469 /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.
474 /// [Bit 21] Debug Store. The processor supports the ability to write debug
475 /// information into a memory resident buffer. This feature is used by the
476 /// branch trace store (BTS) and precise event-based sampling (PEBS)
481 /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The
482 /// processor implements internal MSRs that allow processor temperature to
483 /// be monitored and processor performance to be modulated in predefined
484 /// duty cycles under software control.
488 /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX
493 /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR
494 /// instructions are supported for fast save and restore of the floating
495 /// point context. Presence of this bit also indicates that CR4.OSFXSR is
496 /// available for an operating system to indicate that it supports the
497 /// FXSAVE and FXRSTOR instructions.
501 /// [Bit 25] SSE. The processor supports the SSE extensions.
505 /// [Bit 26] SSE2. The processor supports the SSE2 extensions.
509 /// [Bit 27] Self Snoop. The processor supports the management of
510 /// conflicting memory types by performing a snoop of its own cache
511 /// structure for transactions issued to the bus.
515 /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT
516 /// indicates there is only a single logical processor in the package and
517 /// software should assume only a single APIC ID is reserved. A value of 1
518 /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of
519 /// addressable IDs for logical processors in this package) is valid for the
524 /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor
525 /// automatic thermal control circuitry (TCC).
530 /// [Bit 31] Pending Break Enable. The processor supports the use of the
531 /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is
532 /// asserted) to signal the processor that an interrupt is pending and that
533 /// the processor should return to normal operation to handle the interrupt.
534 /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.
539 /// All bit fields as a 32-bit value
542 } CPUID_VERSION_INFO_EDX
;
546 CPUID Cache and TLB Information
548 @param EAX CPUID_CACHE_INFO (0x02)
550 @retval EAX Cache and TLB Information described by the type
551 CPUID_CACHE_INFO_CACHE_TLB.
552 CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns
553 0x01 and must be ignored. Only valid if
554 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
555 @retval EBX Cache and TLB Information described by the type
556 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
557 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
558 @retval ECX Cache and TLB Information described by the type
559 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
560 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
561 @retval EDX Cache and TLB Information described by the type
562 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
563 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
567 CPUID_CACHE_INFO_CACHE_TLB Eax;
568 CPUID_CACHE_INFO_CACHE_TLB Ebx;
569 CPUID_CACHE_INFO_CACHE_TLB Ecx;
570 CPUID_CACHE_INFO_CACHE_TLB Edx;
572 AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
575 <b>Cache Descriptor values</b>
577 <tr><th>Value </th><th> Type </th><th> Description </th></tr>
578 <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr>
579 <tr><td> 0x01 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr>
580 <tr><td> 0x02 </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr>
581 <tr><td> 0x03 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr>
582 <tr><td> 0x04 </td><td> TLB </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr>
583 <tr><td> 0x05 </td><td> TLB </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr>
584 <tr><td> 0x06 </td><td> Cache </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative,
585 32 byte line size</td></tr>
586 <tr><td> 0x08 </td><td> Cache </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative,
587 32 byte line size</td></tr>
588 <tr><td> 0x09 </td><td> Cache </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative,
589 64 byte line size</td></tr>
590 <tr><td> 0x0A </td><td> Cache </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr>
591 <tr><td> 0x0B </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr>
592 <tr><td> 0x0C </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr>
593 <tr><td> 0x0D </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr>
594 <tr><td> 0x0E </td><td> Cache </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr>
595 <tr><td> 0x1D </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr>
596 <tr><td> 0x21 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr>
597 <tr><td> 0x22 </td><td> Cache </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size,
598 2 lines per sector</td></tr>
599 <tr><td> 0x23 </td><td> Cache </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size,
600 2 lines per sector</td></tr>
601 <tr><td> 0x24 </td><td> Cache </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr>
602 <tr><td> 0x25 </td><td> Cache </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size,
603 2 lines per sector</td></tr>
604 <tr><td> 0x29 </td><td> Cache </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size,
605 2 lines per sector</td></tr>
606 <tr><td> 0x2C </td><td> Cache </td><td> 1st-level data cache: 32 KBytes, 8-way set associative,
607 64 byte line size</td></tr>
608 <tr><td> 0x30 </td><td> Cache </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative,
609 64 byte line size</td></tr>
610 <tr><td> 0x40 </td><td> Cache </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache,
611 no 3rd-level cache</td></tr>
612 <tr><td> 0x41 </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr>
613 <tr><td> 0x42 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr>
614 <tr><td> 0x43 </td><td> Cache </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr>
615 <tr><td> 0x44 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr>
616 <tr><td> 0x45 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr>
617 <tr><td> 0x46 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr>
618 <tr><td> 0x47 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr>
619 <tr><td> 0x48 </td><td> Cache </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr>
620 <tr><td> 0x49 </td><td> Cache </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size
621 (Intel Xeon processor MP, Family 0FH, Model 06H)<BR>
622 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
623 <tr><td> 0x4A </td><td> Cache </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr>
624 <tr><td> 0x4B </td><td> Cache </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr>
625 <tr><td> 0x4C </td><td> Cache </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr>
626 <tr><td> 0x4D </td><td> Cache </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr>
627 <tr><td> 0x4E </td><td> Cache </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr>
628 <tr><td> 0x4F </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr>
629 <tr><td> 0x50 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr>
630 <tr><td> 0x51 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr>
631 <tr><td> 0x52 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr>
632 <tr><td> 0x55 </td><td> TLB </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr>
633 <tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>
634 <tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>
635 <tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>
636 <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>
637 <tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>
638 <tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>
639 <tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>
640 <tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>
641 <tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>
642 <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 2 MByte or 4 MByte pages, 4-way set associative,
643 32 entries and a separate array with 1 GByte pages, 4-way set associative,
645 <tr><td> 0x64 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 512 entries</td></tr>
646 <tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>
647 <tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>
648 <tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>
649 <tr><td> 0x6A </td><td> Cache </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr>
650 <tr><td> 0x6B </td><td> Cache </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr>
651 <tr><td> 0x6C </td><td> Cache </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr>
652 <tr><td> 0x6D </td><td> Cache </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr>
653 <tr><td> 0x70 </td><td> Cache </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr>
654 <tr><td> 0x71 </td><td> Cache </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr>
655 <tr><td> 0x72 </td><td> Cache </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr>
656 <tr><td> 0x76 </td><td> TLB </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr>
657 <tr><td> 0x78 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr>
658 <tr><td> 0x79 </td><td> Cache </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size,
659 2 lines per sector</td></tr>
660 <tr><td> 0x7A </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size,
661 2 lines per sector</td></tr>
662 <tr><td> 0x7B </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size,
663 2 lines per sector</td></tr>
664 <tr><td> 0x7C </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size,
665 2 lines per sector</td></tr>
666 <tr><td> 0x7D </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr>
667 <tr><td> 0x7F </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr>
668 <tr><td> 0x80 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr>
669 <tr><td> 0x82 </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr>
670 <tr><td> 0x83 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr>
671 <tr><td> 0x84 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr>
672 <tr><td> 0x85 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr>
673 <tr><td> 0x86 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
674 <tr><td> 0x87 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
675 <tr><td> 0xA0 </td><td> DTLB </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr>
676 <tr><td> 0xB0 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
677 <tr><td> 0xB1 </td><td> TLB </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr>
678 <tr><td> 0xB2 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr>
679 <tr><td> 0xB3 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
680 <tr><td> 0xB4 </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr>
681 <tr><td> 0xB5 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr>
682 <tr><td> 0xB6 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative,
683 128 entries</td></tr>
684 <tr><td> 0xBA </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr>
685 <tr><td> 0xC0 </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr>
686 <tr><td> 0xC1 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative,
687 1024 entries</td></tr>
688 <tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>
689 <tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,
690 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>
691 <tr><td> 0xC4 </td><td> DTLB </td><td> DTLB: 2M/4M Byte pages, 4-way associative, 32 entries</td></tr>
692 <tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>
693 <tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
694 <tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>
695 <tr><td> 0xD2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr>
696 <tr><td> 0xD6 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
697 <tr><td> 0xD7 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr>
698 <tr><td> 0xD8 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr>
699 <tr><td> 0xDC </td><td> Cache </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr>
700 <tr><td> 0xDD </td><td> Cache </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr>
701 <tr><td> 0xDE </td><td> Cache </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr>
702 <tr><td> 0xE2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr>
703 <tr><td> 0xE3 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
704 <tr><td> 0xE4 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr>
705 <tr><td> 0xEA </td><td> Cache </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr>
706 <tr><td> 0xEB </td><td> Cache </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr>
707 <tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr>
708 <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr>
709 <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr>
710 <tr><td> 0xFE </td><td> General </td><td> CPUID leaf 2 does not report TLB descriptor information; use CPUID
711 leaf 18H to query TLB and other address translation parameters.</td></tr>
712 <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information,
713 use CPUID leaf 4 to query cache parameters</td></tr>
716 #define CPUID_CACHE_INFO 0x02
719 CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID
720 leaf #CPUID_CACHE_INFO.
724 /// Individual bit fields
729 /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.
730 /// if 1, then none of the cache descriptor bytes in the register are valid.
735 /// Array of Cache and TLB descriptor bytes
737 UINT8 CacheDescriptor
[4];
739 /// All bit fields as a 32-bit value
742 } CPUID_CACHE_INFO_CACHE_TLB
;
746 CPUID Processor Serial Number
748 Processor serial number (PSN) is not supported in the Pentium 4 processor
749 or later. On all models, use the PSN flag (returned using CPUID) to check
750 for PSN support before accessing the feature.
752 @param EAX CPUID_SERIAL_NUMBER (0x03)
754 @retval EAX Reserved.
755 @retval EBX Reserved.
756 @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in
757 Pentium III processor only; otherwise, the value in this
758 register is reserved.)
759 @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in
760 Pentium III processor only; otherwise, the value in this
761 register is reserved.)
768 AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);
771 #define CPUID_SERIAL_NUMBER 0x03
775 CPUID Cache Parameters
777 @param EAX CPUID_CACHE_PARAMS (0x04)
778 @param ECX Cache Level. Valid values start at 0. Software can enumerate
779 the deterministic cache parameters for each level of the cache
780 hierarchy starting with an index value of 0, until the
781 parameters report the value associated with the CacheType
782 field in CPUID_CACHE_PARAMS_EAX is 0.
784 @retval EAX Returns cache type information described by the type
785 CPUID_CACHE_PARAMS_EAX.
786 @retval EBX Returns cache line and associativity information described by
787 the type CPUID_CACHE_PARAMS_EBX.
788 @retval ECX Returns the number of sets in the cache.
789 @retval EDX Returns cache WINVD/INVD behavior described by the type
790 CPUID_CACHE_PARAMS_EDX.
795 CPUID_CACHE_PARAMS_EAX Eax;
796 CPUID_CACHE_PARAMS_EBX Ebx;
798 CPUID_CACHE_PARAMS_EDX Edx;
803 CPUID_CACHE_PARAMS, CacheLevel,
804 &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32
807 } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
810 #define CPUID_CACHE_PARAMS 0x04
813 CPUID Cache Parameters Information returned in EAX for CPUID leaf
818 /// Individual bit fields
822 /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,
823 /// then there is no information for the requested cache level.
827 /// [Bits 7:5] Cache level (Starts at 1).
831 /// [Bit 8] Self Initializing cache level (does not need SW initialization).
833 UINT32 SelfInitializingCache
:1;
835 /// [Bit 9] Fully Associative cache.
837 UINT32 FullyAssociativeCache
:1;
839 /// [Bits 13:10] Reserved.
843 /// [Bits 25:14] Maximum number of addressable IDs for logical processors
844 /// sharing this cache.
846 /// Add one to the return value to get the result.
847 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14])
848 /// is the number of unique initial APIC IDs reserved for addressing
849 /// different logical processors sharing this cache.
851 UINT32 MaximumAddressableIdsForLogicalProcessors
:12;
853 /// [Bits 31:26] Maximum number of addressable IDs for processor cores in
854 /// the physical package.
856 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26])
857 /// is the number of unique Core_IDs reserved for addressing different
858 /// processor cores in a physical package. Core ID is a subset of bits of
859 /// the initial APIC ID.
860 /// The returned value is constant for valid initial values in ECX. Valid
861 /// ECX values start from 0.
863 UINT32 MaximumAddressableIdsForProcessorCores
:6;
866 /// All bit fields as a 32-bit value
869 } CPUID_CACHE_PARAMS_EAX
;
872 /// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType
874 #define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00
875 #define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01
876 #define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02
877 #define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03
883 CPUID Cache Parameters Information returned in EBX for CPUID leaf
888 /// Individual bit fields
892 /// [Bits 11:0] System Coherency Line Size. Add one to the return value to
897 /// [Bits 21:12] Physical Line Partitions. Add one to the return value to
900 UINT32 LinePartitions
:10;
902 /// [Bits 31:22] Ways of associativity. Add one to the return value to get
908 /// All bit fields as a 32-bit value
911 } CPUID_CACHE_PARAMS_EBX
;
914 CPUID Cache Parameters Information returned in EDX for CPUID leaf
919 /// Individual bit fields
923 /// [Bit 0] Write-Back Invalidate/Invalidate.
924 /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level
925 /// caches for threads sharing this cache.
926 /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of
927 /// non-originating threads sharing this cache.
931 /// [Bit 1] Cache Inclusiveness.
932 /// 0 = Cache is not inclusive of lower cache levels.
933 /// 1 = Cache is inclusive of lower cache levels.
935 UINT32 CacheInclusiveness
:1;
937 /// [Bit 2] Complex Cache Indexing.
938 /// 0 = Direct mapped cache.
939 /// 1 = A complex function is used to index the cache, potentially using all
942 UINT32 ComplexCacheIndexing
:1;
946 /// All bit fields as a 32-bit value
949 } CPUID_CACHE_PARAMS_EDX
;
953 CPUID MONITOR/MWAIT Information
955 @param EAX CPUID_MONITOR_MWAIT (0x05)
957 @retval EAX Smallest monitor-line size in bytes described by the type
958 CPUID_MONITOR_MWAIT_EAX.
959 @retval EBX Largest monitor-line size in bytes described by the type
960 CPUID_MONITOR_MWAIT_EBX.
961 @retval ECX Enumeration of Monitor-Mwait extensions support described by
962 the type CPUID_MONITOR_MWAIT_ECX.
963 @retval EDX Sub C-states supported described by the type
964 CPUID_MONITOR_MWAIT_EDX.
968 CPUID_MONITOR_MWAIT_EAX Eax;
969 CPUID_MONITOR_MWAIT_EBX Ebx;
970 CPUID_MONITOR_MWAIT_ECX Ecx;
971 CPUID_MONITOR_MWAIT_EDX Edx;
973 AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
976 #define CPUID_MONITOR_MWAIT 0x05
979 CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf
980 #CPUID_MONITOR_MWAIT.
984 /// Individual bit fields
988 /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's
989 /// monitor granularity).
991 UINT32 SmallestMonitorLineSize
:16;
995 /// All bit fields as a 32-bit value
998 } CPUID_MONITOR_MWAIT_EAX
;
1001 CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf
1002 #CPUID_MONITOR_MWAIT.
1006 /// Individual bit fields
1010 /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's
1011 /// monitor granularity).
1013 UINT32 LargestMonitorLineSize
:16;
1017 /// All bit fields as a 32-bit value
1020 } CPUID_MONITOR_MWAIT_EBX
;
1023 CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf
1024 #CPUID_MONITOR_MWAIT.
1028 /// Individual bit fields
1032 /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,
1033 /// and EDX are valid.
1035 UINT32 ExtensionsSupported
:1;
1037 /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when
1038 /// interrupts disabled.
1040 UINT32 InterruptAsBreak
:1;
1044 /// All bit fields as a 32-bit value
1047 } CPUID_MONITOR_MWAIT_ECX
;
1050 CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf
1051 #CPUID_MONITOR_MWAIT.
1054 The definition of C0 through C7 states for MWAIT extension are
1055 processor-specific C-states, not ACPI C-states.
1059 /// Individual bit fields
1063 /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.
1067 /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.
1071 /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.
1075 /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.
1079 /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.
1083 /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.
1087 /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.
1091 /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.
1096 /// All bit fields as a 32-bit value
1099 } CPUID_MONITOR_MWAIT_EDX
;
1103 CPUID Thermal and Power Management
1105 @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06)
1107 @retval EAX Thermal and power management features described by the type
1108 CPUID_THERMAL_POWER_MANAGEMENT_EAX.
1109 @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor
1110 described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX.
1111 @retval ECX Performance features described by the type
1112 CPUID_THERMAL_POWER_MANAGEMENT_ECX.
1113 @retval EDX Reserved.
1115 <b>Example usage</b>
1117 CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;
1118 CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;
1119 CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;
1121 AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
1124 #define CPUID_THERMAL_POWER_MANAGEMENT 0x06
1127 CPUID Thermal and Power Management Information returned in EAX for CPUID leaf
1128 #CPUID_THERMAL_POWER_MANAGEMENT.
1132 /// Individual bit fields
1136 /// [Bit 0] Digital temperature sensor is supported if set.
1138 UINT32 DigitalTemperatureSensor
:1;
1140 /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).
1142 UINT32 TurboBoostTechnology
:1;
1144 /// [Bit 2] APIC-Timer-always-running feature is supported if set.
1149 /// [Bit 4] Power limit notification controls are supported if set.
1153 /// [Bit 5] Clock modulation duty cycle extension is supported if set.
1157 /// [Bit 6] Package thermal management is supported if set.
1161 /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,
1162 /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
1166 /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.
1168 UINT32 HWP_Notification
:1;
1170 /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.
1172 UINT32 HWP_Activity_Window
:1;
1174 /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.
1176 UINT32 HWP_Energy_Performance_Preference
:1;
1178 /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.
1180 UINT32 HWP_Package_Level_Request
:1;
1183 /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,
1184 /// IA32_THREAD_STALL MSRs are supported if set.
1188 /// [Bit 14] Intel Turbo Boost Max Technology 3.0 available.
1190 UINT32 TurboBoostMaxTechnology30
:1;
1192 /// [Bit 15] HWP Capabilities.
1193 /// Highest Performance change is supported if set.
1195 UINT32 HWPCapabilities
:1;
1197 /// [Bit 16] HWP PECI override is supported if set.
1199 UINT32 HWPPECIOverride
:1;
1201 /// [Bit 17] Flexible HWP is supported if set.
1203 UINT32 FlexibleHWP
:1;
1205 /// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.
1207 UINT32 FastAccessMode
:1;
1210 /// [Bit 20] Ignoring Idle Logical Processor HWP request is supported if set.
1212 UINT32 IgnoringIdleLogicalProcessorHWPRequest
:1;
1213 UINT32 Reserved5
:11;
1216 /// All bit fields as a 32-bit value
1219 } CPUID_THERMAL_POWER_MANAGEMENT_EAX
;
1222 CPUID Thermal and Power Management Information returned in EBX for CPUID leaf
1223 #CPUID_THERMAL_POWER_MANAGEMENT.
1227 /// Individual bit fields
1231 /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.
1233 UINT32 InterruptThresholds
:4;
1237 /// All bit fields as a 32-bit value
1240 } CPUID_THERMAL_POWER_MANAGEMENT_EBX
;
1243 CPUID Thermal and Power Management Information returned in ECX for CPUID leaf
1244 #CPUID_THERMAL_POWER_MANAGEMENT.
1248 /// Individual bit fields
1252 /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF
1253 /// and IA32_APERF). The capability to provide a measure of delivered
1254 /// processor performance (since last reset of the counters), as a percentage
1255 /// of the expected processor performance when running at the TSC frequency.
1257 UINT32 HardwareCoordinationFeedback
:1;
1260 /// [Bit 3] If this bit is set, then the processor supports performance-energy
1261 /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS
1264 UINT32 PerformanceEnergyBias
:1;
1265 UINT32 Reserved2
:28;
1268 /// All bit fields as a 32-bit value
1271 } CPUID_THERMAL_POWER_MANAGEMENT_ECX
;
1275 CPUID Structured Extended Feature Flags Enumeration
1277 @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)
1278 @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00).
1281 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
1282 index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.
1284 @retval EAX The maximum input value for ECX to retrieve sub-leaf information.
1285 @retval EBX Structured Extended Feature Flags described by the type
1286 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX.
1287 @retval EBX Structured Extended Feature Flags described by the type
1288 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX.
1289 @retval EDX Reserved.
1291 <b>Example usage</b>
1294 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
1295 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;
1299 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
1300 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
1301 &Eax, NULL, NULL, NULL
1303 for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {
1305 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
1307 NULL, &Ebx.Uint32, &Ecx.Uint32, NULL
1312 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07
1315 /// CPUID Structured Extended Feature Flags Enumeration sub-leaf
1317 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00
1320 CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf
1321 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
1322 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
1326 /// Individual bit fields
1330 /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
1334 /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.
1336 UINT32 IA32_TSC_ADJUST
:1;
1338 /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT
1339 /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".
1343 /// [Bit 3] If 1 indicates the processor supports the first group of advanced
1344 /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)
1348 /// [Bit 4] Hardware Lock Elision
1352 /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.
1356 /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.
1358 UINT32 FDP_EXCPTN_ONLY
:1;
1360 /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.
1364 /// [Bit 8] If 1 indicates the processor supports the second group of
1365 /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,
1366 /// SARX, SHLX, SHRX)
1370 /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.
1372 UINT32 EnhancedRepMovsbStosb
:1;
1374 /// [Bit 10] If 1, supports INVPCID instruction for system software that
1375 /// manages process-context identifiers.
1379 /// [Bit 11] Restricted Transactional Memory
1383 /// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
1384 /// Monitoring capability if 1.
1388 /// [Bit 13] Deprecates FPU CS and FPU DS values if 1.
1390 UINT32 DeprecateFpuCsDs
:1;
1392 /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.
1396 /// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
1397 /// Allocation capability if 1.
1401 /// [Bit 16] AVX512F.
1405 /// [Bit 17] AVX512DQ.
1409 /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.
1413 /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX
1418 /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC
1419 /// instructions) if 1.
1423 /// [Bit 21] AVX512_IFMA.
1425 UINT32 AVX512_IFMA
:1;
1428 /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.
1430 UINT32 CLFLUSHOPT
:1;
1432 /// [Bit 24] If 1 indicates the processor supports the CLWB instruction.
1436 /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace
1439 UINT32 IntelProcessorTrace
:1;
1441 /// [Bit 26] AVX512PF. (Intel Xeon Phi only.).
1445 /// [Bit 27] AVX512ER. (Intel Xeon Phi only.).
1449 /// [Bit 28] AVX512CD.
1453 /// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R)
1454 /// SHA Extensions) if 1.
1458 /// [Bit 30] AVX512BW.
1462 /// [Bit 31] AVX512VL.
1467 /// All bit fields as a 32-bit value
1470 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
;
1473 CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf
1474 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
1475 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
1479 /// Individual bit fields
1483 /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.
1484 /// (Intel Xeon Phi only.)
1486 UINT32 PREFETCHWT1
:1;
1488 /// [Bit 1] AVX512_VBMI.
1490 UINT32 AVX512_VBMI
:1;
1492 /// [Bit 2] Supports user-mode instruction prevention if 1.
1496 /// [Bit 3] Supports protection keys for user-mode pages if 1.
1500 /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the
1501 /// RDPKRU/WRPKRU instructions).
1506 /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).
1508 UINT32 AVX512_VPOPCNTDQ
:1;
1511 /// [Bits 16] Supports 5-level paging if 1.
1513 UINT32 FiveLevelPage
:1;
1515 /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions
1520 /// [Bit 22] RDPID and IA32_TSC_AUX are available if 1.
1525 /// [Bit 30] Supports SGX Launch Configuration if 1.
1531 /// All bit fields as a 32-bit value
1534 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
;
1537 CPUID Structured Extended Feature Flags Enumeration in EDX for CPUID leaf
1538 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
1539 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
1543 /// Individual bit fields
1547 /// [Bit 1:0] Reserved.
1551 /// [Bit 2] AVX512_4VNNIW. (Intel Xeon Phi only.)
1553 UINT32 AVX512_4VNNIW
:1;
1555 /// [Bit 3] AVX512_4FMAPS. (Intel Xeon Phi only.)
1557 UINT32 AVX512_4FMAPS
:1;
1559 /// [Bit 25:4] Reserved.
1561 UINT32 Reserved2
:22;
1563 /// [Bit 26] Enumerates support for indirect branch restricted speculation
1564 /// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors
1565 /// that set this bit support the IA32_SPEC_CTRL MSR and the IA32_PRED_CMD
1566 /// MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS) and
1567 /// IA32_PRED_CMD[0] (IBPB).
1569 UINT32 EnumeratesSupportForIBRSAndIBPB
:1;
1571 /// [Bit 27] Enumerates support for single thread indirect branch
1572 /// predictors (STIBP). Processors that set this bit support the
1573 /// IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[1]
1576 UINT32 EnumeratesSupportForSTIBP
:1;
1578 /// [Bit 28] Enumerates support for L1D_FLUSH. Processors that set this bit
1579 /// support the IA32_FLUSH_CMD MSR. They allow software to set
1580 /// IA32_FLUSH_CMD[0] (L1D_FLUSH).
1582 UINT32 EnumeratesSupportForL1D_FLUSH
:1;
1584 /// [Bit 29] Enumerates support for the IA32_ARCH_CAPABILITIES MSR.
1586 UINT32 EnumeratesSupportForCapability
:1;
1588 /// [Bit 30] Reserved.
1592 /// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD).
1593 /// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow
1594 /// software to set IA32_SPEC_CTRL[2] (SSBD).
1596 UINT32 EnumeratesSupportForSSBD
:1;
1599 /// All bit fields as a 32-bit value
1602 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX
;
1605 CPUID Direct Cache Access Information
1607 @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09)
1609 @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).
1610 @retval EBX Reserved.
1611 @retval ECX Reserved.
1612 @retval EDX Reserved.
1614 <b>Example usage</b>
1618 AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);
1621 #define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09
1625 CPUID Architectural Performance Monitoring
1627 @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A)
1629 @retval EAX Architectural Performance Monitoring information described by
1630 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX.
1631 @retval EBX Architectural Performance Monitoring information described by
1632 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX.
1633 @retval ECX Reserved.
1634 @retval EDX Architectural Performance Monitoring information described by
1635 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX.
1637 <b>Example usage</b>
1639 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;
1640 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;
1641 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;
1643 AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);
1646 #define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A
1649 CPUID Architectural Performance Monitoring EAX for CPUID leaf
1650 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1654 /// Individual bit fields
1658 /// [Bit 7:0] Version ID of architectural performance monitoring.
1660 UINT32 ArchPerfMonVerID
:8;
1662 /// [Bits 15:8] Number of general-purpose performance monitoring counter
1663 /// per logical processor.
1665 /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous
1666 /// block of MSR address space. Each performance event select register is
1667 /// paired with a corresponding performance counter in the 0C1H address
1670 UINT32 PerformanceMonitorCounters
:8;
1672 /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.
1674 /// The bit width of an IA32_PMCx MSR. This the number of valid bits for
1675 /// read operation. On write operations, the lower-order 32 bits of the MSR
1676 /// may be written with any value, and the high-order bits are sign-extended
1677 /// from the value of bit 31.
1679 UINT32 PerformanceMonitorCounterWidth
:8;
1681 /// [Bits 31:24] Length of EBX bit vector to enumerate architectural
1682 /// performance monitoring events.
1684 UINT32 EbxBitVectorLength
:8;
1687 /// All bit fields as a 32-bit value
1690 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX
;
1693 CPUID Architectural Performance Monitoring EBX for CPUID leaf
1694 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1698 /// Individual bit fields
1702 /// [Bit 0] Core cycle event not available if 1.
1704 UINT32 UnhaltedCoreCycles
:1;
1706 /// [Bit 1] Instruction retired event not available if 1.
1708 UINT32 InstructionsRetired
:1;
1710 /// [Bit 2] Reference cycles event not available if 1.
1712 UINT32 UnhaltedReferenceCycles
:1;
1714 /// [Bit 3] Last-level cache reference event not available if 1.
1716 UINT32 LastLevelCacheReferences
:1;
1718 /// [Bit 4] Last-level cache misses event not available if 1.
1720 UINT32 LastLevelCacheMisses
:1;
1722 /// [Bit 5] Branch instruction retired event not available if 1.
1724 UINT32 BranchInstructionsRetired
:1;
1726 /// [Bit 6] Branch mispredict retired event not available if 1.
1728 UINT32 AllBranchMispredictRetired
:1;
1732 /// All bit fields as a 32-bit value
1735 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
;
1738 CPUID Architectural Performance Monitoring EDX for CPUID leaf
1739 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1743 /// Individual bit fields
1747 /// [Bits 4:0] Number of fixed-function performance counters
1748 /// (if Version ID > 1).
1750 UINT32 FixedFunctionPerformanceCounters
:5;
1752 /// [Bits 12:5] Bit width of fixed-function performance counters
1753 /// (if Version ID > 1).
1755 UINT32 FixedFunctionPerformanceCounterWidth
:8;
1758 /// [Bits 15] AnyThread deprecation.
1760 UINT32 AnyThreadDeprecation
:1;
1761 UINT32 Reserved2
:16;
1764 /// All bit fields as a 32-bit value
1767 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX
;
1771 CPUID Extended Topology Information
1774 CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first
1775 checking for the existence of Leaf 1FH before using leaf 0BH.
1776 Most of Leaf 0BH output depends on the initial value in ECX. The EDX output
1777 of leaf 0BH is always valid and does not vary with input value in ECX. Output
1778 value in ECX[7:0] always equals input value in ECX[7:0].
1779 Sub-leaf index 0 enumerates SMT level. Each subsequent higher sub-leaf index
1780 enumerates a higher-level topological entity in hierarchical order.
1781 For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and
1783 If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],
1784 other input values with ECX > n also return 0 in ECX[15:8].
1786 @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B)
1787 @param ECX Level number
1789 @retval EAX Extended topology information described by the type
1790 CPUID_EXTENDED_TOPOLOGY_EAX.
1791 @retval EBX Extended topology information described by the type
1792 CPUID_EXTENDED_TOPOLOGY_EBX.
1793 @retval ECX Extended topology information described by the type
1794 CPUID_EXTENDED_TOPOLOGY_ECX.
1795 @retval EDX x2APIC ID the current logical processor.
1797 <b>Example usage</b>
1799 CPUID_EXTENDED_TOPOLOGY_EAX Eax;
1800 CPUID_EXTENDED_TOPOLOGY_EBX Ebx;
1801 CPUID_EXTENDED_TOPOLOGY_ECX Ecx;
1808 CPUID_EXTENDED_TOPOLOGY, LevelNumber,
1809 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx
1812 } while (Eax.Bits.ApicIdShift != 0);
1815 #define CPUID_EXTENDED_TOPOLOGY 0x0B
1818 CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1822 /// Individual bit fields
1826 /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique
1827 /// topology ID of the next level type. All logical processors with the
1828 /// same next level ID share current level.
1831 /// Software should use this field (EAX[4:0]) to enumerate processor
1832 /// topology of the system.
1834 UINT32 ApicIdShift
:5;
1838 /// All bit fields as a 32-bit value
1841 } CPUID_EXTENDED_TOPOLOGY_EAX
;
1844 CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1848 /// Individual bit fields
1852 /// [Bits 15:0] Number of logical processors at this level type. The number
1853 /// reflects configuration as shipped by Intel.
1856 /// Software must not use EBX[15:0] to enumerate processor topology of the
1857 /// system. This value in this field (EBX[15:0]) is only intended for
1858 /// display/diagnostic purposes. The actual number of logical processors
1859 /// available to BIOS/OS/Applications may be different from the value of
1860 /// EBX[15:0], depending on software and platform hardware configurations.
1862 UINT32 LogicalProcessors
:16;
1866 /// All bit fields as a 32-bit value
1869 } CPUID_EXTENDED_TOPOLOGY_EBX
;
1872 CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1876 /// Individual bit fields
1880 /// [Bits 7:0] Level number. Same value in ECX input.
1882 UINT32 LevelNumber
:8;
1884 /// [Bits 15:8] Level type.
1887 /// The value of the "level type" field is not related to level numbers in
1888 /// any way, higher "level type" values do not mean higher levels.
1894 /// All bit fields as a 32-bit value
1897 } CPUID_EXTENDED_TOPOLOGY_ECX
;
1900 /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
1902 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00
1903 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01
1904 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02
1911 CPUID Extended State Information
1913 @param EAX CPUID_EXTENDED_STATE (0x0D)
1914 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00).
1915 CPUID_EXTENDED_STATE_SUB_LEAF (0x01).
1916 CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).
1917 Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.
1919 #define CPUID_EXTENDED_STATE 0x0D
1922 CPUID Extended State Information Main Leaf
1924 @param EAX CPUID_EXTENDED_STATE (0x0D)
1925 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)
1927 @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n]
1928 can be set to 1 only if EAX[n] is 1. The format of the extended
1929 state main leaf is described by the type
1930 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX.
1931 @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
1932 area) required by enabled features in XCR0. May be different than
1933 ECX if some features at the end of the XSAVE save area are not
1935 @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
1936 area) of the XSAVE/XRSTOR save area required by all supported
1937 features in the processor, i.e., all the valid bit fields in XCR0.
1938 @retval EDX Reports the supported bits of the upper 32 bits of XCR0.
1939 XCR0[n+32] can be set to 1 only if EDX[n] is 1.
1941 <b>Example usage</b>
1943 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;
1949 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,
1950 &Eax.Uint32, &Ebx, &Ecx, &Edx
1954 #define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00
1957 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
1958 sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF.
1962 /// Individual bit fields
1966 /// [Bit 0] x87 state.
1970 /// [Bit 1] SSE state.
1974 /// [Bit 2] AVX state.
1978 /// [Bits 4:3] MPX state.
1982 /// [Bits 7:5] AVX-512 state.
1986 /// [Bit 8] Used for IA32_XSS.
1990 /// [Bit 9] PKRU state.
1995 /// [Bit 13] Used for IA32_XSS, part 2.
1997 UINT32 IA32_XSS_2
:1;
1998 UINT32 Reserved2
:18;
2001 /// All bit fields as a 32-bit value
2004 } CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
;
2007 CPUID Extended State Information Sub Leaf
2009 @param EAX CPUID_EXTENDED_STATE (0x0D)
2010 @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01)
2012 @retval EAX The format of the extended state sub-leaf is described by the
2013 type CPUID_EXTENDED_STATE_SUB_LEAF_EAX.
2014 @retval EBX The size in bytes of the XSAVE area containing all states
2015 enabled by XCRO | IA32_XSS.
2016 @retval ECX The format of the extended state sub-leaf is described by the
2017 type CPUID_EXTENDED_STATE_SUB_LEAF_ECX.
2018 @retval EDX Reports the supported bits of the upper 32 bits of the
2019 IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.
2021 <b>Example usage</b>
2023 CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;
2025 CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;
2029 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,
2030 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx
2034 #define CPUID_EXTENDED_STATE_SUB_LEAF 0x01
2037 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
2038 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
2042 /// Individual bit fields
2046 /// [Bit 0] XSAVEOPT is available.
2050 /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.
2054 /// [Bit 2] Supports XGETBV with ECX = 1 if set.
2058 /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.
2064 /// All bit fields as a 32-bit value
2067 } CPUID_EXTENDED_STATE_SUB_LEAF_EAX
;
2070 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
2071 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
2075 /// Individual bit fields
2079 /// [Bits 7:0] Used for XCR0.
2083 /// [Bit 8] PT STate.
2087 /// [Bit 9] Used for XCR0.
2092 /// [Bit 13] HWP state.
2095 UINT32 Reserved8
:18;
2098 /// All bit fields as a 32-bit value
2101 } CPUID_EXTENDED_STATE_SUB_LEAF_ECX
;
2104 CPUID Extended State Information Size and Offset Sub Leaf
2107 Leaf 0DH output depends on the initial value in ECX.
2108 Each sub-leaf index (starting at position 2) is supported if it corresponds to
2109 a supported bit in either the XCR0 register or the IA32_XSS MSR.
2110 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
2111 n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1
2112 returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0
2113 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].
2115 @param EAX CPUID_EXTENDED_STATE (0x0D)
2116 @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based
2117 on supported bits in XCR0 or IA32_XSS_MSR.
2119 @retval EAX The size in bytes (from the offset specified in EBX) of the save
2120 area for an extended state feature associated with a valid
2122 @retval EBX The offset in bytes of this extended state component's save area
2123 from the beginning of the XSAVE/XRSTOR area. This field reports
2124 0 if the sub-leaf index, n, does not map to a valid bit in the
2126 @retval ECX The format of the extended state components's save area as
2127 described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX.
2128 This field reports 0 if the sub-leaf index, n, is invalid.
2129 @retval EDX This field reports 0 if the sub-leaf index, n, is invalid;
2130 otherwise it is reserved.
2132 <b>Example usage</b>
2136 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;
2140 for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {
2142 CPUID_EXTENDED_STATE, SubLeaf,
2143 &Eax, &Ebx, &Ecx.Uint32, &Edx
2148 #define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02
2151 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
2152 sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET.
2156 /// Individual bit fields
2160 /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is
2161 /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported
2166 /// [Bit 1] is set if, when the compacted format of an XSAVE area is used,
2167 /// this extended state component located on the next 64-byte boundary
2168 /// following the preceding state component (otherwise, it is located
2169 /// immediately following the preceding state component).
2175 /// All bit fields as a 32-bit value
2178 } CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX
;
2182 CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
2184 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
2185 @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00).
2186 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).
2189 #define CPUID_INTEL_RDT_MONITORING 0x0F
2192 CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
2193 Enumeration Sub-leaf
2195 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
2196 @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00)
2198 @retval EAX Reserved.
2199 @retval EBX Maximum range (zero-based) of RMID within this physical
2200 processor of all types.
2201 @retval ECX Reserved.
2202 @retval EDX L3 Cache Intel RDT Monitoring Information Enumeration described by
2203 the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX.
2205 <b>Example usage</b>
2208 CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
2211 CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,
2212 NULL, &Ebx, NULL, &Edx.Uint32
2216 #define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00
2219 CPUID Intel RDT Monitoring Information EDX for CPUID leaf
2220 #CPUID_INTEL_RDT_MONITORING, sub-leaf
2221 #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF.
2225 /// Individual bit fields
2230 /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.
2232 UINT32 L3CacheRDT_M
:1;
2233 UINT32 Reserved2
:30;
2236 /// All bit fields as a 32-bit value
2239 } CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX
;
2242 CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf
2244 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
2245 @param ECX CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01)
2247 @retval EAX Reserved.
2248 @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).
2249 @retval ECX Maximum range (zero-based) of RMID of this resource type.
2250 @retval EDX L3 Cache Intel RDT Monitoring Capability information described by the
2251 type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX.
2253 <b>Example usage</b>
2257 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;
2260 CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,
2261 NULL, &Ebx, &Ecx, &Edx.Uint32
2265 #define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01
2268 CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf
2269 #CPUID_INTEL_RDT_MONITORING, sub-leaf
2270 #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF.
2274 /// Individual bit fields
2278 /// [Bit 0] Supports L3 occupancy monitoring if 1.
2280 UINT32 L3CacheOccupancyMonitoring
:1;
2282 /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1.
2284 UINT32 L3CacheTotalBandwidthMonitoring
:1;
2286 /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1.
2288 UINT32 L3CacheLocalBandwidthMonitoring
:1;
2292 /// All bit fields as a 32-bit value
2295 } CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX
;
2299 CPUID Intel Resource Director Technology (Intel RDT) Allocation Information
2301 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10).
2302 @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).
2303 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01).
2304 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).
2306 #define CPUID_INTEL_RDT_ALLOCATION 0x10
2309 Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf
2311 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
2312 @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).
2314 @retval EAX Reserved.
2315 @retval EBX L3 and L2 Cache Allocation Technology information described by
2316 the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX.
2317 @retval ECX Reserved.
2318 @retval EDX Reserved.
2320 <b>Example usage</b>
2322 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;
2325 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,
2326 NULL, &Ebx.Uint32, NULL, NULL
2330 #define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00
2333 CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf
2334 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2335 #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF.
2339 /// Individual bit fields
2344 /// [Bit 1] Supports L3 Cache Allocation Technology if 1.
2346 UINT32 L3CacheAllocation
:1;
2348 /// [Bit 2] Supports L2 Cache Allocation Technology if 1.
2350 UINT32 L2CacheAllocation
:1;
2352 /// [Bit 3] Supports Memory Bandwidth Allocation if 1.
2354 UINT32 MemoryBandwidth
:1;
2355 UINT32 Reserved3
:28;
2358 /// All bit fields as a 32-bit value
2361 } CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX
;
2365 L3 Cache Allocation Technology Enumeration Sub-leaf
2367 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
2368 @param ECX CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01)
2370 @retval EAX RESID L3 Cache Allocation Technology information described by
2371 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX.
2372 @retval EBX Bit-granular map of isolation/contention of allocation units.
2373 @retval ECX RESID L3 Cache Allocation Technology information described by
2374 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX.
2375 @retval EDX RESID L3 Cache Allocation Technology information described by
2376 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX.
2378 <b>Example usage</b>
2380 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;
2382 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;
2383 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;
2386 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,
2387 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32
2391 #define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01
2394 CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf
2395 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2396 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
2400 /// Individual bit fields
2404 /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
2405 /// using minus-one notation.
2407 UINT32 CapacityLength
:5;
2411 /// All bit fields as a 32-bit value
2414 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX
;
2417 CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf
2418 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2419 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
2423 /// Individual bit fields
2428 /// [Bit 2] Code and Data Prioritization Technology supported if 1.
2430 UINT32 CodeDataPrioritization
:1;
2431 UINT32 Reserved2
:29;
2434 /// All bit fields as a 32-bit value
2437 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX
;
2440 CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf
2441 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2442 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
2446 /// Individual bit fields
2450 /// [Bits 15:0] Highest COS number supported for this ResID.
2452 UINT32 HighestCosNumber
:16;
2456 /// All bit fields as a 32-bit value
2459 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX
;
2462 L2 Cache Allocation Technology Enumeration Sub-leaf
2464 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
2465 @param ECX CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02)
2467 @retval EAX RESID L2 Cache Allocation Technology information described by
2468 the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX.
2469 @retval EBX Bit-granular map of isolation/contention of allocation units.
2470 @retval ECX Reserved.
2471 @retval EDX RESID L2 Cache Allocation Technology information described by
2472 the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX.
2474 <b>Example usage</b>
2476 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;
2478 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;
2481 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,
2482 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
2486 #define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02
2489 CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf
2490 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2491 #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.
2495 /// Individual bit fields
2499 /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
2500 /// using minus-one notation.
2502 UINT32 CapacityLength
:5;
2506 /// All bit fields as a 32-bit value
2509 } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX
;
2512 CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf
2513 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2514 #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.
2518 /// Individual bit fields
2522 /// [Bits 15:0] Highest COS number supported for this ResID.
2524 UINT32 HighestCosNumber
:16;
2528 /// All bit fields as a 32-bit value
2531 } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX
;
2534 Memory Bandwidth Allocation Enumeration Sub-leaf
2536 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
2537 @param ECX CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF (0x03)
2539 @retval EAX RESID memory bandwidth Allocation Technology information
2540 described by the type
2541 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX.
2542 @retval EBX Reserved.
2543 @retval ECX RESID memory bandwidth Allocation Technology information
2544 described by the type
2545 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX.
2546 @retval EDX RESID memory bandwidth Allocation Technology information
2547 described by the type
2548 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX.
2550 <b>Example usage</b>
2552 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX Eax;
2554 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX Ecx;
2555 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx;
2559 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,
2560 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
2564 #define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03
2567 CPUID memory bandwidth Allocation Technology Information EAX for CPUID leaf
2568 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2569 #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.
2573 /// Individual bit fields
2577 /// [Bits 11:0] Reports the maximum MBA throttling value supported for
2578 /// the corresponding ResID using minus-one notation.
2580 UINT32 MaximumMBAThrottling
:12;
2584 /// All bit fields as a 32-bit value
2587 } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX
;
2590 CPUID memory bandwidth Allocation Technology Information ECX for CPUID leaf
2591 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2592 #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.
2596 /// Individual bit fields
2600 /// [Bits 1:0] Reserved.
2604 /// [Bits 3] Reports whether the response of the delay values is linear.
2607 UINT32 Reserved2
:29;
2610 /// All bit fields as a 32-bit value
2613 } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX
;
2616 CPUID memory bandwidth Allocation Technology Information EDX for CPUID leaf
2617 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2618 #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.
2622 /// Individual bit fields
2626 /// [Bits 15:0] Highest COS number supported for this ResID.
2628 UINT32 HighestCosNumber
:16;
2632 /// All bit fields as a 32-bit value
2635 } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX
;
2638 Intel SGX resource capability and configuration.
2639 See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves".
2641 If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying
2642 CPUID with EAX=12H on Intel SGX resource capability and configuration.
2644 @param EAX CPUID_INTEL_SGX (0x12)
2645 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00).
2646 CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01).
2647 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02).
2648 Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0])
2649 until the sub-leaf type is invalid.
2652 #define CPUID_INTEL_SGX 0x12
2655 Sub-Leaf 0 Enumeration of Intel SGX Capabilities.
2656 Enumerates Intel SGX capability, including enclave instruction opcode support.
2658 @param EAX CPUID_INTEL_SGX (0x12)
2659 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00)
2661 @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
2662 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX.
2663 @retval EBX MISCSELECT: Reports the bit vector of supported extended features
2664 that can be written to the MISC region of the SSA.
2665 @retval ECX Reserved.
2666 @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
2667 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX.
2669 <b>Example usage</b>
2671 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;
2673 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;
2676 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,
2677 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
2681 #define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00
2684 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,
2685 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
2689 /// Individual bit fields
2693 /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.
2697 /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.
2702 /// [Bit 5] If 1, indicates Intel SGX supports ENCLV instruction leaves
2703 /// EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT.
2707 /// [Bit 6] If 1, indicates Intel SGX supports ENCLS instruction leaves ETRACKC,
2708 /// ERDINFO, ELDBC, and ELDUC.
2711 UINT32 Reserved2
:25;
2714 /// All bit fields as a 32-bit value
2717 } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX
;
2720 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX,
2721 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
2725 /// Individual bit fields
2729 /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes
2730 /// when not in 64-bit mode.
2732 UINT32 MaxEnclaveSize_Not64
:8;
2734 /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes
2735 /// when operating in 64-bit mode.
2737 UINT32 MaxEnclaveSize_64
:8;
2741 /// All bit fields as a 32-bit value
2744 } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX
;
2748 Sub-Leaf 1 Enumeration of Intel SGX Capabilities.
2749 Enumerates Intel SGX capability of processor state configuration and enclave
2750 configuration in the SECS structure.
2752 @param EAX CPUID_INTEL_SGX (0x12)
2753 @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01)
2755 @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can
2756 set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE
2757 only if EAX[n] is 1, where n < 32.
2758 @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can
2759 set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE
2760 only if EBX[n] is 1, where n < 32.
2761 @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can
2762 set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE
2763 only if ECX[n] is 1, where n < 32.
2764 @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can
2765 set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE
2766 only if EDX[n] is 1, where n < 32.
2768 <b>Example usage</b>
2776 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,
2777 &Eax, &Ebx, &Ecx, &Edx
2781 #define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01
2785 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.
2786 Enumerates available EPC resources.
2788 @param EAX CPUID_INTEL_SGX (0x12)
2789 @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02)
2791 @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2792 Resources is described by the type
2793 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX.
2794 @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2795 Resources is described by the type
2796 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX.
2797 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2798 Resources is described by the type
2799 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX.
2800 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2801 Resources is described by the type
2802 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX.
2804 <b>Example usage</b>
2806 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;
2807 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;
2808 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;
2809 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;
2812 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF,
2813 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
2817 #define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02
2820 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID
2821 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2825 /// Individual bit fields
2829 /// [Bit 3:0] Sub-leaf-type encoding.
2830 /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0.
2831 /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC)
2832 /// in EBX:EAX and EDX:ECX.
2833 /// All other encoding are reserved.
2835 UINT32 SubLeafType
:4;
2838 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of
2839 /// the base of the EPC section.
2841 UINT32 LowAddressOfEpcSection
:20;
2844 /// All bit fields as a 32-bit value
2847 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX
;
2850 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID
2851 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2855 /// Individual bit fields
2859 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of
2860 /// the base of the EPC section.
2862 UINT32 HighAddressOfEpcSection
:20;
2866 /// All bit fields as a 32-bit value
2869 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX
;
2872 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID
2873 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2877 /// Individual bit fields
2881 /// [Bit 3:0] The EPC section encoding.
2882 /// 0000b: Not valid.
2883 /// 0001b: The EPC section is confidentiality, integrity and replay protected.
2884 /// All other encoding are reserved.
2886 UINT32 EpcSection
:4;
2889 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the
2890 /// corresponding EPC section within the Processor Reserved Memory.
2892 UINT32 LowSizeOfEpcSection
:20;
2895 /// All bit fields as a 32-bit value
2898 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX
;
2901 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID
2902 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2906 /// Individual bit fields
2910 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the
2911 /// corresponding EPC section within the Processor Reserved Memory.
2913 UINT32 HighSizeOfEpcSection
:20;
2917 /// All bit fields as a 32-bit value
2920 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX
;
2924 CPUID Intel Processor Trace Information
2926 @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14)
2927 @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00).
2928 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).
2931 #define CPUID_INTEL_PROCESSOR_TRACE 0x14
2934 CPUID Intel Processor Trace Information Main Leaf
2936 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
2937 @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00)
2939 @retval EAX Reports the maximum sub-leaf supported in leaf 14H.
2940 @retval EBX Returns Intel processor trace information described by the
2941 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX.
2942 @retval ECX Returns Intel processor trace information described by the
2943 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX.
2944 @retval EDX Reserved.
2946 <b>Example usage</b>
2949 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;
2950 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
2953 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
2954 &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL
2958 #define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00
2961 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2962 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
2966 /// Individual bit fields
2970 /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,
2971 /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.
2975 /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate
2978 UINT32 ConfigurablePsb
:1;
2980 /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering,
2981 /// and preservation of Intel PT MSRs across warm reset.
2983 UINT32 IpTraceStopFiltering
:1;
2985 /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of
2986 /// COFI-based packets.
2990 /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set
2991 /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE
2992 /// can generate packets.
2996 /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set
2997 /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet
3000 UINT32 PowerEventTrace
:1;
3004 /// All bit fields as a 32-bit value
3007 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
;
3010 CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
3011 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
3015 /// Individual bit fields
3019 /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence
3020 /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and
3021 /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
3025 /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to
3026 /// the maximum allowed by the MaskOrTableOffset field of
3027 /// IA32_RTIT_OUTPUT_MASK_PTRS.
3031 /// [Bit 2] If 1, indicates support of Single-Range Output scheme.
3033 UINT32 SingleRangeOutput
:1;
3035 /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem.
3037 UINT32 TraceTransportSubsystem
:1;
3040 /// [Bit 31] If 1, generated packets which contain IP payloads have LIP
3041 /// values, which include the CS base component.
3046 /// All bit fields as a 32-bit value
3049 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX
;
3053 CPUID Intel Processor Trace Information Sub-leaf
3055 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
3056 @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01)
3058 @retval EAX Returns Intel processor trace information described by the
3059 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX.
3060 @retval EBX Returns Intel processor trace information described by the
3061 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX.
3062 @retval ECX Reserved.
3063 @retval EDX Reserved.
3065 <b>Example usage</b>
3067 UINT32 MaximumSubLeaf;
3069 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;
3070 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;
3073 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
3074 &MaximumSubLeaf, NULL, NULL, NULL
3077 for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {
3079 CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,
3080 &Eax.Uint32, &Ebx.Uint32, NULL, NULL
3085 #define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01
3088 CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
3089 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
3093 /// Individual bit fields
3097 /// [Bits 2:0] Number of configurable Address Ranges for filtering.
3099 UINT32 ConfigurableAddressRanges
:3;
3102 /// [Bits 31:16] Bitmap of supported MTC period encodings
3104 UINT32 MtcPeriodEncodings
:16;
3108 /// All bit fields as a 32-bit value
3111 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX
;
3114 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
3115 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
3119 /// Individual bit fields
3123 /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.
3125 UINT32 CycleThresholdEncodings
:16;
3127 /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.
3129 UINT32 PsbFrequencyEncodings
:16;
3133 /// All bit fields as a 32-bit value
3136 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX
;
3140 CPUID Time Stamp Counter and Nominal Core Crystal Clock Information
3143 If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.
3144 EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core
3145 crystal clock frequency.
3146 If ECX is 0, the nominal core crystal clock frequency is not enumerated.
3147 "TSC frequency" = "core crystal clock frequency" * EBX/EAX.
3148 The core crystal clock may differ from the reference clock, bus clock, or core
3151 @param EAX CPUID_TIME_STAMP_COUNTER (0x15)
3153 @retval EAX An unsigned integer which is the denominator of the
3154 TSC/"core crystal clock" ratio
3155 @retval EBX An unsigned integer which is the numerator of the
3156 TSC/"core crystal clock" ratio.
3157 @retval ECX An unsigned integer which is the nominal frequency
3158 of the core crystal clock in Hz.
3159 @retval EDX Reserved.
3161 <b>Example usage</b>
3167 AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);
3170 #define CPUID_TIME_STAMP_COUNTER 0x15
3174 CPUID Processor Frequency Information
3177 Data is returned from this interface in accordance with the processor's
3178 specification and does not reflect actual values. Suitable use of this data
3179 includes the display of processor information in like manner to the processor
3180 brand string and for determining the appropriate range to use when displaying
3181 processor information e.g. frequency history graphs. The returned information
3182 should not be used for any other purpose as the returned information does not
3183 accurately correlate to information / counters returned by other processor
3184 interfaces. While a processor may support the Processor Frequency Information
3185 leaf, fields that return a value of zero are not supported.
3187 @param EAX CPUID_TIME_STAMP_COUNTER (0x16)
3189 @retval EAX Returns processor base frequency information described by the
3190 type CPUID_PROCESSOR_FREQUENCY_EAX.
3191 @retval EBX Returns maximum frequency information described by the type
3192 CPUID_PROCESSOR_FREQUENCY_EBX.
3193 @retval ECX Returns bus frequency information described by the type
3194 CPUID_PROCESSOR_FREQUENCY_ECX.
3195 @retval EDX Reserved.
3197 <b>Example usage</b>
3199 CPUID_PROCESSOR_FREQUENCY_EAX Eax;
3200 CPUID_PROCESSOR_FREQUENCY_EBX Ebx;
3201 CPUID_PROCESSOR_FREQUENCY_ECX Ecx;
3203 AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
3206 #define CPUID_PROCESSOR_FREQUENCY 0x16
3209 CPUID Processor Frequency Information EAX for CPUID leaf
3210 #CPUID_PROCESSOR_FREQUENCY.
3214 /// Individual bit fields
3218 /// [Bits 15:0] Processor Base Frequency (in MHz).
3220 UINT32 ProcessorBaseFrequency
:16;
3224 /// All bit fields as a 32-bit value
3227 } CPUID_PROCESSOR_FREQUENCY_EAX
;
3230 CPUID Processor Frequency Information EBX for CPUID leaf
3231 #CPUID_PROCESSOR_FREQUENCY.
3235 /// Individual bit fields
3239 /// [Bits 15:0] Maximum Frequency (in MHz).
3241 UINT32 MaximumFrequency
:16;
3245 /// All bit fields as a 32-bit value
3248 } CPUID_PROCESSOR_FREQUENCY_EBX
;
3251 CPUID Processor Frequency Information ECX for CPUID leaf
3252 #CPUID_PROCESSOR_FREQUENCY.
3256 /// Individual bit fields
3260 /// [Bits 15:0] Bus (Reference) Frequency (in MHz).
3262 UINT32 BusFrequency
:16;
3266 /// All bit fields as a 32-bit value
3269 } CPUID_PROCESSOR_FREQUENCY_ECX
;
3273 CPUID SoC Vendor Information
3275 @param EAX CPUID_SOC_VENDOR (0x17)
3276 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
3277 CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
3278 CPUID_SOC_VENDOR_BRAND_STRING1 (0x02)
3279 CPUID_SOC_VENDOR_BRAND_STRING1 (0x03)
3282 Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String
3283 is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC
3284 Vendor Brand String is constructed by concatenating in ascending order of
3285 EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.
3288 #define CPUID_SOC_VENDOR 0x17
3291 CPUID SoC Vendor Information
3293 @param EAX CPUID_SOC_VENDOR (0x17)
3294 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
3296 @retval EAX MaxSOCID_Index. Reports the maximum input value of supported
3297 sub-leaf in leaf 17H.
3298 @retval EBX Returns SoC Vendor information described by the type
3299 CPUID_SOC_VENDOR_MAIN_LEAF_EBX.
3300 @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC
3302 @retval EDX Stepping ID. A unique number within an SOC project that an SOC
3305 <b>Example usage</b>
3308 CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;
3313 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,
3314 &Eax, &Ebx.Uint32, &Ecx, &Edx
3318 #define CPUID_SOC_VENDOR_MAIN_LEAF 0x00
3321 CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf
3322 #CPUID_SOC_VENDOR_MAIN_LEAF.
3326 /// Individual bit fields
3330 /// [Bits 15:0] SOC Vendor ID.
3332 UINT32 SocVendorId
:16;
3334 /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry
3335 /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is
3336 /// assigned by Intel.
3338 UINT32 IsVendorScheme
:1;
3342 /// All bit fields as a 32-bit value
3345 } CPUID_SOC_VENDOR_MAIN_LEAF_EBX
;
3348 CPUID SoC Vendor Information
3350 @param EAX CPUID_SOC_VENDOR (0x17)
3351 @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
3353 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
3354 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3355 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
3356 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3357 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
3358 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3359 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
3360 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3362 <b>Example usage</b>
3364 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
3365 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
3366 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
3367 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
3370 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,
3371 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
3375 #define CPUID_SOC_VENDOR_BRAND_STRING1 0x01
3378 CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,
3379 #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3.
3383 /// 4 UTF-8 characters of Soc Vendor Brand String
3385 CHAR8 BrandString
[4];
3387 /// All fields as a 32-bit value
3390 } CPUID_SOC_VENDOR_BRAND_STRING_DATA
;
3393 CPUID SoC Vendor Information
3395 @param EAX CPUID_SOC_VENDOR (0x17)
3396 @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02)
3398 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
3399 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3400 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
3401 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3402 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
3403 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3404 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
3405 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3407 <b>Example usage</b>
3409 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
3410 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
3411 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
3412 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
3415 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,
3416 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
3420 #define CPUID_SOC_VENDOR_BRAND_STRING2 0x02
3423 CPUID SoC Vendor Information
3425 @param EAX CPUID_SOC_VENDOR (0x17)
3426 @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03)
3428 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
3429 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3430 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
3431 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3432 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
3433 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3434 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
3435 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3437 <b>Example usage</b>
3439 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
3440 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
3441 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
3442 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
3445 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,
3446 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
3450 #define CPUID_SOC_VENDOR_BRAND_STRING3 0x03
3453 CPUID Deterministic Address Translation Parameters
3456 Each sub-leaf enumerates a different address translation structure.
3457 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
3458 index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX. A
3459 sub-leaf index is also invalid if EDX[4:0] returns 0.
3460 Valid sub-leaves do not need to be contiguous or in any particular order. A
3461 valid sub-leaf may be in a higher input ECX value than an invalid sub-leaf or
3462 than a valid sub-leaf of a higher or lower-level structure.
3463 * Some unified TLBs will allow a single TLB entry to satisfy data read/write
3464 and instruction fetches. Others will require separate entries (e.g., one
3465 loaded on data read/write and another loaded on an instruction fetch).
3466 Please see the Intel 64 and IA-32 Architectures Optimization Reference Manual
3467 for details of a particular product.
3468 ** Add one to the return value to get the result.
3470 @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18)
3471 @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00)
3472 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_SUB_LEAF (0x*)
3475 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18
3478 CPUID Deterministic Address Translation Parameters
3480 @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18)
3481 @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00)
3483 @retval EAX Reports the maximum input value of supported sub-leaf in leaf 18H.
3484 @retval EBX Returns Deterministic Address Translation Parameters described by
3485 the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX.
3486 @retval ECX Number of Sets.
3487 @retval EDX Returns Deterministic Address Translation Parameters described by
3488 the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.
3490 <b>Example usage</b>
3493 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX Ebx;
3495 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX Edx;
3498 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS,
3499 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF,
3500 &Eax, &Ebx.Uint32, &Ecx, &Edx.Uint32
3504 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00
3507 CPUID Deterministic Address Translation Parameters EBX for CPUID leafs.
3511 /// Individual bit fields
3515 /// [Bits 0] 4K page size entries supported by this structure.
3519 /// [Bits 1] 2MB page size entries supported by this structure.
3523 /// [Bits 2] 4MB page size entries supported by this structure.
3527 /// [Bits 3] 1 GB page size entries supported by this structure.
3531 /// [Bits 7:4] Reserved.
3535 /// [Bits 10:8] Partitioning (0: Soft partitioning between the logical
3536 /// processors sharing this structure)
3538 UINT32 Partitioning
:3;
3540 /// [Bits 15:11] Reserved.
3544 /// [Bits 31:16] W = Ways of associativity.
3549 /// All bit fields as a 32-bit value
3552 } CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX
;
3555 CPUID Deterministic Address Translation Parameters EDX for CPUID leafs.
3559 /// Individual bit fields
3563 /// [Bits 4:0] Translation cache type field.
3565 UINT32 TranslationCacheType
:5;
3567 /// [Bits 7:5] Translation cache level (starts at 1).
3569 UINT32 TranslationCacheLevel
:3;
3571 /// [Bits 8] Fully associative structure.
3573 UINT32 FullyAssociative
:1;
3575 /// [Bits 13:9] Reserved.
3579 /// [Bits 25:14] Maximum number of addressable IDs for logical
3580 /// processors sharing this translation cache.
3582 UINT32 MaximumNum
:12;
3584 /// [Bits 31:26] Reserved.
3589 /// All bit fields as a 32-bit value
3592 } CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX
;
3595 /// @{ Define value for CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.TranslationCacheType
3597 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INVALID 0x00
3598 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_DATA_TLB 0x01
3599 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INSTRUCTION_TLB 0x02
3600 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_UNIFIED_TLB 0x03
3607 CPUID V2 Extended Topology Enumeration Leaf
3610 CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking
3611 for the existence of Leaf 1FH and using this if available.
3612 Most of Leaf 1FH output depends on the initial value in ECX. The EDX output of leaf
3613 1FH is always valid and does not vary with input value in ECX. Output value in ECX[7:0]
3614 always equals input value in ECX[7:0]. Sub-leaf index 0 enumerates SMT level. Each
3615 subsequent higher sub-leaf index enumerates a higher-level topological entity in
3616 hierarchical order. For sub-leaves that return an invalid level-type of 0 in ECX[15:8];
3617 EAX and EBX will return 0. If an input value n in ECX returns the invalid level-type of
3618 0 in ECX[15:8], other input values with ECX > n also return 0 in ECX[15:8].
3620 Software should use this field (EAX[4:0]) to enumerate processor topology of the system.
3621 Software must not use EBX[15:0] to enumerate processor topology of the system. This value
3622 in this field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual
3623 number of logical processors available to BIOS/OS/Applications may be different from the
3624 value of EBX[15:0], depending on software and platform hardware configurations.
3626 @param EAX CPUID_V2_EXTENDED_TOPOLOGY (0x1F)
3627 @param ECX Level number
3630 #define CPUID_V2_EXTENDED_TOPOLOGY 0x1F
3633 /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
3634 /// The value of the "level type" field is not related to level numbers in
3635 /// any way, higher "level type" values do not mean higher levels.
3637 #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03
3638 #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04
3639 #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05
3645 CPUID Extended Function
3647 @param EAX CPUID_EXTENDED_FUNCTION (0x80000000)
3649 @retval EAX Maximum Input Value for Extended Function CPUID Information.
3650 @retval EBX Reserved.
3651 @retval ECX Reserved.
3652 @retval EDX Reserved.
3654 <b>Example usage</b>
3658 AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
3661 #define CPUID_EXTENDED_FUNCTION 0x80000000
3665 CPUID Extended Processor Signature and Feature Bits
3667 @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)
3669 @retval EAX CPUID_EXTENDED_CPU_SIG.
3670 @retval EBX Reserved.
3671 @retval ECX Extended Processor Signature and Feature Bits information
3672 described by the type CPUID_EXTENDED_CPU_SIG_ECX.
3673 @retval EDX Extended Processor Signature and Feature Bits information
3674 described by the type CPUID_EXTENDED_CPU_SIG_EDX.
3676 <b>Example usage</b>
3679 CPUID_EXTENDED_CPU_SIG_ECX Ecx;
3680 CPUID_EXTENDED_CPU_SIG_EDX Edx;
3682 AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);
3685 #define CPUID_EXTENDED_CPU_SIG 0x80000001
3688 CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf
3689 #CPUID_EXTENDED_CPU_SIG.
3693 /// Individual bit fields
3697 /// [Bit 0] LAHF/SAHF available in 64-bit mode.
3707 /// [Bit 8] PREFETCHW.
3710 UINT32 Reserved3
:23;
3713 /// All bit fields as a 32-bit value
3716 } CPUID_EXTENDED_CPU_SIG_ECX
;
3719 CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf
3720 #CPUID_EXTENDED_CPU_SIG.
3724 /// Individual bit fields
3727 UINT32 Reserved1
:11;
3729 /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.
3731 UINT32 SYSCALL_SYSRET
:1;
3734 /// [Bit 20] Execute Disable Bit available.
3739 /// [Bit 26] 1-GByte pages are available if 1.
3743 /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.
3748 /// [Bit 29] Intel(R) 64 Architecture available if 1.
3754 /// All bit fields as a 32-bit value
3757 } CPUID_EXTENDED_CPU_SIG_EDX
;
3761 CPUID Processor Brand String
3763 @param EAX CPUID_BRAND_STRING1 (0x80000002)
3765 @retval EAX Processor Brand String in type CPUID_BRAND_STRING_DATA.
3766 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3767 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3768 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3770 <b>Example usage</b>
3772 CPUID_BRAND_STRING_DATA Eax;
3773 CPUID_BRAND_STRING_DATA Ebx;
3774 CPUID_BRAND_STRING_DATA Ecx;
3775 CPUID_BRAND_STRING_DATA Edx;
3777 AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
3780 #define CPUID_BRAND_STRING1 0x80000002
3783 CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,
3784 #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3.
3788 /// 4 ASCII characters of Processor Brand String
3790 CHAR8 BrandString
[4];
3792 /// All fields as a 32-bit value
3795 } CPUID_BRAND_STRING_DATA
;
3798 CPUID Processor Brand String
3800 @param EAX CPUID_BRAND_STRING2 (0x80000003)
3802 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3803 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3804 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3805 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3807 <b>Example usage</b>
3809 CPUID_BRAND_STRING_DATA Eax;
3810 CPUID_BRAND_STRING_DATA Ebx;
3811 CPUID_BRAND_STRING_DATA Ecx;
3812 CPUID_BRAND_STRING_DATA Edx;
3814 AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
3817 #define CPUID_BRAND_STRING2 0x80000003
3820 CPUID Processor Brand String
3822 @param EAX CPUID_BRAND_STRING3 (0x80000004)
3824 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3825 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3826 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3827 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3829 <b>Example usage</b>
3831 CPUID_BRAND_STRING_DATA Eax;
3832 CPUID_BRAND_STRING_DATA Ebx;
3833 CPUID_BRAND_STRING_DATA Ecx;
3834 CPUID_BRAND_STRING_DATA Edx;
3836 AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
3839 #define CPUID_BRAND_STRING3 0x80000004
3843 CPUID Extended Cache information
3845 @param EAX CPUID_EXTENDED_CACHE_INFO (0x80000006)
3847 @retval EAX Reserved.
3848 @retval EBX Reserved.
3849 @retval ECX Extended cache information described by the type
3850 CPUID_EXTENDED_CACHE_INFO_ECX.
3851 @retval EDX Reserved.
3853 <b>Example usage</b>
3855 CPUID_EXTENDED_CACHE_INFO_ECX Ecx;
3857 AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);
3860 #define CPUID_EXTENDED_CACHE_INFO 0x80000006
3863 CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.
3867 /// Individual bit fields
3871 /// [Bits 7:0] Cache line size in bytes.
3873 UINT32 CacheLineSize
:8;
3876 /// [Bits 15:12] L2 Associativity field. Supported values are in the range
3877 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to
3878 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL
3880 UINT32 L2Associativity
:4;
3882 /// [Bits 31:16] Cache size in 1K units.
3884 UINT32 CacheSize
:16;
3887 /// All bit fields as a 32-bit value
3890 } CPUID_EXTENDED_CACHE_INFO_ECX
;
3893 /// @{ Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity
3895 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED 0x00
3896 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED 0x01
3897 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY 0x02
3898 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04
3899 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06
3900 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08
3901 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_32_WAY 0x0A
3902 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_48_WAY 0x0B
3903 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_64_WAY 0x0C
3904 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_96_WAY 0x0D
3905 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_128_WAY 0x0E
3906 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F
3912 CPUID Extended Time Stamp Counter information
3914 @param EAX CPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007)
3916 @retval EAX Reserved.
3917 @retval EBX Reserved.
3918 @retval ECX Reserved.
3919 @retval EDX Extended time stamp counter (TSC) information described by the
3920 type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX.
3922 <b>Example usage</b>
3924 CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;
3926 AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);
3929 #define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007
3932 CPUID Extended Time Stamp Counter information EDX for CPUID leaf
3933 #CPUID_EXTENDED_TIME_STAMP_COUNTER.
3937 /// Individual bit fields
3942 /// [Bit 8] Invariant TSC available if 1.
3944 UINT32 InvariantTsc
:1;
3945 UINT32 Reserved2
:23;
3948 /// All bit fields as a 32-bit value
3951 } CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX
;
3955 CPUID Linear Physical Address Size
3957 @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
3959 @retval EAX Linear/Physical Address Size described by the type
3960 CPUID_VIR_PHY_ADDRESS_SIZE_EAX.
3961 @retval EBX Reserved.
3962 @retval ECX Reserved.
3963 @retval EDX Reserved.
3965 <b>Example usage</b>
3967 CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;
3969 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);
3972 #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
3975 CPUID Linear Physical Address Size EAX for CPUID leaf
3976 #CPUID_VIR_PHY_ADDRESS_SIZE.
3980 /// Individual bit fields
3984 /// [Bits 7:0] Number of physical address bits.
3987 /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address
3988 /// number supported should come from this field.
3990 UINT32 PhysicalAddressBits
:8;
3992 /// [Bits 15:8] Number of linear address bits.
3994 UINT32 LinearAddressBits
:8;
3998 /// All bit fields as a 32-bit value
4001 } CPUID_VIR_PHY_ADDRESS_SIZE_EAX
;
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