UefiCpuPkg/Include/Register/LocalApic.h

   1 /** @file
   2   IA32 Local APIC Definitions.
   3
   4   Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef __LOCAL_APIC_H__
  16 #define __LOCAL_APIC_H__
  17
  18 //
  19 // Definitions for IA32 architectural MSRs
  20 //
  21 #define MSR_IA32_APIC_BASE_ADDRESS              0x1B
  22
  23 //
  24 // Definitions for CPUID instruction
  25 //
  26 #define CPUID_VERSION_INFO                      0x1
  27 #define CPUID_EXTENDED_FUNCTION                 0x80000000
  28 #define CPUID_VIR_PHY_ADDRESS_SIZE              0x80000008
  29
  30 //
  31 // Definition for Local APIC registers and related values
  32 //
  33 #define XAPIC_ID_OFFSET                         0x20
  34 #define XAPIC_VERSION_OFFSET                    0x30
  35 #define XAPIC_EOI_OFFSET                        0x0b0
  36 #define XAPIC_ICR_DFR_OFFSET                    0x0e0
  37 #define XAPIC_SPURIOUS_VECTOR_OFFSET            0x0f0
  38 #define XAPIC_ICR_LOW_OFFSET                    0x300
  39 #define XAPIC_ICR_HIGH_OFFSET                   0x310
  40 #define XAPIC_LVT_TIMER_OFFSET                  0x320
  41 #define XAPIC_LVT_LINT0_OFFSET                  0x350
  42 #define XAPIC_LVT_LINT1_OFFSET                  0x360
  43 #define XAPIC_TIMER_INIT_COUNT_OFFSET           0x380
  44 #define XAPIC_TIMER_CURRENT_COUNT_OFFSET        0x390
  45 #define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0
  46
  47 #define X2APIC_MSR_BASE_ADDRESS                 0x800
  48 #define X2APIC_MSR_ICR_ADDRESS                  0x830
  49
  50 #define LOCAL_APIC_DELIVERY_MODE_FIXED           0
  51 #define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
  52 #define LOCAL_APIC_DELIVERY_MODE_SMI             2
  53 #define LOCAL_APIC_DELIVERY_MODE_NMI             4
  54 #define LOCAL_APIC_DELIVERY_MODE_INIT            5
  55 #define LOCAL_APIC_DELIVERY_MODE_STARTUP         6
  56 #define LOCAL_APIC_DELIVERY_MODE_EXTINT          7
  57
  58 #define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND       0
  59 #define LOCAL_APIC_DESTINATION_SHORTHAND_SELF               1
  60 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
  61 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3
  62
  63 typedef union {
  64   struct {
  65     UINT64  Reserved0:8;   ///< Reserved.
  66     UINT64  Bsp:1;         ///< Processor is BSP.
  67     UINT64  Reserved1:1;   ///< Reserved.
  68     UINT64  Extd:1;        ///< Enable x2APIC mode.
  69     UINT64  En:1;          ///< xAPIC global enable/disable.
  70     UINT64  ApicBase:52;   ///< APIC Base physical address. The actual field width depends on physical address width.
  71   } Bits;
  72   UINT64    Uint64;
  73 } MSR_IA32_APIC_BASE;
  74
  75 //
  76 // Local APIC Version Register.
  77 //
  78 typedef union {
  79   struct {
  80     UINT32  Version:8;                  ///< The version numbers of the local APIC.
  81     UINT32  Reserved0:8;                ///< Reserved.
  82     UINT32  MaxLvtEntry:8;              ///< Number of LVT entries minus 1.
  83     UINT32  EoiBroadcastSuppression:1;  ///< 1 if EOI-broadcast suppression supported.
  84     UINT32  Reserved1:7;                ///< Reserved.
  85   } Bits;
  86   UINT32    Uint32;
  87 } LOCAL_APIC_VERSION;
  88
  89 //
  90 // Low half of Interrupt Command Register (ICR).
  91 //
  92 typedef union {
  93   struct {
  94     UINT32  Vector:8;                ///< The vector number of the interrupt being sent.
  95     UINT32  DeliveryMode:3;          ///< Specifies the type of IPI to be sent.
  96     UINT32  DestinationMode:1;       ///< 0: physical destination mode, 1: logical destination mode.
  97     UINT32  DeliveryStatus:1;        ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.
  98     UINT32  Reserved0:1;             ///< Reserved.
  99     UINT32  Level:1;                 ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.
 100     UINT32  TriggerMode:1;           ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.
 101     UINT32  Reserved1:2;             ///< Reserved.
 102     UINT32  DestinationShorthand:2;  ///< A shorthand notation to specify the destination of the interrupt.
 103     UINT32  Reserved2:12;            ///< Reserved.
 104   } Bits;
 105   UINT32    Uint32;
 106 } LOCAL_APIC_ICR_LOW;
 107
 108 //
 109 // High half of Interrupt Command Register (ICR)
 110 //
 111 typedef union {
 112   struct {
 113     UINT32  Reserved0:24;   ///< Reserved.
 114     UINT32  Destination:8;  ///< Specifies the target processor or processors in xAPIC mode.
 115   } Bits;
 116   UINT32    Uint32;         ///< Destination field expanded to 32-bit in x2APIC mode.
 117 } LOCAL_APIC_ICR_HIGH;
 118
 119 //
 120 // Spurious-Interrupt Vector Register (SVR)
 121 //
 122 typedef union {
 123   struct {
 124     UINT32  SpuriousVector:8;           ///< Spurious Vector.
 125     UINT32  SoftwareEnable:1;           ///< APIC Software Enable/Disable.
 126     UINT32  FocusProcessorChecking:1;   ///< Focus Processor Checking.
 127     UINT32  Reserved0:2;                ///< Reserved.
 128     UINT32  EoiBroadcastSuppression:1;  ///< EOI-Broadcast Suppression.
 129     UINT32  Reserved1:19;               ///< Reserved.
 130   } Bits;
 131   UINT32    Uint32;
 132 } LOCAL_APIC_SVR;
 133
 134 //
 135 // Divide Configuration Register (DCR)
 136 //
 137 typedef union {
 138   struct {
 139     UINT32  DivideValue1:2;  ///< Low 2 bits of the divide value.
 140     UINT32  Reserved0:1;     ///< Always 0.
 141     UINT32  DivideValue2:1;  ///< Highest 1 bit of the divide value.
 142     UINT32  Reserved1:28;    ///< Reserved.
 143   } Bits;
 144   UINT32    Uint32;
 145 } LOCAL_APIC_DCR;
 146
 147 //
 148 // LVT Timer Register
 149 //
 150 typedef union {
 151   struct {
 152     UINT32  Vector:8;          ///< The vector number of the interrupt being sent.
 153     UINT32  Reserved0:4;       ///< Reserved.
 154     UINT32  DeliveryStatus:1;  ///< 0: Idle, 1: send pending.
 155     UINT32  Reserved1:3;       ///< Reserved.
 156     UINT32  Mask:1;            ///< 0: Not masked, 1: Masked.
 157     UINT32  TimerMode:1;       ///< 0: One-shot, 1: Periodic.
 158     UINT32  Reserved2:14;      ///< Reserved.
 159   } Bits;
 160   UINT32    Uint32;
 161 } LOCAL_APIC_LVT_TIMER;
 162
 163 //
 164 // LVT LINT0/LINT1 Register
 165 //
 166 typedef union {
 167   struct {
 168     UINT32  Vector:8;            ///< The vector number of the interrupt being sent.
 169     UINT32  DeliveryMode:3;      ///< Specifies the type of interrupt to be sent.
 170     UINT32  Reserved0:1;         ///< Reserved.
 171     UINT32  DeliveryStatus:1;    ///< 0: Idle, 1: send pending.
 172     UINT32  InputPinPolarity:1;  ///< Interrupt Input Pin Polarity.
 173     UINT32  RemoteIrr:1;         ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.
 174     UINT32  TriggerMode:1;       ///< 0:edge, 1:level.
 175     UINT32  Mask:1;              ///< 0: Not masked, 1: Masked.
 176     UINT32  Reserved1:15;        ///< Reserved.
 177   } Bits;
 178   UINT32    Uint32;
 179 } LOCAL_APIC_LVT_LINT;
 180
 181 #endif
 182