]> git.proxmox.com Git - mirror_edk2.git/blob - UefiCpuPkg/Include/Register/Msr/AtomMsr.h
projects / mirror_edk2.git / blob
? search:


2025b652933d87da70c949be2a70bda81f7a4920
[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / AtomMsr.h
1 /** @file
2 MSR Definitions for the Intel(R) Atom(TM) Processor Family.
3
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
7 provided for that MSR.
8
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
14
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
20 May 2018, Volume 4: Model-Specific-Registers (MSR)
21
22 **/
23
24 #ifndef __ATOM_MSR_H__
25 #define __ATOM_MSR_H__
26
27 #include <Register/ArchitecturalMsr.h>
28
29 /**
30 Is Intel(R) Atom(TM) Processor Family?
31
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
34
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
37 **/
38 #define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
40 ( \
41 DisplayModel == 0x1C || \
42 DisplayModel == 0x26 || \
43 DisplayModel == 0x27 || \
44 DisplayModel == 0x35 || \
45 DisplayModel == 0x36 \
46 ) \
47 )
48
49 /**
50 Shared. Model Specific Platform ID (R).
51
52 @param ECX MSR_ATOM_PLATFORM_ID (0x00000017)
53 @param EAX Lower 32-bits of MSR value.
54 Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
55 @param EDX Upper 32-bits of MSR value.
56 Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
57
58 <b>Example usage</b>
59 @code
60 MSR_ATOM_PLATFORM_ID_REGISTER Msr;
61
62 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);
63 @endcode
64 @note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
65 **/
66 #define MSR_ATOM_PLATFORM_ID 0x00000017
67
68 /**
69 MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID
70 **/
71 typedef union {
72 ///
73 /// Individual bit fields
74 ///
75 struct {
76 UINT32 Reserved1:8;
77 ///
78 /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
79 ///
80 UINT32 MaximumQualifiedRatio:5;
81 UINT32 Reserved2:19;
82 UINT32 Reserved3:32;
83 } Bits;
84 ///
85 /// All bit fields as a 32-bit value
86 ///
87 UINT32 Uint32;
88 ///
89 /// All bit fields as a 64-bit value
90 ///
91 UINT64 Uint64;
92 } MSR_ATOM_PLATFORM_ID_REGISTER;
93
94
95 /**
96 Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
97 processor features; (R) indicates current processor configuration.
98
99 @param ECX MSR_ATOM_EBL_CR_POWERON (0x0000002A)
100 @param EAX Lower 32-bits of MSR value.
101 Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
102 @param EDX Upper 32-bits of MSR value.
103 Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
104
105 <b>Example usage</b>
106 @code
107 MSR_ATOM_EBL_CR_POWERON_REGISTER Msr;
108
109 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);
110 AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);
111 @endcode
112 @note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
113 **/
114 #define MSR_ATOM_EBL_CR_POWERON 0x0000002A
115
116 /**
117 MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON
118 **/
119 typedef union {
120 ///
121 /// Individual bit fields
122 ///
123 struct {
124 UINT32 Reserved1:1;
125 ///
126 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
127 /// Always 0.
128 ///
129 UINT32 DataErrorCheckingEnable:1;
130 ///
131 /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
132 /// Always 0.
133 ///
134 UINT32 ResponseErrorCheckingEnable:1;
135 ///
136 /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
137 ///
138 UINT32 AERR_DriveEnable:1;
139 ///
140 /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
141 /// Disabled Always 0.
142 ///
143 UINT32 BERR_Enable:1;
144 UINT32 Reserved2:1;
145 UINT32 Reserved3:1;
146 ///
147 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
148 ///
149 UINT32 BINIT_DriverEnable:1;
150 UINT32 Reserved4:1;
151 ///
152 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
153 ///
154 UINT32 ExecuteBIST:1;
155 ///
156 /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
157 /// Always 0.
158 ///
159 UINT32 AERR_ObservationEnabled:1;
160 UINT32 Reserved5:1;
161 ///
162 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
163 /// Always 0.
164 ///
165 UINT32 BINIT_ObservationEnabled:1;
166 UINT32 Reserved6:1;
167 ///
168 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
169 ///
170 UINT32 ResetVector:1;
171 UINT32 Reserved7:1;
172 ///
173 /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.
174 ///
175 UINT32 APICClusterID:2;
176 UINT32 Reserved8:2;
177 ///
178 /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.
179 ///
180 UINT32 SymmetricArbitrationID:2;
181 ///
182 /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
183 ///
184 UINT32 IntegerBusFrequencyRatio:5;
185 UINT32 Reserved9:5;
186 UINT32 Reserved10:32;
187 } Bits;
188 ///
189 /// All bit fields as a 32-bit value
190 ///
191 UINT32 Uint32;
192 ///
193 /// All bit fields as a 64-bit value
194 ///
195 UINT64 Uint64;
196 } MSR_ATOM_EBL_CR_POWERON_REGISTER;
197
198
199 /**
200 Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch
201 record registers on the last branch record stack. The From_IP part of the
202 stack contains pointers to the source instruction . See also: - Last Branch
203 Record Stack TOS at 1C9H - Section 17.5.
204
205 @param ECX MSR_ATOM_LASTBRANCH_n_FROM_IP
206 @param EAX Lower 32-bits of MSR value.
207 @param EDX Upper 32-bits of MSR value.
208
209 <b>Example usage</b>
210 @code
211 UINT64 Msr;
212
213 Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
214 AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);
215 @endcode
216 @note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
217 MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
218 MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
219 MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
220 MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
221 MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
222 MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
223 MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
224 @{
225 **/
226 #define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040
227 #define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041
228 #define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042
229 #define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043
230 #define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044
231 #define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045
232 #define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046
233 #define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047
234 /// @}
235
236
237 /**
238 Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch
239 record registers on the last branch record stack. The To_IP part of the
240 stack contains pointers to the destination instruction.
241
242 @param ECX MSR_ATOM_LASTBRANCH_n_TO_IP
243 @param EAX Lower 32-bits of MSR value.
244 @param EDX Upper 32-bits of MSR value.
245
246 <b>Example usage</b>
247 @code
248 UINT64 Msr;
249
250 Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
251 AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);
252 @endcode
253 @note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
254 MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
255 MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
256 MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
257 MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
258 MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
259 MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
260 MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
261 @{
262 **/
263 #define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060
264 #define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061
265 #define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062
266 #define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063
267 #define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064
268 #define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065
269 #define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066
270 #define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067
271 /// @}
272
273
274 /**
275 Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
276 bus clock speed for processors based on Intel Atom microarchitecture:.
277
278 @param ECX MSR_ATOM_FSB_FREQ (0x000000CD)
279 @param EAX Lower 32-bits of MSR value.
280 Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
281 @param EDX Upper 32-bits of MSR value.
282 Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
283
284 <b>Example usage</b>
285 @code
286 MSR_ATOM_FSB_FREQ_REGISTER Msr;
287
288 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);
289 @endcode
290 @note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
291 **/
292 #define MSR_ATOM_FSB_FREQ 0x000000CD
293
294 /**
295 MSR information returned for MSR index #MSR_ATOM_FSB_FREQ
296 **/
297 typedef union {
298 ///
299 /// Individual bit fields
300 ///
301 struct {
302 ///
303 /// [Bits 2:0] - Scalable Bus Speed
304 ///
305 /// Atom Processor Family
306 /// ---------------------
307 /// 111B: 083 MHz (FSB 333)
308 /// 101B: 100 MHz (FSB 400)
309 /// 001B: 133 MHz (FSB 533)
310 /// 011B: 167 MHz (FSB 667)
311 ///
312 /// 133.33 MHz should be utilized if performing calculation with
313 /// System Bus Speed when encoding is 001B.
314 /// 166.67 MHz should be utilized if performing calculation with
315 /// System Bus Speed when
316 /// encoding is 011B.
317 ///
318 UINT32 ScalableBusSpeed:3;
319 UINT32 Reserved1:29;
320 UINT32 Reserved2:32;
321 } Bits;
322 ///
323 /// All bit fields as a 32-bit value
324 ///
325 UINT32 Uint32;
326 ///
327 /// All bit fields as a 64-bit value
328 ///
329 UINT64 Uint64;
330 } MSR_ATOM_FSB_FREQ_REGISTER;
331
332
333 /**
334 Shared.
335
336 @param ECX MSR_ATOM_BBL_CR_CTL3 (0x0000011E)
337 @param EAX Lower 32-bits of MSR value.
338 Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
339 @param EDX Upper 32-bits of MSR value.
340 Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
341
342 <b>Example usage</b>
343 @code
344 MSR_ATOM_BBL_CR_CTL3_REGISTER Msr;
345
346 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);
347 AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);
348 @endcode
349 @note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
350 **/
351 #define MSR_ATOM_BBL_CR_CTL3 0x0000011E
352
353 /**
354 MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3
355 **/
356 typedef union {
357 ///
358 /// Individual bit fields
359 ///
360 struct {
361 ///
362 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
363 /// Indicates if the L2 is hardware-disabled.
364 ///
365 UINT32 L2HardwareEnabled:1;
366 UINT32 Reserved1:7;
367 ///
368 /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =
369 /// Disabled (default) Until this bit is set the processor will not
370 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
371 ///
372 UINT32 L2Enabled:1;
373 UINT32 Reserved2:14;
374 ///
375 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
376 ///
377 UINT32 L2NotPresent:1;
378 UINT32 Reserved3:8;
379 UINT32 Reserved4:32;
380 } Bits;
381 ///
382 /// All bit fields as a 32-bit value
383 ///
384 UINT32 Uint32;
385 ///
386 /// All bit fields as a 64-bit value
387 ///
388 UINT64 Uint64;
389 } MSR_ATOM_BBL_CR_CTL3_REGISTER;
390
391
392 /**
393 Shared.
394
395 @param ECX MSR_ATOM_PERF_STATUS (0x00000198)
396 @param EAX Lower 32-bits of MSR value.
397 Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
398 @param EDX Upper 32-bits of MSR value.
399 Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
400
401 <b>Example usage</b>
402 @code
403 MSR_ATOM_PERF_STATUS_REGISTER Msr;
404
405 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);
406 AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);
407 @endcode
408 @note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
409 **/
410 #define MSR_ATOM_PERF_STATUS 0x00000198
411
412 /**
413 MSR information returned for MSR index #MSR_ATOM_PERF_STATUS
414 **/
415 typedef union {
416 ///
417 /// Individual bit fields
418 ///
419 struct {
420 ///
421 /// [Bits 15:0] Current Performance State Value.
422 ///
423 UINT32 CurrentPerformanceStateValue:16;
424 UINT32 Reserved1:16;
425 UINT32 Reserved2:8;
426 ///
427 /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
428 /// configured for the processor.
429 ///
430 UINT32 MaximumBusRatio:5;
431 UINT32 Reserved3:19;
432 } Bits;
433 ///
434 /// All bit fields as a 64-bit value
435 ///
436 UINT64 Uint64;
437 } MSR_ATOM_PERF_STATUS_REGISTER;
438
439
440 /**
441 Shared.
442
443 @param ECX MSR_ATOM_THERM2_CTL (0x0000019D)
444 @param EAX Lower 32-bits of MSR value.
445 Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
446 @param EDX Upper 32-bits of MSR value.
447 Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
448
449 <b>Example usage</b>
450 @code
451 MSR_ATOM_THERM2_CTL_REGISTER Msr;
452
453 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);
454 AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);
455 @endcode
456 @note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
457 **/
458 #define MSR_ATOM_THERM2_CTL 0x0000019D
459
460 /**
461 MSR information returned for MSR index #MSR_ATOM_THERM2_CTL
462 **/
463 typedef union {
464 ///
465 /// Individual bit fields
466 ///
467 struct {
468 UINT32 Reserved1:16;
469 ///
470 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
471 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
472 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
473 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
474 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
475 ///
476 UINT32 TM_SELECT:1;
477 UINT32 Reserved2:15;
478 UINT32 Reserved3:32;
479 } Bits;
480 ///
481 /// All bit fields as a 32-bit value
482 ///
483 UINT32 Uint32;
484 ///
485 /// All bit fields as a 64-bit value
486 ///
487 UINT64 Uint64;
488 } MSR_ATOM_THERM2_CTL_REGISTER;
489
490
491 /**
492 Unique. Enable Misc. Processor Features (R/W) Allows a variety of processor
493 functions to be enabled and disabled.
494
495 @param ECX MSR_ATOM_IA32_MISC_ENABLE (0x000001A0)
496 @param EAX Lower 32-bits of MSR value.
497 Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
498 @param EDX Upper 32-bits of MSR value.
499 Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
500
501 <b>Example usage</b>
502 @code
503 MSR_ATOM_IA32_MISC_ENABLE_REGISTER Msr;
504
505 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);
506 AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);
507 @endcode
508 @note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
509 **/
510 #define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0
511
512 /**
513 MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE
514 **/
515 typedef union {
516 ///
517 /// Individual bit fields
518 ///
519 struct {
520 ///
521 /// [Bit 0] Fast-Strings Enable See Table 2-2.
522 ///
523 UINT32 FastStrings:1;
524 UINT32 Reserved1:2;
525 ///
526 /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
527 /// Table 2-2. Default value is 0.
528 ///
529 UINT32 AutomaticThermalControlCircuit:1;
530 UINT32 Reserved2:3;
531 ///
532 /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
533 ///
534 UINT32 PerformanceMonitoring:1;
535 UINT32 Reserved3:1;
536 UINT32 Reserved4:1;
537 ///
538 /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
539 /// the processor to indicate a pending break event within the processor 0
540 /// = Indicates compatible FERR# signaling behavior This bit must be set
541 /// to 1 to support XAPIC interrupt model usage.
542 ///
543 UINT32 FERR:1;
544 ///
545 /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
546 ///
547 UINT32 BTS:1;
548 ///
549 /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
550 /// Table 2-2.
551 ///
552 UINT32 PEBS:1;
553 ///
554 /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
555 /// thermal sensor indicates that the die temperature is at the
556 /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
557 /// TM2 will reduce the bus to core ratio and voltage according to the
558 /// value last written to MSR_THERM2_CTL bits 15:0.
559 /// When this bit is clear (0, default), the processor does not change
560 /// the VID signals or the bus to core ratio when the processor enters a
561 /// thermally managed state. The BIOS must enable this feature if the
562 /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
563 /// not set, this feature is not supported and BIOS must not alter the
564 /// contents of the TM2 bit location. The processor is operating out of
565 /// specification if both this bit and the TM1 bit are set to 0.
566 ///
567 UINT32 TM2:1;
568 UINT32 Reserved5:2;
569 ///
570 /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
571 /// Table 2-2.
572 ///
573 UINT32 EIST:1;
574 UINT32 Reserved6:1;
575 ///
576 /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
577 ///
578 UINT32 MONITOR:1;
579 UINT32 Reserved7:1;
580 ///
581 /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
582 /// (R/WO) When set, this bit causes the following bits to become
583 /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this
584 /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must
585 /// be set before an Enhanced Intel SpeedStep Technology transition is
586 /// requested. This bit is cleared on reset.
587 ///
588 UINT32 EISTLock:1;
589 UINT32 Reserved8:1;
590 ///
591 /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 2-2.
592 ///
593 UINT32 LimitCpuidMaxval:1;
594 ///
595 /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
596 ///
597 UINT32 xTPR_Message_Disable:1;
598 UINT32 Reserved9:8;
599 UINT32 Reserved10:2;
600 ///
601 /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
602 ///
603 UINT32 XD:1;
604 UINT32 Reserved11:29;
605 } Bits;
606 ///
607 /// All bit fields as a 64-bit value
608 ///
609 UINT64 Uint64;
610 } MSR_ATOM_IA32_MISC_ENABLE_REGISTER;
611
612
613 /**
614 Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2)
615 that points to the MSR containing the most recent branch record. See
616 MSR_LASTBRANCH_0_FROM_IP (at 40H).
617
618 @param ECX MSR_ATOM_LASTBRANCH_TOS (0x000001C9)
619 @param EAX Lower 32-bits of MSR value.
620 @param EDX Upper 32-bits of MSR value.
621
622 <b>Example usage</b>
623 @code
624 UINT64 Msr;
625
626 Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);
627 AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);
628 @endcode
629 @note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
630 **/
631 #define MSR_ATOM_LASTBRANCH_TOS 0x000001C9
632
633
634 /**
635 Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
636 last branch instruction that the processor executed prior to the last
637 exception that was generated or the last interrupt that was handled.
638
639 @param ECX MSR_ATOM_LER_FROM_LIP (0x000001DD)
640 @param EAX Lower 32-bits of MSR value.
641 @param EDX Upper 32-bits of MSR value.
642
643 <b>Example usage</b>
644 @code
645 UINT64 Msr;
646
647 Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);
648 @endcode
649 @note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
650 **/
651 #define MSR_ATOM_LER_FROM_LIP 0x000001DD
652
653
654 /**
655 Unique. Last Exception Record To Linear IP (R) This area contains a pointer
656 to the target of the last branch instruction that the processor executed
657 prior to the last exception that was generated or the last interrupt that
658 was handled.
659
660 @param ECX MSR_ATOM_LER_TO_LIP (0x000001DE)
661 @param EAX Lower 32-bits of MSR value.
662 @param EDX Upper 32-bits of MSR value.
663
664 <b>Example usage</b>
665 @code
666 UINT64 Msr;
667
668 Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);
669 @endcode
670 @note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
671 **/
672 #define MSR_ATOM_LER_TO_LIP 0x000001DE
673
674
675 /**
676 Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
677 (PEBS).".
678
679 @param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1)
680 @param EAX Lower 32-bits of MSR value.
681 Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
682 @param EDX Upper 32-bits of MSR value.
683 Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
684
685 <b>Example usage</b>
686 @code
687 MSR_ATOM_PEBS_ENABLE_REGISTER Msr;
688
689 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);
690 AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);
691 @endcode
692 @note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
693 **/
694 #define MSR_ATOM_PEBS_ENABLE 0x000003F1
695
696 /**
697 MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE
698 **/
699 typedef union {
700 ///
701 /// Individual bit fields
702 ///
703 struct {
704 ///
705 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
706 ///
707 UINT32 Enable:1;
708 UINT32 Reserved1:31;
709 UINT32 Reserved2:32;
710 } Bits;
711 ///
712 /// All bit fields as a 32-bit value
713 ///
714 UINT32 Uint32;
715 ///
716 /// All bit fields as a 64-bit value
717 ///
718 UINT64 Uint64;
719 } MSR_ATOM_PEBS_ENABLE_REGISTER;
720
721
722 /**
723 Package. Package C2 Residency Note: C-state values are processor specific
724 C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
725 C-States. Package. Package C2 Residency Counter. (R/O) Time that this
726 package is in processor-specific C2 states since last reset. Counts at 1 Mhz
727 frequency.
728
729 @param ECX MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8)
730 @param EAX Lower 32-bits of MSR value.
731 @param EDX Upper 32-bits of MSR value.
732
733 <b>Example usage</b>
734 @code
735 UINT64 Msr;
736
737 Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);
738 AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);
739 @endcode
740 @note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
741 **/
742 #define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8
743
744
745 /**
746 Package. Package C4 Residency Note: C-state values are processor specific
747 C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
748 C-States. Package. Package C4 Residency Counter. (R/O) Time that this
749 package is in processor-specific C4 states since last reset. Counts at 1 Mhz
750 frequency.
751
752 @param ECX MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9)
753 @param EAX Lower 32-bits of MSR value.
754 @param EDX Upper 32-bits of MSR value.
755
756 <b>Example usage</b>
757 @code
758 UINT64 Msr;
759
760 Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);
761 AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);
762 @endcode
763 @note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.
764 **/
765 #define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9
766
767
768 /**
769 Package. Package C6 Residency Note: C-state values are processor specific
770 C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
771 C-States. Package. Package C6 Residency Counter. (R/O) Time that this
772 package is in processor-specific C6 states since last reset. Counts at 1 Mhz
773 frequency.
774
775 @param ECX MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA)
776 @param EAX Lower 32-bits of MSR value.
777 @param EDX Upper 32-bits of MSR value.
778
779 <b>Example usage</b>
780 @code
781 UINT64 Msr;
782
783 Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);
784 AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);
785 @endcode
786 @note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
787 **/
788 #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA
789
790 #endif
EFI Development Kit II mirror for PVE