2 MSR Definitions for the Intel(R) Atom(TM) Processor Family.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __ATOM_MSR_H__
19 #define __ATOM_MSR_H__
21 #include <Register/ArchitecturalMsr.h>
24 Is Intel(R) Atom(TM) Processor Family?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
35 DisplayModel == 0x1C || \
36 DisplayModel == 0x26 || \
37 DisplayModel == 0x27 || \
38 DisplayModel == 0x35 || \
39 DisplayModel == 0x36 \
44 Shared. Model Specific Platform ID (R).
46 @param ECX MSR_ATOM_PLATFORM_ID (0x00000017)
47 @param EAX Lower 32-bits of MSR value.
48 Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
49 @param EDX Upper 32-bits of MSR value.
50 Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
54 MSR_ATOM_PLATFORM_ID_REGISTER Msr;
56 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);
58 @note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
60 #define MSR_ATOM_PLATFORM_ID 0x00000017
63 MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID
67 /// Individual bit fields
72 /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
74 UINT32 MaximumQualifiedRatio
:5;
79 /// All bit fields as a 32-bit value
83 /// All bit fields as a 64-bit value
86 } MSR_ATOM_PLATFORM_ID_REGISTER
;
90 Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
91 processor features; (R) indicates current processor configuration.
93 @param ECX MSR_ATOM_EBL_CR_POWERON (0x0000002A)
94 @param EAX Lower 32-bits of MSR value.
95 Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
96 @param EDX Upper 32-bits of MSR value.
97 Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
101 MSR_ATOM_EBL_CR_POWERON_REGISTER Msr;
103 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);
104 AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);
106 @note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
108 #define MSR_ATOM_EBL_CR_POWERON 0x0000002A
111 MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON
115 /// Individual bit fields
120 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
123 UINT32 DataErrorCheckingEnable
:1;
125 /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
128 UINT32 ResponseErrorCheckingEnable
:1;
130 /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
132 UINT32 AERR_DriveEnable
:1;
134 /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
135 /// Disabled Always 0.
137 UINT32 BERR_Enable
:1;
141 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
143 UINT32 BINIT_DriverEnable
:1;
146 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
148 UINT32 ExecuteBIST
:1;
150 /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
153 UINT32 AERR_ObservationEnabled
:1;
156 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
159 UINT32 BINIT_ObservationEnabled
:1;
162 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
164 UINT32 ResetVector
:1;
167 /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.
169 UINT32 APICClusterID
:2;
172 /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.
174 UINT32 SymmetricArbitrationID
:2;
176 /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
178 UINT32 IntegerBusFrequencyRatio
:5;
180 UINT32 Reserved10
:32;
183 /// All bit fields as a 32-bit value
187 /// All bit fields as a 64-bit value
190 } MSR_ATOM_EBL_CR_POWERON_REGISTER
;
194 Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch
195 record registers on the last branch record stack. The From_IP part of the
196 stack contains pointers to the source instruction . See also: - Last Branch
197 Record Stack TOS at 1C9H - Section 17.5.
199 @param ECX MSR_ATOM_LASTBRANCH_n_FROM_IP
200 @param EAX Lower 32-bits of MSR value.
201 @param EDX Upper 32-bits of MSR value.
207 Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
208 AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);
210 @note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
211 MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
212 MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
213 MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
214 MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
215 MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
216 MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
217 MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
220 #define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040
221 #define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041
222 #define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042
223 #define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043
224 #define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044
225 #define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045
226 #define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046
227 #define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047
232 Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch
233 record registers on the last branch record stack. The To_IP part of the
234 stack contains pointers to the destination instruction.
236 @param ECX MSR_ATOM_LASTBRANCH_n_TO_IP
237 @param EAX Lower 32-bits of MSR value.
238 @param EDX Upper 32-bits of MSR value.
244 Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
245 AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);
247 @note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
248 MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
249 MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
250 MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
251 MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
252 MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
253 MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
254 MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
257 #define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060
258 #define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061
259 #define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062
260 #define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063
261 #define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064
262 #define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065
263 #define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066
264 #define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067
269 Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
270 bus clock speed for processors based on Intel Atom microarchitecture:.
272 @param ECX MSR_ATOM_FSB_FREQ (0x000000CD)
273 @param EAX Lower 32-bits of MSR value.
274 Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
275 @param EDX Upper 32-bits of MSR value.
276 Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
280 MSR_ATOM_FSB_FREQ_REGISTER Msr;
282 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);
284 @note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
286 #define MSR_ATOM_FSB_FREQ 0x000000CD
289 MSR information returned for MSR index #MSR_ATOM_FSB_FREQ
293 /// Individual bit fields
297 /// [Bits 2:0] - Scalable Bus Speed
299 /// Atom Processor Family
300 /// ---------------------
301 /// 111B: 083 MHz (FSB 333)
302 /// 101B: 100 MHz (FSB 400)
303 /// 001B: 133 MHz (FSB 533)
304 /// 011B: 167 MHz (FSB 667)
306 /// 133.33 MHz should be utilized if performing calculation with
307 /// System Bus Speed when encoding is 001B.
308 /// 166.67 MHz should be utilized if performing calculation with
309 /// System Bus Speed when
310 /// encoding is 011B.
312 UINT32 ScalableBusSpeed
:3;
317 /// All bit fields as a 32-bit value
321 /// All bit fields as a 64-bit value
324 } MSR_ATOM_FSB_FREQ_REGISTER
;
330 @param ECX MSR_ATOM_BBL_CR_CTL3 (0x0000011E)
331 @param EAX Lower 32-bits of MSR value.
332 Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
333 @param EDX Upper 32-bits of MSR value.
334 Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
338 MSR_ATOM_BBL_CR_CTL3_REGISTER Msr;
340 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);
341 AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);
343 @note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
345 #define MSR_ATOM_BBL_CR_CTL3 0x0000011E
348 MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3
352 /// Individual bit fields
356 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
357 /// Indicates if the L2 is hardware-disabled.
359 UINT32 L2HardwareEnabled
:1;
362 /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =
363 /// Disabled (default) Until this bit is set the processor will not
364 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
369 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
371 UINT32 L2NotPresent
:1;
376 /// All bit fields as a 32-bit value
380 /// All bit fields as a 64-bit value
383 } MSR_ATOM_BBL_CR_CTL3_REGISTER
;
389 @param ECX MSR_ATOM_PERF_STATUS (0x00000198)
390 @param EAX Lower 32-bits of MSR value.
391 Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
392 @param EDX Upper 32-bits of MSR value.
393 Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
397 MSR_ATOM_PERF_STATUS_REGISTER Msr;
399 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);
400 AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);
402 @note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
404 #define MSR_ATOM_PERF_STATUS 0x00000198
407 MSR information returned for MSR index #MSR_ATOM_PERF_STATUS
411 /// Individual bit fields
415 /// [Bits 15:0] Current Performance State Value.
417 UINT32 CurrentPerformanceStateValue
:16;
421 /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
422 /// configured for the processor.
424 UINT32 MaximumBusRatio
:5;
428 /// All bit fields as a 64-bit value
431 } MSR_ATOM_PERF_STATUS_REGISTER
;
437 @param ECX MSR_ATOM_THERM2_CTL (0x0000019D)
438 @param EAX Lower 32-bits of MSR value.
439 Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
440 @param EDX Upper 32-bits of MSR value.
441 Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
445 MSR_ATOM_THERM2_CTL_REGISTER Msr;
447 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);
448 AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);
450 @note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
452 #define MSR_ATOM_THERM2_CTL 0x0000019D
455 MSR information returned for MSR index #MSR_ATOM_THERM2_CTL
459 /// Individual bit fields
464 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
465 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
466 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
467 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
468 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
475 /// All bit fields as a 32-bit value
479 /// All bit fields as a 64-bit value
482 } MSR_ATOM_THERM2_CTL_REGISTER
;
486 Unique. Enable Misc. Processor Features (R/W) Allows a variety of processor
487 functions to be enabled and disabled.
489 @param ECX MSR_ATOM_IA32_MISC_ENABLE (0x000001A0)
490 @param EAX Lower 32-bits of MSR value.
491 Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
492 @param EDX Upper 32-bits of MSR value.
493 Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
497 MSR_ATOM_IA32_MISC_ENABLE_REGISTER Msr;
499 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);
500 AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);
502 @note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
504 #define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0
507 MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE
511 /// Individual bit fields
515 /// [Bit 0] Fast-Strings Enable See Table 2-2.
517 UINT32 FastStrings
:1;
520 /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
521 /// Table 2-2. Default value is 0.
523 UINT32 AutomaticThermalControlCircuit
:1;
526 /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
528 UINT32 PerformanceMonitoring
:1;
532 /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
533 /// the processor to indicate a pending break event within the processor 0
534 /// = Indicates compatible FERR# signaling behavior This bit must be set
535 /// to 1 to support XAPIC interrupt model usage.
539 /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
543 /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
548 /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
549 /// thermal sensor indicates that the die temperature is at the
550 /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
551 /// TM2 will reduce the bus to core ratio and voltage according to the
552 /// value last written to MSR_THERM2_CTL bits 15:0.
553 /// When this bit is clear (0, default), the processor does not change
554 /// the VID signals or the bus to core ratio when the processor enters a
555 /// thermally managed state. The BIOS must enable this feature if the
556 /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
557 /// not set, this feature is not supported and BIOS must not alter the
558 /// contents of the TM2 bit location. The processor is operating out of
559 /// specification if both this bit and the TM1 bit are set to 0.
564 /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
570 /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
575 /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
576 /// (R/WO) When set, this bit causes the following bits to become
577 /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this
578 /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must
579 /// be set before an Enhanced Intel SpeedStep Technology transition is
580 /// requested. This bit is cleared on reset.
585 /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 2-2.
587 UINT32 LimitCpuidMaxval
:1;
589 /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
591 UINT32 xTPR_Message_Disable
:1;
595 /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
598 UINT32 Reserved11
:29;
601 /// All bit fields as a 64-bit value
604 } MSR_ATOM_IA32_MISC_ENABLE_REGISTER
;
608 Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2)
609 that points to the MSR containing the most recent branch record. See
610 MSR_LASTBRANCH_0_FROM_IP (at 40H).
612 @param ECX MSR_ATOM_LASTBRANCH_TOS (0x000001C9)
613 @param EAX Lower 32-bits of MSR value.
614 @param EDX Upper 32-bits of MSR value.
620 Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);
621 AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);
623 @note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
625 #define MSR_ATOM_LASTBRANCH_TOS 0x000001C9
629 Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
630 last branch instruction that the processor executed prior to the last
631 exception that was generated or the last interrupt that was handled.
633 @param ECX MSR_ATOM_LER_FROM_LIP (0x000001DD)
634 @param EAX Lower 32-bits of MSR value.
635 @param EDX Upper 32-bits of MSR value.
641 Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);
643 @note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
645 #define MSR_ATOM_LER_FROM_LIP 0x000001DD
649 Unique. Last Exception Record To Linear IP (R) This area contains a pointer
650 to the target of the last branch instruction that the processor executed
651 prior to the last exception that was generated or the last interrupt that
654 @param ECX MSR_ATOM_LER_TO_LIP (0x000001DE)
655 @param EAX Lower 32-bits of MSR value.
656 @param EDX Upper 32-bits of MSR value.
662 Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);
664 @note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
666 #define MSR_ATOM_LER_TO_LIP 0x000001DE
670 Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
673 @param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1)
674 @param EAX Lower 32-bits of MSR value.
675 Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
676 @param EDX Upper 32-bits of MSR value.
677 Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
681 MSR_ATOM_PEBS_ENABLE_REGISTER Msr;
683 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);
684 AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);
686 @note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
688 #define MSR_ATOM_PEBS_ENABLE 0x000003F1
691 MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE
695 /// Individual bit fields
699 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
706 /// All bit fields as a 32-bit value
710 /// All bit fields as a 64-bit value
713 } MSR_ATOM_PEBS_ENABLE_REGISTER
;
717 Package. Package C2 Residency Note: C-state values are processor specific
718 C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
719 C-States. Package. Package C2 Residency Counter. (R/O) Time that this
720 package is in processor-specific C2 states since last reset. Counts at 1 Mhz
723 @param ECX MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8)
724 @param EAX Lower 32-bits of MSR value.
725 @param EDX Upper 32-bits of MSR value.
731 Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);
732 AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);
734 @note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
736 #define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8
740 Package. Package C4 Residency Note: C-state values are processor specific
741 C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
742 C-States. Package. Package C4 Residency Counter. (R/O) Time that this
743 package is in processor-specific C4 states since last reset. Counts at 1 Mhz
746 @param ECX MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9)
747 @param EAX Lower 32-bits of MSR value.
748 @param EDX Upper 32-bits of MSR value.
754 Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);
755 AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);
757 @note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.
759 #define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9
763 Package. Package C6 Residency Note: C-state values are processor specific
764 C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
765 C-States. Package. Package C6 Residency Counter. (R/O) Time that this
766 package is in processor-specific C6 states since last reset. Counts at 1 Mhz
769 @param ECX MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA)
770 @param EAX Lower 32-bits of MSR value.
771 @param EDX Upper 32-bits of MSR value.
777 Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);
778 AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);
780 @note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
782 #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA