UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h

   1 /** @file
   2   MSR Definitions for Intel processors based on the Broadwell microarchitecture.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
  10   This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18   @par Specification Reference:
  19   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
  20   May 2018, Volume 4: Model-Specific-Registers (MSR)
  21
  22 **/
  23
  24 #ifndef __BROADWELL_MSR_H__
  25 #define __BROADWELL_MSR_H__
  26
  27 #include <Register/ArchitecturalMsr.h>
  28
  29 /**
  30   Is Intel processors based on the Broadwell microarchitecture?
  31
  32   @param   DisplayFamily  Display Family ID
  33   @param   DisplayModel   Display Model ID
  34
  35   @retval  TRUE   Yes, it is.
  36   @retval  FALSE  No, it isn't.
  37 **/
  38 #define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \
  39   (DisplayFamily == 0x06 && \
  40    (                        \
  41     DisplayModel == 0x3D || \
  42     DisplayModel == 0x47 || \
  43     DisplayModel == 0x4F || \
  44     DisplayModel == 0x56    \
  45     )                       \
  46    )
  47
  48 /**
  49   Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control
  50   Facilities.".
  51
  52   @param  ECX  MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)
  53   @param  EAX  Lower 32-bits of MSR value.
  54                Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
  55   @param  EDX  Upper 32-bits of MSR value.
  56                Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
  57
  58   <b>Example usage</b>
  59   @code
  60   MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER  Msr;
  61
  62   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);
  63   AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
  64   @endcode
  65   @note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
  66 **/
  67 #define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS    0x0000038E
  68
  69 /**
  70   MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS
  71 **/
  72 typedef union {
  73   ///
  74   /// Individual bit fields
  75   ///
  76   struct {
  77     ///
  78     /// [Bit 0] Ovf_PMC0.
  79     ///
  80     UINT32  Ovf_PMC0:1;
  81     ///
  82     /// [Bit 1] Ovf_PMC1.
  83     ///
  84     UINT32  Ovf_PMC1:1;
  85     ///
  86     /// [Bit 2] Ovf_PMC2.
  87     ///
  88     UINT32  Ovf_PMC2:1;
  89     ///
  90     /// [Bit 3] Ovf_PMC3.
  91     ///
  92     UINT32  Ovf_PMC3:1;
  93     UINT32  Reserved1:28;
  94     ///
  95     /// [Bit 32] Ovf_FixedCtr0.
  96     ///
  97     UINT32  Ovf_FixedCtr0:1;
  98     ///
  99     /// [Bit 33] Ovf_FixedCtr1.
 100     ///
 101     UINT32  Ovf_FixedCtr1:1;
 102     ///
 103     /// [Bit 34] Ovf_FixedCtr2.
 104     ///
 105     UINT32  Ovf_FixedCtr2:1;
 106     UINT32  Reserved2:20;
 107     ///
 108     /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical
 109     /// Addresses (ToPA).".
 110     ///
 111     UINT32  Trace_ToPA_PMI:1;
 112     UINT32  Reserved3:5;
 113     ///
 114     /// [Bit 61] Ovf_Uncore.
 115     ///
 116     UINT32  Ovf_Uncore:1;
 117     ///
 118     /// [Bit 62] Ovf_BufDSSAVE.
 119     ///
 120     UINT32  OvfBuf:1;
 121     ///
 122     /// [Bit 63] CondChgd.
 123     ///
 124     UINT32  CondChgd:1;
 125   } Bits;
 126   ///
 127   /// All bit fields as a 64-bit value
 128   ///
 129   UINT64  Uint64;
 130 } MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;
 131
 132
 133 /**
 134   Core. C-State Configuration Control (R/W) Note: C-state values are processor
 135   specific C-state code names, unrelated to MWAIT extension C-state parameters
 136   or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
 137
 138   @param  ECX  MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
 139   @param  EAX  Lower 32-bits of MSR value.
 140                Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
 141   @param  EDX  Upper 32-bits of MSR value.
 142                Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
 143
 144   <b>Example usage</b>
 145   @code
 146   MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
 147
 148   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
 149   AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
 150   @endcode
 151   @note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
 152 **/
 153 #define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL     0x000000E2
 154
 155 /**
 156   MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL
 157 **/
 158 typedef union {
 159   ///
 160   /// Individual bit fields
 161   ///
 162   struct {
 163     ///
 164     /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
 165     /// processor-specific C-state code name (consuming the least power) for
 166     /// the package. The default is set as factory-configured package C-state
 167     /// limit. The following C-state code name encodings are supported: 0000b:
 168     /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
 169     /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.
 170     ///
 171     UINT32  Limit:4;
 172     UINT32  Reserved1:6;
 173     ///
 174     /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
 175     ///
 176     UINT32  IO_MWAIT:1;
 177     UINT32  Reserved2:4;
 178     ///
 179     /// [Bit 15] CFG Lock (R/WO).
 180     ///
 181     UINT32  CFGLock:1;
 182     UINT32  Reserved3:9;
 183     ///
 184     /// [Bit 25] C3 State Auto Demotion Enable (R/W).
 185     ///
 186     UINT32  C3AutoDemotion:1;
 187     ///
 188     /// [Bit 26] C1 State Auto Demotion Enable (R/W).
 189     ///
 190     UINT32  C1AutoDemotion:1;
 191     ///
 192     /// [Bit 27] Enable C3 Undemotion (R/W).
 193     ///
 194     UINT32  C3Undemotion:1;
 195     ///
 196     /// [Bit 28] Enable C1 Undemotion (R/W).
 197     ///
 198     UINT32  C1Undemotion:1;
 199     ///
 200     /// [Bit 29] Enable Package C-State Auto-demotion (R/W).
 201     ///
 202     UINT32  CStateAutoDemotion:1;
 203     ///
 204     /// [Bit 30] Enable Package C-State Undemotion (R/W).
 205     ///
 206     UINT32  CStateUndemotion:1;
 207     UINT32  Reserved4:1;
 208     UINT32  Reserved5:32;
 209   } Bits;
 210   ///
 211   /// All bit fields as a 32-bit value
 212   ///
 213   UINT32  Uint32;
 214   ///
 215   /// All bit fields as a 64-bit value
 216   ///
 217   UINT64  Uint64;
 218 } MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;
 219
 220
 221 /**
 222   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
 223   RW if MSR_PLATFORM_INFO.[28] = 1.
 224
 225   @param  ECX  MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)
 226   @param  EAX  Lower 32-bits of MSR value.
 227                Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
 228   @param  EDX  Upper 32-bits of MSR value.
 229                Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
 230
 231   <b>Example usage</b>
 232   @code
 233   MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER  Msr;
 234
 235   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);
 236   @endcode
 237   @note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 238 **/
 239 #define MSR_BROADWELL_TURBO_RATIO_LIMIT          0x000001AD
 240
 241 /**
 242   MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT
 243 **/
 244 typedef union {
 245   ///
 246   /// Individual bit fields
 247   ///
 248   struct {
 249     ///
 250     /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
 251     /// limit of 1 core active.
 252     ///
 253     UINT32  Maximum1C:8;
 254     ///
 255     /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
 256     /// limit of 2 core active.
 257     ///
 258     UINT32  Maximum2C:8;
 259     ///
 260     /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
 261     /// limit of 3 core active.
 262     ///
 263     UINT32  Maximum3C:8;
 264     ///
 265     /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
 266     /// limit of 4 core active.
 267     ///
 268     UINT32  Maximum4C:8;
 269     ///
 270     /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
 271     /// limit of 5core active.
 272     ///
 273     UINT32  Maximum5C:8;
 274     ///
 275     /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
 276     /// limit of 6core active.
 277     ///
 278     UINT32  Maximum6C:8;
 279     UINT32  Reserved:16;
 280   } Bits;
 281   ///
 282   /// All bit fields as a 64-bit value
 283   ///
 284   UINT64  Uint64;
 285 } MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;
 286
 287
 288 /**
 289   Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
 290   fields represent the widest possible range of uncore frequencies. Writing to
 291   these fields allows software to control the minimum and the maximum
 292   frequency that hardware will select.
 293
 294   @param  ECX  MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620)
 295   @param  EAX  Lower 32-bits of MSR value.
 296                Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
 297   @param  EDX  Upper 32-bits of MSR value.
 298                Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
 299
 300   <b>Example usage</b>
 301   @code
 302   MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;
 303
 304   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);
 305   AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
 306   @endcode
 307 **/
 308 #define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT      0x00000620
 309
 310 /**
 311   MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT
 312 **/
 313 typedef union {
 314   ///
 315   /// Individual bit fields
 316   ///
 317   struct {
 318     ///
 319     /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
 320     /// LLC/Ring.
 321     ///
 322     UINT32  MAX_RATIO:7;
 323     UINT32  Reserved2:1;
 324     ///
 325     /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
 326     /// possible ratio of the LLC/Ring.
 327     ///
 328     UINT32  MIN_RATIO:7;
 329     UINT32  Reserved3:17;
 330     UINT32  Reserved4:32;
 331   } Bits;
 332   ///
 333   /// All bit fields as a 32-bit value
 334   ///
 335   UINT32  Uint32;
 336   ///
 337   /// All bit fields as a 64-bit value
 338   ///
 339   UINT64  Uint64;
 340 } MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER;
 341
 342 /**
 343   Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
 344   Domains.".
 345
 346   @param  ECX  MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)
 347   @param  EAX  Lower 32-bits of MSR value.
 348   @param  EDX  Upper 32-bits of MSR value.
 349
 350   <b>Example usage</b>
 351   @code
 352   UINT64  Msr;
 353
 354   Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);
 355   @endcode
 356   @note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
 357 **/
 358 #define MSR_BROADWELL_PP0_ENERGY_STATUS          0x00000639
 359
 360 #endif