UefiCpuPkg/Include/Register/Msr/CoreMsr.h

   1 /** @file
   2   MSR Definitions for Intel Core Solo and Intel Core Duo Processors.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
  10   This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18   @par Specification Reference:
  19   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
  20   December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-17.
  21
  22 **/
  23
  24 #ifndef __CORE_MSR_H__
  25 #define __CORE_MSR_H__
  26
  27 #include <Register/ArchitecturalMsr.h>
  28
  29 /**
  30   Unique. See Section 35.20, "MSRs in Pentium Processors," and see Table 35-2.
  31
  32   @param  ECX  MSR_CORE_P5_MC_ADDR (0x00000000)
  33   @param  EAX  Lower 32-bits of MSR value.
  34   @param  EDX  Upper 32-bits of MSR value.
  35
  36   <b>Example usage</b>
  37   @code
  38   UINT64  Msr;
  39
  40   Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);
  41   AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);
  42   @endcode
  43 **/
  44 #define MSR_CORE_P5_MC_ADDR                      0x00000000
  45
  46
  47 /**
  48   Unique. See Section 35.20, "MSRs in Pentium Processors," and see Table 35-2.
  49
  50   @param  ECX  MSR_CORE_P5_MC_TYPE (0x00000001)
  51   @param  EAX  Lower 32-bits of MSR value.
  52   @param  EDX  Upper 32-bits of MSR value.
  53
  54   <b>Example usage</b>
  55   @code
  56   UINT64  Msr;
  57
  58   Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);
  59   AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);
  60   @endcode
  61 **/
  62 #define MSR_CORE_P5_MC_TYPE                      0x00000001
  63
  64
  65 /**
  66   Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
  67   processor features; (R) indicates current processor configuration.
  68
  69   @param  ECX  MSR_CORE_EBL_CR_POWERON (0x0000002A)
  70   @param  EAX  Lower 32-bits of MSR value.
  71                Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
  72   @param  EDX  Upper 32-bits of MSR value.
  73                Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
  74
  75   <b>Example usage</b>
  76   @code
  77   MSR_CORE_EBL_CR_POWERON_REGISTER  Msr;
  78
  79   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);
  80   AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);
  81   @endcode
  82 **/
  83 #define MSR_CORE_EBL_CR_POWERON                  0x0000002A
  84
  85 /**
  86   MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON
  87 **/
  88 typedef union {
  89   ///
  90   /// Individual bit fields
  91   ///
  92   struct {
  93     UINT32  Reserved1:1;
  94     ///
  95     /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
  96     /// Note: Not all processor implements R/W.
  97     ///
  98     UINT32  DataErrorCheckingEnable:1;
  99     ///
 100     /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
 101     /// Note: Not all processor implements R/W.
 102     ///
 103     UINT32  ResponseErrorCheckingEnable:1;
 104     ///
 105     /// [Bit 3] MCERR# Drive Enable (R/W)  1 = Enabled; 0 = Disabled Note: Not
 106     /// all processor implements R/W.
 107     ///
 108     UINT32  MCERR_DriveEnable:1;
 109     ///
 110     /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
 111     /// Not all processor implements R/W.
 112     ///
 113     UINT32  AddressParityEnable:1;
 114     UINT32  Reserved2:2;
 115     ///
 116     /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
 117     /// all processor implements R/W.
 118     ///
 119     UINT32  BINIT_DriverEnable:1;
 120     ///
 121     /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
 122     ///
 123     UINT32  OutputTriStateEnable:1;
 124     ///
 125     /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
 126     ///
 127     UINT32  ExecuteBIST:1;
 128     ///
 129     /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
 130     ///
 131     UINT32  MCERR_ObservationEnabled:1;
 132     UINT32  Reserved3:1;
 133     ///
 134     /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
 135     ///
 136     UINT32  BINIT_ObservationEnabled:1;
 137     UINT32  Reserved4:1;
 138     ///
 139     /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
 140     ///
 141     UINT32  ResetVector:1;
 142     UINT32  Reserved5:1;
 143     ///
 144     /// [Bits 17:16] APIC Cluster ID (R/O).
 145     ///
 146     UINT32  APICClusterID:2;
 147     ///
 148     /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved.
 149     ///
 150     UINT32  SystemBusFrequency:1;
 151     UINT32  Reserved6:1;
 152     ///
 153     /// [Bits 21:20] Symmetric Arbitration ID (R/O).
 154     ///
 155     UINT32  SymmetricArbitrationID:2;
 156     ///
 157     /// [Bits 26:22] Clock Frequency Ratio (R/O).
 158     ///
 159     UINT32  ClockFrequencyRatio:5;
 160     UINT32  Reserved7:5;
 161     UINT32  Reserved8:32;
 162   } Bits;
 163   ///
 164   /// All bit fields as a 32-bit value
 165   ///
 166   UINT32  Uint32;
 167   ///
 168   /// All bit fields as a 64-bit value
 169   ///
 170   UINT64  Uint64;
 171 } MSR_CORE_EBL_CR_POWERON_REGISTER;
 172
 173
 174 /**
 175   Unique. Last Branch Record n (R/W) One of 8 last branch record registers on
 176   the last branch record stack: bits 31-0 hold the 'from' address and bits
 177   63-32 hold the 'to' address. See also: -  Last Branch Record Stack TOS at
 178   1C9H -  Section 17.12, "Last Branch, Interrupt, and Exception Recording
 179   (Pentium M Processors).".
 180
 181   @param  ECX  MSR_CORE_LASTBRANCH_n
 182   @param  EAX  Lower 32-bits of MSR value.
 183   @param  EDX  Upper 32-bits of MSR value.
 184
 185   <b>Example usage</b>
 186   @code
 187   UINT64  Msr;
 188
 189   Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
 190   AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);
 191   @endcode
 192   @{
 193 **/
 194 #define MSR_CORE_LASTBRANCH_0                    0x00000040
 195 #define MSR_CORE_LASTBRANCH_1                    0x00000041
 196 #define MSR_CORE_LASTBRANCH_2                    0x00000042
 197 #define MSR_CORE_LASTBRANCH_3                    0x00000043
 198 #define MSR_CORE_LASTBRANCH_4                    0x00000044
 199 #define MSR_CORE_LASTBRANCH_5                    0x00000045
 200 #define MSR_CORE_LASTBRANCH_6                    0x00000046
 201 #define MSR_CORE_LASTBRANCH_7                    0x00000047
 202 /// @}
 203
 204
 205 /**
 206   Shared. Scalable Bus Speed (RO) This field indicates the scalable bus
 207   clock speed:.
 208
 209   @param  ECX  MSR_CORE_FSB_FREQ (0x000000CD)
 210   @param  EAX  Lower 32-bits of MSR value.
 211                Described by the type MSR_CORE_FSB_FREQ_REGISTER.
 212   @param  EDX  Upper 32-bits of MSR value.
 213                Described by the type MSR_CORE_FSB_FREQ_REGISTER.
 214
 215   <b>Example usage</b>
 216   @code
 217   MSR_CORE_FSB_FREQ_REGISTER  Msr;
 218
 219   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ);
 220   @endcode
 221 **/
 222 #define MSR_CORE_FSB_FREQ                        0x000000CD
 223
 224 /**
 225   MSR information returned for MSR index #MSR_CORE_FSB_FREQ
 226 **/
 227 typedef union {
 228   ///
 229   /// Individual bit fields
 230   ///
 231   struct {
 232     ///
 233     /// [Bits 2:0] - Scalable Bus Speed
 234     ///   101B: 100 MHz (FSB 400)
 235     ///   001B: 133 MHz (FSB 533)
 236     ///   011B: 167 MHz (FSB 667)
 237     ///
 238     /// 133.33 MHz should be utilized if performing calculation with System Bus
 239     /// Speed when encoding is 101B. 166.67 MHz should be utilized if
 240     /// performing calculation with System Bus Speed when encoding is 001B.
 241     ///
 242     UINT32  ScalableBusSpeed:3;
 243     UINT32  Reserved1:29;
 244     UINT32  Reserved2:32;
 245   } Bits;
 246   ///
 247   /// All bit fields as a 32-bit value
 248   ///
 249   UINT32  Uint32;
 250   ///
 251   /// All bit fields as a 64-bit value
 252   ///
 253   UINT64  Uint64;
 254 } MSR_CORE_FSB_FREQ_REGISTER;
 255
 256
 257 /**
 258   Shared.
 259
 260   @param  ECX  MSR_CORE_BBL_CR_CTL3 (0x0000011E)
 261   @param  EAX  Lower 32-bits of MSR value.
 262                Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
 263   @param  EDX  Upper 32-bits of MSR value.
 264                Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
 265
 266   <b>Example usage</b>
 267   @code
 268   MSR_CORE_BBL_CR_CTL3_REGISTER  Msr;
 269
 270   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_BBL_CR_CTL3);
 271   AsmWriteMsr64 (MSR_CORE_BBL_CR_CTL3, Msr.Uint64);
 272   @endcode
 273 **/
 274 #define MSR_CORE_BBL_CR_CTL3                     0x0000011E
 275
 276 /**
 277   MSR information returned for MSR index #MSR_CORE_BBL_CR_CTL3
 278 **/
 279 typedef union {
 280   ///
 281   /// Individual bit fields
 282   ///
 283   struct {
 284     ///
 285     /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
 286     /// Indicates if the L2 is hardware-disabled.
 287     ///
 288     UINT32  L2HardwareEnabled:1;
 289     UINT32  Reserved1:7;
 290     ///
 291     /// [Bit 8] L2 Enabled (R/W)  1 = L2 cache has been initialized 0 =
 292     /// Disabled (default) Until this bit is set the processor will not
 293     /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
 294     ///
 295     UINT32  L2Enabled:1;
 296     UINT32  Reserved2:14;
 297     ///
 298     /// [Bit 23] L2 Not Present (RO)  1. = L2 Present 2. = L2 Not Present.
 299     ///
 300     UINT32  L2NotPresent:1;
 301     UINT32  Reserved3:8;
 302     UINT32  Reserved4:32;
 303   } Bits;
 304   ///
 305   /// All bit fields as a 32-bit value
 306   ///
 307   UINT32  Uint32;
 308   ///
 309   /// All bit fields as a 64-bit value
 310   ///
 311   UINT64  Uint64;
 312 } MSR_CORE_BBL_CR_CTL3_REGISTER;
 313
 314
 315 /**
 316   Unique.
 317
 318   @param  ECX  MSR_CORE_THERM2_CTL (0x0000019D)
 319   @param  EAX  Lower 32-bits of MSR value.
 320                Described by the type MSR_CORE_THERM2_CTL_REGISTER.
 321   @param  EDX  Upper 32-bits of MSR value.
 322                Described by the type MSR_CORE_THERM2_CTL_REGISTER.
 323
 324   <b>Example usage</b>
 325   @code
 326   MSR_CORE_THERM2_CTL_REGISTER  Msr;
 327
 328   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_THERM2_CTL);
 329   AsmWriteMsr64 (MSR_CORE_THERM2_CTL, Msr.Uint64);
 330   @endcode
 331 **/
 332 #define MSR_CORE_THERM2_CTL                      0x0000019D
 333
 334 /**
 335   MSR information returned for MSR index #MSR_CORE_THERM2_CTL
 336 **/
 337 typedef union {
 338   ///
 339   /// Individual bit fields
 340   ///
 341   struct {
 342     UINT32  Reserved1:16;
 343     ///
 344     /// [Bit 16] TM_SELECT (R/W)  Mode of automatic thermal monitor: 1. =
 345     /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
 346     /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
 347     /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
 348     /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
 349     ///
 350     UINT32  TM_SELECT:1;
 351     UINT32  Reserved2:15;
 352     UINT32  Reserved3:32;
 353   } Bits;
 354   ///
 355   /// All bit fields as a 32-bit value
 356   ///
 357   UINT32  Uint32;
 358   ///
 359   /// All bit fields as a 64-bit value
 360   ///
 361   UINT64  Uint64;
 362 } MSR_CORE_THERM2_CTL_REGISTER;
 363
 364
 365 /**
 366   Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
 367   functions to be enabled and disabled.
 368
 369   @param  ECX  MSR_CORE_IA32_MISC_ENABLE (0x000001A0)
 370   @param  EAX  Lower 32-bits of MSR value.
 371                Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
 372   @param  EDX  Upper 32-bits of MSR value.
 373                Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
 374
 375   <b>Example usage</b>
 376   @code
 377   MSR_CORE_IA32_MISC_ENABLE_REGISTER  Msr;
 378
 379   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_MISC_ENABLE);
 380   AsmWriteMsr64 (MSR_CORE_IA32_MISC_ENABLE, Msr.Uint64);
 381   @endcode
 382 **/
 383 #define MSR_CORE_IA32_MISC_ENABLE                0x000001A0
 384
 385 /**
 386   MSR information returned for MSR index #MSR_CORE_IA32_MISC_ENABLE
 387 **/
 388 typedef union {
 389   ///
 390   /// Individual bit fields
 391   ///
 392   struct {
 393     UINT32  Reserved1:3;
 394     ///
 395     /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
 396     /// Table 35-2.
 397     ///
 398     UINT32  AutomaticThermalControlCircuit:1;
 399     UINT32  Reserved2:3;
 400     ///
 401     /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
 402     ///
 403     UINT32  PerformanceMonitoring:1;
 404     UINT32  Reserved3:2;
 405     ///
 406     /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
 407     /// the processor to indicate a pending break event within the processor 0
 408     /// = Indicates compatible FERR# signaling behavior This bit must be set
 409     /// to 1 to support XAPIC interrupt model usage.
 410     ///
 411     UINT32  FERR:1;
 412     ///
 413     /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
 414     ///
 415     UINT32  BTS:1;
 416     UINT32  Reserved4:1;
 417     ///
 418     /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
 419     /// thermal sensor indicates that the die temperature is at the
 420     /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
 421     /// TM2 will reduce the bus to core ratio and voltage according to the
 422     /// value last written to MSR_THERM2_CTL bits 15:0.
 423     ///   When this bit is clear (0, default), the processor does not change
 424     ///   the VID signals or the bus to core ratio when the processor enters a
 425     ///   thermal managed state. If the TM2 feature flag (ECX[8]) is not set
 426     ///   to 1 after executing CPUID with EAX = 1, then this feature is not
 427     ///   supported and BIOS must not alter the contents of this bit location.
 428     ///   The processor is operating out of spec if both this bit and the TM1
 429     ///   bit are set to disabled states.
 430     ///
 431     UINT32  TM2:1;
 432     UINT32  Reserved5:2;
 433     ///
 434     /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
 435     /// Enhanced Intel SpeedStep Technology enabled.
 436     ///
 437     UINT32  EIST:1;
 438     UINT32  Reserved6:1;
 439     ///
 440     /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
 441     ///
 442     UINT32  MONITOR:1;
 443     UINT32  Reserved7:1;
 444     UINT32  Reserved8:2;
 445     ///
 446     /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2. Setting this
 447     /// bit may cause behavior in software that depends on the availability of
 448     /// CPUID leaves greater than 3.
 449     ///
 450     UINT32  LimitCpuidMaxval:1;
 451     UINT32  Reserved9:9;
 452     UINT32  Reserved10:2;
 453     ///
 454     /// [Bit 34] Shared. XD Bit Disable (R/W) See Table 35-2.
 455     ///
 456     UINT32  XD:1;
 457     UINT32  Reserved11:29;
 458   } Bits;
 459   ///
 460   /// All bit fields as a 64-bit value
 461   ///
 462   UINT64  Uint64;
 463 } MSR_CORE_IA32_MISC_ENABLE_REGISTER;
 464
 465
 466 /**
 467   Unique. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-3)
 468   that points to the MSR containing the most recent branch record. See
 469   MSR_LASTBRANCH_0_FROM_IP (at 40H).
 470
 471   @param  ECX  MSR_CORE_LASTBRANCH_TOS (0x000001C9)
 472   @param  EAX  Lower 32-bits of MSR value.
 473   @param  EDX  Upper 32-bits of MSR value.
 474
 475   <b>Example usage</b>
 476   @code
 477   UINT64  Msr;
 478
 479   Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_TOS);
 480   AsmWriteMsr64 (MSR_CORE_LASTBRANCH_TOS, Msr);
 481   @endcode
 482 **/
 483 #define MSR_CORE_LASTBRANCH_TOS                  0x000001C9
 484
 485
 486 /**
 487   Unique. Last Exception Record From Linear IP (R)  Contains a pointer to the
 488   last branch instruction that the processor executed prior to the last
 489   exception that was generated or the last interrupt that was handled.
 490
 491   @param  ECX  MSR_CORE_LER_FROM_LIP (0x000001DD)
 492   @param  EAX  Lower 32-bits of MSR value.
 493   @param  EDX  Upper 32-bits of MSR value.
 494
 495   <b>Example usage</b>
 496   @code
 497   UINT64  Msr;
 498
 499   Msr = AsmReadMsr64 (MSR_CORE_LER_FROM_LIP);
 500   @endcode
 501 **/
 502 #define MSR_CORE_LER_FROM_LIP                    0x000001DD
 503
 504
 505 /**
 506   Unique. Last Exception Record To Linear IP (R)  This area contains a pointer
 507   to the target of the last branch instruction that the processor executed
 508   prior to the last exception that was generated or the last interrupt that
 509   was handled.
 510
 511   @param  ECX  MSR_CORE_LER_TO_LIP (0x000001DE)
 512   @param  EAX  Lower 32-bits of MSR value.
 513   @param  EDX  Upper 32-bits of MSR value.
 514
 515   <b>Example usage</b>
 516   @code
 517   UINT64  Msr;
 518
 519   Msr = AsmReadMsr64 (MSR_CORE_LER_TO_LIP);
 520   @endcode
 521 **/
 522 #define MSR_CORE_LER_TO_LIP                      0x000001DE
 523
 524
 525 /**
 526   Unique.
 527
 528   @param  ECX  MSR_CORE_ROB_CR_BKUPTMPDR6 (0x000001E0)
 529   @param  EAX  Lower 32-bits of MSR value.
 530                Described by the type MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER.
 531   @param  EDX  Upper 32-bits of MSR value.
 532                Described by the type MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER.
 533
 534   <b>Example usage</b>
 535   @code
 536   MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER  Msr;
 537
 538   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6);
 539   AsmWriteMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6, Msr.Uint64);
 540   @endcode
 541 **/
 542 #define MSR_CORE_ROB_CR_BKUPTMPDR6               0x000001E0
 543
 544 /**
 545   MSR information returned for MSR index #MSR_CORE_ROB_CR_BKUPTMPDR6
 546 **/
 547 typedef union {
 548   ///
 549   /// Individual bit fields
 550   ///
 551   struct {
 552     UINT32  Reserved1:2;
 553     ///
 554     /// [Bit 2] Fast Strings Enable bit. (Default, enabled).
 555     ///
 556     UINT32  FastStrings:1;
 557     UINT32  Reserved2:29;
 558     UINT32  Reserved3:32;
 559   } Bits;
 560   ///
 561   /// All bit fields as a 32-bit value
 562   ///
 563   UINT32  Uint32;
 564   ///
 565   /// All bit fields as a 64-bit value
 566   ///
 567   UINT64  Uint64;
 568 } MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER;
 569
 570
 571 /**
 572   Unique.
 573
 574   @param  ECX  MSR_CORE_MTRRPHYSBASEn
 575   @param  EAX  Lower 32-bits of MSR value.
 576   @param  EDX  Upper 32-bits of MSR value.
 577
 578   <b>Example usage</b>
 579   @code
 580   UINT64  Msr;
 581
 582   Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
 583   AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);
 584   @endcode
 585   @{
 586 **/
 587 #define MSR_CORE_MTRRPHYSBASE0                   0x00000200
 588 #define MSR_CORE_MTRRPHYSBASE1                   0x00000202
 589 #define MSR_CORE_MTRRPHYSBASE2                   0x00000204
 590 #define MSR_CORE_MTRRPHYSBASE3                   0x00000206
 591 #define MSR_CORE_MTRRPHYSBASE4                   0x00000208
 592 #define MSR_CORE_MTRRPHYSBASE5                   0x0000020A
 593 #define MSR_CORE_MTRRPHYSMASK6                   0x0000020D
 594 #define MSR_CORE_MTRRPHYSMASK7                   0x0000020F
 595 /// @}
 596
 597
 598 /**
 599   Unique.
 600
 601   @param  ECX  MSR_CORE_MTRRPHYSMASKn (0x00000201)
 602   @param  EAX  Lower 32-bits of MSR value.
 603   @param  EDX  Upper 32-bits of MSR value.
 604
 605   <b>Example usage</b>
 606   @code
 607   UINT64  Msr;
 608
 609   Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);
 610   AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);
 611   @endcode
 612   @{
 613 **/
 614 #define MSR_CORE_MTRRPHYSMASK0                   0x00000201
 615 #define MSR_CORE_MTRRPHYSMASK1                   0x00000203
 616 #define MSR_CORE_MTRRPHYSMASK2                   0x00000205
 617 #define MSR_CORE_MTRRPHYSMASK3                   0x00000207
 618 #define MSR_CORE_MTRRPHYSMASK4                   0x00000209
 619 #define MSR_CORE_MTRRPHYSMASK5                   0x0000020B
 620 #define MSR_CORE_MTRRPHYSBASE6                   0x0000020C
 621 #define MSR_CORE_MTRRPHYSBASE7                   0x0000020E
 622 /// @}
 623
 624
 625 /**
 626   Unique.
 627
 628   @param  ECX  MSR_CORE_MTRRFIX64K_00000 (0x00000250)
 629   @param  EAX  Lower 32-bits of MSR value.
 630   @param  EDX  Upper 32-bits of MSR value.
 631
 632   <b>Example usage</b>
 633   @code
 634   UINT64  Msr;
 635
 636   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX64K_00000);
 637   AsmWriteMsr64 (MSR_CORE_MTRRFIX64K_00000, Msr);
 638   @endcode
 639 **/
 640 #define MSR_CORE_MTRRFIX64K_00000                0x00000250
 641
 642
 643 /**
 644   Unique.
 645
 646   @param  ECX  MSR_CORE_MTRRFIX16K_80000 (0x00000258)
 647   @param  EAX  Lower 32-bits of MSR value.
 648   @param  EDX  Upper 32-bits of MSR value.
 649
 650   <b>Example usage</b>
 651   @code
 652   UINT64  Msr;
 653
 654   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_80000);
 655   AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_80000, Msr);
 656   @endcode
 657 **/
 658 #define MSR_CORE_MTRRFIX16K_80000                0x00000258
 659
 660
 661 /**
 662   Unique.
 663
 664   @param  ECX  MSR_CORE_MTRRFIX16K_A0000 (0x00000259)
 665   @param  EAX  Lower 32-bits of MSR value.
 666   @param  EDX  Upper 32-bits of MSR value.
 667
 668   <b>Example usage</b>
 669   @code
 670   UINT64  Msr;
 671
 672   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_A0000);
 673   AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_A0000, Msr);
 674   @endcode
 675 **/
 676 #define MSR_CORE_MTRRFIX16K_A0000                0x00000259
 677
 678
 679 /**
 680   Unique.
 681
 682   @param  ECX  MSR_CORE_MTRRFIX4K_C0000 (0x00000268)
 683   @param  EAX  Lower 32-bits of MSR value.
 684   @param  EDX  Upper 32-bits of MSR value.
 685
 686   <b>Example usage</b>
 687   @code
 688   UINT64  Msr;
 689
 690   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C0000);
 691   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C0000, Msr);
 692   @endcode
 693 **/
 694 #define MSR_CORE_MTRRFIX4K_C0000                 0x00000268
 695
 696
 697 /**
 698   Unique.
 699
 700   @param  ECX  MSR_CORE_MTRRFIX4K_C8000 (0x00000269)
 701   @param  EAX  Lower 32-bits of MSR value.
 702   @param  EDX  Upper 32-bits of MSR value.
 703
 704   <b>Example usage</b>
 705   @code
 706   UINT64  Msr;
 707
 708   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C8000);
 709   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C8000, Msr);
 710   @endcode
 711 **/
 712 #define MSR_CORE_MTRRFIX4K_C8000                 0x00000269
 713
 714
 715 /**
 716   Unique.
 717
 718   @param  ECX  MSR_CORE_MTRRFIX4K_D0000 (0x0000026A)
 719   @param  EAX  Lower 32-bits of MSR value.
 720   @param  EDX  Upper 32-bits of MSR value.
 721
 722   <b>Example usage</b>
 723   @code
 724   UINT64  Msr;
 725
 726   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D0000);
 727   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D0000, Msr);
 728   @endcode
 729 **/
 730 #define MSR_CORE_MTRRFIX4K_D0000                 0x0000026A
 731
 732
 733 /**
 734   Unique.
 735
 736   @param  ECX  MSR_CORE_MTRRFIX4K_D8000 (0x0000026B)
 737   @param  EAX  Lower 32-bits of MSR value.
 738   @param  EDX  Upper 32-bits of MSR value.
 739
 740   <b>Example usage</b>
 741   @code
 742   UINT64  Msr;
 743
 744   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D8000);
 745   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D8000, Msr);
 746   @endcode
 747 **/
 748 #define MSR_CORE_MTRRFIX4K_D8000                 0x0000026B
 749
 750
 751 /**
 752   Unique.
 753
 754   @param  ECX  MSR_CORE_MTRRFIX4K_E0000 (0x0000026C)
 755   @param  EAX  Lower 32-bits of MSR value.
 756   @param  EDX  Upper 32-bits of MSR value.
 757
 758   <b>Example usage</b>
 759   @code
 760   UINT64  Msr;
 761
 762   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E0000);
 763   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E0000, Msr);
 764   @endcode
 765 **/
 766 #define MSR_CORE_MTRRFIX4K_E0000                 0x0000026C
 767
 768
 769 /**
 770   Unique.
 771
 772   @param  ECX  MSR_CORE_MTRRFIX4K_E8000 (0x0000026D)
 773   @param  EAX  Lower 32-bits of MSR value.
 774   @param  EDX  Upper 32-bits of MSR value.
 775
 776   <b>Example usage</b>
 777   @code
 778   UINT64  Msr;
 779
 780   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E8000);
 781   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E8000, Msr);
 782   @endcode
 783 **/
 784 #define MSR_CORE_MTRRFIX4K_E8000                 0x0000026D
 785
 786
 787 /**
 788   Unique.
 789
 790   @param  ECX  MSR_CORE_MTRRFIX4K_F0000 (0x0000026E)
 791   @param  EAX  Lower 32-bits of MSR value.
 792   @param  EDX  Upper 32-bits of MSR value.
 793
 794   <b>Example usage</b>
 795   @code
 796   UINT64  Msr;
 797
 798   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F0000);
 799   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F0000, Msr);
 800   @endcode
 801 **/
 802 #define MSR_CORE_MTRRFIX4K_F0000                 0x0000026E
 803
 804
 805 /**
 806   Unique.
 807
 808   @param  ECX  MSR_CORE_MTRRFIX4K_F8000 (0x0000026F)
 809   @param  EAX  Lower 32-bits of MSR value.
 810   @param  EDX  Upper 32-bits of MSR value.
 811
 812   <b>Example usage</b>
 813   @code
 814   UINT64  Msr;
 815
 816   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F8000);
 817   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F8000, Msr);
 818   @endcode
 819 **/
 820 #define MSR_CORE_MTRRFIX4K_F8000                 0x0000026F
 821
 822
 823 /**
 824   Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
 825
 826   @param  ECX  MSR_CORE_MC4_CTL (0x0000040C)
 827   @param  EAX  Lower 32-bits of MSR value.
 828   @param  EDX  Upper 32-bits of MSR value.
 829
 830   <b>Example usage</b>
 831   @code
 832   UINT64  Msr;
 833
 834   Msr = AsmReadMsr64 (MSR_CORE_MC4_CTL);
 835   AsmWriteMsr64 (MSR_CORE_MC4_CTL, Msr);
 836   @endcode
 837 **/
 838 #define MSR_CORE_MC4_CTL                         0x0000040C
 839
 840
 841 /**
 842   Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
 843
 844   @param  ECX  MSR_CORE_MC4_STATUS (0x0000040D)
 845   @param  EAX  Lower 32-bits of MSR value.
 846   @param  EDX  Upper 32-bits of MSR value.
 847
 848   <b>Example usage</b>
 849   @code
 850   UINT64  Msr;
 851
 852   Msr = AsmReadMsr64 (MSR_CORE_MC4_STATUS);
 853   AsmWriteMsr64 (MSR_CORE_MC4_STATUS, Msr);
 854   @endcode
 855 **/
 856 #define MSR_CORE_MC4_STATUS                      0x0000040D
 857
 858
 859 /**
 860   Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR
 861   register is either not implemented or contains no address if the ADDRV flag
 862   in the MSR_MC4_STATUS register is clear. When not implemented in the
 863   processor, all reads and writes to this MSR will cause a general-protection
 864   exception.
 865
 866   @param  ECX  MSR_CORE_MC4_ADDR (0x0000040E)
 867   @param  EAX  Lower 32-bits of MSR value.
 868   @param  EDX  Upper 32-bits of MSR value.
 869
 870   <b>Example usage</b>
 871   @code
 872   UINT64  Msr;
 873
 874   Msr = AsmReadMsr64 (MSR_CORE_MC4_ADDR);
 875   AsmWriteMsr64 (MSR_CORE_MC4_ADDR, Msr);
 876   @endcode
 877 **/
 878 #define MSR_CORE_MC4_ADDR                        0x0000040E
 879
 880
 881 /**
 882   See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
 883
 884   @param  ECX  MSR_CORE_MC3_CTL (0x00000410)
 885   @param  EAX  Lower 32-bits of MSR value.
 886   @param  EDX  Upper 32-bits of MSR value.
 887
 888   <b>Example usage</b>
 889   @code
 890   UINT64  Msr;
 891
 892   Msr = AsmReadMsr64 (MSR_CORE_MC3_CTL);
 893   AsmWriteMsr64 (MSR_CORE_MC3_CTL, Msr);
 894   @endcode
 895 **/
 896 #define MSR_CORE_MC3_CTL                         0x00000410
 897
 898
 899 /**
 900   See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
 901
 902   @param  ECX  MSR_CORE_MC3_STATUS (0x00000411)
 903   @param  EAX  Lower 32-bits of MSR value.
 904   @param  EDX  Upper 32-bits of MSR value.
 905
 906   <b>Example usage</b>
 907   @code
 908   UINT64  Msr;
 909
 910   Msr = AsmReadMsr64 (MSR_CORE_MC3_STATUS);
 911   AsmWriteMsr64 (MSR_CORE_MC3_STATUS, Msr);
 912   @endcode
 913 **/
 914 #define MSR_CORE_MC3_STATUS                      0x00000411
 915
 916
 917 /**
 918   Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR
 919   register is either not implemented or contains no address if the ADDRV flag
 920   in the MSR_MC3_STATUS register is clear. When not implemented in the
 921   processor, all reads and writes to this MSR will cause a general-protection
 922   exception.
 923
 924   @param  ECX  MSR_CORE_MC3_ADDR (0x00000412)
 925   @param  EAX  Lower 32-bits of MSR value.
 926   @param  EDX  Upper 32-bits of MSR value.
 927
 928   <b>Example usage</b>
 929   @code
 930   UINT64  Msr;
 931
 932   Msr = AsmReadMsr64 (MSR_CORE_MC3_ADDR);
 933   AsmWriteMsr64 (MSR_CORE_MC3_ADDR, Msr);
 934   @endcode
 935 **/
 936 #define MSR_CORE_MC3_ADDR                        0x00000412
 937
 938
 939 /**
 940   Unique.
 941
 942   @param  ECX  MSR_CORE_MC3_MISC (0x00000413)
 943   @param  EAX  Lower 32-bits of MSR value.
 944   @param  EDX  Upper 32-bits of MSR value.
 945
 946   <b>Example usage</b>
 947   @code
 948   UINT64  Msr;
 949
 950   Msr = AsmReadMsr64 (MSR_CORE_MC3_MISC);
 951   AsmWriteMsr64 (MSR_CORE_MC3_MISC, Msr);
 952   @endcode
 953 **/
 954 #define MSR_CORE_MC3_MISC                        0x00000413
 955
 956
 957 /**
 958   Unique.
 959
 960   @param  ECX  MSR_CORE_MC5_CTL (0x00000414)
 961   @param  EAX  Lower 32-bits of MSR value.
 962   @param  EDX  Upper 32-bits of MSR value.
 963
 964   <b>Example usage</b>
 965   @code
 966   UINT64  Msr;
 967
 968   Msr = AsmReadMsr64 (MSR_CORE_MC5_CTL);
 969   AsmWriteMsr64 (MSR_CORE_MC5_CTL, Msr);
 970   @endcode
 971 **/
 972 #define MSR_CORE_MC5_CTL                         0x00000414
 973
 974
 975 /**
 976   Unique.
 977
 978   @param  ECX  MSR_CORE_MC5_STATUS (0x00000415)
 979   @param  EAX  Lower 32-bits of MSR value.
 980   @param  EDX  Upper 32-bits of MSR value.
 981
 982   <b>Example usage</b>
 983   @code
 984   UINT64  Msr;
 985
 986   Msr = AsmReadMsr64 (MSR_CORE_MC5_STATUS);
 987   AsmWriteMsr64 (MSR_CORE_MC5_STATUS, Msr);
 988   @endcode
 989 **/
 990 #define MSR_CORE_MC5_STATUS                      0x00000415
 991
 992
 993 /**
 994   Unique.
 995
 996   @param  ECX  MSR_CORE_MC5_ADDR (0x00000416)
 997   @param  EAX  Lower 32-bits of MSR value.
 998   @param  EDX  Upper 32-bits of MSR value.
 999
1000   <b>Example usage</b>
1001   @code
1002   UINT64  Msr;
1003
1004   Msr = AsmReadMsr64 (MSR_CORE_MC5_ADDR);
1005   AsmWriteMsr64 (MSR_CORE_MC5_ADDR, Msr);
1006   @endcode
1007 **/
1008 #define MSR_CORE_MC5_ADDR                        0x00000416
1009
1010
1011 /**
1012   Unique.
1013
1014   @param  ECX  MSR_CORE_MC5_MISC (0x00000417)
1015   @param  EAX  Lower 32-bits of MSR value.
1016   @param  EDX  Upper 32-bits of MSR value.
1017
1018   <b>Example usage</b>
1019   @code
1020   UINT64  Msr;
1021
1022   Msr = AsmReadMsr64 (MSR_CORE_MC5_MISC);
1023   AsmWriteMsr64 (MSR_CORE_MC5_MISC, Msr);
1024   @endcode
1025 **/
1026 #define MSR_CORE_MC5_MISC                        0x00000417
1027
1028
1029 /**
1030   Unique. See Table 35-2.
1031
1032   @param  ECX  MSR_CORE_IA32_EFER (0xC0000080)
1033   @param  EAX  Lower 32-bits of MSR value.
1034                Described by the type MSR_CORE_IA32_EFER_REGISTER.
1035   @param  EDX  Upper 32-bits of MSR value.
1036                Described by the type MSR_CORE_IA32_EFER_REGISTER.
1037
1038   <b>Example usage</b>
1039   @code
1040   MSR_CORE_IA32_EFER_REGISTER  Msr;
1041
1042   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);
1043   AsmWriteMsr64 (MSR_CORE_IA32_EFER, Msr.Uint64);
1044   @endcode
1045 **/
1046 #define MSR_CORE_IA32_EFER                       0xC0000080
1047
1048 /**
1049   MSR information returned for MSR index #MSR_CORE_IA32_EFER
1050 **/
1051 typedef union {
1052   ///
1053   /// Individual bit fields
1054   ///
1055   struct {
1056     UINT32  Reserved1:11;
1057     ///
1058     /// [Bit 11] Execute Disable Bit Enable.
1059     ///
1060     UINT32  NXE:1;
1061     UINT32  Reserved2:20;
1062     UINT32  Reserved3:32;
1063   } Bits;
1064   ///
1065   /// All bit fields as a 32-bit value
1066   ///
1067   UINT32  Uint32;
1068   ///
1069   /// All bit fields as a 64-bit value
1070   ///
1071   UINT64  Uint64;
1072 } MSR_CORE_IA32_EFER_REGISTER;
1073
1074 #endif