2 MSR Definitions for Intel Core Solo and Intel Core Duo Processors.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __CORE_MSR_H__
19 #define __CORE_MSR_H__
21 #include <Register/ArchitecturalMsr.h>
24 Is Intel Core Solo and Intel Core Duo Processors?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_CORE_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
35 DisplayModel == 0x0E \
40 Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.
42 @param ECX MSR_CORE_P5_MC_ADDR (0x00000000)
43 @param EAX Lower 32-bits of MSR value.
44 @param EDX Upper 32-bits of MSR value.
50 Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);
51 AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);
53 @note MSR_CORE_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
55 #define MSR_CORE_P5_MC_ADDR 0x00000000
59 Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.
61 @param ECX MSR_CORE_P5_MC_TYPE (0x00000001)
62 @param EAX Lower 32-bits of MSR value.
63 @param EDX Upper 32-bits of MSR value.
69 Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);
70 AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);
72 @note MSR_CORE_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
74 #define MSR_CORE_P5_MC_TYPE 0x00000001
78 Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
79 processor features; (R) indicates current processor configuration.
81 @param ECX MSR_CORE_EBL_CR_POWERON (0x0000002A)
82 @param EAX Lower 32-bits of MSR value.
83 Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
84 @param EDX Upper 32-bits of MSR value.
85 Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
89 MSR_CORE_EBL_CR_POWERON_REGISTER Msr;
91 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);
92 AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);
94 @note MSR_CORE_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
96 #define MSR_CORE_EBL_CR_POWERON 0x0000002A
99 MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON
103 /// Individual bit fields
108 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
109 /// Note: Not all processor implements R/W.
111 UINT32 DataErrorCheckingEnable
:1;
113 /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
114 /// Note: Not all processor implements R/W.
116 UINT32 ResponseErrorCheckingEnable
:1;
118 /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
119 /// all processor implements R/W.
121 UINT32 MCERR_DriveEnable
:1;
123 /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
124 /// Not all processor implements R/W.
126 UINT32 AddressParityEnable
:1;
129 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
130 /// all processor implements R/W.
132 UINT32 BINIT_DriverEnable
:1;
134 /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
136 UINT32 OutputTriStateEnable
:1;
138 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
140 UINT32 ExecuteBIST
:1;
142 /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
144 UINT32 MCERR_ObservationEnabled
:1;
147 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
149 UINT32 BINIT_ObservationEnabled
:1;
152 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
154 UINT32 ResetVector
:1;
157 /// [Bits 17:16] APIC Cluster ID (R/O).
159 UINT32 APICClusterID
:2;
161 /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved.
163 UINT32 SystemBusFrequency
:1;
166 /// [Bits 21:20] Symmetric Arbitration ID (R/O).
168 UINT32 SymmetricArbitrationID
:2;
170 /// [Bits 26:22] Clock Frequency Ratio (R/O).
172 UINT32 ClockFrequencyRatio
:5;
177 /// All bit fields as a 32-bit value
181 /// All bit fields as a 64-bit value
184 } MSR_CORE_EBL_CR_POWERON_REGISTER
;
188 Unique. Last Branch Record n (R/W) One of 8 last branch record registers on
189 the last branch record stack: bits 31-0 hold the 'from' address and bits
190 63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at
191 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording
192 (Pentium M Processors).".
194 @param ECX MSR_CORE_LASTBRANCH_n
195 @param EAX Lower 32-bits of MSR value.
196 @param EDX Upper 32-bits of MSR value.
202 Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
203 AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);
205 @note MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
206 MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
207 MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
208 MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
209 MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
210 MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
211 MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
212 MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
215 #define MSR_CORE_LASTBRANCH_0 0x00000040
216 #define MSR_CORE_LASTBRANCH_1 0x00000041
217 #define MSR_CORE_LASTBRANCH_2 0x00000042
218 #define MSR_CORE_LASTBRANCH_3 0x00000043
219 #define MSR_CORE_LASTBRANCH_4 0x00000044
220 #define MSR_CORE_LASTBRANCH_5 0x00000045
221 #define MSR_CORE_LASTBRANCH_6 0x00000046
222 #define MSR_CORE_LASTBRANCH_7 0x00000047
227 Shared. Scalable Bus Speed (RO) This field indicates the scalable bus
230 @param ECX MSR_CORE_FSB_FREQ (0x000000CD)
231 @param EAX Lower 32-bits of MSR value.
232 Described by the type MSR_CORE_FSB_FREQ_REGISTER.
233 @param EDX Upper 32-bits of MSR value.
234 Described by the type MSR_CORE_FSB_FREQ_REGISTER.
238 MSR_CORE_FSB_FREQ_REGISTER Msr;
240 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ);
242 @note MSR_CORE_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
244 #define MSR_CORE_FSB_FREQ 0x000000CD
247 MSR information returned for MSR index #MSR_CORE_FSB_FREQ
251 /// Individual bit fields
255 /// [Bits 2:0] - Scalable Bus Speed
256 /// 101B: 100 MHz (FSB 400)
257 /// 001B: 133 MHz (FSB 533)
258 /// 011B: 167 MHz (FSB 667)
260 /// 133.33 MHz should be utilized if performing calculation with System Bus
261 /// Speed when encoding is 101B. 166.67 MHz should be utilized if
262 /// performing calculation with System Bus Speed when encoding is 001B.
264 UINT32 ScalableBusSpeed
:3;
269 /// All bit fields as a 32-bit value
273 /// All bit fields as a 64-bit value
276 } MSR_CORE_FSB_FREQ_REGISTER
;
282 @param ECX MSR_CORE_BBL_CR_CTL3 (0x0000011E)
283 @param EAX Lower 32-bits of MSR value.
284 Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
285 @param EDX Upper 32-bits of MSR value.
286 Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
290 MSR_CORE_BBL_CR_CTL3_REGISTER Msr;
292 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_BBL_CR_CTL3);
293 AsmWriteMsr64 (MSR_CORE_BBL_CR_CTL3, Msr.Uint64);
295 @note MSR_CORE_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
297 #define MSR_CORE_BBL_CR_CTL3 0x0000011E
300 MSR information returned for MSR index #MSR_CORE_BBL_CR_CTL3
304 /// Individual bit fields
308 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
309 /// Indicates if the L2 is hardware-disabled.
311 UINT32 L2HardwareEnabled
:1;
314 /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
315 /// Disabled (default) Until this bit is set the processor will not
316 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
321 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
323 UINT32 L2NotPresent
:1;
328 /// All bit fields as a 32-bit value
332 /// All bit fields as a 64-bit value
335 } MSR_CORE_BBL_CR_CTL3_REGISTER
;
341 @param ECX MSR_CORE_THERM2_CTL (0x0000019D)
342 @param EAX Lower 32-bits of MSR value.
343 Described by the type MSR_CORE_THERM2_CTL_REGISTER.
344 @param EDX Upper 32-bits of MSR value.
345 Described by the type MSR_CORE_THERM2_CTL_REGISTER.
349 MSR_CORE_THERM2_CTL_REGISTER Msr;
351 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_THERM2_CTL);
352 AsmWriteMsr64 (MSR_CORE_THERM2_CTL, Msr.Uint64);
354 @note MSR_CORE_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
356 #define MSR_CORE_THERM2_CTL 0x0000019D
359 MSR information returned for MSR index #MSR_CORE_THERM2_CTL
363 /// Individual bit fields
368 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
369 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
370 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
371 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
372 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
379 /// All bit fields as a 32-bit value
383 /// All bit fields as a 64-bit value
386 } MSR_CORE_THERM2_CTL_REGISTER
;
390 Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
391 functions to be enabled and disabled.
393 @param ECX MSR_CORE_IA32_MISC_ENABLE (0x000001A0)
394 @param EAX Lower 32-bits of MSR value.
395 Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
396 @param EDX Upper 32-bits of MSR value.
397 Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
401 MSR_CORE_IA32_MISC_ENABLE_REGISTER Msr;
403 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_MISC_ENABLE);
404 AsmWriteMsr64 (MSR_CORE_IA32_MISC_ENABLE, Msr.Uint64);
406 @note MSR_CORE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
408 #define MSR_CORE_IA32_MISC_ENABLE 0x000001A0
411 MSR information returned for MSR index #MSR_CORE_IA32_MISC_ENABLE
415 /// Individual bit fields
420 /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
423 UINT32 AutomaticThermalControlCircuit
:1;
426 /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
428 UINT32 PerformanceMonitoring
:1;
431 /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
432 /// the processor to indicate a pending break event within the processor 0
433 /// = Indicates compatible FERR# signaling behavior This bit must be set
434 /// to 1 to support XAPIC interrupt model usage.
438 /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
443 /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
444 /// thermal sensor indicates that the die temperature is at the
445 /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
446 /// TM2 will reduce the bus to core ratio and voltage according to the
447 /// value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear
448 /// (0, default), the processor does not change the VID signals or the bus
449 /// to core ratio when the processor enters a thermal managed state. If
450 /// the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID
451 /// with EAX = 1, then this feature is not supported and BIOS must not
452 /// alter the contents of this bit location. The processor is operating
453 /// out of spec if both this bit and the TM1 bit are set to disabled
459 /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
460 /// Enhanced Intel SpeedStep Technology enabled.
465 /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
471 /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2. Setting this
472 /// bit may cause behavior in software that depends on the availability of
473 /// CPUID leaves greater than 2.
475 UINT32 LimitCpuidMaxval
:1;
479 /// [Bit 34] Shared. XD Bit Disable (R/W) See Table 2-2.
482 UINT32 Reserved11
:29;
485 /// All bit fields as a 64-bit value
488 } MSR_CORE_IA32_MISC_ENABLE_REGISTER
;
492 Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
493 that points to the MSR containing the most recent branch record. See
494 MSR_LASTBRANCH_0_FROM_IP (at 40H).
496 @param ECX MSR_CORE_LASTBRANCH_TOS (0x000001C9)
497 @param EAX Lower 32-bits of MSR value.
498 @param EDX Upper 32-bits of MSR value.
504 Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_TOS);
505 AsmWriteMsr64 (MSR_CORE_LASTBRANCH_TOS, Msr);
507 @note MSR_CORE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
509 #define MSR_CORE_LASTBRANCH_TOS 0x000001C9
513 Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
514 last branch instruction that the processor executed prior to the last
515 exception that was generated or the last interrupt that was handled.
517 @param ECX MSR_CORE_LER_FROM_LIP (0x000001DD)
518 @param EAX Lower 32-bits of MSR value.
519 @param EDX Upper 32-bits of MSR value.
525 Msr = AsmReadMsr64 (MSR_CORE_LER_FROM_LIP);
527 @note MSR_CORE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
529 #define MSR_CORE_LER_FROM_LIP 0x000001DD
533 Unique. Last Exception Record To Linear IP (R) This area contains a pointer
534 to the target of the last branch instruction that the processor executed
535 prior to the last exception that was generated or the last interrupt that
538 @param ECX MSR_CORE_LER_TO_LIP (0x000001DE)
539 @param EAX Lower 32-bits of MSR value.
540 @param EDX Upper 32-bits of MSR value.
546 Msr = AsmReadMsr64 (MSR_CORE_LER_TO_LIP);
548 @note MSR_CORE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
550 #define MSR_CORE_LER_TO_LIP 0x000001DE
555 @param ECX MSR_CORE_MTRRPHYSBASEn
556 @param EAX Lower 32-bits of MSR value.
557 @param EDX Upper 32-bits of MSR value.
563 Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
564 AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);
566 @note MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.
567 MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.
568 MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.
569 MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.
570 MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.
571 MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.
572 MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.
573 MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.
576 #define MSR_CORE_MTRRPHYSBASE0 0x00000200
577 #define MSR_CORE_MTRRPHYSBASE1 0x00000202
578 #define MSR_CORE_MTRRPHYSBASE2 0x00000204
579 #define MSR_CORE_MTRRPHYSBASE3 0x00000206
580 #define MSR_CORE_MTRRPHYSBASE4 0x00000208
581 #define MSR_CORE_MTRRPHYSBASE5 0x0000020A
582 #define MSR_CORE_MTRRPHYSMASK6 0x0000020D
583 #define MSR_CORE_MTRRPHYSMASK7 0x0000020F
590 @param ECX MSR_CORE_MTRRPHYSMASKn (0x00000201)
591 @param EAX Lower 32-bits of MSR value.
592 @param EDX Upper 32-bits of MSR value.
598 Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);
599 AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);
601 @note MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.
602 MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.
603 MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.
604 MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.
605 MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.
606 MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.
607 MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.
608 MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.
611 #define MSR_CORE_MTRRPHYSMASK0 0x00000201
612 #define MSR_CORE_MTRRPHYSMASK1 0x00000203
613 #define MSR_CORE_MTRRPHYSMASK2 0x00000205
614 #define MSR_CORE_MTRRPHYSMASK3 0x00000207
615 #define MSR_CORE_MTRRPHYSMASK4 0x00000209
616 #define MSR_CORE_MTRRPHYSMASK5 0x0000020B
617 #define MSR_CORE_MTRRPHYSBASE6 0x0000020C
618 #define MSR_CORE_MTRRPHYSBASE7 0x0000020E
625 @param ECX MSR_CORE_MTRRFIX64K_00000 (0x00000250)
626 @param EAX Lower 32-bits of MSR value.
627 @param EDX Upper 32-bits of MSR value.
633 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX64K_00000);
634 AsmWriteMsr64 (MSR_CORE_MTRRFIX64K_00000, Msr);
636 @note MSR_CORE_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.
638 #define MSR_CORE_MTRRFIX64K_00000 0x00000250
644 @param ECX MSR_CORE_MTRRFIX16K_80000 (0x00000258)
645 @param EAX Lower 32-bits of MSR value.
646 @param EDX Upper 32-bits of MSR value.
652 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_80000);
653 AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_80000, Msr);
655 @note MSR_CORE_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.
657 #define MSR_CORE_MTRRFIX16K_80000 0x00000258
663 @param ECX MSR_CORE_MTRRFIX16K_A0000 (0x00000259)
664 @param EAX Lower 32-bits of MSR value.
665 @param EDX Upper 32-bits of MSR value.
671 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_A0000);
672 AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_A0000, Msr);
674 @note MSR_CORE_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.
676 #define MSR_CORE_MTRRFIX16K_A0000 0x00000259
682 @param ECX MSR_CORE_MTRRFIX4K_C0000 (0x00000268)
683 @param EAX Lower 32-bits of MSR value.
684 @param EDX Upper 32-bits of MSR value.
690 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C0000);
691 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C0000, Msr);
693 @note MSR_CORE_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.
695 #define MSR_CORE_MTRRFIX4K_C0000 0x00000268
701 @param ECX MSR_CORE_MTRRFIX4K_C8000 (0x00000269)
702 @param EAX Lower 32-bits of MSR value.
703 @param EDX Upper 32-bits of MSR value.
709 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C8000);
710 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C8000, Msr);
712 @note MSR_CORE_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.
714 #define MSR_CORE_MTRRFIX4K_C8000 0x00000269
720 @param ECX MSR_CORE_MTRRFIX4K_D0000 (0x0000026A)
721 @param EAX Lower 32-bits of MSR value.
722 @param EDX Upper 32-bits of MSR value.
728 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D0000);
729 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D0000, Msr);
731 @note MSR_CORE_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.
733 #define MSR_CORE_MTRRFIX4K_D0000 0x0000026A
739 @param ECX MSR_CORE_MTRRFIX4K_D8000 (0x0000026B)
740 @param EAX Lower 32-bits of MSR value.
741 @param EDX Upper 32-bits of MSR value.
747 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D8000);
748 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D8000, Msr);
750 @note MSR_CORE_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.
752 #define MSR_CORE_MTRRFIX4K_D8000 0x0000026B
758 @param ECX MSR_CORE_MTRRFIX4K_E0000 (0x0000026C)
759 @param EAX Lower 32-bits of MSR value.
760 @param EDX Upper 32-bits of MSR value.
766 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E0000);
767 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E0000, Msr);
769 @note MSR_CORE_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.
771 #define MSR_CORE_MTRRFIX4K_E0000 0x0000026C
777 @param ECX MSR_CORE_MTRRFIX4K_E8000 (0x0000026D)
778 @param EAX Lower 32-bits of MSR value.
779 @param EDX Upper 32-bits of MSR value.
785 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E8000);
786 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E8000, Msr);
788 @note MSR_CORE_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.
790 #define MSR_CORE_MTRRFIX4K_E8000 0x0000026D
796 @param ECX MSR_CORE_MTRRFIX4K_F0000 (0x0000026E)
797 @param EAX Lower 32-bits of MSR value.
798 @param EDX Upper 32-bits of MSR value.
804 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F0000);
805 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F0000, Msr);
807 @note MSR_CORE_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.
809 #define MSR_CORE_MTRRFIX4K_F0000 0x0000026E
815 @param ECX MSR_CORE_MTRRFIX4K_F8000 (0x0000026F)
816 @param EAX Lower 32-bits of MSR value.
817 @param EDX Upper 32-bits of MSR value.
823 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F8000);
824 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F8000, Msr);
826 @note MSR_CORE_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.
828 #define MSR_CORE_MTRRFIX4K_F8000 0x0000026F
832 Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
834 @param ECX MSR_CORE_MC4_CTL (0x0000040C)
835 @param EAX Lower 32-bits of MSR value.
836 @param EDX Upper 32-bits of MSR value.
842 Msr = AsmReadMsr64 (MSR_CORE_MC4_CTL);
843 AsmWriteMsr64 (MSR_CORE_MC4_CTL, Msr);
845 @note MSR_CORE_MC4_CTL is defined as MSR_MC4_CTL in SDM.
847 #define MSR_CORE_MC4_CTL 0x0000040C
851 Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
853 @param ECX MSR_CORE_MC4_STATUS (0x0000040D)
854 @param EAX Lower 32-bits of MSR value.
855 @param EDX Upper 32-bits of MSR value.
861 Msr = AsmReadMsr64 (MSR_CORE_MC4_STATUS);
862 AsmWriteMsr64 (MSR_CORE_MC4_STATUS, Msr);
864 @note MSR_CORE_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
866 #define MSR_CORE_MC4_STATUS 0x0000040D
870 Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR
871 register is either not implemented or contains no address if the ADDRV flag
872 in the MSR_MC4_STATUS register is clear. When not implemented in the
873 processor, all reads and writes to this MSR will cause a general-protection
876 @param ECX MSR_CORE_MC4_ADDR (0x0000040E)
877 @param EAX Lower 32-bits of MSR value.
878 @param EDX Upper 32-bits of MSR value.
884 Msr = AsmReadMsr64 (MSR_CORE_MC4_ADDR);
885 AsmWriteMsr64 (MSR_CORE_MC4_ADDR, Msr);
887 @note MSR_CORE_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
889 #define MSR_CORE_MC4_ADDR 0x0000040E
893 Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR
894 register is either not implemented or contains no address if the ADDRV flag
895 in the MSR_MC3_STATUS register is clear. When not implemented in the
896 processor, all reads and writes to this MSR will cause a general-protection
899 @param ECX MSR_CORE_MC3_ADDR (0x00000412)
900 @param EAX Lower 32-bits of MSR value.
901 @param EDX Upper 32-bits of MSR value.
907 Msr = AsmReadMsr64 (MSR_CORE_MC3_ADDR);
908 AsmWriteMsr64 (MSR_CORE_MC3_ADDR, Msr);
910 @note MSR_CORE_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
912 #define MSR_CORE_MC3_ADDR 0x00000412
918 @param ECX MSR_CORE_MC3_MISC (0x00000413)
919 @param EAX Lower 32-bits of MSR value.
920 @param EDX Upper 32-bits of MSR value.
926 Msr = AsmReadMsr64 (MSR_CORE_MC3_MISC);
927 AsmWriteMsr64 (MSR_CORE_MC3_MISC, Msr);
929 @note MSR_CORE_MC3_MISC is defined as MSR_MC3_MISC in SDM.
931 #define MSR_CORE_MC3_MISC 0x00000413
937 @param ECX MSR_CORE_MC5_CTL (0x00000414)
938 @param EAX Lower 32-bits of MSR value.
939 @param EDX Upper 32-bits of MSR value.
945 Msr = AsmReadMsr64 (MSR_CORE_MC5_CTL);
946 AsmWriteMsr64 (MSR_CORE_MC5_CTL, Msr);
948 @note MSR_CORE_MC5_CTL is defined as MSR_MC5_CTL in SDM.
950 #define MSR_CORE_MC5_CTL 0x00000414
956 @param ECX MSR_CORE_MC5_STATUS (0x00000415)
957 @param EAX Lower 32-bits of MSR value.
958 @param EDX Upper 32-bits of MSR value.
964 Msr = AsmReadMsr64 (MSR_CORE_MC5_STATUS);
965 AsmWriteMsr64 (MSR_CORE_MC5_STATUS, Msr);
967 @note MSR_CORE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
969 #define MSR_CORE_MC5_STATUS 0x00000415
975 @param ECX MSR_CORE_MC5_ADDR (0x00000416)
976 @param EAX Lower 32-bits of MSR value.
977 @param EDX Upper 32-bits of MSR value.
983 Msr = AsmReadMsr64 (MSR_CORE_MC5_ADDR);
984 AsmWriteMsr64 (MSR_CORE_MC5_ADDR, Msr);
986 @note MSR_CORE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
988 #define MSR_CORE_MC5_ADDR 0x00000416
994 @param ECX MSR_CORE_MC5_MISC (0x00000417)
995 @param EAX Lower 32-bits of MSR value.
996 @param EDX Upper 32-bits of MSR value.
1002 Msr = AsmReadMsr64 (MSR_CORE_MC5_MISC);
1003 AsmWriteMsr64 (MSR_CORE_MC5_MISC, Msr);
1005 @note MSR_CORE_MC5_MISC is defined as MSR_MC5_MISC in SDM.
1007 #define MSR_CORE_MC5_MISC 0x00000417
1011 Unique. See Table 2-2.
1013 @param ECX MSR_CORE_IA32_EFER (0xC0000080)
1014 @param EAX Lower 32-bits of MSR value.
1015 Described by the type MSR_CORE_IA32_EFER_REGISTER.
1016 @param EDX Upper 32-bits of MSR value.
1017 Described by the type MSR_CORE_IA32_EFER_REGISTER.
1019 <b>Example usage</b>
1021 MSR_CORE_IA32_EFER_REGISTER Msr;
1023 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);
1024 AsmWriteMsr64 (MSR_CORE_IA32_EFER, Msr.Uint64);
1026 @note MSR_CORE_IA32_EFER is defined as IA32_EFER in SDM.
1028 #define MSR_CORE_IA32_EFER 0xC0000080
1031 MSR information returned for MSR index #MSR_CORE_IA32_EFER
1035 /// Individual bit fields
1038 UINT32 Reserved1
:11;
1040 /// [Bit 11] Execute Disable Bit Enable.
1043 UINT32 Reserved2
:20;
1044 UINT32 Reserved3
:32;
1047 /// All bit fields as a 32-bit value
1051 /// All bit fields as a 64-bit value
1054 } MSR_CORE_IA32_EFER_REGISTER
;