UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h

   1 /** @file
   2   MSR Defintions for Intel Atom processors based on the Goldmont Plus microarchitecture.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
  10   SPDX-License-Identifier: BSD-2-Clause-Patent
  11
  12   @par Specification Reference:
  13   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
  14   May 2018, Volume 4: Model-Specific-Registers (MSR)
  15
  16 **/
  17
  18 #ifndef __GOLDMONT_PLUS_MSR_H__
  19 #define __GOLDMONT_PLUS_MSR_H__
  20
  21 #include <Register/ArchitecturalMsr.h>
  22
  23 /**
  24   Is Intel Atom processors based on the Goldmont plus microarchitecture?
  25
  26   @param   DisplayFamily  Display Family ID
  27   @param   DisplayModel   Display Model ID
  28
  29   @retval  TRUE   Yes, it is.
  30   @retval  FALSE  No, it isn't.
  31 **/
  32 #define IS_GOLDMONT_PLUS_PROCESSOR(DisplayFamily, DisplayModel) \
  33   (DisplayFamily == 0x06 && \
  34    (                        \
  35     DisplayModel == 0x7A    \
  36     )                       \
  37    )
  38
  39 /**
  40   Core. (R/W) See Table 2-2. See Section 18.6.2.4, "Processor Event Based
  41   Sampling (PEBS).".
  42
  43   @param  ECX  MSR_GOLDMONT_PLUS_PEBS_ENABLE (0x000003F1)
  44   @param  EAX  Lower 32-bits of MSR value.
  45                Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
  46   @param  EDX  Upper 32-bits of MSR value.
  47                Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
  48
  49   <b>Example usage</b>
  50   @code
  51   MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER  Msr;
  52
  53   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE);
  54   AsmWriteMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE, Msr.Uint64);
  55   @endcode
  56 **/
  57 #define MSR_GOLDMONT_PLUS_PEBS_ENABLE            0x000003F1
  58
  59 /**
  60   MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE
  61 **/
  62 typedef union {
  63   ///
  64   /// Individual bit fields
  65   ///
  66   struct {
  67     ///
  68     /// [Bit 0] Enable PEBS trigger and recording for the programmed event
  69     /// (precise or otherwise) on IA32_PMC0.
  70     ///
  71     UINT32  Fix_Me_1:1;
  72     ///
  73     /// [Bit 1] Enable PEBS trigger and recording for the programmed event
  74     /// (precise or otherwise) on IA32_PMC1.
  75     ///
  76     UINT32  Fix_Me_2:1;
  77     ///
  78     /// [Bit 2] Enable PEBS trigger and recording for the programmed event
  79     /// (precise or otherwise) on IA32_PMC2.
  80     ///
  81     UINT32  Fix_Me_3:1;
  82     ///
  83     /// [Bit 3] Enable PEBS trigger and recording for the programmed event
  84     /// (precise or otherwise) on IA32_PMC3.
  85     ///
  86     UINT32  Fix_Me_4:1;
  87     UINT32  Reserved1:28;
  88     ///
  89     /// [Bit 32] Enable PEBS trigger and recording for IA32_FIXED_CTR0.
  90     ///
  91     UINT32  Fix_Me_5:1;
  92     ///
  93     /// [Bit 33] Enable PEBS trigger and recording for IA32_FIXED_CTR1.
  94     ///
  95     UINT32  Fix_Me_6:1;
  96     ///
  97     /// [Bit 34] Enable PEBS trigger and recording for IA32_FIXED_CTR2.
  98     ///
  99     UINT32  Fix_Me_7:1;
 100     UINT32  Reserved2:29;
 101   } Bits;
 102   ///
 103   /// All bit fields as a 64-bit value
 104   ///
 105   UINT64  Uint64;
 106 } MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER;
 107
 108
 109 /**
 110   Core. Last Branch Record N From IP (R/W) One of the three MSRs that make up
 111   the first entry of the 32-entry LBR stack. The From_IP part of the stack
 112   contains pointers to the source instruction. See also: -  Last Branch Record
 113   Stack TOS at 1C9H. -  Section 17.7, "Last Branch, Call Stack, Interrupt, and
 114   .. Exception Recording for Processors based on Goldmont Plus
 115   Microarchitecture.".
 116
 117   @param  ECX  MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP (0x0000068N)
 118   @param  EAX  Lower 32-bits of MSR value.
 119   @param  EDX  Upper 32-bits of MSR value.
 120
 121   <b>Example usage</b>
 122   @code
 123   UINT64  Msr;
 124
 125   Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP);
 126   AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP, Msr);
 127   @endcode
 128 **/
 129 #define MSR_GOLDMONT_PLUS_LASTBRANCH_0_FROM_IP    0x00000680
 130 #define MSR_GOLDMONT_PLUS_LASTBRANCH_1_FROM_IP    0x00000681
 131 #define MSR_GOLDMONT_PLUS_LASTBRANCH_2_FROM_IP    0x00000682
 132 #define MSR_GOLDMONT_PLUS_LASTBRANCH_3_FROM_IP    0x00000683
 133 #define MSR_GOLDMONT_PLUS_LASTBRANCH_4_FROM_IP    0x00000684
 134 #define MSR_GOLDMONT_PLUS_LASTBRANCH_5_FROM_IP    0x00000685
 135 #define MSR_GOLDMONT_PLUS_LASTBRANCH_6_FROM_IP    0x00000686
 136 #define MSR_GOLDMONT_PLUS_LASTBRANCH_7_FROM_IP    0x00000687
 137 #define MSR_GOLDMONT_PLUS_LASTBRANCH_8_FROM_IP    0x00000688
 138 #define MSR_GOLDMONT_PLUS_LASTBRANCH_9_FROM_IP    0x00000689
 139 #define MSR_GOLDMONT_PLUS_LASTBRANCH_10_FROM_IP   0x0000068A
 140 #define MSR_GOLDMONT_PLUS_LASTBRANCH_11_FROM_IP   0x0000068B
 141 #define MSR_GOLDMONT_PLUS_LASTBRANCH_12_FROM_IP   0x0000068C
 142 #define MSR_GOLDMONT_PLUS_LASTBRANCH_13_FROM_IP   0x0000068D
 143 #define MSR_GOLDMONT_PLUS_LASTBRANCH_14_FROM_IP   0x0000068E
 144 #define MSR_GOLDMONT_PLUS_LASTBRANCH_15_FROM_IP   0x0000068F
 145 #define MSR_GOLDMONT_PLUS_LASTBRANCH_16_FROM_IP   0x00000690
 146 #define MSR_GOLDMONT_PLUS_LASTBRANCH_17_FROM_IP   0x00000691
 147 #define MSR_GOLDMONT_PLUS_LASTBRANCH_18_FROM_IP   0x00000692
 148 #define MSR_GOLDMONT_PLUS_LASTBRANCH_19_FROM_IP   0x00000693
 149 #define MSR_GOLDMONT_PLUS_LASTBRANCH_20_FROM_IP   0x00000694
 150 #define MSR_GOLDMONT_PLUS_LASTBRANCH_21_FROM_IP   0x00000695
 151 #define MSR_GOLDMONT_PLUS_LASTBRANCH_22_FROM_IP   0x00000696
 152 #define MSR_GOLDMONT_PLUS_LASTBRANCH_23_FROM_IP   0x00000697
 153 #define MSR_GOLDMONT_PLUS_LASTBRANCH_24_FROM_IP   0x00000698
 154 #define MSR_GOLDMONT_PLUS_LASTBRANCH_25_FROM_IP   0x00000699
 155 #define MSR_GOLDMONT_PLUS_LASTBRANCH_26_FROM_IP   0x0000069A
 156 #define MSR_GOLDMONT_PLUS_LASTBRANCH_27_FROM_IP   0x0000069B
 157 #define MSR_GOLDMONT_PLUS_LASTBRANCH_28_FROM_IP   0x0000069C
 158 #define MSR_GOLDMONT_PLUS_LASTBRANCH_29_FROM_IP   0x0000069D
 159 #define MSR_GOLDMONT_PLUS_LASTBRANCH_30_FROM_IP   0x0000069E
 160 #define MSR_GOLDMONT_PLUS_LASTBRANCH_31_FROM_IP   0x0000069F
 161
 162 /**
 163   Core. Last Branch Record N To IP (R/W) One of the three MSRs that make up
 164   the first entry of the 32-entry LBR stack. The To_IP part of the stack
 165   contains pointers to the Destination instruction. See also: - Section 17.7,
 166   "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors
 167   based on Goldmont Plus Microarchitecture.".
 168
 169   @param  ECX  MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP (0x000006C0)
 170   @param  EAX  Lower 32-bits of MSR value.
 171   @param  EDX  Upper 32-bits of MSR value.
 172
 173   <b>Example usage</b>
 174   @code
 175   UINT64  Msr;
 176
 177   Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP);
 178   AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP, Msr);
 179   @endcode
 180 **/
 181 #define MSR_GOLDMONT_PLUS_LASTBRANCH_0_TO_IP      0x000006C0
 182 #define MSR_GOLDMONT_PLUS_LASTBRANCH_1_TO_IP      0x000006C1
 183 #define MSR_GOLDMONT_PLUS_LASTBRANCH_2_TO_IP      0x000006C2
 184 #define MSR_GOLDMONT_PLUS_LASTBRANCH_3_TO_IP      0x000006C3
 185 #define MSR_GOLDMONT_PLUS_LASTBRANCH_4_TO_IP      0x000006C4
 186 #define MSR_GOLDMONT_PLUS_LASTBRANCH_5_TO_IP      0x000006C5
 187 #define MSR_GOLDMONT_PLUS_LASTBRANCH_6_TO_IP      0x000006C6
 188 #define MSR_GOLDMONT_PLUS_LASTBRANCH_7_TO_IP      0x000006C7
 189 #define MSR_GOLDMONT_PLUS_LASTBRANCH_8_TO_IP      0x000006C8
 190 #define MSR_GOLDMONT_PLUS_LASTBRANCH_9_TO_IP      0x000006C9
 191 #define MSR_GOLDMONT_PLUS_LASTBRANCH_10_TO_IP     0x000006CA
 192 #define MSR_GOLDMONT_PLUS_LASTBRANCH_11_TO_IP     0x000006CB
 193 #define MSR_GOLDMONT_PLUS_LASTBRANCH_12_TO_IP     0x000006CC
 194 #define MSR_GOLDMONT_PLUS_LASTBRANCH_13_TO_IP     0x000006CD
 195 #define MSR_GOLDMONT_PLUS_LASTBRANCH_14_TO_IP     0x000006CE
 196 #define MSR_GOLDMONT_PLUS_LASTBRANCH_15_TO_IP     0x000006CF
 197 #define MSR_GOLDMONT_PLUS_LASTBRANCH_16_TO_IP     0x000006D0
 198 #define MSR_GOLDMONT_PLUS_LASTBRANCH_17_TO_IP     0x000006D1
 199 #define MSR_GOLDMONT_PLUS_LASTBRANCH_18_TO_IP     0x000006D2
 200 #define MSR_GOLDMONT_PLUS_LASTBRANCH_19_TO_IP     0x000006D3
 201 #define MSR_GOLDMONT_PLUS_LASTBRANCH_20_TO_IP     0x000006D4
 202 #define MSR_GOLDMONT_PLUS_LASTBRANCH_21_TO_IP     0x000006D5
 203 #define MSR_GOLDMONT_PLUS_LASTBRANCH_22_TO_IP     0x000006D6
 204 #define MSR_GOLDMONT_PLUS_LASTBRANCH_23_TO_IP     0x000006D7
 205 #define MSR_GOLDMONT_PLUS_LASTBRANCH_24_TO_IP     0x000006D8
 206 #define MSR_GOLDMONT_PLUS_LASTBRANCH_25_TO_IP     0x000006D9
 207 #define MSR_GOLDMONT_PLUS_LASTBRANCH_26_TO_IP     0x000006DA
 208 #define MSR_GOLDMONT_PLUS_LASTBRANCH_27_TO_IP     0x000006DB
 209 #define MSR_GOLDMONT_PLUS_LASTBRANCH_28_TO_IP     0x000006DC
 210 #define MSR_GOLDMONT_PLUS_LASTBRANCH_29_TO_IP     0x000006DD
 211 #define MSR_GOLDMONT_PLUS_LASTBRANCH_30_TO_IP     0x000006DE
 212 #define MSR_GOLDMONT_PLUS_LASTBRANCH_31_TO_IP     0x000006DF
 213
 214
 215 /**
 216   Core. Last Branch Record N Additional Information (R/W) One of the three
 217   MSRs that make up the first entry of the 32-entry LBR stack. This part of
 218   the stack contains flag and elapsed cycle information. See also: -  Last
 219   Branch Record Stack TOS at 1C9H. -  Section 17.9.1, "LBR Stack.".
 220
 221   @param  ECX  MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N (0x00000DCN)
 222   @param  EAX  Lower 32-bits of MSR value.
 223   @param  EDX  Upper 32-bits of MSR value.
 224
 225   <b>Example usage</b>
 226   @code
 227   UINT64  Msr;
 228
 229   Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N);
 230   AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N, Msr);
 231   @endcode
 232 **/
 233 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_0      0x00000DC0
 234 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_1      0x00000DC1
 235 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_2      0x00000DC2
 236 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_3      0x00000DC3
 237 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_4      0x00000DC4
 238 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_5      0x00000DC5
 239 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_6      0x00000DC6
 240 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_7      0x00000DC7
 241 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_8      0x00000DC8
 242 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_9      0x00000DC9
 243 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_10     0x00000DCA
 244 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_11     0x00000DCB
 245 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_12     0x00000DCC
 246 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_13     0x00000DCD
 247 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_14     0x00000DCE
 248 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_15     0x00000DCF
 249 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_16     0x00000DD0
 250 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_17     0x00000DD1
 251 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_18     0x00000DD2
 252 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_19     0x00000DD3
 253 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_20     0x00000DD4
 254 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_21     0x00000DD5
 255 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_22     0x00000DD6
 256 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_23     0x00000DD7
 257 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_24     0x00000DD8
 258 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_25     0x00000DD9
 259 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_26     0x00000DDA
 260 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_27     0x00000DDB
 261 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_28     0x00000DDC
 262 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_29     0x00000DDD
 263 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_30     0x00000DDE
 264 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_31     0x00000DDF
 265
 266 #endif