UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h

   1 /** @file
   2   MSR Defintions for Intel Atom processors based on the Goldmont Plus microarchitecture.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
  10   This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18   @par Specification Reference:
  19   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
  20   May 2018, Volume 4: Model-Specific-Registers (MSR)
  21
  22 **/
  23
  24 #ifndef __GOLDMONT_PLUS_MSR_H__
  25 #define __GOLDMONT_PLUS_MSR_H__
  26
  27 #include <Register/ArchitecturalMsr.h>
  28
  29 /**
  30   Is Intel Atom processors based on the Goldmont plus microarchitecture?
  31
  32   @param   DisplayFamily  Display Family ID
  33   @param   DisplayModel   Display Model ID
  34
  35   @retval  TRUE   Yes, it is.
  36   @retval  FALSE  No, it isn't.
  37 **/
  38 #define IS_GOLDMONT_PLUS_PROCESSOR(DisplayFamily, DisplayModel) \
  39   (DisplayFamily == 0x06 && \
  40    (                        \
  41     DisplayModel == 0x7A    \
  42     )                       \
  43    )
  44
  45 /**
  46   Core. (R/W) See Table 2-2. See Section 18.6.2.4, "Processor Event Based
  47   Sampling (PEBS).".
  48
  49   @param  ECX  MSR_GOLDMONT_PLUS_PEBS_ENABLE (0x000003F1)
  50   @param  EAX  Lower 32-bits of MSR value.
  51                Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
  52   @param  EDX  Upper 32-bits of MSR value.
  53                Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
  54
  55   <b>Example usage</b>
  56   @code
  57   MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER  Msr;
  58
  59   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE);
  60   AsmWriteMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE, Msr.Uint64);
  61   @endcode
  62 **/
  63 #define MSR_GOLDMONT_PLUS_PEBS_ENABLE            0x000003F1
  64
  65 /**
  66   MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE
  67 **/
  68 typedef union {
  69   ///
  70   /// Individual bit fields
  71   ///
  72   struct {
  73     ///
  74     /// [Bit 0] Enable PEBS trigger and recording for the programmed event
  75     /// (precise or otherwise) on IA32_PMC0.
  76     ///
  77     UINT32  Fix_Me_1:1;
  78     ///
  79     /// [Bit 1] Enable PEBS trigger and recording for the programmed event
  80     /// (precise or otherwise) on IA32_PMC1.
  81     ///
  82     UINT32  Fix_Me_2:1;
  83     ///
  84     /// [Bit 2] Enable PEBS trigger and recording for the programmed event
  85     /// (precise or otherwise) on IA32_PMC2.
  86     ///
  87     UINT32  Fix_Me_3:1;
  88     ///
  89     /// [Bit 3] Enable PEBS trigger and recording for the programmed event
  90     /// (precise or otherwise) on IA32_PMC3.
  91     ///
  92     UINT32  Fix_Me_4:1;
  93     UINT32  Reserved1:28;
  94     ///
  95     /// [Bit 32] Enable PEBS trigger and recording for IA32_FIXED_CTR0.
  96     ///
  97     UINT32  Fix_Me_5:1;
  98     ///
  99     /// [Bit 33] Enable PEBS trigger and recording for IA32_FIXED_CTR1.
 100     ///
 101     UINT32  Fix_Me_6:1;
 102     ///
 103     /// [Bit 34] Enable PEBS trigger and recording for IA32_FIXED_CTR2.
 104     ///
 105     UINT32  Fix_Me_7:1;
 106     UINT32  Reserved2:29;
 107   } Bits;
 108   ///
 109   /// All bit fields as a 64-bit value
 110   ///
 111   UINT64  Uint64;
 112 } MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER;
 113
 114
 115 /**
 116   Core. Last Branch Record N From IP (R/W) One of the three MSRs that make up
 117   the first entry of the 32-entry LBR stack. The From_IP part of the stack
 118   contains pointers to the source instruction. See also: -  Last Branch Record
 119   Stack TOS at 1C9H. -  Section 17.7, "Last Branch, Call Stack, Interrupt, and
 120   .. Exception Recording for Processors based on Goldmont Plus
 121   Microarchitecture.".
 122
 123   @param  ECX  MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP (0x0000068N)
 124   @param  EAX  Lower 32-bits of MSR value.
 125   @param  EDX  Upper 32-bits of MSR value.
 126
 127   <b>Example usage</b>
 128   @code
 129   UINT64  Msr;
 130
 131   Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP);
 132   AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP, Msr);
 133   @endcode
 134 **/
 135 #define MSR_GOLDMONT_PLUS_LASTBRANCH_0_FROM_IP    0x00000680
 136 #define MSR_GOLDMONT_PLUS_LASTBRANCH_1_FROM_IP    0x00000681
 137 #define MSR_GOLDMONT_PLUS_LASTBRANCH_2_FROM_IP    0x00000682
 138 #define MSR_GOLDMONT_PLUS_LASTBRANCH_3_FROM_IP    0x00000683
 139 #define MSR_GOLDMONT_PLUS_LASTBRANCH_4_FROM_IP    0x00000684
 140 #define MSR_GOLDMONT_PLUS_LASTBRANCH_5_FROM_IP    0x00000685
 141 #define MSR_GOLDMONT_PLUS_LASTBRANCH_6_FROM_IP    0x00000686
 142 #define MSR_GOLDMONT_PLUS_LASTBRANCH_7_FROM_IP    0x00000687
 143 #define MSR_GOLDMONT_PLUS_LASTBRANCH_8_FROM_IP    0x00000688
 144 #define MSR_GOLDMONT_PLUS_LASTBRANCH_9_FROM_IP    0x00000689
 145 #define MSR_GOLDMONT_PLUS_LASTBRANCH_10_FROM_IP   0x0000068A
 146 #define MSR_GOLDMONT_PLUS_LASTBRANCH_11_FROM_IP   0x0000068B
 147 #define MSR_GOLDMONT_PLUS_LASTBRANCH_12_FROM_IP   0x0000068C
 148 #define MSR_GOLDMONT_PLUS_LASTBRANCH_13_FROM_IP   0x0000068D
 149 #define MSR_GOLDMONT_PLUS_LASTBRANCH_14_FROM_IP   0x0000068E
 150 #define MSR_GOLDMONT_PLUS_LASTBRANCH_15_FROM_IP   0x0000068F
 151 #define MSR_GOLDMONT_PLUS_LASTBRANCH_16_FROM_IP   0x00000690
 152 #define MSR_GOLDMONT_PLUS_LASTBRANCH_17_FROM_IP   0x00000691
 153 #define MSR_GOLDMONT_PLUS_LASTBRANCH_18_FROM_IP   0x00000692
 154 #define MSR_GOLDMONT_PLUS_LASTBRANCH_19_FROM_IP   0x00000693
 155 #define MSR_GOLDMONT_PLUS_LASTBRANCH_20_FROM_IP   0x00000694
 156 #define MSR_GOLDMONT_PLUS_LASTBRANCH_21_FROM_IP   0x00000695
 157 #define MSR_GOLDMONT_PLUS_LASTBRANCH_22_FROM_IP   0x00000696
 158 #define MSR_GOLDMONT_PLUS_LASTBRANCH_23_FROM_IP   0x00000697
 159 #define MSR_GOLDMONT_PLUS_LASTBRANCH_24_FROM_IP   0x00000698
 160 #define MSR_GOLDMONT_PLUS_LASTBRANCH_25_FROM_IP   0x00000699
 161 #define MSR_GOLDMONT_PLUS_LASTBRANCH_26_FROM_IP   0x0000069A
 162 #define MSR_GOLDMONT_PLUS_LASTBRANCH_27_FROM_IP   0x0000069B
 163 #define MSR_GOLDMONT_PLUS_LASTBRANCH_28_FROM_IP   0x0000069C
 164 #define MSR_GOLDMONT_PLUS_LASTBRANCH_29_FROM_IP   0x0000069D
 165 #define MSR_GOLDMONT_PLUS_LASTBRANCH_30_FROM_IP   0x0000069E
 166 #define MSR_GOLDMONT_PLUS_LASTBRANCH_31_FROM_IP   0x0000069F
 167
 168 /**
 169   Core. Last Branch Record N To IP (R/W) One of the three MSRs that make up
 170   the first entry of the 32-entry LBR stack. The To_IP part of the stack
 171   contains pointers to the Destination instruction. See also: - Section 17.7,
 172   "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors
 173   based on Goldmont Plus Microarchitecture.".
 174
 175   @param  ECX  MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP (0x000006C0)
 176   @param  EAX  Lower 32-bits of MSR value.
 177   @param  EDX  Upper 32-bits of MSR value.
 178
 179   <b>Example usage</b>
 180   @code
 181   UINT64  Msr;
 182
 183   Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP);
 184   AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP, Msr);
 185   @endcode
 186 **/
 187 #define MSR_GOLDMONT_PLUS_LASTBRANCH_0_TO_IP      0x000006C0
 188 #define MSR_GOLDMONT_PLUS_LASTBRANCH_1_TO_IP      0x000006C1
 189 #define MSR_GOLDMONT_PLUS_LASTBRANCH_2_TO_IP      0x000006C2
 190 #define MSR_GOLDMONT_PLUS_LASTBRANCH_3_TO_IP      0x000006C3
 191 #define MSR_GOLDMONT_PLUS_LASTBRANCH_4_TO_IP      0x000006C4
 192 #define MSR_GOLDMONT_PLUS_LASTBRANCH_5_TO_IP      0x000006C5
 193 #define MSR_GOLDMONT_PLUS_LASTBRANCH_6_TO_IP      0x000006C6
 194 #define MSR_GOLDMONT_PLUS_LASTBRANCH_7_TO_IP      0x000006C7
 195 #define MSR_GOLDMONT_PLUS_LASTBRANCH_8_TO_IP      0x000006C8
 196 #define MSR_GOLDMONT_PLUS_LASTBRANCH_9_TO_IP      0x000006C9
 197 #define MSR_GOLDMONT_PLUS_LASTBRANCH_10_TO_IP     0x000006CA
 198 #define MSR_GOLDMONT_PLUS_LASTBRANCH_11_TO_IP     0x000006CB
 199 #define MSR_GOLDMONT_PLUS_LASTBRANCH_12_TO_IP     0x000006CC
 200 #define MSR_GOLDMONT_PLUS_LASTBRANCH_13_TO_IP     0x000006CD
 201 #define MSR_GOLDMONT_PLUS_LASTBRANCH_14_TO_IP     0x000006CE
 202 #define MSR_GOLDMONT_PLUS_LASTBRANCH_15_TO_IP     0x000006CF
 203 #define MSR_GOLDMONT_PLUS_LASTBRANCH_16_TO_IP     0x000006D0
 204 #define MSR_GOLDMONT_PLUS_LASTBRANCH_17_TO_IP     0x000006D1
 205 #define MSR_GOLDMONT_PLUS_LASTBRANCH_18_TO_IP     0x000006D2
 206 #define MSR_GOLDMONT_PLUS_LASTBRANCH_19_TO_IP     0x000006D3
 207 #define MSR_GOLDMONT_PLUS_LASTBRANCH_20_TO_IP     0x000006D4
 208 #define MSR_GOLDMONT_PLUS_LASTBRANCH_21_TO_IP     0x000006D5
 209 #define MSR_GOLDMONT_PLUS_LASTBRANCH_22_TO_IP     0x000006D6
 210 #define MSR_GOLDMONT_PLUS_LASTBRANCH_23_TO_IP     0x000006D7
 211 #define MSR_GOLDMONT_PLUS_LASTBRANCH_24_TO_IP     0x000006D8
 212 #define MSR_GOLDMONT_PLUS_LASTBRANCH_25_TO_IP     0x000006D9
 213 #define MSR_GOLDMONT_PLUS_LASTBRANCH_26_TO_IP     0x000006DA
 214 #define MSR_GOLDMONT_PLUS_LASTBRANCH_27_TO_IP     0x000006DB
 215 #define MSR_GOLDMONT_PLUS_LASTBRANCH_28_TO_IP     0x000006DC
 216 #define MSR_GOLDMONT_PLUS_LASTBRANCH_29_TO_IP     0x000006DD
 217 #define MSR_GOLDMONT_PLUS_LASTBRANCH_30_TO_IP     0x000006DE
 218 #define MSR_GOLDMONT_PLUS_LASTBRANCH_31_TO_IP     0x000006DF
 219
 220
 221 /**
 222   Core. Last Branch Record N Additional Information (R/W) One of the three
 223   MSRs that make up the first entry of the 32-entry LBR stack. This part of
 224   the stack contains flag and elapsed cycle information. See also: -  Last
 225   Branch Record Stack TOS at 1C9H. -  Section 17.9.1, "LBR Stack.".
 226
 227   @param  ECX  MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N (0x00000DCN)
 228   @param  EAX  Lower 32-bits of MSR value.
 229   @param  EDX  Upper 32-bits of MSR value.
 230
 231   <b>Example usage</b>
 232   @code
 233   UINT64  Msr;
 234
 235   Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N);
 236   AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N, Msr);
 237   @endcode
 238 **/
 239 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_0      0x00000DC0
 240 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_1      0x00000DC1
 241 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_2      0x00000DC2
 242 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_3      0x00000DC3
 243 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_4      0x00000DC4
 244 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_5      0x00000DC5
 245 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_6      0x00000DC6
 246 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_7      0x00000DC7
 247 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_8      0x00000DC8
 248 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_9      0x00000DC9
 249 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_10     0x00000DCA
 250 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_11     0x00000DCB
 251 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_12     0x00000DCC
 252 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_13     0x00000DCD
 253 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_14     0x00000DCE
 254 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_15     0x00000DCF
 255 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_16     0x00000DD0
 256 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_17     0x00000DD1
 257 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_18     0x00000DD2
 258 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_19     0x00000DD3
 259 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_20     0x00000DD4
 260 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_21     0x00000DD5
 261 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_22     0x00000DD6
 262 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_23     0x00000DD7
 263 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_24     0x00000DD8
 264 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_25     0x00000DD9
 265 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_26     0x00000DDA
 266 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_27     0x00000DDB
 267 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_28     0x00000DDC
 268 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_29     0x00000DDD
 269 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_30     0x00000DDE
 270 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_31     0x00000DDF
 271
 272 #endif