2 MSR Definitions for Intel processors based on the Haswell-E microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __HASWELL_E_MSR_H__
19 #define __HASWELL_E_MSR_H__
21 #include <Register/ArchitecturalMsr.h>
24 Is Intel processors based on the Haswell-E microarchitecture?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
35 DisplayModel == 0x3F \
40 Package. Configured State of Enabled Processor Core Count and Logical
41 Processor Count (RO) - After a Power-On RESET, enumerates factory
42 configuration of the number of processor cores and logical processors in the
43 physical package. - Following the sequence of (i) BIOS modified a
44 Configuration Mask which selects a subset of processor cores to be active
45 post RESET and (ii) a RESET event after the modification, enumerates the
46 current configuration of enabled processor core count and logical processor
47 count in the physical package.
49 @param ECX MSR_HASWELL_E_CORE_THREAD_COUNT (0x00000035)
50 @param EAX Lower 32-bits of MSR value.
51 Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.
52 @param EDX Upper 32-bits of MSR value.
53 Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.
57 MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER Msr;
59 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_THREAD_COUNT);
61 @note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.
63 #define MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035
66 MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT
70 /// Individual bit fields
74 /// [Bits 15:0] Core_COUNT (RO) The number of processor cores that are
75 /// currently enabled (by either factory configuration or BIOS
76 /// configuration) in the physical package.
80 /// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that
81 /// are currently enabled (by either factory configuration or BIOS
82 /// configuration) in the physical package.
84 UINT32 Thread_Count
:16;
88 /// All bit fields as a 32-bit value
92 /// All bit fields as a 64-bit value
95 } MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER
;
99 Thread. A Hardware Assigned ID for the Logical Processor (RO).
101 @param ECX MSR_HASWELL_E_THREAD_ID_INFO (0x00000053)
102 @param EAX Lower 32-bits of MSR value.
103 Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.
104 @param EDX Upper 32-bits of MSR value.
105 Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.
109 MSR_HASWELL_E_THREAD_ID_INFO_REGISTER Msr;
111 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_THREAD_ID_INFO);
113 @note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.
115 #define MSR_HASWELL_E_THREAD_ID_INFO 0x00000053
118 MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO
122 /// Individual bit fields
126 /// [Bits 7:0] Logical_Processor_ID (RO) An implementation-specific
127 /// numerical. value physically assigned to each logical processor. This
128 /// ID is not related to Initial APIC ID or x2APIC ID, it is unique within
129 /// a physical package.
131 UINT32 Logical_Processor_ID
:8;
136 /// All bit fields as a 32-bit value
140 /// All bit fields as a 64-bit value
143 } MSR_HASWELL_E_THREAD_ID_INFO_REGISTER
;
147 Core. C-State Configuration Control (R/W) Note: C-state values are processor
148 specific C-state code names, unrelated to MWAIT extension C-state parameters
149 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
151 @param ECX MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2)
152 @param EAX Lower 32-bits of MSR value.
153 Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
154 @param EDX Upper 32-bits of MSR value.
155 Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
159 MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
161 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);
162 AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
164 @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
166 #define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2
169 MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL
173 /// Individual bit fields
177 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
178 /// processor-specific C-state code name (consuming the least power) for
179 /// the package. The default is set as factory-configured package C-state
180 /// limit. The following C-state code name encodings are supported: 000b:
181 /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
182 /// 011b: C6 (retention) 111b: No Package C state limits. All C states
183 /// supported by the processor are available.
188 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
193 /// [Bit 15] CFG Lock (R/WO).
198 /// [Bit 25] C3 State Auto Demotion Enable (R/W).
200 UINT32 C3AutoDemotion
:1;
202 /// [Bit 26] C1 State Auto Demotion Enable (R/W).
204 UINT32 C1AutoDemotion
:1;
206 /// [Bit 27] Enable C3 Undemotion (R/W).
208 UINT32 C3Undemotion
:1;
210 /// [Bit 28] Enable C1 Undemotion (R/W).
212 UINT32 C1Undemotion
:1;
214 /// [Bit 29] Package C State Demotion Enable (R/W).
216 UINT32 CStateDemotion
:1;
218 /// [Bit 30] Package C State UnDemotion Enable (R/W).
220 UINT32 CStateUndemotion
:1;
225 /// All bit fields as a 32-bit value
229 /// All bit fields as a 64-bit value
232 } MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER
;
236 Thread. Global Machine Check Capability (R/O).
238 @param ECX MSR_HASWELL_E_IA32_MCG_CAP (0x00000179)
239 @param EAX Lower 32-bits of MSR value.
240 Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
241 @param EDX Upper 32-bits of MSR value.
242 Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
246 MSR_HASWELL_E_IA32_MCG_CAP_REGISTER Msr;
248 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);
250 @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
252 #define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179
255 MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP
259 /// Individual bit fields
263 /// [Bits 7:0] Count.
267 /// [Bit 8] MCG_CTL_P.
271 /// [Bit 9] MCG_EXT_P.
275 /// [Bit 10] MCP_CMCI_P.
279 /// [Bit 11] MCG_TES_P.
284 /// [Bits 23:16] MCG_EXT_CNT.
286 UINT32 MCG_EXT_CNT
:8;
288 /// [Bit 24] MCG_SER_P.
292 /// [Bit 25] MCG_EM_P.
296 /// [Bit 26] MCG_ELOG_P.
303 /// All bit fields as a 32-bit value
307 /// All bit fields as a 64-bit value
310 } MSR_HASWELL_E_IA32_MCG_CAP_REGISTER
;
314 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
315 Enhancement. Accessible only while in SMM.
317 @param ECX MSR_HASWELL_E_SMM_MCA_CAP (0x0000017D)
318 @param EAX Lower 32-bits of MSR value.
319 Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
320 @param EDX Upper 32-bits of MSR value.
321 Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
325 MSR_HASWELL_E_SMM_MCA_CAP_REGISTER Msr;
327 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);
328 AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);
330 @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
332 #define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D
335 MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP
339 /// Individual bit fields
345 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
346 /// SMM code access restriction is supported and a host-space interface
347 /// available to SMM handler.
349 UINT32 SMM_Code_Access_Chk
:1;
351 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
352 /// SMM long flow indicator is supported and a host-space interface
353 /// available to SMM handler.
355 UINT32 Long_Flow_Indication
:1;
359 /// All bit fields as a 64-bit value
362 } MSR_HASWELL_E_SMM_MCA_CAP_REGISTER
;
366 Package. MC Bank Error Configuration (R/W).
368 @param ECX MSR_HASWELL_E_ERROR_CONTROL (0x0000017F)
369 @param EAX Lower 32-bits of MSR value.
370 Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
371 @param EDX Upper 32-bits of MSR value.
372 Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
376 MSR_HASWELL_E_ERROR_CONTROL_REGISTER Msr;
378 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);
379 AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);
381 @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
383 #define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F
386 MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL
390 /// Individual bit fields
395 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
396 /// to log additional info in bits 36:32.
398 UINT32 MemErrorLogEnable
:1;
403 /// All bit fields as a 32-bit value
407 /// All bit fields as a 64-bit value
410 } MSR_HASWELL_E_ERROR_CONTROL_REGISTER
;
414 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
415 RW if MSR_PLATFORM_INFO.[28] = 1.
417 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD)
418 @param EAX Lower 32-bits of MSR value.
419 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
420 @param EDX Upper 32-bits of MSR value.
421 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
425 MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER Msr;
427 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);
429 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
431 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD
434 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT
438 /// Individual bit fields
442 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
443 /// limit of 1 core active.
447 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
448 /// limit of 2 core active.
452 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
453 /// limit of 3 core active.
457 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
458 /// limit of 4 core active.
462 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
463 /// limit of 5 core active.
467 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
468 /// limit of 6 core active.
472 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
473 /// limit of 7 core active.
477 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
478 /// limit of 8 core active.
483 /// All bit fields as a 64-bit value
486 } MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER
;
490 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
491 RW if MSR_PLATFORM_INFO.[28] = 1.
493 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE)
494 @param EAX Lower 32-bits of MSR value.
495 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
496 @param EDX Upper 32-bits of MSR value.
497 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
501 MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER Msr;
503 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);
505 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
507 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE
510 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1
514 /// Individual bit fields
518 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
519 /// limit of 9 core active.
523 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
524 /// limit of 10 core active.
528 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
529 /// limit of 11 core active.
533 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
534 /// limit of 12 core active.
538 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
539 /// limit of 13 core active.
543 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
544 /// limit of 14 core active.
548 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
549 /// limit of 15 core active.
553 /// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio
554 /// limit of 16 core active.
559 /// All bit fields as a 64-bit value
562 } MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER
;
566 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
567 RW if MSR_PLATFORM_INFO.[28] = 1.
569 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF)
570 @param EAX Lower 32-bits of MSR value.
571 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
572 @param EDX Upper 32-bits of MSR value.
573 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
577 MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER Msr;
579 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);
581 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.
583 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF
586 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2
590 /// Individual bit fields
594 /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio
595 /// limit of 17 core active.
599 /// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio
600 /// limit of 18 core active.
606 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
607 /// the processor uses override configuration specified in
608 /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and
609 /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set
610 /// configuration (Default).
612 UINT32 TurboRatioLimitConfigurationSemaphore
:1;
615 /// All bit fields as a 64-bit value
618 } MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER
;
622 Package. Unit Multipliers used in RAPL Interfaces (R/O).
624 @param ECX MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606)
625 @param EAX Lower 32-bits of MSR value.
626 Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
627 @param EDX Upper 32-bits of MSR value.
628 Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
632 MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER Msr;
634 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT);
636 @note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
638 #define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606
641 MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT
645 /// Individual bit fields
649 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
654 /// [Bits 12:8] Package. Energy Status Units Energy related information
655 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
656 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
659 UINT32 EnergyStatusUnits
:5;
662 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
670 /// All bit fields as a 32-bit value
674 /// All bit fields as a 64-bit value
677 } MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER
;
681 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
684 @param ECX MSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618)
685 @param EAX Lower 32-bits of MSR value.
686 @param EDX Upper 32-bits of MSR value.
692 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT);
693 AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr);
695 @note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
697 #define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618
701 Package. DRAM Energy Status (R/O) Energy Consumed by DRAM devices.
703 @param ECX MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)
704 @param EAX Lower 32-bits of MSR value.
705 Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.
706 @param EDX Upper 32-bits of MSR value.
707 Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.
711 MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER Msr;
713 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);
715 @note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
717 #define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619
720 MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS
724 /// Individual bit fields
728 /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
729 /// to enable DRAM RAPL mode 0 (Direct VR).
735 /// All bit fields as a 32-bit value
739 /// All bit fields as a 64-bit value
742 } MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER
;
746 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
749 @param ECX MSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B)
750 @param EAX Lower 32-bits of MSR value.
751 @param EDX Upper 32-bits of MSR value.
757 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS);
759 @note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
761 #define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B
765 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
767 @param ECX MSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C)
768 @param EAX Lower 32-bits of MSR value.
769 @param EDX Upper 32-bits of MSR value.
775 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO);
776 AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr);
778 @note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
780 #define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C
784 Package. Configuration of PCIE PLL Relative to BCLK(R/W).
786 @param ECX MSR_HASWELL_E_PCIE_PLL_RATIO (0x0000061E)
787 @param EAX Lower 32-bits of MSR value.
788 Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.
789 @param EDX Upper 32-bits of MSR value.
790 Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.
794 MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER Msr;
796 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO);
797 AsmWriteMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO, Msr.Uint64);
799 @note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.
801 #define MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E
804 MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO
808 /// Individual bit fields
812 /// [Bits 1:0] Package. PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz
813 /// operation (default) 01b: Use 5:4 mapping for125MHz operation 10b: Use
814 /// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz
819 /// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of
824 /// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out
825 /// before re-locking Gen2/Gen3 PLLs.
832 /// All bit fields as a 32-bit value
836 /// All bit fields as a 64-bit value
839 } MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER
;
843 Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
844 fields represent the widest possible range of uncore frequencies. Writing to
845 these fields allows software to control the minimum and the maximum
846 frequency that hardware will select.
848 @param ECX MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT (0x00000620)
849 @param EAX Lower 32-bits of MSR value.
850 Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
851 @param EDX Upper 32-bits of MSR value.
852 Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
856 MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
858 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT);
859 AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
862 #define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT 0x00000620
865 MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT
869 /// Individual bit fields
873 /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
879 /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
880 /// possible ratio of the LLC/Ring.
887 /// All bit fields as a 32-bit value
891 /// All bit fields as a 64-bit value
894 } MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER
;
897 Package. Reserved (R/O) Reads return 0.
899 @param ECX MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639)
900 @param EAX Lower 32-bits of MSR value.
901 @param EDX Upper 32-bits of MSR value.
907 Msr = AsmReadMsr64 (MSR_HASWELL_E_PP0_ENERGY_STATUS);
909 @note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
911 #define MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639
915 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
916 refers to processor core frequency).
918 @param ECX MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690)
919 @param EAX Lower 32-bits of MSR value.
920 Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
921 @param EDX Upper 32-bits of MSR value.
922 Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
926 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
928 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS);
929 AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
931 @note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
933 #define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690
936 MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS
940 /// Individual bit fields
944 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
945 /// reduced below the operating system request due to assertion of
946 /// external PROCHOT.
948 UINT32 PROCHOT_Status
:1;
950 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
951 /// operating system request due to a thermal event.
953 UINT32 ThermalStatus
:1;
955 /// [Bit 2] Power Budget Management Status (R0) When set, frequency is
956 /// reduced below the operating system request due to PBM limit.
958 UINT32 PowerBudgetManagementStatus
:1;
960 /// [Bit 3] Platform Configuration Services Status (R0) When set,
961 /// frequency is reduced below the operating system request due to PCS
964 UINT32 PlatformConfigurationServicesStatus
:1;
967 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
968 /// When set, frequency is reduced below the operating system request
969 /// because the processor has detected that utilization is low.
971 UINT32 AutonomousUtilizationBasedFrequencyControlStatus
:1;
973 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
974 /// below the operating system request due to a thermal alert from the
975 /// Voltage Regulator.
977 UINT32 VRThermAlertStatus
:1;
980 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
981 /// reduced below the operating system request due to electrical design
982 /// point constraints (e.g. maximum electrical current consumption).
984 UINT32 ElectricalDesignPointStatus
:1;
987 /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced
988 /// below the operating system request due to Multi-Core Turbo limits.
990 UINT32 MultiCoreTurboStatus
:1;
993 /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced
994 /// below max non-turbo P1.
996 UINT32 FrequencyP1Status
:1;
998 /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When
999 /// set, frequency is reduced below max n-core turbo frequency.
1001 UINT32 TurboFrequencyLimitingStatus
:1;
1003 /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is
1004 /// reduced below the operating system request.
1006 UINT32 FrequencyLimitingStatus
:1;
1008 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
1009 /// has asserted since the log bit was last cleared. This log bit will
1010 /// remain set until cleared by software writing 0.
1012 UINT32 PROCHOT_Log
:1;
1014 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
1015 /// has asserted since the log bit was last cleared. This log bit will
1016 /// remain set until cleared by software writing 0.
1018 UINT32 ThermalLog
:1;
1020 /// [Bit 18] Power Budget Management Log When set, indicates that the PBM
1021 /// Status bit has asserted since the log bit was last cleared. This log
1022 /// bit will remain set until cleared by software writing 0.
1024 UINT32 PowerBudgetManagementLog
:1;
1026 /// [Bit 19] Platform Configuration Services Log When set, indicates that
1027 /// the PCS Status bit has asserted since the log bit was last cleared.
1028 /// This log bit will remain set until cleared by software writing 0.
1030 UINT32 PlatformConfigurationServicesLog
:1;
1033 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
1034 /// indicates that the AUBFC Status bit has asserted since the log bit was
1035 /// last cleared. This log bit will remain set until cleared by software
1038 UINT32 AutonomousUtilizationBasedFrequencyControlLog
:1;
1040 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
1041 /// Alert Status bit has asserted since the log bit was last cleared. This
1042 /// log bit will remain set until cleared by software writing 0.
1044 UINT32 VRThermAlertLog
:1;
1047 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
1048 /// Status bit has asserted since the log bit was last cleared. This log
1049 /// bit will remain set until cleared by software writing 0.
1051 UINT32 ElectricalDesignPointLog
:1;
1054 /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core
1055 /// Turbo Status bit has asserted since the log bit was last cleared. This
1056 /// log bit will remain set until cleared by software writing 0.
1058 UINT32 MultiCoreTurboLog
:1;
1061 /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core
1062 /// Frequency P1 Status bit has asserted since the log bit was last
1063 /// cleared. This log bit will remain set until cleared by software
1066 UINT32 CoreFrequencyP1Log
:1;
1068 /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,
1069 /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit
1070 /// has asserted since the log bit was last cleared. This log bit will
1071 /// remain set until cleared by software writing 0.
1073 UINT32 TurboFrequencyLimitingLog
:1;
1075 /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core
1076 /// Frequency Limiting Status bit has asserted since the log bit was last
1077 /// cleared. This log bit will remain set until cleared by software
1080 UINT32 CoreFrequencyLimitingLog
:1;
1081 UINT32 Reserved9
:32;
1084 /// All bit fields as a 32-bit value
1088 /// All bit fields as a 64-bit value
1091 } MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER
;
1095 THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,
1096 ECX=0):EBX.RDT-M[bit 12] = 1.
1098 @param ECX MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)
1099 @param EAX Lower 32-bits of MSR value.
1100 Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
1101 @param EDX Upper 32-bits of MSR value.
1102 Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
1104 <b>Example usage</b>
1106 MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER Msr;
1108 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL);
1109 AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64);
1111 @note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
1113 #define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D
1116 MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL
1120 /// Individual bit fields
1124 /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3
1125 /// occupancy monitoring all other encoding reserved..
1128 UINT32 Reserved1
:24;
1130 /// [Bits 41:32] RMID (RW).
1133 UINT32 Reserved2
:22;
1136 /// All bit fields as a 64-bit value
1139 } MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER
;
1143 THREAD. Resource Association Register (R/W)..
1145 @param ECX MSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F)
1146 @param EAX Lower 32-bits of MSR value.
1147 Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
1148 @param EDX Upper 32-bits of MSR value.
1149 Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
1151 <b>Example usage</b>
1153 MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER Msr;
1155 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC);
1156 AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64);
1158 @note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
1160 #define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F
1163 MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC
1167 /// Individual bit fields
1171 /// [Bits 9:0] RMID.
1174 UINT32 Reserved1
:22;
1175 UINT32 Reserved2
:32;
1178 /// All bit fields as a 32-bit value
1182 /// All bit fields as a 64-bit value
1185 } MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER
;
1189 Package. Uncore perfmon per-socket global control.
1191 @param ECX MSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700)
1192 @param EAX Lower 32-bits of MSR value.
1193 @param EDX Upper 32-bits of MSR value.
1195 <b>Example usage</b>
1199 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL);
1200 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr);
1202 @note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.
1204 #define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700
1208 Package. Uncore perfmon per-socket global status.
1210 @param ECX MSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701)
1211 @param EAX Lower 32-bits of MSR value.
1212 @param EDX Upper 32-bits of MSR value.
1214 <b>Example usage</b>
1218 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS);
1219 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr);
1221 @note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.
1223 #define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701
1227 Package. Uncore perfmon per-socket global configuration.
1229 @param ECX MSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702)
1230 @param EAX Lower 32-bits of MSR value.
1231 @param EDX Upper 32-bits of MSR value.
1233 <b>Example usage</b>
1237 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG);
1238 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr);
1240 @note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.
1242 #define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702
1246 Package. Uncore U-box UCLK fixed counter control.
1248 @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703)
1249 @param EAX Lower 32-bits of MSR value.
1250 @param EDX Upper 32-bits of MSR value.
1252 <b>Example usage</b>
1256 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL);
1257 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr);
1259 @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.
1261 #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703
1265 Package. Uncore U-box UCLK fixed counter.
1267 @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704)
1268 @param EAX Lower 32-bits of MSR value.
1269 @param EDX Upper 32-bits of MSR value.
1271 <b>Example usage</b>
1275 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR);
1276 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr);
1278 @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.
1280 #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704
1284 Package. Uncore U-box perfmon event select for U-box counter 0.
1286 @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705)
1287 @param EAX Lower 32-bits of MSR value.
1288 @param EDX Upper 32-bits of MSR value.
1290 <b>Example usage</b>
1294 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0);
1295 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr);
1297 @note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.
1299 #define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705
1303 Package. Uncore U-box perfmon event select for U-box counter 1.
1305 @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706)
1306 @param EAX Lower 32-bits of MSR value.
1307 @param EDX Upper 32-bits of MSR value.
1309 <b>Example usage</b>
1313 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1);
1314 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr);
1316 @note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.
1318 #define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706
1322 Package. Uncore U-box perfmon U-box wide status.
1324 @param ECX MSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708)
1325 @param EAX Lower 32-bits of MSR value.
1326 @param EDX Upper 32-bits of MSR value.
1328 <b>Example usage</b>
1332 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS);
1333 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr);
1335 @note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.
1337 #define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708
1341 Package. Uncore U-box perfmon counter 0.
1343 @param ECX MSR_HASWELL_E_U_PMON_CTR0 (0x00000709)
1344 @param EAX Lower 32-bits of MSR value.
1345 @param EDX Upper 32-bits of MSR value.
1347 <b>Example usage</b>
1351 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0);
1352 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr);
1354 @note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.
1356 #define MSR_HASWELL_E_U_PMON_CTR0 0x00000709
1360 Package. Uncore U-box perfmon counter 1.
1362 @param ECX MSR_HASWELL_E_U_PMON_CTR1 (0x0000070A)
1363 @param EAX Lower 32-bits of MSR value.
1364 @param EDX Upper 32-bits of MSR value.
1366 <b>Example usage</b>
1370 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1);
1371 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr);
1373 @note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.
1375 #define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A
1379 Package. Uncore PCU perfmon for PCU-box-wide control.
1381 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710)
1382 @param EAX Lower 32-bits of MSR value.
1383 @param EDX Upper 32-bits of MSR value.
1385 <b>Example usage</b>
1389 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL);
1390 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr);
1392 @note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.
1394 #define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710
1398 Package. Uncore PCU perfmon event select for PCU counter 0.
1400 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711)
1401 @param EAX Lower 32-bits of MSR value.
1402 @param EDX Upper 32-bits of MSR value.
1404 <b>Example usage</b>
1408 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0);
1409 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr);
1411 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.
1413 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711
1417 Package. Uncore PCU perfmon event select for PCU counter 1.
1419 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712)
1420 @param EAX Lower 32-bits of MSR value.
1421 @param EDX Upper 32-bits of MSR value.
1423 <b>Example usage</b>
1427 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1);
1428 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr);
1430 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.
1432 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712
1436 Package. Uncore PCU perfmon event select for PCU counter 2.
1438 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713)
1439 @param EAX Lower 32-bits of MSR value.
1440 @param EDX Upper 32-bits of MSR value.
1442 <b>Example usage</b>
1446 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2);
1447 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr);
1449 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.
1451 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713
1455 Package. Uncore PCU perfmon event select for PCU counter 3.
1457 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714)
1458 @param EAX Lower 32-bits of MSR value.
1459 @param EDX Upper 32-bits of MSR value.
1461 <b>Example usage</b>
1465 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3);
1466 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr);
1468 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.
1470 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714
1474 Package. Uncore PCU perfmon box-wide filter.
1476 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715)
1477 @param EAX Lower 32-bits of MSR value.
1478 @param EDX Upper 32-bits of MSR value.
1480 <b>Example usage</b>
1484 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER);
1485 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr);
1487 @note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.
1489 #define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715
1493 Package. Uncore PCU perfmon box wide status.
1495 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716)
1496 @param EAX Lower 32-bits of MSR value.
1497 @param EDX Upper 32-bits of MSR value.
1499 <b>Example usage</b>
1503 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS);
1504 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr);
1506 @note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.
1508 #define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716
1512 Package. Uncore PCU perfmon counter 0.
1514 @param ECX MSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717)
1515 @param EAX Lower 32-bits of MSR value.
1516 @param EDX Upper 32-bits of MSR value.
1518 <b>Example usage</b>
1522 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0);
1523 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr);
1525 @note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.
1527 #define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717
1531 Package. Uncore PCU perfmon counter 1.
1533 @param ECX MSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718)
1534 @param EAX Lower 32-bits of MSR value.
1535 @param EDX Upper 32-bits of MSR value.
1537 <b>Example usage</b>
1541 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1);
1542 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr);
1544 @note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.
1546 #define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718
1550 Package. Uncore PCU perfmon counter 2.
1552 @param ECX MSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719)
1553 @param EAX Lower 32-bits of MSR value.
1554 @param EDX Upper 32-bits of MSR value.
1556 <b>Example usage</b>
1560 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2);
1561 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr);
1563 @note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.
1565 #define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719
1569 Package. Uncore PCU perfmon counter 3.
1571 @param ECX MSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A)
1572 @param EAX Lower 32-bits of MSR value.
1573 @param EDX Upper 32-bits of MSR value.
1575 <b>Example usage</b>
1579 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3);
1580 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr);
1582 @note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.
1584 #define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A
1588 Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.
1590 @param ECX MSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720)
1591 @param EAX Lower 32-bits of MSR value.
1592 @param EDX Upper 32-bits of MSR value.
1594 <b>Example usage</b>
1598 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL);
1599 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr);
1601 @note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.
1603 #define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720
1607 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.
1609 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721)
1610 @param EAX Lower 32-bits of MSR value.
1611 @param EDX Upper 32-bits of MSR value.
1613 <b>Example usage</b>
1617 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0);
1618 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr);
1620 @note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.
1622 #define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721
1626 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.
1628 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722)
1629 @param EAX Lower 32-bits of MSR value.
1630 @param EDX Upper 32-bits of MSR value.
1632 <b>Example usage</b>
1636 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1);
1637 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr);
1639 @note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.
1641 #define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722
1645 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.
1647 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723)
1648 @param EAX Lower 32-bits of MSR value.
1649 @param EDX Upper 32-bits of MSR value.
1651 <b>Example usage</b>
1655 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2);
1656 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr);
1658 @note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.
1660 #define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723
1664 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.
1666 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724)
1667 @param EAX Lower 32-bits of MSR value.
1668 @param EDX Upper 32-bits of MSR value.
1670 <b>Example usage</b>
1674 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3);
1675 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr);
1677 @note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.
1679 #define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724
1683 Package. Uncore SBo 0 perfmon box-wide filter.
1685 @param ECX MSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725)
1686 @param EAX Lower 32-bits of MSR value.
1687 @param EDX Upper 32-bits of MSR value.
1689 <b>Example usage</b>
1693 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER);
1694 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr);
1696 @note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.
1698 #define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725
1702 Package. Uncore SBo 0 perfmon counter 0.
1704 @param ECX MSR_HASWELL_E_S0_PMON_CTR0 (0x00000726)
1705 @param EAX Lower 32-bits of MSR value.
1706 @param EDX Upper 32-bits of MSR value.
1708 <b>Example usage</b>
1712 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0);
1713 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr);
1715 @note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.
1717 #define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726
1721 Package. Uncore SBo 0 perfmon counter 1.
1723 @param ECX MSR_HASWELL_E_S0_PMON_CTR1 (0x00000727)
1724 @param EAX Lower 32-bits of MSR value.
1725 @param EDX Upper 32-bits of MSR value.
1727 <b>Example usage</b>
1731 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1);
1732 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr);
1734 @note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.
1736 #define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727
1740 Package. Uncore SBo 0 perfmon counter 2.
1742 @param ECX MSR_HASWELL_E_S0_PMON_CTR2 (0x00000728)
1743 @param EAX Lower 32-bits of MSR value.
1744 @param EDX Upper 32-bits of MSR value.
1746 <b>Example usage</b>
1750 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2);
1751 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr);
1753 @note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.
1755 #define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728
1759 Package. Uncore SBo 0 perfmon counter 3.
1761 @param ECX MSR_HASWELL_E_S0_PMON_CTR3 (0x00000729)
1762 @param EAX Lower 32-bits of MSR value.
1763 @param EDX Upper 32-bits of MSR value.
1765 <b>Example usage</b>
1769 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3);
1770 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr);
1772 @note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.
1774 #define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729
1778 Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.
1780 @param ECX MSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A)
1781 @param EAX Lower 32-bits of MSR value.
1782 @param EDX Upper 32-bits of MSR value.
1784 <b>Example usage</b>
1788 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL);
1789 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr);
1791 @note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.
1793 #define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A
1797 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.
1799 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B)
1800 @param EAX Lower 32-bits of MSR value.
1801 @param EDX Upper 32-bits of MSR value.
1803 <b>Example usage</b>
1807 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0);
1808 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr);
1810 @note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.
1812 #define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B
1816 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.
1818 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C)
1819 @param EAX Lower 32-bits of MSR value.
1820 @param EDX Upper 32-bits of MSR value.
1822 <b>Example usage</b>
1826 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1);
1827 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr);
1829 @note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.
1831 #define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C
1835 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.
1837 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D)
1838 @param EAX Lower 32-bits of MSR value.
1839 @param EDX Upper 32-bits of MSR value.
1841 <b>Example usage</b>
1845 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2);
1846 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr);
1848 @note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.
1850 #define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D
1854 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.
1856 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E)
1857 @param EAX Lower 32-bits of MSR value.
1858 @param EDX Upper 32-bits of MSR value.
1860 <b>Example usage</b>
1864 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3);
1865 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr);
1867 @note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.
1869 #define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E
1873 Package. Uncore SBo 1 perfmon box-wide filter.
1875 @param ECX MSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F)
1876 @param EAX Lower 32-bits of MSR value.
1877 @param EDX Upper 32-bits of MSR value.
1879 <b>Example usage</b>
1883 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER);
1884 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr);
1886 @note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.
1888 #define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F
1892 Package. Uncore SBo 1 perfmon counter 0.
1894 @param ECX MSR_HASWELL_E_S1_PMON_CTR0 (0x00000730)
1895 @param EAX Lower 32-bits of MSR value.
1896 @param EDX Upper 32-bits of MSR value.
1898 <b>Example usage</b>
1902 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0);
1903 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr);
1905 @note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.
1907 #define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730
1911 Package. Uncore SBo 1 perfmon counter 1.
1913 @param ECX MSR_HASWELL_E_S1_PMON_CTR1 (0x00000731)
1914 @param EAX Lower 32-bits of MSR value.
1915 @param EDX Upper 32-bits of MSR value.
1917 <b>Example usage</b>
1921 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1);
1922 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr);
1924 @note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.
1926 #define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731
1930 Package. Uncore SBo 1 perfmon counter 2.
1932 @param ECX MSR_HASWELL_E_S1_PMON_CTR2 (0x00000732)
1933 @param EAX Lower 32-bits of MSR value.
1934 @param EDX Upper 32-bits of MSR value.
1936 <b>Example usage</b>
1940 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2);
1941 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr);
1943 @note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.
1945 #define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732
1949 Package. Uncore SBo 1 perfmon counter 3.
1951 @param ECX MSR_HASWELL_E_S1_PMON_CTR3 (0x00000733)
1952 @param EAX Lower 32-bits of MSR value.
1953 @param EDX Upper 32-bits of MSR value.
1955 <b>Example usage</b>
1959 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3);
1960 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr);
1962 @note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.
1964 #define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733
1968 Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.
1970 @param ECX MSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734)
1971 @param EAX Lower 32-bits of MSR value.
1972 @param EDX Upper 32-bits of MSR value.
1974 <b>Example usage</b>
1978 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL);
1979 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr);
1981 @note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.
1983 #define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734
1987 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.
1989 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735)
1990 @param EAX Lower 32-bits of MSR value.
1991 @param EDX Upper 32-bits of MSR value.
1993 <b>Example usage</b>
1997 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0);
1998 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr);
2000 @note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.
2002 #define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735
2006 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.
2008 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736)
2009 @param EAX Lower 32-bits of MSR value.
2010 @param EDX Upper 32-bits of MSR value.
2012 <b>Example usage</b>
2016 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1);
2017 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr);
2019 @note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.
2021 #define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736
2025 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.
2027 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737)
2028 @param EAX Lower 32-bits of MSR value.
2029 @param EDX Upper 32-bits of MSR value.
2031 <b>Example usage</b>
2035 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2);
2036 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr);
2038 @note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.
2040 #define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737
2044 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.
2046 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738)
2047 @param EAX Lower 32-bits of MSR value.
2048 @param EDX Upper 32-bits of MSR value.
2050 <b>Example usage</b>
2054 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3);
2055 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr);
2057 @note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.
2059 #define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738
2063 Package. Uncore SBo 2 perfmon box-wide filter.
2065 @param ECX MSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739)
2066 @param EAX Lower 32-bits of MSR value.
2067 @param EDX Upper 32-bits of MSR value.
2069 <b>Example usage</b>
2073 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER);
2074 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr);
2076 @note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.
2078 #define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739
2082 Package. Uncore SBo 2 perfmon counter 0.
2084 @param ECX MSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A)
2085 @param EAX Lower 32-bits of MSR value.
2086 @param EDX Upper 32-bits of MSR value.
2088 <b>Example usage</b>
2092 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0);
2093 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr);
2095 @note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.
2097 #define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A
2101 Package. Uncore SBo 2 perfmon counter 1.
2103 @param ECX MSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B)
2104 @param EAX Lower 32-bits of MSR value.
2105 @param EDX Upper 32-bits of MSR value.
2107 <b>Example usage</b>
2111 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1);
2112 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr);
2114 @note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.
2116 #define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B
2120 Package. Uncore SBo 2 perfmon counter 2.
2122 @param ECX MSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C)
2123 @param EAX Lower 32-bits of MSR value.
2124 @param EDX Upper 32-bits of MSR value.
2126 <b>Example usage</b>
2130 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2);
2131 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr);
2133 @note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.
2135 #define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C
2139 Package. Uncore SBo 2 perfmon counter 3.
2141 @param ECX MSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D)
2142 @param EAX Lower 32-bits of MSR value.
2143 @param EDX Upper 32-bits of MSR value.
2145 <b>Example usage</b>
2149 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3);
2150 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr);
2152 @note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.
2154 #define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D
2158 Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.
2160 @param ECX MSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E)
2161 @param EAX Lower 32-bits of MSR value.
2162 @param EDX Upper 32-bits of MSR value.
2164 <b>Example usage</b>
2168 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL);
2169 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr);
2171 @note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.
2173 #define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E
2177 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.
2179 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F)
2180 @param EAX Lower 32-bits of MSR value.
2181 @param EDX Upper 32-bits of MSR value.
2183 <b>Example usage</b>
2187 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0);
2188 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr);
2190 @note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.
2192 #define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F
2196 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.
2198 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740)
2199 @param EAX Lower 32-bits of MSR value.
2200 @param EDX Upper 32-bits of MSR value.
2202 <b>Example usage</b>
2206 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1);
2207 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr);
2209 @note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.
2211 #define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740
2215 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.
2217 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741)
2218 @param EAX Lower 32-bits of MSR value.
2219 @param EDX Upper 32-bits of MSR value.
2221 <b>Example usage</b>
2225 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2);
2226 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr);
2228 @note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.
2230 #define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741
2234 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.
2236 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742)
2237 @param EAX Lower 32-bits of MSR value.
2238 @param EDX Upper 32-bits of MSR value.
2240 <b>Example usage</b>
2244 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3);
2245 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr);
2247 @note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.
2249 #define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742
2253 Package. Uncore SBo 3 perfmon box-wide filter.
2255 @param ECX MSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743)
2256 @param EAX Lower 32-bits of MSR value.
2257 @param EDX Upper 32-bits of MSR value.
2259 <b>Example usage</b>
2263 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER);
2264 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr);
2266 @note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.
2268 #define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743
2272 Package. Uncore SBo 3 perfmon counter 0.
2274 @param ECX MSR_HASWELL_E_S3_PMON_CTR0 (0x00000744)
2275 @param EAX Lower 32-bits of MSR value.
2276 @param EDX Upper 32-bits of MSR value.
2278 <b>Example usage</b>
2282 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0);
2283 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr);
2285 @note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.
2287 #define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744
2291 Package. Uncore SBo 3 perfmon counter 1.
2293 @param ECX MSR_HASWELL_E_S3_PMON_CTR1 (0x00000745)
2294 @param EAX Lower 32-bits of MSR value.
2295 @param EDX Upper 32-bits of MSR value.
2297 <b>Example usage</b>
2301 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1);
2302 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr);
2304 @note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.
2306 #define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745
2310 Package. Uncore SBo 3 perfmon counter 2.
2312 @param ECX MSR_HASWELL_E_S3_PMON_CTR2 (0x00000746)
2313 @param EAX Lower 32-bits of MSR value.
2314 @param EDX Upper 32-bits of MSR value.
2316 <b>Example usage</b>
2320 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2);
2321 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr);
2323 @note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.
2325 #define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746
2329 Package. Uncore SBo 3 perfmon counter 3.
2331 @param ECX MSR_HASWELL_E_S3_PMON_CTR3 (0x00000747)
2332 @param EAX Lower 32-bits of MSR value.
2333 @param EDX Upper 32-bits of MSR value.
2335 <b>Example usage</b>
2339 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3);
2340 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr);
2342 @note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.
2344 #define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747
2348 Package. Uncore C-box 0 perfmon for box-wide control.
2350 @param ECX MSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00)
2351 @param EAX Lower 32-bits of MSR value.
2352 @param EDX Upper 32-bits of MSR value.
2354 <b>Example usage</b>
2358 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL);
2359 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr);
2361 @note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.
2363 #define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00
2367 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.
2369 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01)
2370 @param EAX Lower 32-bits of MSR value.
2371 @param EDX Upper 32-bits of MSR value.
2373 <b>Example usage</b>
2377 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0);
2378 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr);
2380 @note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.
2382 #define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01
2386 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.
2388 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02)
2389 @param EAX Lower 32-bits of MSR value.
2390 @param EDX Upper 32-bits of MSR value.
2392 <b>Example usage</b>
2396 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1);
2397 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr);
2399 @note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.
2401 #define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02
2405 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.
2407 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03)
2408 @param EAX Lower 32-bits of MSR value.
2409 @param EDX Upper 32-bits of MSR value.
2411 <b>Example usage</b>
2415 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2);
2416 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr);
2418 @note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.
2420 #define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03
2424 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.
2426 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04)
2427 @param EAX Lower 32-bits of MSR value.
2428 @param EDX Upper 32-bits of MSR value.
2430 <b>Example usage</b>
2434 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3);
2435 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr);
2437 @note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.
2439 #define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04
2443 Package. Uncore C-box 0 perfmon box wide filter 0.
2445 @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05)
2446 @param EAX Lower 32-bits of MSR value.
2447 @param EDX Upper 32-bits of MSR value.
2449 <b>Example usage</b>
2453 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0);
2454 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr);
2456 @note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.
2458 #define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05
2462 Package. Uncore C-box 0 perfmon box wide filter 1.
2464 @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06)
2465 @param EAX Lower 32-bits of MSR value.
2466 @param EDX Upper 32-bits of MSR value.
2468 <b>Example usage</b>
2472 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1);
2473 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr);
2475 @note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.
2477 #define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06
2481 Package. Uncore C-box 0 perfmon box wide status.
2483 @param ECX MSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07)
2484 @param EAX Lower 32-bits of MSR value.
2485 @param EDX Upper 32-bits of MSR value.
2487 <b>Example usage</b>
2491 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS);
2492 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr);
2494 @note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.
2496 #define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07
2500 Package. Uncore C-box 0 perfmon counter 0.
2502 @param ECX MSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08)
2503 @param EAX Lower 32-bits of MSR value.
2504 @param EDX Upper 32-bits of MSR value.
2506 <b>Example usage</b>
2510 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0);
2511 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr);
2513 @note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
2515 #define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08
2519 Package. Uncore C-box 0 perfmon counter 1.
2521 @param ECX MSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09)
2522 @param EAX Lower 32-bits of MSR value.
2523 @param EDX Upper 32-bits of MSR value.
2525 <b>Example usage</b>
2529 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1);
2530 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr);
2532 @note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
2534 #define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09
2538 Package. Uncore C-box 0 perfmon counter 2.
2540 @param ECX MSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A)
2541 @param EAX Lower 32-bits of MSR value.
2542 @param EDX Upper 32-bits of MSR value.
2544 <b>Example usage</b>
2548 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2);
2549 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr);
2551 @note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
2553 #define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A
2557 Package. Uncore C-box 0 perfmon counter 3.
2559 @param ECX MSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B)
2560 @param EAX Lower 32-bits of MSR value.
2561 @param EDX Upper 32-bits of MSR value.
2563 <b>Example usage</b>
2567 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3);
2568 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr);
2570 @note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
2572 #define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B
2576 Package. Uncore C-box 1 perfmon for box-wide control.
2578 @param ECX MSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10)
2579 @param EAX Lower 32-bits of MSR value.
2580 @param EDX Upper 32-bits of MSR value.
2582 <b>Example usage</b>
2586 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL);
2587 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr);
2589 @note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.
2591 #define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10
2595 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.
2597 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11)
2598 @param EAX Lower 32-bits of MSR value.
2599 @param EDX Upper 32-bits of MSR value.
2601 <b>Example usage</b>
2605 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0);
2606 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr);
2608 @note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.
2610 #define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11
2614 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.
2616 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12)
2617 @param EAX Lower 32-bits of MSR value.
2618 @param EDX Upper 32-bits of MSR value.
2620 <b>Example usage</b>
2624 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1);
2625 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr);
2627 @note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.
2629 #define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12
2633 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.
2635 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13)
2636 @param EAX Lower 32-bits of MSR value.
2637 @param EDX Upper 32-bits of MSR value.
2639 <b>Example usage</b>
2643 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2);
2644 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr);
2646 @note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.
2648 #define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13
2652 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.
2654 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14)
2655 @param EAX Lower 32-bits of MSR value.
2656 @param EDX Upper 32-bits of MSR value.
2658 <b>Example usage</b>
2662 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3);
2663 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr);
2665 @note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.
2667 #define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14
2671 Package. Uncore C-box 1 perfmon box wide filter 0.
2673 @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15)
2674 @param EAX Lower 32-bits of MSR value.
2675 @param EDX Upper 32-bits of MSR value.
2677 <b>Example usage</b>
2681 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0);
2682 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr);
2684 @note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.
2686 #define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15
2690 Package. Uncore C-box 1 perfmon box wide filter1.
2692 @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16)
2693 @param EAX Lower 32-bits of MSR value.
2694 @param EDX Upper 32-bits of MSR value.
2696 <b>Example usage</b>
2700 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1);
2701 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr);
2703 @note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.
2705 #define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16
2709 Package. Uncore C-box 1 perfmon box wide status.
2711 @param ECX MSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17)
2712 @param EAX Lower 32-bits of MSR value.
2713 @param EDX Upper 32-bits of MSR value.
2715 <b>Example usage</b>
2719 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS);
2720 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr);
2722 @note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.
2724 #define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17
2728 Package. Uncore C-box 1 perfmon counter 0.
2730 @param ECX MSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18)
2731 @param EAX Lower 32-bits of MSR value.
2732 @param EDX Upper 32-bits of MSR value.
2734 <b>Example usage</b>
2738 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0);
2739 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr);
2741 @note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
2743 #define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18
2747 Package. Uncore C-box 1 perfmon counter 1.
2749 @param ECX MSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19)
2750 @param EAX Lower 32-bits of MSR value.
2751 @param EDX Upper 32-bits of MSR value.
2753 <b>Example usage</b>
2757 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1);
2758 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr);
2760 @note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
2762 #define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19
2766 Package. Uncore C-box 1 perfmon counter 2.
2768 @param ECX MSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A)
2769 @param EAX Lower 32-bits of MSR value.
2770 @param EDX Upper 32-bits of MSR value.
2772 <b>Example usage</b>
2776 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2);
2777 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr);
2779 @note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
2781 #define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A
2785 Package. Uncore C-box 1 perfmon counter 3.
2787 @param ECX MSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B)
2788 @param EAX Lower 32-bits of MSR value.
2789 @param EDX Upper 32-bits of MSR value.
2791 <b>Example usage</b>
2795 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3);
2796 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr);
2798 @note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
2800 #define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B
2804 Package. Uncore C-box 2 perfmon for box-wide control.
2806 @param ECX MSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20)
2807 @param EAX Lower 32-bits of MSR value.
2808 @param EDX Upper 32-bits of MSR value.
2810 <b>Example usage</b>
2814 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL);
2815 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr);
2817 @note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.
2819 #define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20
2823 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.
2825 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21)
2826 @param EAX Lower 32-bits of MSR value.
2827 @param EDX Upper 32-bits of MSR value.
2829 <b>Example usage</b>
2833 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0);
2834 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr);
2836 @note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.
2838 #define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21
2842 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.
2844 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22)
2845 @param EAX Lower 32-bits of MSR value.
2846 @param EDX Upper 32-bits of MSR value.
2848 <b>Example usage</b>
2852 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1);
2853 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr);
2855 @note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.
2857 #define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22
2861 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.
2863 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23)
2864 @param EAX Lower 32-bits of MSR value.
2865 @param EDX Upper 32-bits of MSR value.
2867 <b>Example usage</b>
2871 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2);
2872 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr);
2874 @note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.
2876 #define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23
2880 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.
2882 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24)
2883 @param EAX Lower 32-bits of MSR value.
2884 @param EDX Upper 32-bits of MSR value.
2886 <b>Example usage</b>
2890 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3);
2891 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr);
2893 @note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.
2895 #define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24
2899 Package. Uncore C-box 2 perfmon box wide filter 0.
2901 @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25)
2902 @param EAX Lower 32-bits of MSR value.
2903 @param EDX Upper 32-bits of MSR value.
2905 <b>Example usage</b>
2909 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0);
2910 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr);
2912 @note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.
2914 #define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25
2918 Package. Uncore C-box 2 perfmon box wide filter1.
2920 @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26)
2921 @param EAX Lower 32-bits of MSR value.
2922 @param EDX Upper 32-bits of MSR value.
2924 <b>Example usage</b>
2928 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1);
2929 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr);
2931 @note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.
2933 #define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26
2937 Package. Uncore C-box 2 perfmon box wide status.
2939 @param ECX MSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27)
2940 @param EAX Lower 32-bits of MSR value.
2941 @param EDX Upper 32-bits of MSR value.
2943 <b>Example usage</b>
2947 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS);
2948 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr);
2950 @note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.
2952 #define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27
2956 Package. Uncore C-box 2 perfmon counter 0.
2958 @param ECX MSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28)
2959 @param EAX Lower 32-bits of MSR value.
2960 @param EDX Upper 32-bits of MSR value.
2962 <b>Example usage</b>
2966 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0);
2967 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr);
2969 @note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
2971 #define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28
2975 Package. Uncore C-box 2 perfmon counter 1.
2977 @param ECX MSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29)
2978 @param EAX Lower 32-bits of MSR value.
2979 @param EDX Upper 32-bits of MSR value.
2981 <b>Example usage</b>
2985 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1);
2986 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr);
2988 @note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
2990 #define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29
2994 Package. Uncore C-box 2 perfmon counter 2.
2996 @param ECX MSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A)
2997 @param EAX Lower 32-bits of MSR value.
2998 @param EDX Upper 32-bits of MSR value.
3000 <b>Example usage</b>
3004 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2);
3005 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr);
3007 @note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
3009 #define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A
3013 Package. Uncore C-box 2 perfmon counter 3.
3015 @param ECX MSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B)
3016 @param EAX Lower 32-bits of MSR value.
3017 @param EDX Upper 32-bits of MSR value.
3019 <b>Example usage</b>
3023 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3);
3024 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr);
3026 @note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
3028 #define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B
3032 Package. Uncore C-box 3 perfmon for box-wide control.
3034 @param ECX MSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30)
3035 @param EAX Lower 32-bits of MSR value.
3036 @param EDX Upper 32-bits of MSR value.
3038 <b>Example usage</b>
3042 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL);
3043 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr);
3045 @note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.
3047 #define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30
3051 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.
3053 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31)
3054 @param EAX Lower 32-bits of MSR value.
3055 @param EDX Upper 32-bits of MSR value.
3057 <b>Example usage</b>
3061 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0);
3062 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr);
3064 @note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.
3066 #define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31
3070 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.
3072 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32)
3073 @param EAX Lower 32-bits of MSR value.
3074 @param EDX Upper 32-bits of MSR value.
3076 <b>Example usage</b>
3080 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1);
3081 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr);
3083 @note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.
3085 #define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32
3089 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.
3091 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33)
3092 @param EAX Lower 32-bits of MSR value.
3093 @param EDX Upper 32-bits of MSR value.
3095 <b>Example usage</b>
3099 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2);
3100 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr);
3102 @note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.
3104 #define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33
3108 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.
3110 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34)
3111 @param EAX Lower 32-bits of MSR value.
3112 @param EDX Upper 32-bits of MSR value.
3114 <b>Example usage</b>
3118 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3);
3119 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr);
3121 @note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.
3123 #define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34
3127 Package. Uncore C-box 3 perfmon box wide filter 0.
3129 @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35)
3130 @param EAX Lower 32-bits of MSR value.
3131 @param EDX Upper 32-bits of MSR value.
3133 <b>Example usage</b>
3137 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0);
3138 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr);
3140 @note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.
3142 #define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35
3146 Package. Uncore C-box 3 perfmon box wide filter1.
3148 @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36)
3149 @param EAX Lower 32-bits of MSR value.
3150 @param EDX Upper 32-bits of MSR value.
3152 <b>Example usage</b>
3156 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1);
3157 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr);
3159 @note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.
3161 #define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36
3165 Package. Uncore C-box 3 perfmon box wide status.
3167 @param ECX MSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37)
3168 @param EAX Lower 32-bits of MSR value.
3169 @param EDX Upper 32-bits of MSR value.
3171 <b>Example usage</b>
3175 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS);
3176 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr);
3178 @note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.
3180 #define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37
3184 Package. Uncore C-box 3 perfmon counter 0.
3186 @param ECX MSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38)
3187 @param EAX Lower 32-bits of MSR value.
3188 @param EDX Upper 32-bits of MSR value.
3190 <b>Example usage</b>
3194 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0);
3195 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr);
3197 @note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
3199 #define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38
3203 Package. Uncore C-box 3 perfmon counter 1.
3205 @param ECX MSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39)
3206 @param EAX Lower 32-bits of MSR value.
3207 @param EDX Upper 32-bits of MSR value.
3209 <b>Example usage</b>
3213 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1);
3214 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr);
3216 @note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
3218 #define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39
3222 Package. Uncore C-box 3 perfmon counter 2.
3224 @param ECX MSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A)
3225 @param EAX Lower 32-bits of MSR value.
3226 @param EDX Upper 32-bits of MSR value.
3228 <b>Example usage</b>
3232 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2);
3233 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr);
3235 @note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
3237 #define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A
3241 Package. Uncore C-box 3 perfmon counter 3.
3243 @param ECX MSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B)
3244 @param EAX Lower 32-bits of MSR value.
3245 @param EDX Upper 32-bits of MSR value.
3247 <b>Example usage</b>
3251 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3);
3252 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr);
3254 @note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
3256 #define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B
3260 Package. Uncore C-box 4 perfmon for box-wide control.
3262 @param ECX MSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40)
3263 @param EAX Lower 32-bits of MSR value.
3264 @param EDX Upper 32-bits of MSR value.
3266 <b>Example usage</b>
3270 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL);
3271 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr);
3273 @note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.
3275 #define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40
3279 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.
3281 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41)
3282 @param EAX Lower 32-bits of MSR value.
3283 @param EDX Upper 32-bits of MSR value.
3285 <b>Example usage</b>
3289 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0);
3290 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr);
3292 @note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.
3294 #define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41
3298 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.
3300 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42)
3301 @param EAX Lower 32-bits of MSR value.
3302 @param EDX Upper 32-bits of MSR value.
3304 <b>Example usage</b>
3308 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1);
3309 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr);
3311 @note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.
3313 #define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42
3317 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.
3319 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43)
3320 @param EAX Lower 32-bits of MSR value.
3321 @param EDX Upper 32-bits of MSR value.
3323 <b>Example usage</b>
3327 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2);
3328 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr);
3330 @note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.
3332 #define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43
3336 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.
3338 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44)
3339 @param EAX Lower 32-bits of MSR value.
3340 @param EDX Upper 32-bits of MSR value.
3342 <b>Example usage</b>
3346 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3);
3347 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr);
3349 @note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.
3351 #define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44
3355 Package. Uncore C-box 4 perfmon box wide filter 0.
3357 @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45)
3358 @param EAX Lower 32-bits of MSR value.
3359 @param EDX Upper 32-bits of MSR value.
3361 <b>Example usage</b>
3365 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0);
3366 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr);
3368 @note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.
3370 #define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45
3374 Package. Uncore C-box 4 perfmon box wide filter1.
3376 @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46)
3377 @param EAX Lower 32-bits of MSR value.
3378 @param EDX Upper 32-bits of MSR value.
3380 <b>Example usage</b>
3384 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1);
3385 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr);
3387 @note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.
3389 #define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46
3393 Package. Uncore C-box 4 perfmon box wide status.
3395 @param ECX MSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47)
3396 @param EAX Lower 32-bits of MSR value.
3397 @param EDX Upper 32-bits of MSR value.
3399 <b>Example usage</b>
3403 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS);
3404 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr);
3406 @note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.
3408 #define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47
3412 Package. Uncore C-box 4 perfmon counter 0.
3414 @param ECX MSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48)
3415 @param EAX Lower 32-bits of MSR value.
3416 @param EDX Upper 32-bits of MSR value.
3418 <b>Example usage</b>
3422 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0);
3423 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr);
3425 @note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
3427 #define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48
3431 Package. Uncore C-box 4 perfmon counter 1.
3433 @param ECX MSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49)
3434 @param EAX Lower 32-bits of MSR value.
3435 @param EDX Upper 32-bits of MSR value.
3437 <b>Example usage</b>
3441 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1);
3442 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr);
3444 @note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
3446 #define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49
3450 Package. Uncore C-box 4 perfmon counter 2.
3452 @param ECX MSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A)
3453 @param EAX Lower 32-bits of MSR value.
3454 @param EDX Upper 32-bits of MSR value.
3456 <b>Example usage</b>
3460 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2);
3461 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr);
3463 @note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
3465 #define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A
3469 Package. Uncore C-box 4 perfmon counter 3.
3471 @param ECX MSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B)
3472 @param EAX Lower 32-bits of MSR value.
3473 @param EDX Upper 32-bits of MSR value.
3475 <b>Example usage</b>
3479 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3);
3480 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr);
3482 @note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
3484 #define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B
3488 Package. Uncore C-box 5 perfmon for box-wide control.
3490 @param ECX MSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50)
3491 @param EAX Lower 32-bits of MSR value.
3492 @param EDX Upper 32-bits of MSR value.
3494 <b>Example usage</b>
3498 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL);
3499 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr);
3501 @note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.
3503 #define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50
3507 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.
3509 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51)
3510 @param EAX Lower 32-bits of MSR value.
3511 @param EDX Upper 32-bits of MSR value.
3513 <b>Example usage</b>
3517 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0);
3518 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr);
3520 @note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.
3522 #define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51
3526 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.
3528 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52)
3529 @param EAX Lower 32-bits of MSR value.
3530 @param EDX Upper 32-bits of MSR value.
3532 <b>Example usage</b>
3536 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1);
3537 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr);
3539 @note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.
3541 #define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52
3545 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.
3547 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53)
3548 @param EAX Lower 32-bits of MSR value.
3549 @param EDX Upper 32-bits of MSR value.
3551 <b>Example usage</b>
3555 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2);
3556 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr);
3558 @note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.
3560 #define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53
3564 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.
3566 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54)
3567 @param EAX Lower 32-bits of MSR value.
3568 @param EDX Upper 32-bits of MSR value.
3570 <b>Example usage</b>
3574 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3);
3575 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr);
3577 @note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.
3579 #define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54
3583 Package. Uncore C-box 5 perfmon box wide filter 0.
3585 @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55)
3586 @param EAX Lower 32-bits of MSR value.
3587 @param EDX Upper 32-bits of MSR value.
3589 <b>Example usage</b>
3593 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0);
3594 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr);
3596 @note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.
3598 #define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55
3602 Package. Uncore C-box 5 perfmon box wide filter1.
3604 @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56)
3605 @param EAX Lower 32-bits of MSR value.
3606 @param EDX Upper 32-bits of MSR value.
3608 <b>Example usage</b>
3612 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1);
3613 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr);
3615 @note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.
3617 #define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56
3621 Package. Uncore C-box 5 perfmon box wide status.
3623 @param ECX MSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57)
3624 @param EAX Lower 32-bits of MSR value.
3625 @param EDX Upper 32-bits of MSR value.
3627 <b>Example usage</b>
3631 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS);
3632 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr);
3634 @note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.
3636 #define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57
3640 Package. Uncore C-box 5 perfmon counter 0.
3642 @param ECX MSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58)
3643 @param EAX Lower 32-bits of MSR value.
3644 @param EDX Upper 32-bits of MSR value.
3646 <b>Example usage</b>
3650 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0);
3651 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr);
3653 @note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
3655 #define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58
3659 Package. Uncore C-box 5 perfmon counter 1.
3661 @param ECX MSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59)
3662 @param EAX Lower 32-bits of MSR value.
3663 @param EDX Upper 32-bits of MSR value.
3665 <b>Example usage</b>
3669 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1);
3670 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr);
3672 @note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
3674 #define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59
3678 Package. Uncore C-box 5 perfmon counter 2.
3680 @param ECX MSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A)
3681 @param EAX Lower 32-bits of MSR value.
3682 @param EDX Upper 32-bits of MSR value.
3684 <b>Example usage</b>
3688 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2);
3689 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr);
3691 @note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
3693 #define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A
3697 Package. Uncore C-box 5 perfmon counter 3.
3699 @param ECX MSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B)
3700 @param EAX Lower 32-bits of MSR value.
3701 @param EDX Upper 32-bits of MSR value.
3703 <b>Example usage</b>
3707 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3);
3708 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr);
3710 @note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
3712 #define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B
3716 Package. Uncore C-box 6 perfmon for box-wide control.
3718 @param ECX MSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60)
3719 @param EAX Lower 32-bits of MSR value.
3720 @param EDX Upper 32-bits of MSR value.
3722 <b>Example usage</b>
3726 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL);
3727 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr);
3729 @note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.
3731 #define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60
3735 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.
3737 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61)
3738 @param EAX Lower 32-bits of MSR value.
3739 @param EDX Upper 32-bits of MSR value.
3741 <b>Example usage</b>
3745 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0);
3746 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr);
3748 @note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.
3750 #define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61
3754 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.
3756 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62)
3757 @param EAX Lower 32-bits of MSR value.
3758 @param EDX Upper 32-bits of MSR value.
3760 <b>Example usage</b>
3764 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1);
3765 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr);
3767 @note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.
3769 #define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62
3773 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.
3775 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63)
3776 @param EAX Lower 32-bits of MSR value.
3777 @param EDX Upper 32-bits of MSR value.
3779 <b>Example usage</b>
3783 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2);
3784 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr);
3786 @note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.
3788 #define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63
3792 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.
3794 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64)
3795 @param EAX Lower 32-bits of MSR value.
3796 @param EDX Upper 32-bits of MSR value.
3798 <b>Example usage</b>
3802 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3);
3803 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr);
3805 @note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.
3807 #define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64
3811 Package. Uncore C-box 6 perfmon box wide filter 0.
3813 @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65)
3814 @param EAX Lower 32-bits of MSR value.
3815 @param EDX Upper 32-bits of MSR value.
3817 <b>Example usage</b>
3821 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0);
3822 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr);
3824 @note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.
3826 #define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65
3830 Package. Uncore C-box 6 perfmon box wide filter1.
3832 @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66)
3833 @param EAX Lower 32-bits of MSR value.
3834 @param EDX Upper 32-bits of MSR value.
3836 <b>Example usage</b>
3840 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1);
3841 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr);
3843 @note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.
3845 #define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66
3849 Package. Uncore C-box 6 perfmon box wide status.
3851 @param ECX MSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67)
3852 @param EAX Lower 32-bits of MSR value.
3853 @param EDX Upper 32-bits of MSR value.
3855 <b>Example usage</b>
3859 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS);
3860 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr);
3862 @note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.
3864 #define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67
3868 Package. Uncore C-box 6 perfmon counter 0.
3870 @param ECX MSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68)
3871 @param EAX Lower 32-bits of MSR value.
3872 @param EDX Upper 32-bits of MSR value.
3874 <b>Example usage</b>
3878 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0);
3879 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr);
3881 @note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
3883 #define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68
3887 Package. Uncore C-box 6 perfmon counter 1.
3889 @param ECX MSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69)
3890 @param EAX Lower 32-bits of MSR value.
3891 @param EDX Upper 32-bits of MSR value.
3893 <b>Example usage</b>
3897 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1);
3898 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr);
3900 @note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
3902 #define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69
3906 Package. Uncore C-box 6 perfmon counter 2.
3908 @param ECX MSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A)
3909 @param EAX Lower 32-bits of MSR value.
3910 @param EDX Upper 32-bits of MSR value.
3912 <b>Example usage</b>
3916 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2);
3917 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr);
3919 @note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
3921 #define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A
3925 Package. Uncore C-box 6 perfmon counter 3.
3927 @param ECX MSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B)
3928 @param EAX Lower 32-bits of MSR value.
3929 @param EDX Upper 32-bits of MSR value.
3931 <b>Example usage</b>
3935 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3);
3936 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr);
3938 @note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
3940 #define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B
3944 Package. Uncore C-box 7 perfmon for box-wide control.
3946 @param ECX MSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70)
3947 @param EAX Lower 32-bits of MSR value.
3948 @param EDX Upper 32-bits of MSR value.
3950 <b>Example usage</b>
3954 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL);
3955 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr);
3957 @note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.
3959 #define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70
3963 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.
3965 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71)
3966 @param EAX Lower 32-bits of MSR value.
3967 @param EDX Upper 32-bits of MSR value.
3969 <b>Example usage</b>
3973 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0);
3974 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr);
3976 @note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.
3978 #define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71
3982 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.
3984 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72)
3985 @param EAX Lower 32-bits of MSR value.
3986 @param EDX Upper 32-bits of MSR value.
3988 <b>Example usage</b>
3992 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1);
3993 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr);
3995 @note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.
3997 #define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72
4001 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.
4003 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73)
4004 @param EAX Lower 32-bits of MSR value.
4005 @param EDX Upper 32-bits of MSR value.
4007 <b>Example usage</b>
4011 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2);
4012 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr);
4014 @note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.
4016 #define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73
4020 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.
4022 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74)
4023 @param EAX Lower 32-bits of MSR value.
4024 @param EDX Upper 32-bits of MSR value.
4026 <b>Example usage</b>
4030 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3);
4031 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr);
4033 @note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.
4035 #define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74
4039 Package. Uncore C-box 7 perfmon box wide filter 0.
4041 @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75)
4042 @param EAX Lower 32-bits of MSR value.
4043 @param EDX Upper 32-bits of MSR value.
4045 <b>Example usage</b>
4049 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0);
4050 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr);
4052 @note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.
4054 #define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75
4058 Package. Uncore C-box 7 perfmon box wide filter1.
4060 @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76)
4061 @param EAX Lower 32-bits of MSR value.
4062 @param EDX Upper 32-bits of MSR value.
4064 <b>Example usage</b>
4068 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1);
4069 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr);
4071 @note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.
4073 #define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76
4077 Package. Uncore C-box 7 perfmon box wide status.
4079 @param ECX MSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77)
4080 @param EAX Lower 32-bits of MSR value.
4081 @param EDX Upper 32-bits of MSR value.
4083 <b>Example usage</b>
4087 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS);
4088 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr);
4090 @note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.
4092 #define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77
4096 Package. Uncore C-box 7 perfmon counter 0.
4098 @param ECX MSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78)
4099 @param EAX Lower 32-bits of MSR value.
4100 @param EDX Upper 32-bits of MSR value.
4102 <b>Example usage</b>
4106 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0);
4107 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr);
4109 @note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
4111 #define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78
4115 Package. Uncore C-box 7 perfmon counter 1.
4117 @param ECX MSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79)
4118 @param EAX Lower 32-bits of MSR value.
4119 @param EDX Upper 32-bits of MSR value.
4121 <b>Example usage</b>
4125 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1);
4126 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr);
4128 @note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
4130 #define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79
4134 Package. Uncore C-box 7 perfmon counter 2.
4136 @param ECX MSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A)
4137 @param EAX Lower 32-bits of MSR value.
4138 @param EDX Upper 32-bits of MSR value.
4140 <b>Example usage</b>
4144 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2);
4145 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr);
4147 @note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
4149 #define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A
4153 Package. Uncore C-box 7 perfmon counter 3.
4155 @param ECX MSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B)
4156 @param EAX Lower 32-bits of MSR value.
4157 @param EDX Upper 32-bits of MSR value.
4159 <b>Example usage</b>
4163 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3);
4164 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr);
4166 @note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
4168 #define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B
4172 Package. Uncore C-box 8 perfmon local box wide control.
4174 @param ECX MSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80)
4175 @param EAX Lower 32-bits of MSR value.
4176 @param EDX Upper 32-bits of MSR value.
4178 <b>Example usage</b>
4182 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL);
4183 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr);
4185 @note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.
4187 #define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80
4191 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
4193 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81)
4194 @param EAX Lower 32-bits of MSR value.
4195 @param EDX Upper 32-bits of MSR value.
4197 <b>Example usage</b>
4201 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0);
4202 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr);
4204 @note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.
4206 #define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81
4210 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
4212 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82)
4213 @param EAX Lower 32-bits of MSR value.
4214 @param EDX Upper 32-bits of MSR value.
4216 <b>Example usage</b>
4220 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1);
4221 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr);
4223 @note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.
4225 #define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82
4229 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
4231 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83)
4232 @param EAX Lower 32-bits of MSR value.
4233 @param EDX Upper 32-bits of MSR value.
4235 <b>Example usage</b>
4239 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2);
4240 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr);
4242 @note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.
4244 #define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83
4248 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
4250 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84)
4251 @param EAX Lower 32-bits of MSR value.
4252 @param EDX Upper 32-bits of MSR value.
4254 <b>Example usage</b>
4258 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3);
4259 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr);
4261 @note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.
4263 #define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84
4267 Package. Uncore C-box 8 perfmon box wide filter0.
4269 @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85)
4270 @param EAX Lower 32-bits of MSR value.
4271 @param EDX Upper 32-bits of MSR value.
4273 <b>Example usage</b>
4277 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0);
4278 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr);
4280 @note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.
4282 #define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85
4286 Package. Uncore C-box 8 perfmon box wide filter1.
4288 @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86)
4289 @param EAX Lower 32-bits of MSR value.
4290 @param EDX Upper 32-bits of MSR value.
4292 <b>Example usage</b>
4296 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1);
4297 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr);
4299 @note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.
4301 #define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86
4305 Package. Uncore C-box 8 perfmon box wide status.
4307 @param ECX MSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87)
4308 @param EAX Lower 32-bits of MSR value.
4309 @param EDX Upper 32-bits of MSR value.
4311 <b>Example usage</b>
4315 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS);
4316 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr);
4318 @note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
4320 #define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87
4324 Package. Uncore C-box 8 perfmon counter 0.
4326 @param ECX MSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88)
4327 @param EAX Lower 32-bits of MSR value.
4328 @param EDX Upper 32-bits of MSR value.
4330 <b>Example usage</b>
4334 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0);
4335 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr);
4337 @note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
4339 #define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88
4343 Package. Uncore C-box 8 perfmon counter 1.
4345 @param ECX MSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89)
4346 @param EAX Lower 32-bits of MSR value.
4347 @param EDX Upper 32-bits of MSR value.
4349 <b>Example usage</b>
4353 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1);
4354 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr);
4356 @note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
4358 #define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89
4362 Package. Uncore C-box 8 perfmon counter 2.
4364 @param ECX MSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A)
4365 @param EAX Lower 32-bits of MSR value.
4366 @param EDX Upper 32-bits of MSR value.
4368 <b>Example usage</b>
4372 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2);
4373 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr);
4375 @note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
4377 #define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A
4381 Package. Uncore C-box 8 perfmon counter 3.
4383 @param ECX MSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B)
4384 @param EAX Lower 32-bits of MSR value.
4385 @param EDX Upper 32-bits of MSR value.
4387 <b>Example usage</b>
4391 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3);
4392 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr);
4394 @note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
4396 #define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B
4400 Package. Uncore C-box 9 perfmon local box wide control.
4402 @param ECX MSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90)
4403 @param EAX Lower 32-bits of MSR value.
4404 @param EDX Upper 32-bits of MSR value.
4406 <b>Example usage</b>
4410 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL);
4411 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr);
4413 @note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.
4415 #define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90
4419 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
4421 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91)
4422 @param EAX Lower 32-bits of MSR value.
4423 @param EDX Upper 32-bits of MSR value.
4425 <b>Example usage</b>
4429 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0);
4430 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr);
4432 @note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.
4434 #define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91
4438 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
4440 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92)
4441 @param EAX Lower 32-bits of MSR value.
4442 @param EDX Upper 32-bits of MSR value.
4444 <b>Example usage</b>
4448 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1);
4449 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr);
4451 @note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.
4453 #define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92
4457 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
4459 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93)
4460 @param EAX Lower 32-bits of MSR value.
4461 @param EDX Upper 32-bits of MSR value.
4463 <b>Example usage</b>
4467 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2);
4468 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr);
4470 @note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.
4472 #define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93
4476 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
4478 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94)
4479 @param EAX Lower 32-bits of MSR value.
4480 @param EDX Upper 32-bits of MSR value.
4482 <b>Example usage</b>
4486 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3);
4487 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr);
4489 @note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.
4491 #define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94
4495 Package. Uncore C-box 9 perfmon box wide filter0.
4497 @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95)
4498 @param EAX Lower 32-bits of MSR value.
4499 @param EDX Upper 32-bits of MSR value.
4501 <b>Example usage</b>
4505 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0);
4506 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr);
4508 @note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.
4510 #define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95
4514 Package. Uncore C-box 9 perfmon box wide filter1.
4516 @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96)
4517 @param EAX Lower 32-bits of MSR value.
4518 @param EDX Upper 32-bits of MSR value.
4520 <b>Example usage</b>
4524 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1);
4525 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr);
4527 @note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.
4529 #define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96
4533 Package. Uncore C-box 9 perfmon box wide status.
4535 @param ECX MSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97)
4536 @param EAX Lower 32-bits of MSR value.
4537 @param EDX Upper 32-bits of MSR value.
4539 <b>Example usage</b>
4543 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS);
4544 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr);
4546 @note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
4548 #define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97
4552 Package. Uncore C-box 9 perfmon counter 0.
4554 @param ECX MSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98)
4555 @param EAX Lower 32-bits of MSR value.
4556 @param EDX Upper 32-bits of MSR value.
4558 <b>Example usage</b>
4562 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0);
4563 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr);
4565 @note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
4567 #define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98
4571 Package. Uncore C-box 9 perfmon counter 1.
4573 @param ECX MSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99)
4574 @param EAX Lower 32-bits of MSR value.
4575 @param EDX Upper 32-bits of MSR value.
4577 <b>Example usage</b>
4581 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1);
4582 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr);
4584 @note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
4586 #define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99
4590 Package. Uncore C-box 9 perfmon counter 2.
4592 @param ECX MSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A)
4593 @param EAX Lower 32-bits of MSR value.
4594 @param EDX Upper 32-bits of MSR value.
4596 <b>Example usage</b>
4600 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2);
4601 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr);
4603 @note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
4605 #define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A
4609 Package. Uncore C-box 9 perfmon counter 3.
4611 @param ECX MSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B)
4612 @param EAX Lower 32-bits of MSR value.
4613 @param EDX Upper 32-bits of MSR value.
4615 <b>Example usage</b>
4619 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3);
4620 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr);
4622 @note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
4624 #define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B
4628 Package. Uncore C-box 10 perfmon local box wide control.
4630 @param ECX MSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0)
4631 @param EAX Lower 32-bits of MSR value.
4632 @param EDX Upper 32-bits of MSR value.
4634 <b>Example usage</b>
4638 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL);
4639 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr);
4641 @note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.
4643 #define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0
4647 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
4649 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1)
4650 @param EAX Lower 32-bits of MSR value.
4651 @param EDX Upper 32-bits of MSR value.
4653 <b>Example usage</b>
4657 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0);
4658 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr);
4660 @note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.
4662 #define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1
4666 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
4668 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2)
4669 @param EAX Lower 32-bits of MSR value.
4670 @param EDX Upper 32-bits of MSR value.
4672 <b>Example usage</b>
4676 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1);
4677 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr);
4679 @note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.
4681 #define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2
4685 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
4687 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3)
4688 @param EAX Lower 32-bits of MSR value.
4689 @param EDX Upper 32-bits of MSR value.
4691 <b>Example usage</b>
4695 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2);
4696 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr);
4698 @note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.
4700 #define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3
4704 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
4706 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4)
4707 @param EAX Lower 32-bits of MSR value.
4708 @param EDX Upper 32-bits of MSR value.
4710 <b>Example usage</b>
4714 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3);
4715 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr);
4717 @note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.
4719 #define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4
4723 Package. Uncore C-box 10 perfmon box wide filter0.
4725 @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5)
4726 @param EAX Lower 32-bits of MSR value.
4727 @param EDX Upper 32-bits of MSR value.
4729 <b>Example usage</b>
4733 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0);
4734 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr);
4736 @note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.
4738 #define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5
4742 Package. Uncore C-box 10 perfmon box wide filter1.
4744 @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6)
4745 @param EAX Lower 32-bits of MSR value.
4746 @param EDX Upper 32-bits of MSR value.
4748 <b>Example usage</b>
4752 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1);
4753 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr);
4755 @note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.
4757 #define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6
4761 Package. Uncore C-box 10 perfmon box wide status.
4763 @param ECX MSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7)
4764 @param EAX Lower 32-bits of MSR value.
4765 @param EDX Upper 32-bits of MSR value.
4767 <b>Example usage</b>
4771 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS);
4772 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr);
4774 @note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.
4776 #define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7
4780 Package. Uncore C-box 10 perfmon counter 0.
4782 @param ECX MSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8)
4783 @param EAX Lower 32-bits of MSR value.
4784 @param EDX Upper 32-bits of MSR value.
4786 <b>Example usage</b>
4790 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0);
4791 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr);
4793 @note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.
4795 #define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8
4799 Package. Uncore C-box 10 perfmon counter 1.
4801 @param ECX MSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9)
4802 @param EAX Lower 32-bits of MSR value.
4803 @param EDX Upper 32-bits of MSR value.
4805 <b>Example usage</b>
4809 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1);
4810 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr);
4812 @note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.
4814 #define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9
4818 Package. Uncore C-box 10 perfmon counter 2.
4820 @param ECX MSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA)
4821 @param EAX Lower 32-bits of MSR value.
4822 @param EDX Upper 32-bits of MSR value.
4824 <b>Example usage</b>
4828 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2);
4829 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr);
4831 @note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.
4833 #define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA
4837 Package. Uncore C-box 10 perfmon counter 3.
4839 @param ECX MSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB)
4840 @param EAX Lower 32-bits of MSR value.
4841 @param EDX Upper 32-bits of MSR value.
4843 <b>Example usage</b>
4847 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3);
4848 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr);
4850 @note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.
4852 #define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB
4856 Package. Uncore C-box 11 perfmon local box wide control.
4858 @param ECX MSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0)
4859 @param EAX Lower 32-bits of MSR value.
4860 @param EDX Upper 32-bits of MSR value.
4862 <b>Example usage</b>
4866 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL);
4867 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr);
4869 @note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.
4871 #define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0
4875 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
4877 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1)
4878 @param EAX Lower 32-bits of MSR value.
4879 @param EDX Upper 32-bits of MSR value.
4881 <b>Example usage</b>
4885 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0);
4886 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr);
4888 @note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.
4890 #define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1
4894 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
4896 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2)
4897 @param EAX Lower 32-bits of MSR value.
4898 @param EDX Upper 32-bits of MSR value.
4900 <b>Example usage</b>
4904 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1);
4905 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr);
4907 @note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.
4909 #define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2
4913 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
4915 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3)
4916 @param EAX Lower 32-bits of MSR value.
4917 @param EDX Upper 32-bits of MSR value.
4919 <b>Example usage</b>
4923 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2);
4924 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr);
4926 @note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.
4928 #define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3
4932 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
4934 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4)
4935 @param EAX Lower 32-bits of MSR value.
4936 @param EDX Upper 32-bits of MSR value.
4938 <b>Example usage</b>
4942 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3);
4943 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr);
4945 @note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.
4947 #define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4
4951 Package. Uncore C-box 11 perfmon box wide filter0.
4953 @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5)
4954 @param EAX Lower 32-bits of MSR value.
4955 @param EDX Upper 32-bits of MSR value.
4957 <b>Example usage</b>
4961 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0);
4962 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr);
4964 @note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.
4966 #define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5
4970 Package. Uncore C-box 11 perfmon box wide filter1.
4972 @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6)
4973 @param EAX Lower 32-bits of MSR value.
4974 @param EDX Upper 32-bits of MSR value.
4976 <b>Example usage</b>
4980 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1);
4981 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr);
4983 @note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.
4985 #define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6
4989 Package. Uncore C-box 11 perfmon box wide status.
4991 @param ECX MSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7)
4992 @param EAX Lower 32-bits of MSR value.
4993 @param EDX Upper 32-bits of MSR value.
4995 <b>Example usage</b>
4999 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS);
5000 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr);
5002 @note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.
5004 #define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7
5008 Package. Uncore C-box 11 perfmon counter 0.
5010 @param ECX MSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8)
5011 @param EAX Lower 32-bits of MSR value.
5012 @param EDX Upper 32-bits of MSR value.
5014 <b>Example usage</b>
5018 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0);
5019 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr);
5021 @note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.
5023 #define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8
5027 Package. Uncore C-box 11 perfmon counter 1.
5029 @param ECX MSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9)
5030 @param EAX Lower 32-bits of MSR value.
5031 @param EDX Upper 32-bits of MSR value.
5033 <b>Example usage</b>
5037 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1);
5038 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr);
5040 @note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.
5042 #define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9
5046 Package. Uncore C-box 11 perfmon counter 2.
5048 @param ECX MSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA)
5049 @param EAX Lower 32-bits of MSR value.
5050 @param EDX Upper 32-bits of MSR value.
5052 <b>Example usage</b>
5056 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2);
5057 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr);
5059 @note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.
5061 #define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA
5065 Package. Uncore C-box 11 perfmon counter 3.
5067 @param ECX MSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB)
5068 @param EAX Lower 32-bits of MSR value.
5069 @param EDX Upper 32-bits of MSR value.
5071 <b>Example usage</b>
5075 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3);
5076 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr);
5078 @note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.
5080 #define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB
5084 Package. Uncore C-box 12 perfmon local box wide control.
5086 @param ECX MSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0)
5087 @param EAX Lower 32-bits of MSR value.
5088 @param EDX Upper 32-bits of MSR value.
5090 <b>Example usage</b>
5094 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL);
5095 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr);
5097 @note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.
5099 #define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0
5103 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
5105 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1)
5106 @param EAX Lower 32-bits of MSR value.
5107 @param EDX Upper 32-bits of MSR value.
5109 <b>Example usage</b>
5113 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0);
5114 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr);
5116 @note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.
5118 #define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1
5122 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
5124 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2)
5125 @param EAX Lower 32-bits of MSR value.
5126 @param EDX Upper 32-bits of MSR value.
5128 <b>Example usage</b>
5132 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1);
5133 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr);
5135 @note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.
5137 #define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2
5141 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
5143 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3)
5144 @param EAX Lower 32-bits of MSR value.
5145 @param EDX Upper 32-bits of MSR value.
5147 <b>Example usage</b>
5151 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2);
5152 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr);
5154 @note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.
5156 #define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3
5160 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
5162 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4)
5163 @param EAX Lower 32-bits of MSR value.
5164 @param EDX Upper 32-bits of MSR value.
5166 <b>Example usage</b>
5170 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3);
5171 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr);
5173 @note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.
5175 #define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4
5179 Package. Uncore C-box 12 perfmon box wide filter0.
5181 @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5)
5182 @param EAX Lower 32-bits of MSR value.
5183 @param EDX Upper 32-bits of MSR value.
5185 <b>Example usage</b>
5189 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0);
5190 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr);
5192 @note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.
5194 #define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5
5198 Package. Uncore C-box 12 perfmon box wide filter1.
5200 @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6)
5201 @param EAX Lower 32-bits of MSR value.
5202 @param EDX Upper 32-bits of MSR value.
5204 <b>Example usage</b>
5208 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1);
5209 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr);
5211 @note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.
5213 #define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6
5217 Package. Uncore C-box 12 perfmon box wide status.
5219 @param ECX MSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7)
5220 @param EAX Lower 32-bits of MSR value.
5221 @param EDX Upper 32-bits of MSR value.
5223 <b>Example usage</b>
5227 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS);
5228 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr);
5230 @note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.
5232 #define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7
5236 Package. Uncore C-box 12 perfmon counter 0.
5238 @param ECX MSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8)
5239 @param EAX Lower 32-bits of MSR value.
5240 @param EDX Upper 32-bits of MSR value.
5242 <b>Example usage</b>
5246 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0);
5247 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr);
5249 @note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.
5251 #define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8
5255 Package. Uncore C-box 12 perfmon counter 1.
5257 @param ECX MSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9)
5258 @param EAX Lower 32-bits of MSR value.
5259 @param EDX Upper 32-bits of MSR value.
5261 <b>Example usage</b>
5265 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1);
5266 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr);
5268 @note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.
5270 #define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9
5274 Package. Uncore C-box 12 perfmon counter 2.
5276 @param ECX MSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA)
5277 @param EAX Lower 32-bits of MSR value.
5278 @param EDX Upper 32-bits of MSR value.
5280 <b>Example usage</b>
5284 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2);
5285 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr);
5287 @note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.
5289 #define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA
5293 Package. Uncore C-box 12 perfmon counter 3.
5295 @param ECX MSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB)
5296 @param EAX Lower 32-bits of MSR value.
5297 @param EDX Upper 32-bits of MSR value.
5299 <b>Example usage</b>
5303 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3);
5304 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr);
5306 @note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.
5308 #define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB
5312 Package. Uncore C-box 13 perfmon local box wide control.
5314 @param ECX MSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0)
5315 @param EAX Lower 32-bits of MSR value.
5316 @param EDX Upper 32-bits of MSR value.
5318 <b>Example usage</b>
5322 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL);
5323 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr);
5325 @note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.
5327 #define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0
5331 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
5333 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1)
5334 @param EAX Lower 32-bits of MSR value.
5335 @param EDX Upper 32-bits of MSR value.
5337 <b>Example usage</b>
5341 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0);
5342 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr);
5344 @note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.
5346 #define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1
5350 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
5352 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2)
5353 @param EAX Lower 32-bits of MSR value.
5354 @param EDX Upper 32-bits of MSR value.
5356 <b>Example usage</b>
5360 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1);
5361 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr);
5363 @note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.
5365 #define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2
5369 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
5371 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3)
5372 @param EAX Lower 32-bits of MSR value.
5373 @param EDX Upper 32-bits of MSR value.
5375 <b>Example usage</b>
5379 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2);
5380 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr);
5382 @note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.
5384 #define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3
5388 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
5390 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4)
5391 @param EAX Lower 32-bits of MSR value.
5392 @param EDX Upper 32-bits of MSR value.
5394 <b>Example usage</b>
5398 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3);
5399 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr);
5401 @note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.
5403 #define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4
5407 Package. Uncore C-box 13 perfmon box wide filter0.
5409 @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5)
5410 @param EAX Lower 32-bits of MSR value.
5411 @param EDX Upper 32-bits of MSR value.
5413 <b>Example usage</b>
5417 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0);
5418 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr);
5420 @note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.
5422 #define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5
5426 Package. Uncore C-box 13 perfmon box wide filter1.
5428 @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6)
5429 @param EAX Lower 32-bits of MSR value.
5430 @param EDX Upper 32-bits of MSR value.
5432 <b>Example usage</b>
5436 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1);
5437 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr);
5439 @note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.
5441 #define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6
5445 Package. Uncore C-box 13 perfmon box wide status.
5447 @param ECX MSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7)
5448 @param EAX Lower 32-bits of MSR value.
5449 @param EDX Upper 32-bits of MSR value.
5451 <b>Example usage</b>
5455 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS);
5456 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr);
5458 @note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.
5460 #define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7
5464 Package. Uncore C-box 13 perfmon counter 0.
5466 @param ECX MSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8)
5467 @param EAX Lower 32-bits of MSR value.
5468 @param EDX Upper 32-bits of MSR value.
5470 <b>Example usage</b>
5474 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0);
5475 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr);
5477 @note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.
5479 #define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8
5483 Package. Uncore C-box 13 perfmon counter 1.
5485 @param ECX MSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9)
5486 @param EAX Lower 32-bits of MSR value.
5487 @param EDX Upper 32-bits of MSR value.
5489 <b>Example usage</b>
5493 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1);
5494 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr);
5496 @note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.
5498 #define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9
5502 Package. Uncore C-box 13 perfmon counter 2.
5504 @param ECX MSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA)
5505 @param EAX Lower 32-bits of MSR value.
5506 @param EDX Upper 32-bits of MSR value.
5508 <b>Example usage</b>
5512 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2);
5513 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr);
5515 @note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.
5517 #define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA
5521 Package. Uncore C-box 13 perfmon counter 3.
5523 @param ECX MSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB)
5524 @param EAX Lower 32-bits of MSR value.
5525 @param EDX Upper 32-bits of MSR value.
5527 <b>Example usage</b>
5531 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3);
5532 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr);
5534 @note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.
5536 #define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB
5540 Package. Uncore C-box 14 perfmon local box wide control.
5542 @param ECX MSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0)
5543 @param EAX Lower 32-bits of MSR value.
5544 @param EDX Upper 32-bits of MSR value.
5546 <b>Example usage</b>
5550 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL);
5551 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr);
5553 @note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.
5555 #define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0
5559 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
5561 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1)
5562 @param EAX Lower 32-bits of MSR value.
5563 @param EDX Upper 32-bits of MSR value.
5565 <b>Example usage</b>
5569 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0);
5570 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr);
5572 @note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.
5574 #define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1
5578 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
5580 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2)
5581 @param EAX Lower 32-bits of MSR value.
5582 @param EDX Upper 32-bits of MSR value.
5584 <b>Example usage</b>
5588 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1);
5589 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr);
5591 @note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.
5593 #define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2
5597 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
5599 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3)
5600 @param EAX Lower 32-bits of MSR value.
5601 @param EDX Upper 32-bits of MSR value.
5603 <b>Example usage</b>
5607 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2);
5608 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr);
5610 @note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.
5612 #define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3
5616 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
5618 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4)
5619 @param EAX Lower 32-bits of MSR value.
5620 @param EDX Upper 32-bits of MSR value.
5622 <b>Example usage</b>
5626 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3);
5627 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr);
5629 @note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.
5631 #define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4
5635 Package. Uncore C-box 14 perfmon box wide filter0.
5637 @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5)
5638 @param EAX Lower 32-bits of MSR value.
5639 @param EDX Upper 32-bits of MSR value.
5641 <b>Example usage</b>
5645 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER);
5646 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr);
5648 @note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.
5650 #define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5
5654 Package. Uncore C-box 14 perfmon box wide filter1.
5656 @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6)
5657 @param EAX Lower 32-bits of MSR value.
5658 @param EDX Upper 32-bits of MSR value.
5660 <b>Example usage</b>
5664 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1);
5665 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr);
5667 @note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.
5669 #define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6
5673 Package. Uncore C-box 14 perfmon box wide status.
5675 @param ECX MSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7)
5676 @param EAX Lower 32-bits of MSR value.
5677 @param EDX Upper 32-bits of MSR value.
5679 <b>Example usage</b>
5683 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS);
5684 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr);
5686 @note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.
5688 #define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7
5692 Package. Uncore C-box 14 perfmon counter 0.
5694 @param ECX MSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8)
5695 @param EAX Lower 32-bits of MSR value.
5696 @param EDX Upper 32-bits of MSR value.
5698 <b>Example usage</b>
5702 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0);
5703 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr);
5705 @note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.
5707 #define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8
5711 Package. Uncore C-box 14 perfmon counter 1.
5713 @param ECX MSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9)
5714 @param EAX Lower 32-bits of MSR value.
5715 @param EDX Upper 32-bits of MSR value.
5717 <b>Example usage</b>
5721 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1);
5722 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr);
5724 @note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.
5726 #define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9
5730 Package. Uncore C-box 14 perfmon counter 2.
5732 @param ECX MSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA)
5733 @param EAX Lower 32-bits of MSR value.
5734 @param EDX Upper 32-bits of MSR value.
5736 <b>Example usage</b>
5740 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2);
5741 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr);
5743 @note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.
5745 #define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA
5749 Package. Uncore C-box 14 perfmon counter 3.
5751 @param ECX MSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB)
5752 @param EAX Lower 32-bits of MSR value.
5753 @param EDX Upper 32-bits of MSR value.
5755 <b>Example usage</b>
5759 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3);
5760 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr);
5762 @note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.
5764 #define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB
5768 Package. Uncore C-box 15 perfmon local box wide control.
5770 @param ECX MSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0)
5771 @param EAX Lower 32-bits of MSR value.
5772 @param EDX Upper 32-bits of MSR value.
5774 <b>Example usage</b>
5778 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL);
5779 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr);
5781 @note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.
5783 #define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0
5787 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.
5789 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1)
5790 @param EAX Lower 32-bits of MSR value.
5791 @param EDX Upper 32-bits of MSR value.
5793 <b>Example usage</b>
5797 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0);
5798 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr);
5800 @note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.
5802 #define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1
5806 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.
5808 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2)
5809 @param EAX Lower 32-bits of MSR value.
5810 @param EDX Upper 32-bits of MSR value.
5812 <b>Example usage</b>
5816 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1);
5817 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr);
5819 @note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.
5821 #define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2
5825 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.
5827 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3)
5828 @param EAX Lower 32-bits of MSR value.
5829 @param EDX Upper 32-bits of MSR value.
5831 <b>Example usage</b>
5835 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2);
5836 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr);
5838 @note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.
5840 #define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3
5844 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.
5846 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4)
5847 @param EAX Lower 32-bits of MSR value.
5848 @param EDX Upper 32-bits of MSR value.
5850 <b>Example usage</b>
5854 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3);
5855 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr);
5857 @note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.
5859 #define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4
5863 Package. Uncore C-box 15 perfmon box wide filter0.
5865 @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5)
5866 @param EAX Lower 32-bits of MSR value.
5867 @param EDX Upper 32-bits of MSR value.
5869 <b>Example usage</b>
5873 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0);
5874 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr);
5876 @note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.
5878 #define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5
5882 Package. Uncore C-box 15 perfmon box wide filter1.
5884 @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6)
5885 @param EAX Lower 32-bits of MSR value.
5886 @param EDX Upper 32-bits of MSR value.
5888 <b>Example usage</b>
5892 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1);
5893 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr);
5895 @note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.
5897 #define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6
5901 Package. Uncore C-box 15 perfmon box wide status.
5903 @param ECX MSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7)
5904 @param EAX Lower 32-bits of MSR value.
5905 @param EDX Upper 32-bits of MSR value.
5907 <b>Example usage</b>
5911 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS);
5912 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr);
5914 @note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.
5916 #define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7
5920 Package. Uncore C-box 15 perfmon counter 0.
5922 @param ECX MSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8)
5923 @param EAX Lower 32-bits of MSR value.
5924 @param EDX Upper 32-bits of MSR value.
5926 <b>Example usage</b>
5930 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0);
5931 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr);
5933 @note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.
5935 #define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8
5939 Package. Uncore C-box 15 perfmon counter 1.
5941 @param ECX MSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9)
5942 @param EAX Lower 32-bits of MSR value.
5943 @param EDX Upper 32-bits of MSR value.
5945 <b>Example usage</b>
5949 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1);
5950 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr);
5952 @note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.
5954 #define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9
5958 Package. Uncore C-box 15 perfmon counter 2.
5960 @param ECX MSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA)
5961 @param EAX Lower 32-bits of MSR value.
5962 @param EDX Upper 32-bits of MSR value.
5964 <b>Example usage</b>
5968 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2);
5969 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr);
5971 @note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.
5973 #define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA
5977 Package. Uncore C-box 15 perfmon counter 3.
5979 @param ECX MSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB)
5980 @param EAX Lower 32-bits of MSR value.
5981 @param EDX Upper 32-bits of MSR value.
5983 <b>Example usage</b>
5987 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3);
5988 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr);
5990 @note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.
5992 #define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB
5996 Package. Uncore C-box 16 perfmon for box-wide control.
5998 @param ECX MSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00)
5999 @param EAX Lower 32-bits of MSR value.
6000 @param EDX Upper 32-bits of MSR value.
6002 <b>Example usage</b>
6006 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL);
6007 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr);
6009 @note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.
6011 #define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00
6015 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.
6017 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01)
6018 @param EAX Lower 32-bits of MSR value.
6019 @param EDX Upper 32-bits of MSR value.
6021 <b>Example usage</b>
6025 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0);
6026 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr);
6028 @note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.
6030 #define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01
6034 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.
6036 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02)
6037 @param EAX Lower 32-bits of MSR value.
6038 @param EDX Upper 32-bits of MSR value.
6040 <b>Example usage</b>
6044 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1);
6045 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr);
6047 @note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.
6049 #define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02
6053 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.
6055 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03)
6056 @param EAX Lower 32-bits of MSR value.
6057 @param EDX Upper 32-bits of MSR value.
6059 <b>Example usage</b>
6063 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2);
6064 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr);
6066 @note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.
6068 #define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03
6072 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.
6074 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04)
6075 @param EAX Lower 32-bits of MSR value.
6076 @param EDX Upper 32-bits of MSR value.
6078 <b>Example usage</b>
6082 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3);
6083 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr);
6085 @note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.
6087 #define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04
6091 Package. Uncore C-box 16 perfmon box wide filter 0.
6093 @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05)
6094 @param EAX Lower 32-bits of MSR value.
6095 @param EDX Upper 32-bits of MSR value.
6097 <b>Example usage</b>
6101 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0);
6102 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr);
6104 @note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.
6106 #define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05
6110 Package. Uncore C-box 16 perfmon box wide filter 1.
6112 @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06)
6113 @param EAX Lower 32-bits of MSR value.
6114 @param EDX Upper 32-bits of MSR value.
6116 <b>Example usage</b>
6120 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1);
6121 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr);
6123 @note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.
6125 #define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06
6129 Package. Uncore C-box 16 perfmon box wide status.
6131 @param ECX MSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07)
6132 @param EAX Lower 32-bits of MSR value.
6133 @param EDX Upper 32-bits of MSR value.
6135 <b>Example usage</b>
6139 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS);
6140 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr);
6142 @note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.
6144 #define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07
6148 Package. Uncore C-box 16 perfmon counter 0.
6150 @param ECX MSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08)
6151 @param EAX Lower 32-bits of MSR value.
6152 @param EDX Upper 32-bits of MSR value.
6154 <b>Example usage</b>
6158 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0);
6159 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr);
6161 @note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.
6163 #define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08
6167 Package. Uncore C-box 16 perfmon counter 1.
6169 @param ECX MSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09)
6170 @param EAX Lower 32-bits of MSR value.
6171 @param EDX Upper 32-bits of MSR value.
6173 <b>Example usage</b>
6177 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1);
6178 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr);
6180 @note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.
6182 #define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09
6186 Package. Uncore C-box 16 perfmon counter 2.
6188 @param ECX MSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A)
6189 @param EAX Lower 32-bits of MSR value.
6190 @param EDX Upper 32-bits of MSR value.
6192 <b>Example usage</b>
6196 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2);
6197 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr);
6199 @note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.
6201 #define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A
6205 Package. Uncore C-box 16 perfmon counter 3.
6207 @param ECX MSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B)
6208 @param EAX Lower 32-bits of MSR value.
6209 @param EDX Upper 32-bits of MSR value.
6211 <b>Example usage</b>
6215 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3);
6216 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr);
6218 @note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.
6220 #define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B
6224 Package. Uncore C-box 17 perfmon for box-wide control.
6226 @param ECX MSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10)
6227 @param EAX Lower 32-bits of MSR value.
6228 @param EDX Upper 32-bits of MSR value.
6230 <b>Example usage</b>
6234 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL);
6235 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr);
6237 @note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.
6239 #define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10
6243 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.
6245 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11)
6246 @param EAX Lower 32-bits of MSR value.
6247 @param EDX Upper 32-bits of MSR value.
6249 <b>Example usage</b>
6253 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0);
6254 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr);
6256 @note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.
6258 #define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11
6262 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.
6264 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12)
6265 @param EAX Lower 32-bits of MSR value.
6266 @param EDX Upper 32-bits of MSR value.
6268 <b>Example usage</b>
6272 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1);
6273 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr);
6275 @note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.
6277 #define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12
6281 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.
6283 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13)
6284 @param EAX Lower 32-bits of MSR value.
6285 @param EDX Upper 32-bits of MSR value.
6287 <b>Example usage</b>
6291 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2);
6292 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr);
6294 @note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.
6296 #define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13
6300 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.
6302 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14)
6303 @param EAX Lower 32-bits of MSR value.
6304 @param EDX Upper 32-bits of MSR value.
6306 <b>Example usage</b>
6310 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3);
6311 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr);
6313 @note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.
6315 #define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14
6319 Package. Uncore C-box 17 perfmon box wide filter 0.
6321 @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15)
6322 @param EAX Lower 32-bits of MSR value.
6323 @param EDX Upper 32-bits of MSR value.
6325 <b>Example usage</b>
6329 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0);
6330 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr);
6332 @note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.
6334 #define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15
6338 Package. Uncore C-box 17 perfmon box wide filter1.
6340 @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16)
6341 @param EAX Lower 32-bits of MSR value.
6342 @param EDX Upper 32-bits of MSR value.
6344 <b>Example usage</b>
6348 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1);
6349 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr);
6351 @note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.
6353 #define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16
6356 Package. Uncore C-box 17 perfmon box wide status.
6358 @param ECX MSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17)
6359 @param EAX Lower 32-bits of MSR value.
6360 @param EDX Upper 32-bits of MSR value.
6362 <b>Example usage</b>
6366 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS);
6367 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr);
6369 @note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.
6371 #define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17
6375 Package. Uncore C-box 17 perfmon counter n.
6377 @param ECX MSR_HASWELL_E_C17_PMON_CTRn
6378 @param EAX Lower 32-bits of MSR value.
6379 @param EDX Upper 32-bits of MSR value.
6381 <b>Example usage</b>
6385 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);
6386 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);
6388 @note MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM.
6389 MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM.
6390 MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM.
6391 MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.
6394 #define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18
6395 #define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19
6396 #define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A
6397 #define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B