UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h

   1 /** @file
   2   MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
  10   This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18   @par Specification Reference:
  19   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
  20   December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-9.
  21
  22 **/
  23
  24 #ifndef __IVY_BRIDGE_MSR_H__
  25 #define __IVY_BRIDGE_MSR_H__
  26
  27 #include <Register/ArchitecturalMsr.h>
  28
  29 /**
  30   Package. See http://biosbits.org.
  31
  32   @param  ECX  MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE)
  33   @param  EAX  Lower 32-bits of MSR value.
  34                Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
  35   @param  EDX  Upper 32-bits of MSR value.
  36                Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
  37
  38   <b>Example usage</b>
  39   @code
  40   MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER  Msr;
  41
  42   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);
  43   AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
  44   @endcode
  45 **/
  46 #define MSR_IVY_BRIDGE_PLATFORM_INFO             0x000000CE
  47
  48 /**
  49   MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO
  50 **/
  51 typedef union {
  52   ///
  53   /// Individual bit fields
  54   ///
  55   struct {
  56     UINT32  Reserved1:8;
  57     ///
  58     /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
  59     /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
  60     /// MHz.
  61     ///
  62     UINT32  MaximumNonTurboRatio:8;
  63     UINT32  Reserved2:12;
  64     ///
  65     /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
  66     /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
  67     /// enabled, and when set to 0, indicates Programmable Ratio Limits for
  68     /// Turbo mode is disabled.
  69     ///
  70     UINT32  RatioLimit:1;
  71     ///
  72     /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
  73     /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
  74     /// and when set to 0, indicates TDP Limit for Turbo mode is not
  75     /// programmable.
  76     ///
  77     UINT32  TDPLimit:1;
  78     UINT32  Reserved3:2;
  79     ///
  80     /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O)  When set to 1,
  81     /// indicates that LPM is supported, and when set to 0, indicates LPM is
  82     /// not supported.
  83     ///
  84     UINT32  LowPowerModeSupport:1;
  85     ///
  86     /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
  87     /// TDP level available. 01: One additional TDP level available. 02: Two
  88     /// additional TDP level available. 11: Reserved.
  89     ///
  90     UINT32  ConfigTDPLevels:2;
  91     UINT32  Reserved4:5;
  92     ///
  93     /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
  94     /// minimum ratio (maximum efficiency) that the processor can operates, in
  95     /// units of 100MHz.
  96     ///
  97     UINT32  MaximumEfficiencyRatio:8;
  98     ///
  99     /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
 100     /// minimum supported operating ratio in units of 100 MHz.
 101     ///
 102     UINT32  MinimumOperatingRatio:8;
 103     UINT32  Reserved5:8;
 104   } Bits;
 105   ///
 106   /// All bit fields as a 64-bit value
 107   ///
 108   UINT64  Uint64;
 109 } MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER;
 110
 111
 112 /**
 113   Core. C-State Configuration Control (R/W)  Note: C-state values are
 114   processor specific C-state code names, unrelated to MWAIT extension C-state
 115   parameters or ACPI C-States. See http://biosbits.org.
 116
 117   @param  ECX  MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)
 118   @param  EAX  Lower 32-bits of MSR value.
 119                Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
 120   @param  EDX  Upper 32-bits of MSR value.
 121                Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
 122
 123   <b>Example usage</b>
 124   @code
 125   MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
 126
 127   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL);
 128   AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
 129   @endcode
 130 **/
 131 #define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL    0x000000E2
 132
 133 /**
 134   MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL
 135 **/
 136 typedef union {
 137   ///
 138   /// Individual bit fields
 139   ///
 140   struct {
 141     ///
 142     /// [Bits 2:0] Package C-State Limit (R/W)  Specifies the lowest
 143     /// processor-specific C-state code name (consuming the least power). for
 144     /// the package. The default is set as factory-configured package C-state
 145     /// limit. The following C-state code name encodings are supported: 000b:
 146     /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:
 147     /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:
 148     /// This field cannot be used to limit package C-state to C3.
 149     ///
 150     UINT32  Limit:3;
 151     UINT32  Reserved1:7;
 152     ///
 153     /// [Bit 10] I/O MWAIT Redirection Enable (R/W)  When set, will map
 154     /// IO_read instructions sent to IO register specified by
 155     /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
 156     ///
 157     UINT32  IO_MWAIT:1;
 158     UINT32  Reserved2:4;
 159     ///
 160     /// [Bit 15] CFG Lock (R/WO)  When set, lock bits 15:0 of this register
 161     /// until next reset.
 162     ///
 163     UINT32  CFGLock:1;
 164     UINT32  Reserved3:9;
 165     ///
 166     /// [Bit 25] C3 state auto demotion enable (R/W)  When set, the processor
 167     /// will conditionally demote C6/C7 requests to C3 based on uncore
 168     /// auto-demote information.
 169     ///
 170     UINT32  C3AutoDemotion:1;
 171     ///
 172     /// [Bit 26] C1 state auto demotion enable (R/W)  When set, the processor
 173     /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
 174     /// auto-demote information.
 175     ///
 176     UINT32  C1AutoDemotion:1;
 177     ///
 178     /// [Bit 27] Enable C3 undemotion (R/W)  When set, enables undemotion from
 179     /// demoted C3.
 180     ///
 181     UINT32  C3Undemotion:1;
 182     ///
 183     /// [Bit 28] Enable C1 undemotion (R/W)  When set, enables undemotion from
 184     /// demoted C1.
 185     ///
 186     UINT32  C1Undemotion:1;
 187     UINT32  Reserved4:3;
 188     UINT32  Reserved5:32;
 189   } Bits;
 190   ///
 191   /// All bit fields as a 32-bit value
 192   ///
 193   UINT32  Uint32;
 194   ///
 195   /// All bit fields as a 64-bit value
 196   ///
 197   UINT64  Uint64;
 198 } MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;
 199
 200
 201 /**
 202   Package. Base TDP Ratio (R/O).
 203
 204   @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648)
 205   @param  EAX  Lower 32-bits of MSR value.
 206                Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.
 207   @param  EDX  Upper 32-bits of MSR value.
 208                Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.
 209
 210   <b>Example usage</b>
 211   @code
 212   MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER  Msr;
 213
 214   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL);
 215   @endcode
 216 **/
 217 #define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL        0x00000648
 218
 219 /**
 220   MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL
 221 **/
 222 typedef union {
 223   ///
 224   /// Individual bit fields
 225   ///
 226   struct {
 227     ///
 228     /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this
 229     /// specific processor (in units of 100 MHz).
 230     ///
 231     UINT32  Config_TDP_Base:8;
 232     UINT32  Reserved1:24;
 233     UINT32  Reserved2:32;
 234   } Bits;
 235   ///
 236   /// All bit fields as a 32-bit value
 237   ///
 238   UINT32  Uint32;
 239   ///
 240   /// All bit fields as a 64-bit value
 241   ///
 242   UINT64  Uint64;
 243 } MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER;
 244
 245
 246 /**
 247   Package. ConfigTDP Level 1 ratio and power level (R/O).
 248
 249   @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 (0x00000649)
 250   @param  EAX  Lower 32-bits of MSR value.
 251                Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.
 252   @param  EDX  Upper 32-bits of MSR value.
 253                Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.
 254
 255   <b>Example usage</b>
 256   @code
 257   MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER  Msr;
 258
 259   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1);
 260   @endcode
 261 **/
 262 #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1         0x00000649
 263
 264 /**
 265   MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1
 266 **/
 267 typedef union {
 268   ///
 269   /// Individual bit fields
 270   ///
 271   struct {
 272     ///
 273     /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.
 274     ///
 275     UINT32  PKG_TDP_LVL1:15;
 276     UINT32  Reserved1:1;
 277     ///
 278     /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used
 279     /// for this specific processor.
 280     ///
 281     UINT32  Config_TDP_LVL1_Ratio:8;
 282     UINT32  Reserved2:8;
 283     ///
 284     /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP
 285     /// Level 1.
 286     ///
 287     UINT32  PKG_MAX_PWR_LVL1:15;
 288     UINT32  Reserved3:1;
 289     ///
 290     /// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP
 291     /// Level 1.
 292     ///
 293     UINT32  PKG_MIN_PWR_LVL1:15;
 294     UINT32  Reserved4:1;
 295   } Bits;
 296   ///
 297   /// All bit fields as a 64-bit value
 298   ///
 299   UINT64  Uint64;
 300 } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER;
 301
 302
 303 /**
 304   Package. ConfigTDP Level 2 ratio and power level (R/O).
 305
 306   @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 (0x0000064A)
 307   @param  EAX  Lower 32-bits of MSR value.
 308                Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.
 309   @param  EDX  Upper 32-bits of MSR value.
 310                Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.
 311
 312   <b>Example usage</b>
 313   @code
 314   MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER  Msr;
 315
 316   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2);
 317   @endcode
 318 **/
 319 #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2         0x0000064A
 320
 321 /**
 322   MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2
 323 **/
 324 typedef union {
 325   ///
 326   /// Individual bit fields
 327   ///
 328   struct {
 329     ///
 330     /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
 331     ///
 332     UINT32  PKG_TDP_LVL2:15;
 333     UINT32  Reserved1:1;
 334     ///
 335     /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used
 336     /// for this specific processor.
 337     ///
 338     UINT32  Config_TDP_LVL2_Ratio:8;
 339     UINT32  Reserved2:8;
 340     ///
 341     /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP
 342     /// Level 2.
 343     ///
 344     UINT32  PKG_MAX_PWR_LVL2:15;
 345     UINT32  Reserved3:1;
 346     ///
 347     /// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP
 348     /// Level 2.
 349     ///
 350     UINT32  PKG_MIN_PWR_LVL2:15;
 351     UINT32  Reserved4:1;
 352   } Bits;
 353   ///
 354   /// All bit fields as a 64-bit value
 355   ///
 356   UINT64  Uint64;
 357 } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER;
 358
 359
 360 /**
 361   Package. ConfigTDP Control (R/W).
 362
 363   @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL (0x0000064B)
 364   @param  EAX  Lower 32-bits of MSR value.
 365                Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.
 366   @param  EDX  Upper 32-bits of MSR value.
 367                Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.
 368
 369   <b>Example usage</b>
 370   @code
 371   MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER  Msr;
 372
 373   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL);
 374   AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64);
 375   @endcode
 376 **/
 377 #define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL        0x0000064B
 378
 379 /**
 380   MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL
 381 **/
 382 typedef union {
 383   ///
 384   /// Individual bit fields
 385   ///
 386   struct {
 387     ///
 388     /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.
 389     ///
 390     UINT32  TDP_LEVEL:2;
 391     UINT32  Reserved1:29;
 392     ///
 393     /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of
 394     /// this register is locked until a reset.
 395     ///
 396     UINT32  Config_TDP_Lock:1;
 397     UINT32  Reserved2:32;
 398   } Bits;
 399   ///
 400   /// All bit fields as a 32-bit value
 401   ///
 402   UINT32  Uint32;
 403   ///
 404   /// All bit fields as a 64-bit value
 405   ///
 406   UINT64  Uint64;
 407 } MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER;
 408
 409
 410 /**
 411   Package. ConfigTDP Control (R/W).
 412
 413   @param  ECX  MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO (0x0000064C)
 414   @param  EAX  Lower 32-bits of MSR value.
 415                Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.
 416   @param  EDX  Upper 32-bits of MSR value.
 417                Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.
 418
 419   <b>Example usage</b>
 420   @code
 421   MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER  Msr;
 422
 423   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO);
 424   AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64);
 425   @endcode
 426 **/
 427 #define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO    0x0000064C
 428
 429 /**
 430   MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO
 431 **/
 432 typedef union {
 433   ///
 434   /// Individual bit fields
 435   ///
 436   struct {
 437     ///
 438     /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
 439     /// field.
 440     ///
 441     UINT32  MAX_NON_TURBO_RATIO:8;
 442     UINT32  Reserved1:23;
 443     ///
 444     /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
 445     /// content of this register is locked until a reset.
 446     ///
 447     UINT32  TURBO_ACTIVATION_RATIO_Lock:1;
 448     UINT32  Reserved2:32;
 449   } Bits;
 450   ///
 451   /// All bit fields as a 32-bit value
 452   ///
 453   UINT32  Uint32;
 454   ///
 455   /// All bit fields as a 64-bit value
 456   ///
 457   UINT64  Uint64;
 458 } MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER;
 459
 460
 461 /**
 462   Package. Protected Processor Inventory Number Enable Control (R/W).
 463
 464   @param  ECX  MSR_IVY_BRIDGE_PPIN_CTL (0x0000004E)
 465   @param  EAX  Lower 32-bits of MSR value.
 466                Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.
 467   @param  EDX  Upper 32-bits of MSR value.
 468                Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.
 469
 470   <b>Example usage</b>
 471   @code
 472   MSR_IVY_BRIDGE_PPIN_CTL_REGISTER  Msr;
 473
 474   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
 475   AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64);
 476   @endcode
 477 **/
 478 #define MSR_IVY_BRIDGE_PPIN_CTL                  0x0000004E
 479
 480 /**
 481   MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL
 482 **/
 483 typedef union {
 484   ///
 485   /// Individual bit fields
 486   ///
 487   struct {
 488     ///
 489     /// [Bit 0] LockOut (R/WO) Set 1to prevent further writes to MSR_PPIN_CTL.
 490     /// Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit
 491     /// 1] is clear, Default is 0. BIOS should provide an opt-in menu to
 492     /// enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged
 493     /// inventory initialization agent to access MSR_PPIN. After reading
 494     /// MSR_PPIN, the privileged inventory initialization agent should write
 495     /// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
 496     /// prevent unauthorized modification to MSR_PPIN_CTL.
 497     ///
 498     UINT32  LockOut:1;
 499     ///
 500     /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
 501     /// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will
 502     /// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default
 503     /// is 0.
 504     ///
 505     UINT32  Enable_PPIN:1;
 506     UINT32  Reserved1:30;
 507     UINT32  Reserved2:32;
 508   } Bits;
 509   ///
 510   /// All bit fields as a 32-bit value
 511   ///
 512   UINT32  Uint32;
 513   ///
 514   /// All bit fields as a 64-bit value
 515   ///
 516   UINT64  Uint64;
 517 } MSR_IVY_BRIDGE_PPIN_CTL_REGISTER;
 518
 519
 520 /**
 521   Package. Protected Processor Inventory Number (R/O). Protected Processor
 522   Inventory Number (R/O) A unique value within a given CPUID
 523   family/model/stepping signature that a privileged inventory initialization
 524   agent can access to identify each physical processor, when access to
 525   MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if
 526   MSR_PPIN_CTL[bits 1:0] = '10b'.
 527
 528   @param  ECX  MSR_IVY_BRIDGE_PPIN (0x0000004F)
 529   @param  EAX  Lower 32-bits of MSR value.
 530   @param  EDX  Upper 32-bits of MSR value.
 531
 532   <b>Example usage</b>
 533   @code
 534   UINT64  Msr;
 535
 536   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN);
 537   @endcode
 538 **/
 539 #define MSR_IVY_BRIDGE_PPIN                      0x0000004F
 540
 541
 542 /**
 543   Package. See http://biosbits.org.
 544
 545   @param  ECX  MSR_IVY_BRIDGE_PLATFORM_INFO_1 (0x000000CE)
 546   @param  EAX  Lower 32-bits of MSR value.
 547                Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.
 548   @param  EDX  Upper 32-bits of MSR value.
 549                Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.
 550
 551   <b>Example usage</b>
 552   @code
 553   MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER  Msr;
 554
 555   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
 556   AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64);
 557   @endcode
 558 **/
 559 #define MSR_IVY_BRIDGE_PLATFORM_INFO_1           0x000000CE
 560
 561 /**
 562   MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1
 563 **/
 564 typedef union {
 565   ///
 566   /// Individual bit fields
 567   ///
 568   struct {
 569     UINT32  Reserved1:8;
 570     ///
 571     /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
 572     /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
 573     /// MHz.
 574     ///
 575     UINT32  MaximumNonTurboRatio:8;
 576     UINT32  Reserved2:7;
 577     ///
 578     /// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that
 579     /// Protected Processor Inventory Number (PPIN) capability can be enabled
 580     /// for privileged system inventory agent to read PPIN from MSR_PPIN. When
 581     /// set to 0, PPIN capability is not supported. An attempt to access
 582     /// MSR_PPIN_CTL or MSR_PPIN will cause #GP.
 583     ///
 584     UINT32  PPIN_CAP:1;
 585     UINT32  Reserved3:4;
 586     ///
 587     /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
 588     /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
 589     /// enabled, and when set to 0, indicates Programmable Ratio Limits for
 590     /// Turbo mode is disabled.
 591     ///
 592     UINT32  RatioLimit:1;
 593     ///
 594     /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
 595     /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
 596     /// and when set to 0, indicates TDP Limit for Turbo mode is not
 597     /// programmable.
 598     ///
 599     UINT32  TDPLimit:1;
 600     ///
 601     /// [Bit 30] Package. Programmable TJ OFFSET (R/O)  When set to 1,
 602     /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to
 603     /// specify an temperature offset.
 604     ///
 605     UINT32  TJOFFSET:1;
 606     UINT32  Reserved4:1;
 607     UINT32  Reserved5:8;
 608     ///
 609     /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
 610     /// minimum ratio (maximum efficiency) that the processor can operates, in
 611     /// units of 100MHz.
 612     ///
 613     UINT32  MaximumEfficiencyRatio:8;
 614     UINT32  Reserved6:16;
 615   } Bits;
 616   ///
 617   /// All bit fields as a 64-bit value
 618   ///
 619   UINT64  Uint64;
 620 } MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER;
 621
 622
 623 /**
 624   Package. MC Bank Error Configuration (R/W).
 625
 626   @param  ECX  MSR_IVY_BRIDGE_ERROR_CONTROL (0x0000017F)
 627   @param  EAX  Lower 32-bits of MSR value.
 628                Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.
 629   @param  EDX  Upper 32-bits of MSR value.
 630                Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.
 631
 632   <b>Example usage</b>
 633   @code
 634   MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER  Msr;
 635
 636   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL);
 637   AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
 638   @endcode
 639 **/
 640 #define MSR_IVY_BRIDGE_ERROR_CONTROL             0x0000017F
 641
 642 /**
 643   MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL
 644 **/
 645 typedef union {
 646   ///
 647   /// Individual bit fields
 648   ///
 649   struct {
 650     UINT32  Reserved1:1;
 651     ///
 652     /// [Bit 1] MemError Log Enable (R/W)  When set, enables IMC status bank
 653     /// to log additional info in bits 36:32.
 654     ///
 655     UINT32  MemErrorLogEnable:1;
 656     UINT32  Reserved2:30;
 657     UINT32  Reserved3:32;
 658   } Bits;
 659   ///
 660   /// All bit fields as a 32-bit value
 661   ///
 662   UINT32  Uint32;
 663   ///
 664   /// All bit fields as a 64-bit value
 665   ///
 666   UINT64  Uint64;
 667 } MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER;
 668
 669
 670 /**
 671   Package.
 672
 673   @param  ECX  MSR_IVY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)
 674   @param  EAX  Lower 32-bits of MSR value.
 675                Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
 676   @param  EDX  Upper 32-bits of MSR value.
 677                Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
 678
 679   <b>Example usage</b>
 680   @code
 681   MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER  Msr;
 682
 683   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET);
 684   AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
 685   @endcode
 686 **/
 687 #define MSR_IVY_BRIDGE_TEMPERATURE_TARGET        0x000001A2
 688
 689 /**
 690   MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET
 691 **/
 692 typedef union {
 693   ///
 694   /// Individual bit fields
 695   ///
 696   struct {
 697     UINT32  Reserved1:16;
 698     ///
 699     /// [Bits 23:16] Temperature Target (RO)  The minimum temperature at which
 700     /// PROCHOT# will be asserted. The value is degree C.
 701     ///
 702     UINT32  TemperatureTarget:8;
 703     ///
 704     /// [Bits 27:24] TCC Activation Offset (R/W)  Specifies a temperature
 705     /// offset in degrees C from the temperature target (bits 23:16). PROCHOT#
 706     /// will assert at the offset target temperature. Write is permitted only
 707     /// MSR_PLATFORM_INFO.[30] is set.
 708     ///
 709     UINT32  TCCActivationOffset:4;
 710     UINT32  Reserved2:4;
 711     UINT32  Reserved3:32;
 712   } Bits;
 713   ///
 714   /// All bit fields as a 32-bit value
 715   ///
 716   UINT32  Uint32;
 717   ///
 718   /// All bit fields as a 64-bit value
 719   ///
 720   UINT64  Uint64;
 721 } MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER;
 722
 723
 724 /**
 725   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
 726   RW if MSR_PLATFORM_INFO.[28] = 1.
 727
 728   @param  ECX  MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 (0x000001AE)
 729   @param  EAX  Lower 32-bits of MSR value.
 730                Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.
 731   @param  EDX  Upper 32-bits of MSR value.
 732                Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.
 733
 734   <b>Example usage</b>
 735   @code
 736   MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER  Msr;
 737
 738   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1);
 739   @endcode
 740 **/
 741 #define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1        0x000001AE
 742
 743 /**
 744   MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1
 745 **/
 746 typedef union {
 747   ///
 748   /// Individual bit fields
 749   ///
 750   struct {
 751     ///
 752     /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
 753     /// limit of 9 core active.
 754     ///
 755     UINT32  Maximum9C:8;
 756     ///
 757     /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
 758     /// limit of 10core active.
 759     ///
 760     UINT32  Maximum10C:8;
 761     ///
 762     /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
 763     /// limit of 11 core active.
 764     ///
 765     UINT32  Maximum11C:8;
 766     ///
 767     /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
 768     /// limit of 12 core active.
 769     ///
 770     UINT32  Maximum12C:8;
 771     ///
 772     /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
 773     /// limit of 13 core active.
 774     ///
 775     UINT32  Maximum13C:8;
 776     ///
 777     /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
 778     /// limit of 14 core active.
 779     ///
 780     UINT32  Maximum14C:8;
 781     ///
 782     /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
 783     /// limit of 15 core active.
 784     ///
 785     UINT32  Maximum15C:8;
 786     UINT32  Reserved:7;
 787     ///
 788     /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
 789     /// the processor uses override configuration specified in
 790     /// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor
 791     /// uses factory-set configuration (Default).
 792     ///
 793     UINT32  TurboRatioLimitConfigurationSemaphore:1;
 794   } Bits;
 795   ///
 796   /// All bit fields as a 64-bit value
 797   ///
 798   UINT64  Uint64;
 799 } MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER;
 800
 801
 802 /**
 803   Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
 804   15.3.2.4, "IA32_MCi_MISC MSRs.". Bank MC5 reports MC error from the Intel
 805   QPI module.
 806
 807   * Bank MC6 reports MC error from the integrated I/O module.
 808   * Banks MC7 and MC 8 report MC error from the two home agents.
 809   * Banks MC9 through MC 16 report MC error from each channel of the integrated
 810     memory controllers.
 811   * Banks MC17 through MC31 reports MC error from a specific CBo
 812     (core broadcast) and its corresponding slice of L3.
 813
 814   @param  ECX  MSR_IVY_BRIDGE_MCi_CTL
 815   @param  EAX  Lower 32-bits of MSR value.
 816   @param  EDX  Upper 32-bits of MSR value.
 817
 818   <b>Example usage</b>
 819   @code
 820   UINT64  Msr;
 821
 822   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_CTL);
 823   AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_CTL, Msr);
 824   @endcode
 825   @{
 826 **/
 827 #define MSR_IVY_BRIDGE_MC5_CTL                   0x00000414
 828 #define MSR_IVY_BRIDGE_MC6_CTL                   0x00000418
 829 #define MSR_IVY_BRIDGE_MC7_CTL                   0x0000041C
 830 #define MSR_IVY_BRIDGE_MC8_CTL                   0x00000420
 831 #define MSR_IVY_BRIDGE_MC9_CTL                   0x00000424
 832 #define MSR_IVY_BRIDGE_MC10_CTL                  0x00000428
 833 #define MSR_IVY_BRIDGE_MC11_CTL                  0x0000042C
 834 #define MSR_IVY_BRIDGE_MC12_CTL                  0x00000430
 835 #define MSR_IVY_BRIDGE_MC13_CTL                  0x00000434
 836 #define MSR_IVY_BRIDGE_MC14_CTL                  0x00000438
 837 #define MSR_IVY_BRIDGE_MC15_CTL                  0x0000043C
 838 #define MSR_IVY_BRIDGE_MC16_CTL                  0x00000440
 839 #define MSR_IVY_BRIDGE_MC17_CTL                  0x00000444
 840 #define MSR_IVY_BRIDGE_MC18_CTL                  0x00000448
 841 #define MSR_IVY_BRIDGE_MC19_CTL                  0x0000044C
 842 #define MSR_IVY_BRIDGE_MC20_CTL                  0x00000450
 843 #define MSR_IVY_BRIDGE_MC21_CTL                  0x00000454
 844 #define MSR_IVY_BRIDGE_MC22_CTL                  0x00000458
 845 #define MSR_IVY_BRIDGE_MC23_CTL                  0x0000045C
 846 #define MSR_IVY_BRIDGE_MC24_CTL                  0x00000460
 847 #define MSR_IVY_BRIDGE_MC25_CTL                  0x00000464
 848 #define MSR_IVY_BRIDGE_MC26_CTL                  0x00000468
 849 #define MSR_IVY_BRIDGE_MC27_CTL                  0x0000046C
 850 #define MSR_IVY_BRIDGE_MC28_CTL                  0x00000470
 851 #define MSR_IVY_BRIDGE_MC29_CTL                  0x00000474
 852 #define MSR_IVY_BRIDGE_MC30_CTL                  0x00000478
 853 #define MSR_IVY_BRIDGE_MC31_CTL                  0x0000047C
 854 /// @}
 855
 856
 857 /**
 858   Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
 859   15.3.2.4, "IA32_MCi_MISC MSRs.".
 860
 861   Bank MC20 reports MC error from a specific CBo (core broadcast) and
 862   its corresponding slice of L3.
 863
 864   @param  ECX  MSR_IVY_BRIDGE_MCi_STATUS
 865   @param  EAX  Lower 32-bits of MSR value.
 866   @param  EDX  Upper 32-bits of MSR value.
 867
 868   <b>Example usage</b>
 869   @code
 870   UINT64  Msr;
 871
 872   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_STATUS);
 873   AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_STATUS, Msr);
 874   @endcode
 875   @{
 876 **/
 877 #define MSR_IVY_BRIDGE_MC5_STATUS                0x00000415
 878 #define MSR_IVY_BRIDGE_MC6_STATUS                0x00000419
 879 #define MSR_IVY_BRIDGE_MC7_STATUS                0x0000041D
 880 #define MSR_IVY_BRIDGE_MC8_STATUS                0x00000421
 881 #define MSR_IVY_BRIDGE_MC9_STATUS                0x00000425
 882 #define MSR_IVY_BRIDGE_MC10_STATUS               0x00000429
 883 #define MSR_IVY_BRIDGE_MC11_STATUS               0x0000042D
 884 #define MSR_IVY_BRIDGE_MC12_STATUS               0x00000431
 885 #define MSR_IVY_BRIDGE_MC13_STATUS               0x00000435
 886 #define MSR_IVY_BRIDGE_MC14_STATUS               0x00000439
 887 #define MSR_IVY_BRIDGE_MC15_STATUS               0x0000043D
 888 #define MSR_IVY_BRIDGE_MC16_STATUS               0x00000441
 889 #define MSR_IVY_BRIDGE_MC17_STATUS               0x00000445
 890 #define MSR_IVY_BRIDGE_MC18_STATUS               0x00000449
 891 #define MSR_IVY_BRIDGE_MC19_STATUS               0x0000044D
 892 #define MSR_IVY_BRIDGE_MC20_STATUS               0x00000451
 893 #define MSR_IVY_BRIDGE_MC21_STATUS               0x00000455
 894 #define MSR_IVY_BRIDGE_MC22_STATUS               0x00000459
 895 #define MSR_IVY_BRIDGE_MC23_STATUS               0x0000045D
 896 #define MSR_IVY_BRIDGE_MC24_STATUS               0x00000461
 897 #define MSR_IVY_BRIDGE_MC25_STATUS               0x00000465
 898 #define MSR_IVY_BRIDGE_MC26_STATUS               0x00000469
 899 #define MSR_IVY_BRIDGE_MC27_STATUS               0x0000046D
 900 #define MSR_IVY_BRIDGE_MC28_STATUS               0x00000471
 901 #define MSR_IVY_BRIDGE_MC29_STATUS               0x00000475
 902 #define MSR_IVY_BRIDGE_MC30_STATUS               0x00000479
 903 #define MSR_IVY_BRIDGE_MC31_STATUS               0x0000047D
 904 /// @}
 905
 906
 907 /**
 908   Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
 909   15.3.2.4, "IA32_MCi_MISC MSRs.".
 910
 911   @param  ECX  MSR_IVY_BRIDGE_MCi_ADDR
 912   @param  EAX  Lower 32-bits of MSR value.
 913   @param  EDX  Upper 32-bits of MSR value.
 914
 915   <b>Example usage</b>
 916   @code
 917   UINT64  Msr;
 918
 919   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_ADDR);
 920   AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_ADDR, Msr);
 921   @endcode
 922   @{
 923 **/
 924 #define MSR_IVY_BRIDGE_MC5_ADDR                  0x00000416
 925 #define MSR_IVY_BRIDGE_MC6_ADDR                  0x0000041A
 926 #define MSR_IVY_BRIDGE_MC7_ADDR                  0x0000041E
 927 #define MSR_IVY_BRIDGE_MC8_ADDR                  0x00000422
 928 #define MSR_IVY_BRIDGE_MC9_ADDR                  0x00000426
 929 #define MSR_IVY_BRIDGE_MC10_ADDR                 0x0000042A
 930 #define MSR_IVY_BRIDGE_MC11_ADDR                 0x0000042E
 931 #define MSR_IVY_BRIDGE_MC12_ADDR                 0x00000432
 932 #define MSR_IVY_BRIDGE_MC13_ADDR                 0x00000436
 933 #define MSR_IVY_BRIDGE_MC14_ADDR                 0x0000043A
 934 #define MSR_IVY_BRIDGE_MC15_ADDR                 0x0000043E
 935 #define MSR_IVY_BRIDGE_MC16_ADDR                 0x00000442
 936 #define MSR_IVY_BRIDGE_MC17_ADDR                 0x00000446
 937 #define MSR_IVY_BRIDGE_MC18_ADDR                 0x0000044A
 938 #define MSR_IVY_BRIDGE_MC19_ADDR                 0x0000044E
 939 #define MSR_IVY_BRIDGE_MC20_ADDR                 0x00000452
 940 #define MSR_IVY_BRIDGE_MC21_ADDR                 0x00000456
 941 #define MSR_IVY_BRIDGE_MC22_ADDR                 0x0000045A
 942 #define MSR_IVY_BRIDGE_MC23_ADDR                 0x0000045E
 943 #define MSR_IVY_BRIDGE_MC24_ADDR                 0x00000462
 944 #define MSR_IVY_BRIDGE_MC25_ADDR                 0x00000466
 945 #define MSR_IVY_BRIDGE_MC26_ADDR                 0x0000046A
 946 #define MSR_IVY_BRIDGE_MC27_ADDR                 0x0000046E
 947 #define MSR_IVY_BRIDGE_MC28_ADDR                 0x00000472
 948 #define MSR_IVY_BRIDGE_MC29_ADDR                 0x00000476
 949 #define MSR_IVY_BRIDGE_MC30_ADDR                 0x0000047A
 950 #define MSR_IVY_BRIDGE_MC31_ADDR                 0x0000047E
 951 /// @}
 952
 953
 954 /**
 955   Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
 956   15.3.2.4, "IA32_MCi_MISC MSRs.".
 957
 958   @param  ECX  MSR_IVY_BRIDGE_MCi_MISC
 959   @param  EAX  Lower 32-bits of MSR value.
 960   @param  EDX  Upper 32-bits of MSR value.
 961
 962   <b>Example usage</b>
 963   @code
 964   UINT64  Msr;
 965
 966   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_MISC);
 967   AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_MISC, Msr);
 968   @endcode
 969   @{
 970 **/
 971 #define MSR_IVY_BRIDGE_MC5_MISC                  0x00000417
 972 #define MSR_IVY_BRIDGE_MC6_MISC                  0x0000041B
 973 #define MSR_IVY_BRIDGE_MC7_MISC                  0x0000041F
 974 #define MSR_IVY_BRIDGE_MC8_MISC                  0x00000423
 975 #define MSR_IVY_BRIDGE_MC9_MISC                  0x00000427
 976 #define MSR_IVY_BRIDGE_MC10_MISC                 0x0000042B
 977 #define MSR_IVY_BRIDGE_MC11_MISC                 0x0000042F
 978 #define MSR_IVY_BRIDGE_MC12_MISC                 0x00000433
 979 #define MSR_IVY_BRIDGE_MC13_MISC                 0x00000437
 980 #define MSR_IVY_BRIDGE_MC14_MISC                 0x0000043B
 981 #define MSR_IVY_BRIDGE_MC15_MISC                 0x0000043F
 982 #define MSR_IVY_BRIDGE_MC16_MISC                 0x00000443
 983 #define MSR_IVY_BRIDGE_MC17_MISC                 0x00000447
 984 #define MSR_IVY_BRIDGE_MC18_MISC                 0x0000044B
 985 #define MSR_IVY_BRIDGE_MC19_MISC                 0x0000044F
 986 #define MSR_IVY_BRIDGE_MC20_MISC                 0x00000453
 987 #define MSR_IVY_BRIDGE_MC21_MISC                 0x00000457
 988 #define MSR_IVY_BRIDGE_MC22_MISC                 0x0000045B
 989 #define MSR_IVY_BRIDGE_MC23_MISC                 0x0000045F
 990 #define MSR_IVY_BRIDGE_MC24_MISC                 0x00000463
 991 #define MSR_IVY_BRIDGE_MC25_MISC                 0x00000467
 992 #define MSR_IVY_BRIDGE_MC26_MISC                 0x0000046B
 993 #define MSR_IVY_BRIDGE_MC27_MISC                 0x0000046F
 994 #define MSR_IVY_BRIDGE_MC28_MISC                 0x00000473
 995 #define MSR_IVY_BRIDGE_MC29_MISC                 0x00000477
 996 #define MSR_IVY_BRIDGE_MC30_MISC                 0x0000047B
 997 #define MSR_IVY_BRIDGE_MC31_MISC                 0x0000047F
 998 /// @}
 999
1000
1001 /**
1002   Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.
1003
1004   @param  ECX  MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)
1005   @param  EAX  Lower 32-bits of MSR value.
1006                Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
1007   @param  EDX  Upper 32-bits of MSR value.
1008                Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
1009
1010   <b>Example usage</b>
1011   @code
1012   MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER  Msr;
1013
1014   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);
1015   @endcode
1016 **/
1017 #define MSR_IVY_BRIDGE_IA32_MC6_MISC             0x0000041B
1018
1019 /**
1020   MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC
1021 **/
1022 typedef union {
1023   ///
1024   /// Individual bit fields
1025   ///
1026   struct {
1027     ///
1028     /// [Bits 5:0] Recoverable Address LSB.
1029     ///
1030     UINT32  RecoverableAddressLSB:6;
1031     ///
1032     /// [Bits 8:6] Address Mode.
1033     ///
1034     UINT32  AddressMode:3;
1035     UINT32  Reserved1:7;
1036     ///
1037     /// [Bits 31:16] PCI Express Requestor ID.
1038     ///
1039     UINT32  PCIExpressRequestorID:16;
1040     ///
1041     /// [Bits 39:32] PCI Express Segment Number.
1042     ///
1043     UINT32  PCIExpressSegmentNumber:8;
1044     UINT32  Reserved2:24;
1045   } Bits;
1046   ///
1047   /// All bit fields as a 64-bit value
1048   ///
1049   UINT64  Uint64;
1050 } MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;
1051
1052
1053 /**
1054   Package. Package RAPL Perf Status (R/O).
1055
1056   @param  ECX  MSR_IVY_BRIDGE_PKG_PERF_STATUS (0x00000613)
1057   @param  EAX  Lower 32-bits of MSR value.
1058   @param  EDX  Upper 32-bits of MSR value.
1059
1060   <b>Example usage</b>
1061   @code
1062   UINT64  Msr;
1063
1064   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS);
1065   @endcode
1066 **/
1067 #define MSR_IVY_BRIDGE_PKG_PERF_STATUS           0x00000613
1068
1069
1070 /**
1071   Package. DRAM RAPL Power Limit Control (R/W)  See Section 14.9.5, "DRAM RAPL
1072   Domain.".
1073
1074   @param  ECX  MSR_IVY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)
1075   @param  EAX  Lower 32-bits of MSR value.
1076   @param  EDX  Upper 32-bits of MSR value.
1077
1078   <b>Example usage</b>
1079   @code
1080   UINT64  Msr;
1081
1082   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT);
1083   AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr);
1084   @endcode
1085 **/
1086 #define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT          0x00000618
1087
1088
1089 /**
1090   Package. DRAM Energy Status (R/O)  See Section 14.9.5, "DRAM RAPL Domain.".
1091
1092   @param  ECX  MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)
1093   @param  EAX  Lower 32-bits of MSR value.
1094   @param  EDX  Upper 32-bits of MSR value.
1095
1096   <b>Example usage</b>
1097   @code
1098   UINT64  Msr;
1099
1100   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS);
1101   @endcode
1102 **/
1103 #define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS        0x00000619
1104
1105
1106 /**
1107   Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
1108   RAPL Domain.".
1109
1110   @param  ECX  MSR_IVY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)
1111   @param  EAX  Lower 32-bits of MSR value.
1112   @param  EDX  Upper 32-bits of MSR value.
1113
1114   <b>Example usage</b>
1115   @code
1116   UINT64  Msr;
1117
1118   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS);
1119   @endcode
1120 **/
1121 #define MSR_IVY_BRIDGE_DRAM_PERF_STATUS          0x0000061B
1122
1123
1124 /**
1125   Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
1126
1127   @param  ECX  MSR_IVY_BRIDGE_DRAM_POWER_INFO (0x0000061C)
1128   @param  EAX  Lower 32-bits of MSR value.
1129   @param  EDX  Upper 32-bits of MSR value.
1130
1131   <b>Example usage</b>
1132   @code
1133   UINT64  Msr;
1134
1135   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO);
1136   AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr);
1137   @endcode
1138 **/
1139 #define MSR_IVY_BRIDGE_DRAM_POWER_INFO           0x0000061C
1140
1141
1142 /**
1143   Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".
1144
1145   @param  ECX  MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)
1146   @param  EAX  Lower 32-bits of MSR value.
1147                Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.
1148   @param  EDX  Upper 32-bits of MSR value.
1149                Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.
1150
1151   <b>Example usage</b>
1152   @code
1153   MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER  Msr;
1154
1155   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE);
1156   AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64);
1157   @endcode
1158 **/
1159 #define MSR_IVY_BRIDGE_PEBS_ENABLE               0x000003F1
1160
1161 /**
1162   MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE
1163 **/
1164 typedef union {
1165   ///
1166   /// Individual bit fields
1167   ///
1168   struct {
1169     ///
1170     /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1171     ///
1172     UINT32  PEBS_EN_PMC0:1;
1173     ///
1174     /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
1175     ///
1176     UINT32  PEBS_EN_PMC1:1;
1177     ///
1178     /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
1179     ///
1180     UINT32  PEBS_EN_PMC2:1;
1181     ///
1182     /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
1183     ///
1184     UINT32  PEBS_EN_PMC3:1;
1185     UINT32  Reserved1:28;
1186     ///
1187     /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
1188     ///
1189     UINT32  LL_EN_PMC0:1;
1190     ///
1191     /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
1192     ///
1193     UINT32  LL_EN_PMC1:1;
1194     ///
1195     /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
1196     ///
1197     UINT32  LL_EN_PMC2:1;
1198     ///
1199     /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
1200     ///
1201     UINT32  LL_EN_PMC3:1;
1202     UINT32  Reserved2:28;
1203   } Bits;
1204   ///
1205   /// All bit fields as a 64-bit value
1206   ///
1207   UINT64  Uint64;
1208 } MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER;
1209
1210
1211 /**
1212   Package. Uncore perfmon per-socket global control.
1213
1214   @param  ECX  MSR_IVY_BRIDGE_PMON_GLOBAL_CTL (0x00000C00)
1215   @param  EAX  Lower 32-bits of MSR value.
1216   @param  EDX  Upper 32-bits of MSR value.
1217
1218   <b>Example usage</b>
1219   @code
1220   UINT64  Msr;
1221
1222   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL);
1223   AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr);
1224   @endcode
1225 **/
1226 #define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL           0x00000C00
1227
1228
1229 /**
1230   Package. Uncore perfmon per-socket global status.
1231
1232   @param  ECX  MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS (0x00000C01)
1233   @param  EAX  Lower 32-bits of MSR value.
1234   @param  EDX  Upper 32-bits of MSR value.
1235
1236   <b>Example usage</b>
1237   @code
1238   UINT64  Msr;
1239
1240   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS);
1241   AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr);
1242   @endcode
1243 **/
1244 #define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS        0x00000C01
1245
1246
1247 /**
1248   Package. Uncore perfmon per-socket global configuration.
1249
1250   @param  ECX  MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG (0x00000C06)
1251   @param  EAX  Lower 32-bits of MSR value.
1252   @param  EDX  Upper 32-bits of MSR value.
1253
1254   <b>Example usage</b>
1255   @code
1256   UINT64  Msr;
1257
1258   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG);
1259   AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr);
1260   @endcode
1261 **/
1262 #define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG        0x00000C06
1263
1264
1265 /**
1266   Package. Uncore U-box perfmon U-box wide status.
1267
1268   @param  ECX  MSR_IVY_BRIDGE_U_PMON_BOX_STATUS (0x00000C15)
1269   @param  EAX  Lower 32-bits of MSR value.
1270   @param  EDX  Upper 32-bits of MSR value.
1271
1272   <b>Example usage</b>
1273   @code
1274   UINT64  Msr;
1275
1276   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS);
1277   AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr);
1278   @endcode
1279 **/
1280 #define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS         0x00000C15
1281
1282
1283 /**
1284   Package. Uncore PCU perfmon box wide status.
1285
1286   @param  ECX  MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS (0x00000C35)
1287   @param  EAX  Lower 32-bits of MSR value.
1288   @param  EDX  Upper 32-bits of MSR value.
1289
1290   <b>Example usage</b>
1291   @code
1292   UINT64  Msr;
1293
1294   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS);
1295   AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr);
1296   @endcode
1297 **/
1298 #define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS       0x00000C35
1299
1300
1301 /**
1302   Package. Uncore C-box 0 perfmon box wide filter1.
1303
1304   @param  ECX  MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 (0x00000D1A)
1305   @param  EAX  Lower 32-bits of MSR value.
1306   @param  EDX  Upper 32-bits of MSR value.
1307
1308   <b>Example usage</b>
1309   @code
1310   UINT64  Msr;
1311
1312   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1);
1313   AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr);
1314   @endcode
1315 **/
1316 #define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1       0x00000D1A
1317
1318
1319 /**
1320   Package. Uncore C-box 1 perfmon box wide filter1.
1321
1322   @param  ECX  MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 (0x00000D3A)
1323   @param  EAX  Lower 32-bits of MSR value.
1324   @param  EDX  Upper 32-bits of MSR value.
1325
1326   <b>Example usage</b>
1327   @code
1328   UINT64  Msr;
1329
1330   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1);
1331   AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr);
1332   @endcode
1333 **/
1334 #define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1       0x00000D3A
1335
1336
1337 /**
1338   Package. Uncore C-box 2 perfmon box wide filter1.
1339
1340   @param  ECX  MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 (0x00000D5A)
1341   @param  EAX  Lower 32-bits of MSR value.
1342   @param  EDX  Upper 32-bits of MSR value.
1343
1344   <b>Example usage</b>
1345   @code
1346   UINT64  Msr;
1347
1348   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1);
1349   AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr);
1350   @endcode
1351 **/
1352 #define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1       0x00000D5A
1353
1354
1355 /**
1356   Package. Uncore C-box 3 perfmon box wide filter1.
1357
1358   @param  ECX  MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 (0x00000D7A)
1359   @param  EAX  Lower 32-bits of MSR value.
1360   @param  EDX  Upper 32-bits of MSR value.
1361
1362   <b>Example usage</b>
1363   @code
1364   UINT64  Msr;
1365
1366   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1);
1367   AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr);
1368   @endcode
1369 **/
1370 #define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1       0x00000D7A
1371
1372
1373 /**
1374   Package. Uncore C-box 4 perfmon box wide filter1.
1375
1376   @param  ECX  MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 (0x00000D9A)
1377   @param  EAX  Lower 32-bits of MSR value.
1378   @param  EDX  Upper 32-bits of MSR value.
1379
1380   <b>Example usage</b>
1381   @code
1382   UINT64  Msr;
1383
1384   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1);
1385   AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr);
1386   @endcode
1387 **/
1388 #define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1       0x00000D9A
1389
1390
1391 /**
1392   Package. Uncore C-box 5 perfmon box wide filter1.
1393
1394   @param  ECX  MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 (0x00000DBA)
1395   @param  EAX  Lower 32-bits of MSR value.
1396   @param  EDX  Upper 32-bits of MSR value.
1397
1398   <b>Example usage</b>
1399   @code
1400   UINT64  Msr;
1401
1402   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1);
1403   AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr);
1404   @endcode
1405 **/
1406 #define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1       0x00000DBA
1407
1408
1409 /**
1410   Package. Uncore C-box 6 perfmon box wide filter1.
1411
1412   @param  ECX  MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 (0x00000DDA)
1413   @param  EAX  Lower 32-bits of MSR value.
1414   @param  EDX  Upper 32-bits of MSR value.
1415
1416   <b>Example usage</b>
1417   @code
1418   UINT64  Msr;
1419
1420   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1);
1421   AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr);
1422   @endcode
1423 **/
1424 #define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1       0x00000DDA
1425
1426
1427 /**
1428   Package. Uncore C-box 7 perfmon box wide filter1.
1429
1430   @param  ECX  MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 (0x00000DFA)
1431   @param  EAX  Lower 32-bits of MSR value.
1432   @param  EDX  Upper 32-bits of MSR value.
1433
1434   <b>Example usage</b>
1435   @code
1436   UINT64  Msr;
1437
1438   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1);
1439   AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr);
1440   @endcode
1441 **/
1442 #define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1       0x00000DFA
1443
1444
1445 /**
1446   Package. Uncore C-box 8 perfmon local box wide control.
1447
1448   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_BOX_CTL (0x00000E04)
1449   @param  EAX  Lower 32-bits of MSR value.
1450   @param  EDX  Upper 32-bits of MSR value.
1451
1452   <b>Example usage</b>
1453   @code
1454   UINT64  Msr;
1455
1456   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL);
1457   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr);
1458   @endcode
1459 **/
1460 #define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL           0x00000E04
1461
1462
1463 /**
1464   Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
1465
1466   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 (0x00000E10)
1467   @param  EAX  Lower 32-bits of MSR value.
1468   @param  EDX  Upper 32-bits of MSR value.
1469
1470   <b>Example usage</b>
1471   @code
1472   UINT64  Msr;
1473
1474   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0);
1475   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr);
1476   @endcode
1477 **/
1478 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0          0x00000E10
1479
1480
1481 /**
1482   Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
1483
1484   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 (0x00000E11)
1485   @param  EAX  Lower 32-bits of MSR value.
1486   @param  EDX  Upper 32-bits of MSR value.
1487
1488   <b>Example usage</b>
1489   @code
1490   UINT64  Msr;
1491
1492   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1);
1493   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr);
1494   @endcode
1495 **/
1496 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1          0x00000E11
1497
1498
1499 /**
1500   Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
1501
1502   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 (0x00000E12)
1503   @param  EAX  Lower 32-bits of MSR value.
1504   @param  EDX  Upper 32-bits of MSR value.
1505
1506   <b>Example usage</b>
1507   @code
1508   UINT64  Msr;
1509
1510   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2);
1511   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr);
1512   @endcode
1513 **/
1514 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2          0x00000E12
1515
1516
1517 /**
1518   Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
1519
1520   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 (0x00000E13)
1521   @param  EAX  Lower 32-bits of MSR value.
1522   @param  EDX  Upper 32-bits of MSR value.
1523
1524   <b>Example usage</b>
1525   @code
1526   UINT64  Msr;
1527
1528   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3);
1529   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr);
1530   @endcode
1531 **/
1532 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3          0x00000E13
1533
1534
1535 /**
1536   Package. Uncore C-box 8 perfmon box wide filter.
1537
1538   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER (0x00000E14)
1539   @param  EAX  Lower 32-bits of MSR value.
1540   @param  EDX  Upper 32-bits of MSR value.
1541
1542   <b>Example usage</b>
1543   @code
1544   UINT64  Msr;
1545
1546   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER);
1547   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr);
1548   @endcode
1549 **/
1550 #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER        0x00000E14
1551
1552
1553 /**
1554   Package. Uncore C-box 8 perfmon counter 0.
1555
1556   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR0 (0x00000E16)
1557   @param  EAX  Lower 32-bits of MSR value.
1558   @param  EDX  Upper 32-bits of MSR value.
1559
1560   <b>Example usage</b>
1561   @code
1562   UINT64  Msr;
1563
1564   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0);
1565   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr);
1566   @endcode
1567 **/
1568 #define MSR_IVY_BRIDGE_C8_PMON_CTR0              0x00000E16
1569
1570
1571 /**
1572   Package. Uncore C-box 8 perfmon counter 1.
1573
1574   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR1 (0x00000E17)
1575   @param  EAX  Lower 32-bits of MSR value.
1576   @param  EDX  Upper 32-bits of MSR value.
1577
1578   <b>Example usage</b>
1579   @code
1580   UINT64  Msr;
1581
1582   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1);
1583   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr);
1584   @endcode
1585 **/
1586 #define MSR_IVY_BRIDGE_C8_PMON_CTR1              0x00000E17
1587
1588
1589 /**
1590   Package. Uncore C-box 8 perfmon counter 2.
1591
1592   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR2 (0x00000E18)
1593   @param  EAX  Lower 32-bits of MSR value.
1594   @param  EDX  Upper 32-bits of MSR value.
1595
1596   <b>Example usage</b>
1597   @code
1598   UINT64  Msr;
1599
1600   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2);
1601   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr);
1602   @endcode
1603 **/
1604 #define MSR_IVY_BRIDGE_C8_PMON_CTR2              0x00000E18
1605
1606
1607 /**
1608   Package. Uncore C-box 8 perfmon counter 3.
1609
1610   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR3 (0x00000E19)
1611   @param  EAX  Lower 32-bits of MSR value.
1612   @param  EDX  Upper 32-bits of MSR value.
1613
1614   <b>Example usage</b>
1615   @code
1616   UINT64  Msr;
1617
1618   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3);
1619   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr);
1620   @endcode
1621 **/
1622 #define MSR_IVY_BRIDGE_C8_PMON_CTR3              0x00000E19
1623
1624
1625 /**
1626   Package. Uncore C-box 8 perfmon box wide filter1.
1627
1628   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 (0x00000E1A)
1629   @param  EAX  Lower 32-bits of MSR value.
1630   @param  EDX  Upper 32-bits of MSR value.
1631
1632   <b>Example usage</b>
1633   @code
1634   UINT64  Msr;
1635
1636   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1);
1637   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr);
1638   @endcode
1639 **/
1640 #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1       0x00000E1A
1641
1642
1643 /**
1644   Package. Uncore C-box 9 perfmon local box wide control.
1645
1646   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_BOX_CTL (0x00000E24)
1647   @param  EAX  Lower 32-bits of MSR value.
1648   @param  EDX  Upper 32-bits of MSR value.
1649
1650   <b>Example usage</b>
1651   @code
1652   UINT64  Msr;
1653
1654   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL);
1655   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr);
1656   @endcode
1657 **/
1658 #define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL           0x00000E24
1659
1660
1661 /**
1662   Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
1663
1664   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 (0x00000E30)
1665   @param  EAX  Lower 32-bits of MSR value.
1666   @param  EDX  Upper 32-bits of MSR value.
1667
1668   <b>Example usage</b>
1669   @code
1670   UINT64  Msr;
1671
1672   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0);
1673   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr);
1674   @endcode
1675 **/
1676 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0          0x00000E30
1677
1678
1679 /**
1680   Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
1681
1682   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 (0x00000E31)
1683   @param  EAX  Lower 32-bits of MSR value.
1684   @param  EDX  Upper 32-bits of MSR value.
1685
1686   <b>Example usage</b>
1687   @code
1688   UINT64  Msr;
1689
1690   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1);
1691   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr);
1692   @endcode
1693 **/
1694 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1          0x00000E31
1695
1696
1697 /**
1698   Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
1699
1700   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 (0x00000E32)
1701   @param  EAX  Lower 32-bits of MSR value.
1702   @param  EDX  Upper 32-bits of MSR value.
1703
1704   <b>Example usage</b>
1705   @code
1706   UINT64  Msr;
1707
1708   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2);
1709   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr);
1710   @endcode
1711 **/
1712 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2          0x00000E32
1713
1714
1715 /**
1716   Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
1717
1718   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 (0x00000E33)
1719   @param  EAX  Lower 32-bits of MSR value.
1720   @param  EDX  Upper 32-bits of MSR value.
1721
1722   <b>Example usage</b>
1723   @code
1724   UINT64  Msr;
1725
1726   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3);
1727   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr);
1728   @endcode
1729 **/
1730 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3          0x00000E33
1731
1732
1733 /**
1734   Package. Uncore C-box 9 perfmon box wide filter.
1735
1736   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER (0x00000E34)
1737   @param  EAX  Lower 32-bits of MSR value.
1738   @param  EDX  Upper 32-bits of MSR value.
1739
1740   <b>Example usage</b>
1741   @code
1742   UINT64  Msr;
1743
1744   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER);
1745   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr);
1746   @endcode
1747 **/
1748 #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER        0x00000E34
1749
1750
1751 /**
1752   Package. Uncore C-box 9 perfmon counter 0.
1753
1754   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR0 (0x00000E36)
1755   @param  EAX  Lower 32-bits of MSR value.
1756   @param  EDX  Upper 32-bits of MSR value.
1757
1758   <b>Example usage</b>
1759   @code
1760   UINT64  Msr;
1761
1762   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0);
1763   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr);
1764   @endcode
1765 **/
1766 #define MSR_IVY_BRIDGE_C9_PMON_CTR0              0x00000E36
1767
1768
1769 /**
1770   Package. Uncore C-box 9 perfmon counter 1.
1771
1772   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR1 (0x00000E37)
1773   @param  EAX  Lower 32-bits of MSR value.
1774   @param  EDX  Upper 32-bits of MSR value.
1775
1776   <b>Example usage</b>
1777   @code
1778   UINT64  Msr;
1779
1780   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1);
1781   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr);
1782   @endcode
1783 **/
1784 #define MSR_IVY_BRIDGE_C9_PMON_CTR1              0x00000E37
1785
1786
1787 /**
1788   Package. Uncore C-box 9 perfmon counter 2.
1789
1790   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR2 (0x00000E38)
1791   @param  EAX  Lower 32-bits of MSR value.
1792   @param  EDX  Upper 32-bits of MSR value.
1793
1794   <b>Example usage</b>
1795   @code
1796   UINT64  Msr;
1797
1798   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2);
1799   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr);
1800   @endcode
1801 **/
1802 #define MSR_IVY_BRIDGE_C9_PMON_CTR2              0x00000E38
1803
1804
1805 /**
1806   Package. Uncore C-box 9 perfmon counter 3.
1807
1808   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR3 (0x00000E39)
1809   @param  EAX  Lower 32-bits of MSR value.
1810   @param  EDX  Upper 32-bits of MSR value.
1811
1812   <b>Example usage</b>
1813   @code
1814   UINT64  Msr;
1815
1816   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3);
1817   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr);
1818   @endcode
1819 **/
1820 #define MSR_IVY_BRIDGE_C9_PMON_CTR3              0x00000E39
1821
1822
1823 /**
1824   Package. Uncore C-box 9 perfmon box wide filter1.
1825
1826   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 (0x00000E3A)
1827   @param  EAX  Lower 32-bits of MSR value.
1828   @param  EDX  Upper 32-bits of MSR value.
1829
1830   <b>Example usage</b>
1831   @code
1832   UINT64  Msr;
1833
1834   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1);
1835   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr);
1836   @endcode
1837 **/
1838 #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1       0x00000E3A
1839
1840
1841 /**
1842   Package. Uncore C-box 10 perfmon local box wide control.
1843
1844   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_BOX_CTL (0x00000E44)
1845   @param  EAX  Lower 32-bits of MSR value.
1846   @param  EDX  Upper 32-bits of MSR value.
1847
1848   <b>Example usage</b>
1849   @code
1850   UINT64  Msr;
1851
1852   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL);
1853   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr);
1854   @endcode
1855 **/
1856 #define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL          0x00000E44
1857
1858
1859 /**
1860   Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
1861
1862   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 (0x00000E50)
1863   @param  EAX  Lower 32-bits of MSR value.
1864   @param  EDX  Upper 32-bits of MSR value.
1865
1866   <b>Example usage</b>
1867   @code
1868   UINT64  Msr;
1869
1870   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0);
1871   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr);
1872   @endcode
1873 **/
1874 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0         0x00000E50
1875
1876
1877 /**
1878   Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
1879
1880   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 (0x00000E51)
1881   @param  EAX  Lower 32-bits of MSR value.
1882   @param  EDX  Upper 32-bits of MSR value.
1883
1884   <b>Example usage</b>
1885   @code
1886   UINT64  Msr;
1887
1888   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1);
1889   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr);
1890   @endcode
1891 **/
1892 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1         0x00000E51
1893
1894
1895 /**
1896   Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
1897
1898   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 (0x00000E52)
1899   @param  EAX  Lower 32-bits of MSR value.
1900   @param  EDX  Upper 32-bits of MSR value.
1901
1902   <b>Example usage</b>
1903   @code
1904   UINT64  Msr;
1905
1906   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2);
1907   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr);
1908   @endcode
1909 **/
1910 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2         0x00000E52
1911
1912
1913 /**
1914   Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
1915
1916   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 (0x00000E53)
1917   @param  EAX  Lower 32-bits of MSR value.
1918   @param  EDX  Upper 32-bits of MSR value.
1919
1920   <b>Example usage</b>
1921   @code
1922   UINT64  Msr;
1923
1924   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3);
1925   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr);
1926   @endcode
1927 **/
1928 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3         0x00000E53
1929
1930
1931 /**
1932   Package. Uncore C-box 10 perfmon box wide filter.
1933
1934   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER (0x00000E54)
1935   @param  EAX  Lower 32-bits of MSR value.
1936   @param  EDX  Upper 32-bits of MSR value.
1937
1938   <b>Example usage</b>
1939   @code
1940   UINT64  Msr;
1941
1942   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER);
1943   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr);
1944   @endcode
1945 **/
1946 #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER       0x00000E54
1947
1948
1949 /**
1950   Package. Uncore C-box 10 perfmon counter 0.
1951
1952   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR0 (0x00000E56)
1953   @param  EAX  Lower 32-bits of MSR value.
1954   @param  EDX  Upper 32-bits of MSR value.
1955
1956   <b>Example usage</b>
1957   @code
1958   UINT64  Msr;
1959
1960   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0);
1961   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr);
1962   @endcode
1963 **/
1964 #define MSR_IVY_BRIDGE_C10_PMON_CTR0             0x00000E56
1965
1966
1967 /**
1968   Package. Uncore C-box 10 perfmon counter 1.
1969
1970   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR1 (0x00000E57)
1971   @param  EAX  Lower 32-bits of MSR value.
1972   @param  EDX  Upper 32-bits of MSR value.
1973
1974   <b>Example usage</b>
1975   @code
1976   UINT64  Msr;
1977
1978   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1);
1979   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr);
1980   @endcode
1981 **/
1982 #define MSR_IVY_BRIDGE_C10_PMON_CTR1             0x00000E57
1983
1984
1985 /**
1986   Package. Uncore C-box 10 perfmon counter 2.
1987
1988   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR2 (0x00000E58)
1989   @param  EAX  Lower 32-bits of MSR value.
1990   @param  EDX  Upper 32-bits of MSR value.
1991
1992   <b>Example usage</b>
1993   @code
1994   UINT64  Msr;
1995
1996   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2);
1997   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr);
1998   @endcode
1999 **/
2000 #define MSR_IVY_BRIDGE_C10_PMON_CTR2             0x00000E58
2001
2002
2003 /**
2004   Package. Uncore C-box 10 perfmon counter 3.
2005
2006   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR3 (0x00000E59)
2007   @param  EAX  Lower 32-bits of MSR value.
2008   @param  EDX  Upper 32-bits of MSR value.
2009
2010   <b>Example usage</b>
2011   @code
2012   UINT64  Msr;
2013
2014   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3);
2015   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr);
2016   @endcode
2017 **/
2018 #define MSR_IVY_BRIDGE_C10_PMON_CTR3             0x00000E59
2019
2020
2021 /**
2022   Package. Uncore C-box 10 perfmon box wide filter1.
2023
2024   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 (0x00000E5A)
2025   @param  EAX  Lower 32-bits of MSR value.
2026   @param  EDX  Upper 32-bits of MSR value.
2027
2028   <b>Example usage</b>
2029   @code
2030   UINT64  Msr;
2031
2032   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1);
2033   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr);
2034   @endcode
2035 **/
2036 #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1      0x00000E5A
2037
2038
2039 /**
2040   Package. Uncore C-box 11 perfmon local box wide control.
2041
2042   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_BOX_CTL (0x00000E64)
2043   @param  EAX  Lower 32-bits of MSR value.
2044   @param  EDX  Upper 32-bits of MSR value.
2045
2046   <b>Example usage</b>
2047   @code
2048   UINT64  Msr;
2049
2050   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL);
2051   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr);
2052   @endcode
2053 **/
2054 #define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL          0x00000E64
2055
2056
2057 /**
2058   Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
2059
2060   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 (0x00000E70)
2061   @param  EAX  Lower 32-bits of MSR value.
2062   @param  EDX  Upper 32-bits of MSR value.
2063
2064   <b>Example usage</b>
2065   @code
2066   UINT64  Msr;
2067
2068   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0);
2069   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr);
2070   @endcode
2071 **/
2072 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0         0x00000E70
2073
2074
2075 /**
2076   Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
2077
2078   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 (0x00000E71)
2079   @param  EAX  Lower 32-bits of MSR value.
2080   @param  EDX  Upper 32-bits of MSR value.
2081
2082   <b>Example usage</b>
2083   @code
2084   UINT64  Msr;
2085
2086   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1);
2087   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr);
2088   @endcode
2089 **/
2090 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1         0x00000E71
2091
2092
2093 /**
2094   Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
2095
2096   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 (0x00000E72)
2097   @param  EAX  Lower 32-bits of MSR value.
2098   @param  EDX  Upper 32-bits of MSR value.
2099
2100   <b>Example usage</b>
2101   @code
2102   UINT64  Msr;
2103
2104   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2);
2105   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr);
2106   @endcode
2107 **/
2108 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2         0x00000E72
2109
2110
2111 /**
2112   Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
2113
2114   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 (0x00000E73)
2115   @param  EAX  Lower 32-bits of MSR value.
2116   @param  EDX  Upper 32-bits of MSR value.
2117
2118   <b>Example usage</b>
2119   @code
2120   UINT64  Msr;
2121
2122   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3);
2123   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr);
2124   @endcode
2125 **/
2126 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3         0x00000E73
2127
2128
2129 /**
2130   Package. Uncore C-box 11 perfmon box wide filter.
2131
2132   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER (0x00000E74)
2133   @param  EAX  Lower 32-bits of MSR value.
2134   @param  EDX  Upper 32-bits of MSR value.
2135
2136   <b>Example usage</b>
2137   @code
2138   UINT64  Msr;
2139
2140   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER);
2141   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr);
2142   @endcode
2143 **/
2144 #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER       0x00000E74
2145
2146
2147 /**
2148   Package. Uncore C-box 11 perfmon counter 0.
2149
2150   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR0 (0x00000E76)
2151   @param  EAX  Lower 32-bits of MSR value.
2152   @param  EDX  Upper 32-bits of MSR value.
2153
2154   <b>Example usage</b>
2155   @code
2156   UINT64  Msr;
2157
2158   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0);
2159   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr);
2160   @endcode
2161 **/
2162 #define MSR_IVY_BRIDGE_C11_PMON_CTR0             0x00000E76
2163
2164
2165 /**
2166   Package. Uncore C-box 11 perfmon counter 1.
2167
2168   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR1 (0x00000E77)
2169   @param  EAX  Lower 32-bits of MSR value.
2170   @param  EDX  Upper 32-bits of MSR value.
2171
2172   <b>Example usage</b>
2173   @code
2174   UINT64  Msr;
2175
2176   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1);
2177   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr);
2178   @endcode
2179 **/
2180 #define MSR_IVY_BRIDGE_C11_PMON_CTR1             0x00000E77
2181
2182
2183 /**
2184   Package. Uncore C-box 11 perfmon counter 2.
2185
2186   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR2 (0x00000E78)
2187   @param  EAX  Lower 32-bits of MSR value.
2188   @param  EDX  Upper 32-bits of MSR value.
2189
2190   <b>Example usage</b>
2191   @code
2192   UINT64  Msr;
2193
2194   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2);
2195   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr);
2196   @endcode
2197 **/
2198 #define MSR_IVY_BRIDGE_C11_PMON_CTR2             0x00000E78
2199
2200
2201 /**
2202   Package. Uncore C-box 11 perfmon counter 3.
2203
2204   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR3 (0x00000E79)
2205   @param  EAX  Lower 32-bits of MSR value.
2206   @param  EDX  Upper 32-bits of MSR value.
2207
2208   <b>Example usage</b>
2209   @code
2210   UINT64  Msr;
2211
2212   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3);
2213   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr);
2214   @endcode
2215 **/
2216 #define MSR_IVY_BRIDGE_C11_PMON_CTR3             0x00000E79
2217
2218
2219 /**
2220   Package. Uncore C-box 11 perfmon box wide filter1.
2221
2222   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 (0x00000E7A)
2223   @param  EAX  Lower 32-bits of MSR value.
2224   @param  EDX  Upper 32-bits of MSR value.
2225
2226   <b>Example usage</b>
2227   @code
2228   UINT64  Msr;
2229
2230   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1);
2231   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr);
2232   @endcode
2233 **/
2234 #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1      0x00000E7A
2235
2236
2237 /**
2238   Package. Uncore C-box 12 perfmon local box wide control.
2239
2240   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_BOX_CTL (0x00000E84)
2241   @param  EAX  Lower 32-bits of MSR value.
2242   @param  EDX  Upper 32-bits of MSR value.
2243
2244   <b>Example usage</b>
2245   @code
2246   UINT64  Msr;
2247
2248   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL);
2249   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr);
2250   @endcode
2251 **/
2252 #define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL          0x00000E84
2253
2254
2255 /**
2256   Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
2257
2258   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 (0x00000E90)
2259   @param  EAX  Lower 32-bits of MSR value.
2260   @param  EDX  Upper 32-bits of MSR value.
2261
2262   <b>Example usage</b>
2263   @code
2264   UINT64  Msr;
2265
2266   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0);
2267   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr);
2268   @endcode
2269 **/
2270 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0         0x00000E90
2271
2272
2273 /**
2274   Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
2275
2276   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 (0x00000E91)
2277   @param  EAX  Lower 32-bits of MSR value.
2278   @param  EDX  Upper 32-bits of MSR value.
2279
2280   <b>Example usage</b>
2281   @code
2282   UINT64  Msr;
2283
2284   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1);
2285   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr);
2286   @endcode
2287 **/
2288 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1         0x00000E91
2289
2290
2291 /**
2292   Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
2293
2294   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 (0x00000E92)
2295   @param  EAX  Lower 32-bits of MSR value.
2296   @param  EDX  Upper 32-bits of MSR value.
2297
2298   <b>Example usage</b>
2299   @code
2300   UINT64  Msr;
2301
2302   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2);
2303   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr);
2304   @endcode
2305 **/
2306 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2         0x00000E92
2307
2308
2309 /**
2310   Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
2311
2312   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 (0x00000E93)
2313   @param  EAX  Lower 32-bits of MSR value.
2314   @param  EDX  Upper 32-bits of MSR value.
2315
2316   <b>Example usage</b>
2317   @code
2318   UINT64  Msr;
2319
2320   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3);
2321   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr);
2322   @endcode
2323 **/
2324 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3         0x00000E93
2325
2326
2327 /**
2328   Package. Uncore C-box 12 perfmon box wide filter.
2329
2330   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER (0x00000E94)
2331   @param  EAX  Lower 32-bits of MSR value.
2332   @param  EDX  Upper 32-bits of MSR value.
2333
2334   <b>Example usage</b>
2335   @code
2336   UINT64  Msr;
2337
2338   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER);
2339   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr);
2340   @endcode
2341 **/
2342 #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER       0x00000E94
2343
2344
2345 /**
2346   Package. Uncore C-box 12 perfmon counter 0.
2347
2348   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR0 (0x00000E96)
2349   @param  EAX  Lower 32-bits of MSR value.
2350   @param  EDX  Upper 32-bits of MSR value.
2351
2352   <b>Example usage</b>
2353   @code
2354   UINT64  Msr;
2355
2356   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0);
2357   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr);
2358   @endcode
2359 **/
2360 #define MSR_IVY_BRIDGE_C12_PMON_CTR0             0x00000E96
2361
2362
2363 /**
2364   Package. Uncore C-box 12 perfmon counter 1.
2365
2366   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR1 (0x00000E97)
2367   @param  EAX  Lower 32-bits of MSR value.
2368   @param  EDX  Upper 32-bits of MSR value.
2369
2370   <b>Example usage</b>
2371   @code
2372   UINT64  Msr;
2373
2374   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1);
2375   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr);
2376   @endcode
2377 **/
2378 #define MSR_IVY_BRIDGE_C12_PMON_CTR1             0x00000E97
2379
2380
2381 /**
2382   Package. Uncore C-box 12 perfmon counter 2.
2383
2384   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR2 (0x00000E98)
2385   @param  EAX  Lower 32-bits of MSR value.
2386   @param  EDX  Upper 32-bits of MSR value.
2387
2388   <b>Example usage</b>
2389   @code
2390   UINT64  Msr;
2391
2392   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2);
2393   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr);
2394   @endcode
2395 **/
2396 #define MSR_IVY_BRIDGE_C12_PMON_CTR2             0x00000E98
2397
2398
2399 /**
2400   Package. Uncore C-box 12 perfmon counter 3.
2401
2402   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR3 (0x00000E99)
2403   @param  EAX  Lower 32-bits of MSR value.
2404   @param  EDX  Upper 32-bits of MSR value.
2405
2406   <b>Example usage</b>
2407   @code
2408   UINT64  Msr;
2409
2410   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3);
2411   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr);
2412   @endcode
2413 **/
2414 #define MSR_IVY_BRIDGE_C12_PMON_CTR3             0x00000E99
2415
2416
2417 /**
2418   Package. Uncore C-box 12 perfmon box wide filter1.
2419
2420   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 (0x00000E9A)
2421   @param  EAX  Lower 32-bits of MSR value.
2422   @param  EDX  Upper 32-bits of MSR value.
2423
2424   <b>Example usage</b>
2425   @code
2426   UINT64  Msr;
2427
2428   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1);
2429   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr);
2430   @endcode
2431 **/
2432 #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1      0x00000E9A
2433
2434
2435 /**
2436   Package. Uncore C-box 13 perfmon local box wide control.
2437
2438   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_BOX_CTL (0x00000EA4)
2439   @param  EAX  Lower 32-bits of MSR value.
2440   @param  EDX  Upper 32-bits of MSR value.
2441
2442   <b>Example usage</b>
2443   @code
2444   UINT64  Msr;
2445
2446   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL);
2447   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr);
2448   @endcode
2449 **/
2450 #define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL          0x00000EA4
2451
2452
2453 /**
2454   Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
2455
2456   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 (0x00000EB0)
2457   @param  EAX  Lower 32-bits of MSR value.
2458   @param  EDX  Upper 32-bits of MSR value.
2459
2460   <b>Example usage</b>
2461   @code
2462   UINT64  Msr;
2463
2464   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0);
2465   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr);
2466   @endcode
2467 **/
2468 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0         0x00000EB0
2469
2470
2471 /**
2472   Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
2473
2474   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 (0x00000EB1)
2475   @param  EAX  Lower 32-bits of MSR value.
2476   @param  EDX  Upper 32-bits of MSR value.
2477
2478   <b>Example usage</b>
2479   @code
2480   UINT64  Msr;
2481
2482   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1);
2483   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr);
2484   @endcode
2485 **/
2486 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1         0x00000EB1
2487
2488
2489 /**
2490   Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
2491
2492   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 (0x00000EB2)
2493   @param  EAX  Lower 32-bits of MSR value.
2494   @param  EDX  Upper 32-bits of MSR value.
2495
2496   <b>Example usage</b>
2497   @code
2498   UINT64  Msr;
2499
2500   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2);
2501   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr);
2502   @endcode
2503 **/
2504 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2         0x00000EB2
2505
2506
2507 /**
2508   Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
2509
2510   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 (0x00000EB3)
2511   @param  EAX  Lower 32-bits of MSR value.
2512   @param  EDX  Upper 32-bits of MSR value.
2513
2514   <b>Example usage</b>
2515   @code
2516   UINT64  Msr;
2517
2518   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3);
2519   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr);
2520   @endcode
2521 **/
2522 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3         0x00000EB3
2523
2524
2525 /**
2526   Package. Uncore C-box 13 perfmon box wide filter.
2527
2528   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER (0x00000EB4)
2529   @param  EAX  Lower 32-bits of MSR value.
2530   @param  EDX  Upper 32-bits of MSR value.
2531
2532   <b>Example usage</b>
2533   @code
2534   UINT64  Msr;
2535
2536   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER);
2537   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr);
2538   @endcode
2539 **/
2540 #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER       0x00000EB4
2541
2542
2543 /**
2544   Package. Uncore C-box 13 perfmon counter 0.
2545
2546   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR0 (0x00000EB6)
2547   @param  EAX  Lower 32-bits of MSR value.
2548   @param  EDX  Upper 32-bits of MSR value.
2549
2550   <b>Example usage</b>
2551   @code
2552   UINT64  Msr;
2553
2554   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0);
2555   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr);
2556   @endcode
2557 **/
2558 #define MSR_IVY_BRIDGE_C13_PMON_CTR0             0x00000EB6
2559
2560
2561 /**
2562   Package. Uncore C-box 13 perfmon counter 1.
2563
2564   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR1 (0x00000EB7)
2565   @param  EAX  Lower 32-bits of MSR value.
2566   @param  EDX  Upper 32-bits of MSR value.
2567
2568   <b>Example usage</b>
2569   @code
2570   UINT64  Msr;
2571
2572   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1);
2573   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr);
2574   @endcode
2575 **/
2576 #define MSR_IVY_BRIDGE_C13_PMON_CTR1             0x00000EB7
2577
2578
2579 /**
2580   Package. Uncore C-box 13 perfmon counter 2.
2581
2582   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR2 (0x00000EB8)
2583   @param  EAX  Lower 32-bits of MSR value.
2584   @param  EDX  Upper 32-bits of MSR value.
2585
2586   <b>Example usage</b>
2587   @code
2588   UINT64  Msr;
2589
2590   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2);
2591   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr);
2592   @endcode
2593 **/
2594 #define MSR_IVY_BRIDGE_C13_PMON_CTR2             0x00000EB8
2595
2596
2597 /**
2598   Package. Uncore C-box 13 perfmon counter 3.
2599
2600   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR3 (0x00000EB9)
2601   @param  EAX  Lower 32-bits of MSR value.
2602   @param  EDX  Upper 32-bits of MSR value.
2603
2604   <b>Example usage</b>
2605   @code
2606   UINT64  Msr;
2607
2608   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3);
2609   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr);
2610   @endcode
2611 **/
2612 #define MSR_IVY_BRIDGE_C13_PMON_CTR3             0x00000EB9
2613
2614
2615 /**
2616   Package. Uncore C-box 13 perfmon box wide filter1.
2617
2618   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 (0x00000EBA)
2619   @param  EAX  Lower 32-bits of MSR value.
2620   @param  EDX  Upper 32-bits of MSR value.
2621
2622   <b>Example usage</b>
2623   @code
2624   UINT64  Msr;
2625
2626   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1);
2627   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr);
2628   @endcode
2629 **/
2630 #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1      0x00000EBA
2631
2632
2633 /**
2634   Package. Uncore C-box 14 perfmon local box wide control.
2635
2636   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_BOX_CTL (0x00000EC4)
2637   @param  EAX  Lower 32-bits of MSR value.
2638   @param  EDX  Upper 32-bits of MSR value.
2639
2640   <b>Example usage</b>
2641   @code
2642   UINT64  Msr;
2643
2644   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL);
2645   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr);
2646   @endcode
2647 **/
2648 #define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL          0x00000EC4
2649
2650
2651 /**
2652   Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
2653
2654   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 (0x00000ED0)
2655   @param  EAX  Lower 32-bits of MSR value.
2656   @param  EDX  Upper 32-bits of MSR value.
2657
2658   <b>Example usage</b>
2659   @code
2660   UINT64  Msr;
2661
2662   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0);
2663   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr);
2664   @endcode
2665 **/
2666 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0         0x00000ED0
2667
2668
2669 /**
2670   Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
2671
2672   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 (0x00000ED1)
2673   @param  EAX  Lower 32-bits of MSR value.
2674   @param  EDX  Upper 32-bits of MSR value.
2675
2676   <b>Example usage</b>
2677   @code
2678   UINT64  Msr;
2679
2680   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1);
2681   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr);
2682   @endcode
2683 **/
2684 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1         0x00000ED1
2685
2686
2687 /**
2688   Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
2689
2690   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 (0x00000ED2)
2691   @param  EAX  Lower 32-bits of MSR value.
2692   @param  EDX  Upper 32-bits of MSR value.
2693
2694   <b>Example usage</b>
2695   @code
2696   UINT64  Msr;
2697
2698   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2);
2699   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr);
2700   @endcode
2701 **/
2702 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2         0x00000ED2
2703
2704
2705 /**
2706   Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
2707
2708   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 (0x00000ED3)
2709   @param  EAX  Lower 32-bits of MSR value.
2710   @param  EDX  Upper 32-bits of MSR value.
2711
2712   <b>Example usage</b>
2713   @code
2714   UINT64  Msr;
2715
2716   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3);
2717   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr);
2718   @endcode
2719 **/
2720 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3         0x00000ED3
2721
2722
2723 /**
2724   Package. Uncore C-box 14 perfmon box wide filter.
2725
2726   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER (0x00000ED4)
2727   @param  EAX  Lower 32-bits of MSR value.
2728   @param  EDX  Upper 32-bits of MSR value.
2729
2730   <b>Example usage</b>
2731   @code
2732   UINT64  Msr;
2733
2734   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER);
2735   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr);
2736   @endcode
2737 **/
2738 #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER       0x00000ED4
2739
2740
2741 /**
2742   Package. Uncore C-box 14 perfmon counter 0.
2743
2744   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR0 (0x00000ED6)
2745   @param  EAX  Lower 32-bits of MSR value.
2746   @param  EDX  Upper 32-bits of MSR value.
2747
2748   <b>Example usage</b>
2749   @code
2750   UINT64  Msr;
2751
2752   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0);
2753   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr);
2754   @endcode
2755 **/
2756 #define MSR_IVY_BRIDGE_C14_PMON_CTR0             0x00000ED6
2757
2758
2759 /**
2760   Package. Uncore C-box 14 perfmon counter 1.
2761
2762   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR1 (0x00000ED7)
2763   @param  EAX  Lower 32-bits of MSR value.
2764   @param  EDX  Upper 32-bits of MSR value.
2765
2766   <b>Example usage</b>
2767   @code
2768   UINT64  Msr;
2769
2770   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1);
2771   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr);
2772   @endcode
2773 **/
2774 #define MSR_IVY_BRIDGE_C14_PMON_CTR1             0x00000ED7
2775
2776
2777 /**
2778   Package. Uncore C-box 14 perfmon counter 2.
2779
2780   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR2 (0x00000ED8)
2781   @param  EAX  Lower 32-bits of MSR value.
2782   @param  EDX  Upper 32-bits of MSR value.
2783
2784   <b>Example usage</b>
2785   @code
2786   UINT64  Msr;
2787
2788   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2);
2789   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr);
2790   @endcode
2791 **/
2792 #define MSR_IVY_BRIDGE_C14_PMON_CTR2             0x00000ED8
2793
2794
2795 /**
2796   Package. Uncore C-box 14 perfmon counter 3.
2797
2798   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR3 (0x00000ED9)
2799   @param  EAX  Lower 32-bits of MSR value.
2800   @param  EDX  Upper 32-bits of MSR value.
2801
2802   <b>Example usage</b>
2803   @code
2804   UINT64  Msr;
2805
2806   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3);
2807   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr);
2808   @endcode
2809 **/
2810 #define MSR_IVY_BRIDGE_C14_PMON_CTR3             0x00000ED9
2811
2812
2813 /**
2814   Package. Uncore C-box 14 perfmon box wide filter1.
2815
2816   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 (0x00000EDA)
2817   @param  EAX  Lower 32-bits of MSR value.
2818   @param  EDX  Upper 32-bits of MSR value.
2819
2820   <b>Example usage</b>
2821   @code
2822   UINT64  Msr;
2823
2824   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1);
2825   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr);
2826   @endcode
2827 **/
2828 #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1      0x00000EDA
2829
2830 #endif