2 MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.10.
24 #ifndef __IVY_BRIDGE_MSR_H__
25 #define __IVY_BRIDGE_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Intel processors based on the Ivy Bridge microarchitecture?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_IVY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x3A \
46 Package. See http://biosbits.org.
48 @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE)
49 @param EAX Lower 32-bits of MSR value.
50 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
51 @param EDX Upper 32-bits of MSR value.
52 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
56 MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER Msr;
58 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);
59 AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
61 @note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
63 #define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE
66 MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO
70 /// Individual bit fields
75 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
76 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
79 UINT32 MaximumNonTurboRatio
:8;
82 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
83 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
84 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
85 /// Turbo mode is disabled.
89 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
90 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
91 /// and when set to 0, indicates TDP Limit for Turbo mode is not
97 /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,
98 /// indicates that LPM is supported, and when set to 0, indicates LPM is
101 UINT32 LowPowerModeSupport
:1;
103 /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
104 /// TDP level available. 01: One additional TDP level available. 02: Two
105 /// additional TDP level available. 11: Reserved.
107 UINT32 ConfigTDPLevels
:2;
110 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
111 /// minimum ratio (maximum efficiency) that the processor can operates, in
114 UINT32 MaximumEfficiencyRatio
:8;
116 /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
117 /// minimum supported operating ratio in units of 100 MHz.
119 UINT32 MinimumOperatingRatio
:8;
123 /// All bit fields as a 64-bit value
126 } MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER
;
130 Core. C-State Configuration Control (R/W) Note: C-state values are
131 processor specific C-state code names, unrelated to MWAIT extension C-state
132 parameters or ACPI C-States. See http://biosbits.org.
134 @param ECX MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)
135 @param EAX Lower 32-bits of MSR value.
136 Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
137 @param EDX Upper 32-bits of MSR value.
138 Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
142 MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
144 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL);
145 AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
147 @note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
149 #define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2
152 MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL
156 /// Individual bit fields
160 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
161 /// processor-specific C-state code name (consuming the least power). for
162 /// the package. The default is set as factory-configured package C-state
163 /// limit. The following C-state code name encodings are supported: 000b:
164 /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:
165 /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:
166 /// This field cannot be used to limit package C-state to C3.
171 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
172 /// IO_read instructions sent to IO register specified by
173 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
178 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
179 /// until next reset.
184 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor
185 /// will conditionally demote C6/C7 requests to C3 based on uncore
186 /// auto-demote information.
188 UINT32 C3AutoDemotion
:1;
190 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor
191 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
192 /// auto-demote information.
194 UINT32 C1AutoDemotion
:1;
196 /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from
199 UINT32 C3Undemotion
:1;
201 /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from
204 UINT32 C1Undemotion
:1;
209 /// All bit fields as a 32-bit value
213 /// All bit fields as a 64-bit value
216 } MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER
;
220 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
223 @param ECX MSR_IVY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)
224 @param EAX Lower 32-bits of MSR value.
225 @param EDX Upper 32-bits of MSR value.
231 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PP0_ENERGY_STATUS);
233 @note MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
235 #define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639
239 Package. Base TDP Ratio (R/O).
241 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648)
242 @param EAX Lower 32-bits of MSR value.
243 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.
244 @param EDX Upper 32-bits of MSR value.
245 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.
249 MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER Msr;
251 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL);
253 @note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
255 #define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648
258 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL
262 /// Individual bit fields
266 /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this
267 /// specific processor (in units of 100 MHz).
269 UINT32 Config_TDP_Base
:8;
274 /// All bit fields as a 32-bit value
278 /// All bit fields as a 64-bit value
281 } MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER
;
285 Package. ConfigTDP Level 1 ratio and power level (R/O).
287 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 (0x00000649)
288 @param EAX Lower 32-bits of MSR value.
289 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.
290 @param EDX Upper 32-bits of MSR value.
291 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.
295 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER Msr;
297 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1);
299 @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
301 #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649
304 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1
308 /// Individual bit fields
312 /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.
314 UINT32 PKG_TDP_LVL1
:15;
317 /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used
318 /// for this specific processor.
320 UINT32 Config_TDP_LVL1_Ratio
:8;
323 /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP
326 UINT32 PKG_MAX_PWR_LVL1
:15;
329 /// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP
332 UINT32 PKG_MIN_PWR_LVL1
:15;
336 /// All bit fields as a 64-bit value
339 } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER
;
343 Package. ConfigTDP Level 2 ratio and power level (R/O).
345 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 (0x0000064A)
346 @param EAX Lower 32-bits of MSR value.
347 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.
348 @param EDX Upper 32-bits of MSR value.
349 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.
353 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER Msr;
355 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2);
357 @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
359 #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A
362 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2
366 /// Individual bit fields
370 /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
372 UINT32 PKG_TDP_LVL2
:15;
375 /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used
376 /// for this specific processor.
378 UINT32 Config_TDP_LVL2_Ratio
:8;
381 /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP
384 UINT32 PKG_MAX_PWR_LVL2
:15;
387 /// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP
390 UINT32 PKG_MIN_PWR_LVL2
:15;
394 /// All bit fields as a 64-bit value
397 } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER
;
401 Package. ConfigTDP Control (R/W).
403 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL (0x0000064B)
404 @param EAX Lower 32-bits of MSR value.
405 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.
406 @param EDX Upper 32-bits of MSR value.
407 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.
411 MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER Msr;
413 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL);
414 AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64);
416 @note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
418 #define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B
421 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL
425 /// Individual bit fields
429 /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.
434 /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of
435 /// this register is locked until a reset.
437 UINT32 Config_TDP_Lock
:1;
441 /// All bit fields as a 32-bit value
445 /// All bit fields as a 64-bit value
448 } MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER
;
452 Package. ConfigTDP Control (R/W).
454 @param ECX MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO (0x0000064C)
455 @param EAX Lower 32-bits of MSR value.
456 Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.
457 @param EDX Upper 32-bits of MSR value.
458 Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.
462 MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER Msr;
464 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO);
465 AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64);
467 @note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
469 #define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C
472 MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO
476 /// Individual bit fields
480 /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
483 UINT32 MAX_NON_TURBO_RATIO
:8;
486 /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
487 /// content of this register is locked until a reset.
489 UINT32 TURBO_ACTIVATION_RATIO_Lock
:1;
493 /// All bit fields as a 32-bit value
497 /// All bit fields as a 64-bit value
500 } MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER
;
504 Package. Protected Processor Inventory Number Enable Control (R/W).
506 @param ECX MSR_IVY_BRIDGE_PPIN_CTL (0x0000004E)
507 @param EAX Lower 32-bits of MSR value.
508 Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.
509 @param EDX Upper 32-bits of MSR value.
510 Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.
514 MSR_IVY_BRIDGE_PPIN_CTL_REGISTER Msr;
516 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
517 AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64);
519 @note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.
521 #define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E
524 MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL
528 /// Individual bit fields
532 /// [Bit 0] LockOut (R/WO) Set 1to prevent further writes to MSR_PPIN_CTL.
533 /// Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit
534 /// 1] is clear, Default is 0. BIOS should provide an opt-in menu to
535 /// enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged
536 /// inventory initialization agent to access MSR_PPIN. After reading
537 /// MSR_PPIN, the privileged inventory initialization agent should write
538 /// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
539 /// prevent unauthorized modification to MSR_PPIN_CTL.
543 /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
544 /// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will
545 /// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default
548 UINT32 Enable_PPIN
:1;
553 /// All bit fields as a 32-bit value
557 /// All bit fields as a 64-bit value
560 } MSR_IVY_BRIDGE_PPIN_CTL_REGISTER
;
564 Package. Protected Processor Inventory Number (R/O). Protected Processor
565 Inventory Number (R/O) A unique value within a given CPUID
566 family/model/stepping signature that a privileged inventory initialization
567 agent can access to identify each physical processor, when access to
568 MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if
569 MSR_PPIN_CTL[bits 1:0] = '10b'.
571 @param ECX MSR_IVY_BRIDGE_PPIN (0x0000004F)
572 @param EAX Lower 32-bits of MSR value.
573 @param EDX Upper 32-bits of MSR value.
579 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN);
581 @note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM.
583 #define MSR_IVY_BRIDGE_PPIN 0x0000004F
587 Package. See http://biosbits.org.
589 @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO_1 (0x000000CE)
590 @param EAX Lower 32-bits of MSR value.
591 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.
592 @param EDX Upper 32-bits of MSR value.
593 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.
597 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER Msr;
599 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
600 AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64);
602 @note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM.
604 #define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE
607 MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1
611 /// Individual bit fields
616 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
617 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
620 UINT32 MaximumNonTurboRatio
:8;
623 /// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that
624 /// Protected Processor Inventory Number (PPIN) capability can be enabled
625 /// for privileged system inventory agent to read PPIN from MSR_PPIN. When
626 /// set to 0, PPIN capability is not supported. An attempt to access
627 /// MSR_PPIN_CTL or MSR_PPIN will cause #GP.
632 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
633 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
634 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
635 /// Turbo mode is disabled.
639 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
640 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
641 /// and when set to 0, indicates TDP Limit for Turbo mode is not
646 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,
647 /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to
648 /// specify an temperature offset.
654 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
655 /// minimum ratio (maximum efficiency) that the processor can operates, in
658 UINT32 MaximumEfficiencyRatio
:8;
662 /// All bit fields as a 64-bit value
665 } MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER
;
669 Package. MC Bank Error Configuration (R/W).
671 @param ECX MSR_IVY_BRIDGE_ERROR_CONTROL (0x0000017F)
672 @param EAX Lower 32-bits of MSR value.
673 Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.
674 @param EDX Upper 32-bits of MSR value.
675 Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.
679 MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER Msr;
681 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL);
682 AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
684 @note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
686 #define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F
689 MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL
693 /// Individual bit fields
698 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
699 /// to log additional info in bits 36:32.
701 UINT32 MemErrorLogEnable
:1;
706 /// All bit fields as a 32-bit value
710 /// All bit fields as a 64-bit value
713 } MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER
;
719 @param ECX MSR_IVY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)
720 @param EAX Lower 32-bits of MSR value.
721 Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
722 @param EDX Upper 32-bits of MSR value.
723 Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
727 MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;
729 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET);
730 AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
732 @note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
734 #define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2
737 MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET
741 /// Individual bit fields
746 /// [Bits 23:16] Temperature Target (RO) The minimum temperature at which
747 /// PROCHOT# will be asserted. The value is degree C.
749 UINT32 TemperatureTarget
:8;
751 /// [Bits 27:24] TCC Activation Offset (R/W) Specifies a temperature
752 /// offset in degrees C from the temperature target (bits 23:16). PROCHOT#
753 /// will assert at the offset target temperature. Write is permitted only
754 /// MSR_PLATFORM_INFO.[30] is set.
756 UINT32 TCCActivationOffset
:4;
761 /// All bit fields as a 32-bit value
765 /// All bit fields as a 64-bit value
768 } MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER
;
772 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
773 RW if MSR_PLATFORM_INFO.[28] = 1.
775 @param ECX MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 (0x000001AE)
776 @param EAX Lower 32-bits of MSR value.
777 Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.
778 @param EDX Upper 32-bits of MSR value.
779 Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.
783 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER Msr;
785 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1);
787 @note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
789 #define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE
792 MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1
796 /// Individual bit fields
800 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
801 /// limit of 9 core active.
805 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
806 /// limit of 10core active.
810 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
811 /// limit of 11 core active.
815 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
816 /// limit of 12 core active.
820 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
821 /// limit of 13 core active.
825 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
826 /// limit of 14 core active.
830 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
831 /// limit of 15 core active.
836 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
837 /// the processor uses override configuration specified in
838 /// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor
839 /// uses factory-set configuration (Default).
841 UINT32 TurboRatioLimitConfigurationSemaphore
:1;
844 /// All bit fields as a 64-bit value
847 } MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER
;
851 Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.
853 @param ECX MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)
854 @param EAX Lower 32-bits of MSR value.
855 Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
856 @param EDX Upper 32-bits of MSR value.
857 Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
861 MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER Msr;
863 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);
865 @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.
867 #define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B
870 MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC
874 /// Individual bit fields
878 /// [Bits 5:0] Recoverable Address LSB.
880 UINT32 RecoverableAddressLSB
:6;
882 /// [Bits 8:6] Address Mode.
884 UINT32 AddressMode
:3;
887 /// [Bits 31:16] PCI Express Requestor ID.
889 UINT32 PCIExpressRequestorID
:16;
891 /// [Bits 39:32] PCI Express Segment Number.
893 UINT32 PCIExpressSegmentNumber
:8;
897 /// All bit fields as a 64-bit value
900 } MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER
;
904 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
905 15.3.2.4, "IA32_MCi_MISC MSRs.".
907 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
908 and its corresponding slice of L3.
910 @param ECX MSR_IVY_BRIDGE_IA32_MCi_CTL
911 @param EAX Lower 32-bits of MSR value.
912 @param EDX Upper 32-bits of MSR value.
918 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL);
919 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL, Msr);
921 @note MSR_IVY_BRIDGE_IA32_MC29_CTL is defined as IA32_MC29_CTL in SDM.
922 MSR_IVY_BRIDGE_IA32_MC30_CTL is defined as IA32_MC30_CTL in SDM.
923 MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM.
926 #define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474
927 #define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478
928 #define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C
933 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
934 15.3.2.4, "IA32_MCi_MISC MSRs.".
936 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
937 and its corresponding slice of L3.
939 @param ECX MSR_IVY_BRIDGE_IA32_MCi_STATUS
940 @param EAX Lower 32-bits of MSR value.
941 @param EDX Upper 32-bits of MSR value.
947 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS);
948 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS, Msr);
950 @note MSR_IVY_BRIDGE_IA32_MC29_STATUS is defined as IA32_MC29_STATUS in SDM.
951 MSR_IVY_BRIDGE_IA32_MC30_STATUS is defined as IA32_MC30_STATUS in SDM.
952 MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM.
955 #define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475
956 #define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479
957 #define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D
962 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
963 15.3.2.4, "IA32_MCi_MISC MSRs.".
965 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
966 and its corresponding slice of L3.
968 @param ECX MSR_IVY_BRIDGE_IA32_MCi_ADDR
969 @param EAX Lower 32-bits of MSR value.
970 @param EDX Upper 32-bits of MSR value.
976 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR);
977 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR, Msr);
979 @note MSR_IVY_BRIDGE_IA32_MC29_ADDR is defined as IA32_MC29_ADDR in SDM.
980 MSR_IVY_BRIDGE_IA32_MC30_ADDR is defined as IA32_MC30_ADDR in SDM.
981 MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM.
984 #define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476
985 #define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A
986 #define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E
991 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
992 15.3.2.4, "IA32_MCi_MISC MSRs.".
994 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
995 and its corresponding slice of L3.
997 @param ECX MSR_IVY_BRIDGE_IA32_MCi_MISC
998 @param EAX Lower 32-bits of MSR value.
999 @param EDX Upper 32-bits of MSR value.
1001 <b>Example usage</b>
1005 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC);
1006 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC, Msr);
1008 @note MSR_IVY_BRIDGE_IA32_MC29_MISC is defined as IA32_MC29_MISC in SDM.
1009 MSR_IVY_BRIDGE_IA32_MC30_MISC is defined as IA32_MC30_MISC in SDM.
1010 MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM.
1013 #define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477
1014 #define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B
1015 #define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F
1020 Package. Package RAPL Perf Status (R/O).
1022 @param ECX MSR_IVY_BRIDGE_PKG_PERF_STATUS (0x00000613)
1023 @param EAX Lower 32-bits of MSR value.
1024 @param EDX Upper 32-bits of MSR value.
1026 <b>Example usage</b>
1030 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS);
1032 @note MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
1034 #define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613
1038 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
1041 @param ECX MSR_IVY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)
1042 @param EAX Lower 32-bits of MSR value.
1043 @param EDX Upper 32-bits of MSR value.
1045 <b>Example usage</b>
1049 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT);
1050 AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr);
1052 @note MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
1054 #define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618
1058 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
1060 @param ECX MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)
1061 @param EAX Lower 32-bits of MSR value.
1062 @param EDX Upper 32-bits of MSR value.
1064 <b>Example usage</b>
1068 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS);
1070 @note MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
1072 #define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619
1076 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
1079 @param ECX MSR_IVY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)
1080 @param EAX Lower 32-bits of MSR value.
1081 @param EDX Upper 32-bits of MSR value.
1083 <b>Example usage</b>
1087 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS);
1089 @note MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
1091 #define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B
1095 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
1097 @param ECX MSR_IVY_BRIDGE_DRAM_POWER_INFO (0x0000061C)
1098 @param EAX Lower 32-bits of MSR value.
1099 @param EDX Upper 32-bits of MSR value.
1101 <b>Example usage</b>
1105 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO);
1106 AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr);
1108 @note MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
1110 #define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C
1114 Thread. See Section 18.8.1.1, "Precise Event Based Sampling (PEBS).".
1116 @param ECX MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)
1117 @param EAX Lower 32-bits of MSR value.
1118 Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.
1119 @param EDX Upper 32-bits of MSR value.
1120 Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.
1122 <b>Example usage</b>
1124 MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER Msr;
1126 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE);
1127 AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64);
1129 @note MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1131 #define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1
1134 MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE
1138 /// Individual bit fields
1142 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1144 UINT32 PEBS_EN_PMC0
:1;
1146 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
1148 UINT32 PEBS_EN_PMC1
:1;
1150 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
1152 UINT32 PEBS_EN_PMC2
:1;
1154 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
1156 UINT32 PEBS_EN_PMC3
:1;
1157 UINT32 Reserved1
:28;
1159 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
1161 UINT32 LL_EN_PMC0
:1;
1163 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
1165 UINT32 LL_EN_PMC1
:1;
1167 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
1169 UINT32 LL_EN_PMC2
:1;
1171 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
1173 UINT32 LL_EN_PMC3
:1;
1174 UINT32 Reserved2
:28;
1177 /// All bit fields as a 64-bit value
1180 } MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER
;
1184 Package. Uncore perfmon per-socket global control.
1186 @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CTL (0x00000C00)
1187 @param EAX Lower 32-bits of MSR value.
1188 @param EDX Upper 32-bits of MSR value.
1190 <b>Example usage</b>
1194 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL);
1195 AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr);
1197 @note MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.
1199 #define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00
1203 Package. Uncore perfmon per-socket global status.
1205 @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS (0x00000C01)
1206 @param EAX Lower 32-bits of MSR value.
1207 @param EDX Upper 32-bits of MSR value.
1209 <b>Example usage</b>
1213 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS);
1214 AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr);
1216 @note MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.
1218 #define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01
1222 Package. Uncore perfmon per-socket global configuration.
1224 @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG (0x00000C06)
1225 @param EAX Lower 32-bits of MSR value.
1226 @param EDX Upper 32-bits of MSR value.
1228 <b>Example usage</b>
1232 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG);
1233 AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr);
1235 @note MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.
1237 #define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06
1241 Package. Uncore U-box perfmon U-box wide status.
1243 @param ECX MSR_IVY_BRIDGE_U_PMON_BOX_STATUS (0x00000C15)
1244 @param EAX Lower 32-bits of MSR value.
1245 @param EDX Upper 32-bits of MSR value.
1247 <b>Example usage</b>
1251 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS);
1252 AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr);
1254 @note MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.
1256 #define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15
1260 Package. Uncore PCU perfmon box wide status.
1262 @param ECX MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS (0x00000C35)
1263 @param EAX Lower 32-bits of MSR value.
1264 @param EDX Upper 32-bits of MSR value.
1266 <b>Example usage</b>
1270 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS);
1271 AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr);
1273 @note MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.
1275 #define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35
1279 Package. Uncore C-box 0 perfmon box wide filter1.
1281 @param ECX MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 (0x00000D1A)
1282 @param EAX Lower 32-bits of MSR value.
1283 @param EDX Upper 32-bits of MSR value.
1285 <b>Example usage</b>
1289 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1);
1290 AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr);
1292 @note MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.
1294 #define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A
1298 Package. Uncore C-box 1 perfmon box wide filter1.
1300 @param ECX MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 (0x00000D3A)
1301 @param EAX Lower 32-bits of MSR value.
1302 @param EDX Upper 32-bits of MSR value.
1304 <b>Example usage</b>
1308 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1);
1309 AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr);
1311 @note MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.
1313 #define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A
1317 Package. Uncore C-box 2 perfmon box wide filter1.
1319 @param ECX MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 (0x00000D5A)
1320 @param EAX Lower 32-bits of MSR value.
1321 @param EDX Upper 32-bits of MSR value.
1323 <b>Example usage</b>
1327 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1);
1328 AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr);
1330 @note MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.
1332 #define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A
1336 Package. Uncore C-box 3 perfmon box wide filter1.
1338 @param ECX MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 (0x00000D7A)
1339 @param EAX Lower 32-bits of MSR value.
1340 @param EDX Upper 32-bits of MSR value.
1342 <b>Example usage</b>
1346 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1);
1347 AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr);
1349 @note MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.
1351 #define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A
1355 Package. Uncore C-box 4 perfmon box wide filter1.
1357 @param ECX MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 (0x00000D9A)
1358 @param EAX Lower 32-bits of MSR value.
1359 @param EDX Upper 32-bits of MSR value.
1361 <b>Example usage</b>
1365 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1);
1366 AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr);
1368 @note MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.
1370 #define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A
1374 Package. Uncore C-box 5 perfmon box wide filter1.
1376 @param ECX MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 (0x00000DBA)
1377 @param EAX Lower 32-bits of MSR value.
1378 @param EDX Upper 32-bits of MSR value.
1380 <b>Example usage</b>
1384 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1);
1385 AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr);
1387 @note MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.
1389 #define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA
1393 Package. Uncore C-box 6 perfmon box wide filter1.
1395 @param ECX MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 (0x00000DDA)
1396 @param EAX Lower 32-bits of MSR value.
1397 @param EDX Upper 32-bits of MSR value.
1399 <b>Example usage</b>
1403 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1);
1404 AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr);
1406 @note MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.
1408 #define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA
1412 Package. Uncore C-box 7 perfmon box wide filter1.
1414 @param ECX MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 (0x00000DFA)
1415 @param EAX Lower 32-bits of MSR value.
1416 @param EDX Upper 32-bits of MSR value.
1418 <b>Example usage</b>
1422 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1);
1423 AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr);
1425 @note MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.
1427 #define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA
1431 Package. Uncore C-box 8 perfmon local box wide control.
1433 @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_CTL (0x00000E04)
1434 @param EAX Lower 32-bits of MSR value.
1435 @param EDX Upper 32-bits of MSR value.
1437 <b>Example usage</b>
1441 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL);
1442 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr);
1444 @note MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.
1446 #define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04
1450 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
1452 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 (0x00000E10)
1453 @param EAX Lower 32-bits of MSR value.
1454 @param EDX Upper 32-bits of MSR value.
1456 <b>Example usage</b>
1460 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0);
1461 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr);
1463 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.
1465 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10
1469 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
1471 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 (0x00000E11)
1472 @param EAX Lower 32-bits of MSR value.
1473 @param EDX Upper 32-bits of MSR value.
1475 <b>Example usage</b>
1479 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1);
1480 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr);
1482 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.
1484 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11
1488 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
1490 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 (0x00000E12)
1491 @param EAX Lower 32-bits of MSR value.
1492 @param EDX Upper 32-bits of MSR value.
1494 <b>Example usage</b>
1498 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2);
1499 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr);
1501 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.
1503 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12
1507 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
1509 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 (0x00000E13)
1510 @param EAX Lower 32-bits of MSR value.
1511 @param EDX Upper 32-bits of MSR value.
1513 <b>Example usage</b>
1517 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3);
1518 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr);
1520 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.
1522 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13
1526 Package. Uncore C-box 8 perfmon box wide filter.
1528 @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER (0x00000E14)
1529 @param EAX Lower 32-bits of MSR value.
1530 @param EDX Upper 32-bits of MSR value.
1532 <b>Example usage</b>
1536 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER);
1537 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr);
1539 @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM.
1541 #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14
1545 Package. Uncore C-box 8 perfmon counter 0.
1547 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR0 (0x00000E16)
1548 @param EAX Lower 32-bits of MSR value.
1549 @param EDX Upper 32-bits of MSR value.
1551 <b>Example usage</b>
1555 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0);
1556 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr);
1558 @note MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
1560 #define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16
1564 Package. Uncore C-box 8 perfmon counter 1.
1566 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR1 (0x00000E17)
1567 @param EAX Lower 32-bits of MSR value.
1568 @param EDX Upper 32-bits of MSR value.
1570 <b>Example usage</b>
1574 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1);
1575 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr);
1577 @note MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
1579 #define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17
1583 Package. Uncore C-box 8 perfmon counter 2.
1585 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR2 (0x00000E18)
1586 @param EAX Lower 32-bits of MSR value.
1587 @param EDX Upper 32-bits of MSR value.
1589 <b>Example usage</b>
1593 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2);
1594 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr);
1596 @note MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
1598 #define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18
1602 Package. Uncore C-box 8 perfmon counter 3.
1604 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR3 (0x00000E19)
1605 @param EAX Lower 32-bits of MSR value.
1606 @param EDX Upper 32-bits of MSR value.
1608 <b>Example usage</b>
1612 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3);
1613 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr);
1615 @note MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
1617 #define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19
1621 Package. Uncore C-box 8 perfmon box wide filter1.
1623 @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 (0x00000E1A)
1624 @param EAX Lower 32-bits of MSR value.
1625 @param EDX Upper 32-bits of MSR value.
1627 <b>Example usage</b>
1631 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1);
1632 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr);
1634 @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.
1636 #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A
1640 Package. Uncore C-box 9 perfmon local box wide control.
1642 @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_CTL (0x00000E24)
1643 @param EAX Lower 32-bits of MSR value.
1644 @param EDX Upper 32-bits of MSR value.
1646 <b>Example usage</b>
1650 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL);
1651 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr);
1653 @note MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.
1655 #define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24
1659 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
1661 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 (0x00000E30)
1662 @param EAX Lower 32-bits of MSR value.
1663 @param EDX Upper 32-bits of MSR value.
1665 <b>Example usage</b>
1669 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0);
1670 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr);
1672 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.
1674 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30
1678 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
1680 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 (0x00000E31)
1681 @param EAX Lower 32-bits of MSR value.
1682 @param EDX Upper 32-bits of MSR value.
1684 <b>Example usage</b>
1688 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1);
1689 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr);
1691 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.
1693 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31
1697 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
1699 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 (0x00000E32)
1700 @param EAX Lower 32-bits of MSR value.
1701 @param EDX Upper 32-bits of MSR value.
1703 <b>Example usage</b>
1707 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2);
1708 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr);
1710 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.
1712 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32
1716 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
1718 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 (0x00000E33)
1719 @param EAX Lower 32-bits of MSR value.
1720 @param EDX Upper 32-bits of MSR value.
1722 <b>Example usage</b>
1726 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3);
1727 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr);
1729 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.
1731 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33
1735 Package. Uncore C-box 9 perfmon box wide filter.
1737 @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER (0x00000E34)
1738 @param EAX Lower 32-bits of MSR value.
1739 @param EDX Upper 32-bits of MSR value.
1741 <b>Example usage</b>
1745 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER);
1746 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr);
1748 @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM.
1750 #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34
1754 Package. Uncore C-box 9 perfmon counter 0.
1756 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR0 (0x00000E36)
1757 @param EAX Lower 32-bits of MSR value.
1758 @param EDX Upper 32-bits of MSR value.
1760 <b>Example usage</b>
1764 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0);
1765 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr);
1767 @note MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
1769 #define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36
1773 Package. Uncore C-box 9 perfmon counter 1.
1775 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR1 (0x00000E37)
1776 @param EAX Lower 32-bits of MSR value.
1777 @param EDX Upper 32-bits of MSR value.
1779 <b>Example usage</b>
1783 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1);
1784 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr);
1786 @note MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
1788 #define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37
1792 Package. Uncore C-box 9 perfmon counter 2.
1794 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR2 (0x00000E38)
1795 @param EAX Lower 32-bits of MSR value.
1796 @param EDX Upper 32-bits of MSR value.
1798 <b>Example usage</b>
1802 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2);
1803 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr);
1805 @note MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
1807 #define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38
1811 Package. Uncore C-box 9 perfmon counter 3.
1813 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR3 (0x00000E39)
1814 @param EAX Lower 32-bits of MSR value.
1815 @param EDX Upper 32-bits of MSR value.
1817 <b>Example usage</b>
1821 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3);
1822 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr);
1824 @note MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
1826 #define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39
1830 Package. Uncore C-box 9 perfmon box wide filter1.
1832 @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 (0x00000E3A)
1833 @param EAX Lower 32-bits of MSR value.
1834 @param EDX Upper 32-bits of MSR value.
1836 <b>Example usage</b>
1840 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1);
1841 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr);
1843 @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.
1845 #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A
1849 Package. Uncore C-box 10 perfmon local box wide control.
1851 @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_CTL (0x00000E44)
1852 @param EAX Lower 32-bits of MSR value.
1853 @param EDX Upper 32-bits of MSR value.
1855 <b>Example usage</b>
1859 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL);
1860 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr);
1862 @note MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.
1864 #define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44
1868 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
1870 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 (0x00000E50)
1871 @param EAX Lower 32-bits of MSR value.
1872 @param EDX Upper 32-bits of MSR value.
1874 <b>Example usage</b>
1878 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0);
1879 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr);
1881 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.
1883 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50
1887 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
1889 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 (0x00000E51)
1890 @param EAX Lower 32-bits of MSR value.
1891 @param EDX Upper 32-bits of MSR value.
1893 <b>Example usage</b>
1897 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1);
1898 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr);
1900 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.
1902 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51
1906 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
1908 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 (0x00000E52)
1909 @param EAX Lower 32-bits of MSR value.
1910 @param EDX Upper 32-bits of MSR value.
1912 <b>Example usage</b>
1916 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2);
1917 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr);
1919 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.
1921 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52
1925 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
1927 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 (0x00000E53)
1928 @param EAX Lower 32-bits of MSR value.
1929 @param EDX Upper 32-bits of MSR value.
1931 <b>Example usage</b>
1935 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3);
1936 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr);
1938 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.
1940 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53
1944 Package. Uncore C-box 10 perfmon box wide filter.
1946 @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER (0x00000E54)
1947 @param EAX Lower 32-bits of MSR value.
1948 @param EDX Upper 32-bits of MSR value.
1950 <b>Example usage</b>
1954 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER);
1955 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr);
1957 @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM.
1959 #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54
1963 Package. Uncore C-box 10 perfmon counter 0.
1965 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR0 (0x00000E56)
1966 @param EAX Lower 32-bits of MSR value.
1967 @param EDX Upper 32-bits of MSR value.
1969 <b>Example usage</b>
1973 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0);
1974 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr);
1976 @note MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.
1978 #define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56
1982 Package. Uncore C-box 10 perfmon counter 1.
1984 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR1 (0x00000E57)
1985 @param EAX Lower 32-bits of MSR value.
1986 @param EDX Upper 32-bits of MSR value.
1988 <b>Example usage</b>
1992 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1);
1993 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr);
1995 @note MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.
1997 #define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57
2001 Package. Uncore C-box 10 perfmon counter 2.
2003 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR2 (0x00000E58)
2004 @param EAX Lower 32-bits of MSR value.
2005 @param EDX Upper 32-bits of MSR value.
2007 <b>Example usage</b>
2011 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2);
2012 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr);
2014 @note MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.
2016 #define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58
2020 Package. Uncore C-box 10 perfmon counter 3.
2022 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR3 (0x00000E59)
2023 @param EAX Lower 32-bits of MSR value.
2024 @param EDX Upper 32-bits of MSR value.
2026 <b>Example usage</b>
2030 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3);
2031 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr);
2033 @note MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.
2035 #define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59
2039 Package. Uncore C-box 10 perfmon box wide filter1.
2041 @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 (0x00000E5A)
2042 @param EAX Lower 32-bits of MSR value.
2043 @param EDX Upper 32-bits of MSR value.
2045 <b>Example usage</b>
2049 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1);
2050 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr);
2052 @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.
2054 #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A
2058 Package. Uncore C-box 11 perfmon local box wide control.
2060 @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_CTL (0x00000E64)
2061 @param EAX Lower 32-bits of MSR value.
2062 @param EDX Upper 32-bits of MSR value.
2064 <b>Example usage</b>
2068 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL);
2069 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr);
2071 @note MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.
2073 #define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64
2077 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
2079 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 (0x00000E70)
2080 @param EAX Lower 32-bits of MSR value.
2081 @param EDX Upper 32-bits of MSR value.
2083 <b>Example usage</b>
2087 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0);
2088 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr);
2090 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.
2092 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70
2096 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
2098 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 (0x00000E71)
2099 @param EAX Lower 32-bits of MSR value.
2100 @param EDX Upper 32-bits of MSR value.
2102 <b>Example usage</b>
2106 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1);
2107 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr);
2109 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.
2111 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71
2115 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
2117 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 (0x00000E72)
2118 @param EAX Lower 32-bits of MSR value.
2119 @param EDX Upper 32-bits of MSR value.
2121 <b>Example usage</b>
2125 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2);
2126 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr);
2128 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.
2130 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72
2134 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
2136 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 (0x00000E73)
2137 @param EAX Lower 32-bits of MSR value.
2138 @param EDX Upper 32-bits of MSR value.
2140 <b>Example usage</b>
2144 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3);
2145 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr);
2147 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.
2149 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73
2153 Package. Uncore C-box 11 perfmon box wide filter.
2155 @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER (0x00000E74)
2156 @param EAX Lower 32-bits of MSR value.
2157 @param EDX Upper 32-bits of MSR value.
2159 <b>Example usage</b>
2163 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER);
2164 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr);
2166 @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM.
2168 #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74
2172 Package. Uncore C-box 11 perfmon counter 0.
2174 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR0 (0x00000E76)
2175 @param EAX Lower 32-bits of MSR value.
2176 @param EDX Upper 32-bits of MSR value.
2178 <b>Example usage</b>
2182 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0);
2183 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr);
2185 @note MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.
2187 #define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76
2191 Package. Uncore C-box 11 perfmon counter 1.
2193 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR1 (0x00000E77)
2194 @param EAX Lower 32-bits of MSR value.
2195 @param EDX Upper 32-bits of MSR value.
2197 <b>Example usage</b>
2201 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1);
2202 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr);
2204 @note MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.
2206 #define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77
2210 Package. Uncore C-box 11 perfmon counter 2.
2212 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR2 (0x00000E78)
2213 @param EAX Lower 32-bits of MSR value.
2214 @param EDX Upper 32-bits of MSR value.
2216 <b>Example usage</b>
2220 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2);
2221 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr);
2223 @note MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.
2225 #define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78
2229 Package. Uncore C-box 11 perfmon counter 3.
2231 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR3 (0x00000E79)
2232 @param EAX Lower 32-bits of MSR value.
2233 @param EDX Upper 32-bits of MSR value.
2235 <b>Example usage</b>
2239 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3);
2240 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr);
2242 @note MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.
2244 #define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79
2248 Package. Uncore C-box 11 perfmon box wide filter1.
2250 @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 (0x00000E7A)
2251 @param EAX Lower 32-bits of MSR value.
2252 @param EDX Upper 32-bits of MSR value.
2254 <b>Example usage</b>
2258 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1);
2259 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr);
2261 @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.
2263 #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A
2267 Package. Uncore C-box 12 perfmon local box wide control.
2269 @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_CTL (0x00000E84)
2270 @param EAX Lower 32-bits of MSR value.
2271 @param EDX Upper 32-bits of MSR value.
2273 <b>Example usage</b>
2277 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL);
2278 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr);
2280 @note MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.
2282 #define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84
2286 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
2288 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 (0x00000E90)
2289 @param EAX Lower 32-bits of MSR value.
2290 @param EDX Upper 32-bits of MSR value.
2292 <b>Example usage</b>
2296 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0);
2297 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr);
2299 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.
2301 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90
2305 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
2307 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 (0x00000E91)
2308 @param EAX Lower 32-bits of MSR value.
2309 @param EDX Upper 32-bits of MSR value.
2311 <b>Example usage</b>
2315 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1);
2316 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr);
2318 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.
2320 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91
2324 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
2326 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 (0x00000E92)
2327 @param EAX Lower 32-bits of MSR value.
2328 @param EDX Upper 32-bits of MSR value.
2330 <b>Example usage</b>
2334 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2);
2335 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr);
2337 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.
2339 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92
2343 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
2345 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 (0x00000E93)
2346 @param EAX Lower 32-bits of MSR value.
2347 @param EDX Upper 32-bits of MSR value.
2349 <b>Example usage</b>
2353 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3);
2354 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr);
2356 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.
2358 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93
2362 Package. Uncore C-box 12 perfmon box wide filter.
2364 @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER (0x00000E94)
2365 @param EAX Lower 32-bits of MSR value.
2366 @param EDX Upper 32-bits of MSR value.
2368 <b>Example usage</b>
2372 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER);
2373 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr);
2375 @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM.
2377 #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94
2381 Package. Uncore C-box 12 perfmon counter 0.
2383 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR0 (0x00000E96)
2384 @param EAX Lower 32-bits of MSR value.
2385 @param EDX Upper 32-bits of MSR value.
2387 <b>Example usage</b>
2391 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0);
2392 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr);
2394 @note MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.
2396 #define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96
2400 Package. Uncore C-box 12 perfmon counter 1.
2402 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR1 (0x00000E97)
2403 @param EAX Lower 32-bits of MSR value.
2404 @param EDX Upper 32-bits of MSR value.
2406 <b>Example usage</b>
2410 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1);
2411 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr);
2413 @note MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.
2415 #define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97
2419 Package. Uncore C-box 12 perfmon counter 2.
2421 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR2 (0x00000E98)
2422 @param EAX Lower 32-bits of MSR value.
2423 @param EDX Upper 32-bits of MSR value.
2425 <b>Example usage</b>
2429 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2);
2430 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr);
2432 @note MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.
2434 #define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98
2438 Package. Uncore C-box 12 perfmon counter 3.
2440 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR3 (0x00000E99)
2441 @param EAX Lower 32-bits of MSR value.
2442 @param EDX Upper 32-bits of MSR value.
2444 <b>Example usage</b>
2448 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3);
2449 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr);
2451 @note MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.
2453 #define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99
2457 Package. Uncore C-box 12 perfmon box wide filter1.
2459 @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 (0x00000E9A)
2460 @param EAX Lower 32-bits of MSR value.
2461 @param EDX Upper 32-bits of MSR value.
2463 <b>Example usage</b>
2467 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1);
2468 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr);
2470 @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.
2472 #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A
2476 Package. Uncore C-box 13 perfmon local box wide control.
2478 @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_CTL (0x00000EA4)
2479 @param EAX Lower 32-bits of MSR value.
2480 @param EDX Upper 32-bits of MSR value.
2482 <b>Example usage</b>
2486 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL);
2487 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr);
2489 @note MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.
2491 #define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4
2495 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
2497 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 (0x00000EB0)
2498 @param EAX Lower 32-bits of MSR value.
2499 @param EDX Upper 32-bits of MSR value.
2501 <b>Example usage</b>
2505 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0);
2506 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr);
2508 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.
2510 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0
2514 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
2516 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 (0x00000EB1)
2517 @param EAX Lower 32-bits of MSR value.
2518 @param EDX Upper 32-bits of MSR value.
2520 <b>Example usage</b>
2524 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1);
2525 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr);
2527 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.
2529 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1
2533 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
2535 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 (0x00000EB2)
2536 @param EAX Lower 32-bits of MSR value.
2537 @param EDX Upper 32-bits of MSR value.
2539 <b>Example usage</b>
2543 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2);
2544 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr);
2546 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.
2548 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2
2552 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
2554 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 (0x00000EB3)
2555 @param EAX Lower 32-bits of MSR value.
2556 @param EDX Upper 32-bits of MSR value.
2558 <b>Example usage</b>
2562 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3);
2563 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr);
2565 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.
2567 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3
2571 Package. Uncore C-box 13 perfmon box wide filter.
2573 @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER (0x00000EB4)
2574 @param EAX Lower 32-bits of MSR value.
2575 @param EDX Upper 32-bits of MSR value.
2577 <b>Example usage</b>
2581 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER);
2582 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr);
2584 @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM.
2586 #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4
2590 Package. Uncore C-box 13 perfmon counter 0.
2592 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR0 (0x00000EB6)
2593 @param EAX Lower 32-bits of MSR value.
2594 @param EDX Upper 32-bits of MSR value.
2596 <b>Example usage</b>
2600 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0);
2601 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr);
2603 @note MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.
2605 #define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6
2609 Package. Uncore C-box 13 perfmon counter 1.
2611 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR1 (0x00000EB7)
2612 @param EAX Lower 32-bits of MSR value.
2613 @param EDX Upper 32-bits of MSR value.
2615 <b>Example usage</b>
2619 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1);
2620 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr);
2622 @note MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.
2624 #define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7
2628 Package. Uncore C-box 13 perfmon counter 2.
2630 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR2 (0x00000EB8)
2631 @param EAX Lower 32-bits of MSR value.
2632 @param EDX Upper 32-bits of MSR value.
2634 <b>Example usage</b>
2638 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2);
2639 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr);
2641 @note MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.
2643 #define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8
2647 Package. Uncore C-box 13 perfmon counter 3.
2649 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR3 (0x00000EB9)
2650 @param EAX Lower 32-bits of MSR value.
2651 @param EDX Upper 32-bits of MSR value.
2653 <b>Example usage</b>
2657 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3);
2658 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr);
2660 @note MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.
2662 #define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9
2666 Package. Uncore C-box 13 perfmon box wide filter1.
2668 @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 (0x00000EBA)
2669 @param EAX Lower 32-bits of MSR value.
2670 @param EDX Upper 32-bits of MSR value.
2672 <b>Example usage</b>
2676 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1);
2677 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr);
2679 @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.
2681 #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA
2685 Package. Uncore C-box 14 perfmon local box wide control.
2687 @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_CTL (0x00000EC4)
2688 @param EAX Lower 32-bits of MSR value.
2689 @param EDX Upper 32-bits of MSR value.
2691 <b>Example usage</b>
2695 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL);
2696 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr);
2698 @note MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.
2700 #define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4
2704 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
2706 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 (0x00000ED0)
2707 @param EAX Lower 32-bits of MSR value.
2708 @param EDX Upper 32-bits of MSR value.
2710 <b>Example usage</b>
2714 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0);
2715 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr);
2717 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.
2719 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0
2723 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
2725 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 (0x00000ED1)
2726 @param EAX Lower 32-bits of MSR value.
2727 @param EDX Upper 32-bits of MSR value.
2729 <b>Example usage</b>
2733 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1);
2734 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr);
2736 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.
2738 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1
2742 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
2744 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 (0x00000ED2)
2745 @param EAX Lower 32-bits of MSR value.
2746 @param EDX Upper 32-bits of MSR value.
2748 <b>Example usage</b>
2752 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2);
2753 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr);
2755 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.
2757 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2
2761 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
2763 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 (0x00000ED3)
2764 @param EAX Lower 32-bits of MSR value.
2765 @param EDX Upper 32-bits of MSR value.
2767 <b>Example usage</b>
2771 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3);
2772 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr);
2774 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.
2776 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3
2780 Package. Uncore C-box 14 perfmon box wide filter.
2782 @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER (0x00000ED4)
2783 @param EAX Lower 32-bits of MSR value.
2784 @param EDX Upper 32-bits of MSR value.
2786 <b>Example usage</b>
2790 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER);
2791 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr);
2793 @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.
2795 #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4
2799 Package. Uncore C-box 14 perfmon counter 0.
2801 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR0 (0x00000ED6)
2802 @param EAX Lower 32-bits of MSR value.
2803 @param EDX Upper 32-bits of MSR value.
2805 <b>Example usage</b>
2809 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0);
2810 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr);
2812 @note MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.
2814 #define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6
2818 Package. Uncore C-box 14 perfmon counter 1.
2820 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR1 (0x00000ED7)
2821 @param EAX Lower 32-bits of MSR value.
2822 @param EDX Upper 32-bits of MSR value.
2824 <b>Example usage</b>
2828 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1);
2829 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr);
2831 @note MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.
2833 #define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7
2837 Package. Uncore C-box 14 perfmon counter 2.
2839 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR2 (0x00000ED8)
2840 @param EAX Lower 32-bits of MSR value.
2841 @param EDX Upper 32-bits of MSR value.
2843 <b>Example usage</b>
2847 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2);
2848 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr);
2850 @note MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.
2852 #define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8
2856 Package. Uncore C-box 14 perfmon counter 3.
2858 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR3 (0x00000ED9)
2859 @param EAX Lower 32-bits of MSR value.
2860 @param EDX Upper 32-bits of MSR value.
2862 <b>Example usage</b>
2866 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3);
2867 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr);
2869 @note MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.
2871 #define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9
2875 Package. Uncore C-box 14 perfmon box wide filter1.
2877 @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 (0x00000EDA)
2878 @param EAX Lower 32-bits of MSR value.
2879 @param EDX Upper 32-bits of MSR value.
2881 <b>Example usage</b>
2885 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1);
2886 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr);
2888 @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.
2890 #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA