2 MSR Definitions for Intel processors based on the Nehalem microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.6.
24 #ifndef __NEHALEM_MSR_H__
25 #define __NEHALEM_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Intel processors based on the Nehalem microarchitecture?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_NEHALEM_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x1A || \
42 DisplayModel == 0x1E || \
43 DisplayModel == 0x1F || \
44 DisplayModel == 0x2E \
49 Package. Model Specific Platform ID (R).
51 @param ECX MSR_NEHALEM_PLATFORM_ID (0x00000017)
52 @param EAX Lower 32-bits of MSR value.
53 Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.
54 @param EDX Upper 32-bits of MSR value.
55 Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.
59 MSR_NEHALEM_PLATFORM_ID_REGISTER Msr;
61 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID);
63 @note MSR_NEHALEM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
65 #define MSR_NEHALEM_PLATFORM_ID 0x00000017
68 MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_ID
72 /// Individual bit fields
78 /// [Bits 52:50] See Table 35-2.
84 /// All bit fields as a 64-bit value
87 } MSR_NEHALEM_PLATFORM_ID_REGISTER
;
91 Thread. SMI Counter (R/O).
93 @param ECX MSR_NEHALEM_SMI_COUNT (0x00000034)
94 @param EAX Lower 32-bits of MSR value.
95 Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.
96 @param EDX Upper 32-bits of MSR value.
97 Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.
101 MSR_NEHALEM_SMI_COUNT_REGISTER Msr;
103 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT);
105 @note MSR_NEHALEM_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
107 #define MSR_NEHALEM_SMI_COUNT 0x00000034
110 MSR information returned for MSR index #MSR_NEHALEM_SMI_COUNT
114 /// Individual bit fields
118 /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last
125 /// All bit fields as a 32-bit value
129 /// All bit fields as a 64-bit value
132 } MSR_NEHALEM_SMI_COUNT_REGISTER
;
136 Package. see http://biosbits.org.
138 @param ECX MSR_NEHALEM_PLATFORM_INFO (0x000000CE)
139 @param EAX Lower 32-bits of MSR value.
140 Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.
141 @param EDX Upper 32-bits of MSR value.
142 Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.
146 MSR_NEHALEM_PLATFORM_INFO_REGISTER Msr;
148 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO);
149 AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64);
151 @note MSR_NEHALEM_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
153 #define MSR_NEHALEM_PLATFORM_INFO 0x000000CE
156 MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_INFO
160 /// Individual bit fields
165 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
166 /// of the frequency that invariant TSC runs at. The invariant TSC
167 /// frequency can be computed by multiplying this ratio by 133.33 MHz.
169 UINT32 MaximumNonTurboRatio
:8;
172 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
173 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
174 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
175 /// Turbo mode is disabled.
179 /// [Bit 29] Package. Programmable TDC-TDP Limit for Turbo Mode (R/O)
180 /// When set to 1, indicates that TDC/TDP Limits for Turbo mode are
181 /// programmable, and when set to 0, indicates TDC and TDP Limits for
182 /// Turbo mode are not programmable.
184 UINT32 TDC_TDPLimit
:1;
188 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
189 /// minimum ratio (maximum efficiency) that the processor can operates, in
190 /// units of 133.33MHz.
192 UINT32 MaximumEfficiencyRatio
:8;
196 /// All bit fields as a 64-bit value
199 } MSR_NEHALEM_PLATFORM_INFO_REGISTER
;
203 Core. C-State Configuration Control (R/W) Note: C-state values are
204 processor specific C-state code names, unrelated to MWAIT extension C-state
205 parameters or ACPI CStates. See http://biosbits.org.
207 @param ECX MSR_NEHALEM_PKG_CST_CONFIG_CONTROL (0x000000E2)
208 @param EAX Lower 32-bits of MSR value.
209 Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.
210 @param EDX Upper 32-bits of MSR value.
211 Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.
215 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
217 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL);
218 AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
220 @note MSR_NEHALEM_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
222 #define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL 0x000000E2
225 MSR information returned for MSR index #MSR_NEHALEM_PKG_CST_CONFIG_CONTROL
229 /// Individual bit fields
233 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
234 /// processor-specific C-state code name (consuming the least power). for
235 /// the package. The default is set as factory-configured package C-state
236 /// limit. The following C-state code name encodings are supported: 000b:
237 /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)
238 /// 010b: C3 011b: C6 100b: C7 101b and 110b: Reserved 111: No package
239 /// C-state limit. Note: This field cannot be used to limit package
245 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
246 /// IO_read instructions sent to IO register specified by
247 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
252 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
253 /// until next reset.
258 /// [Bit 24] Interrupt filtering enable (R/W) When set, processor cores
259 /// in a deep C-State will wake only when the event message is destined
260 /// for that core. When 0, all processor cores in a deep C-State will wake
261 /// for an event message.
263 UINT32 InterruptFiltering
:1;
265 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor
266 /// will conditionally demote C6/C7 requests to C3 based on uncore
267 /// auto-demote information.
269 UINT32 C3AutoDemotion
:1;
271 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor
272 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
273 /// auto-demote information.
275 UINT32 C1AutoDemotion
:1;
277 /// [Bit 27] Enable C3 Undemotion (R/W).
279 UINT32 C3Undemotion
:1;
281 /// [Bit 28] Enable C1 Undemotion (R/W).
283 UINT32 C1Undemotion
:1;
285 /// [Bit 29] Package C State Demotion Enable (R/W).
287 UINT32 CStateDemotion
:1;
289 /// [Bit 30] Package C State UnDemotion Enable (R/W).
291 UINT32 CStateUndemotion
:1;
296 /// All bit fields as a 32-bit value
300 /// All bit fields as a 64-bit value
303 } MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER
;
307 Core. Power Management IO Redirection in C-state (R/W) See
310 @param ECX MSR_NEHALEM_PMG_IO_CAPTURE_BASE (0x000000E4)
311 @param EAX Lower 32-bits of MSR value.
312 Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.
313 @param EDX Upper 32-bits of MSR value.
314 Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.
318 MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER Msr;
320 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE);
321 AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64);
323 @note MSR_NEHALEM_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
325 #define MSR_NEHALEM_PMG_IO_CAPTURE_BASE 0x000000E4
328 MSR information returned for MSR index #MSR_NEHALEM_PMG_IO_CAPTURE_BASE
332 /// Individual bit fields
336 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address
337 /// visible to software for IO redirection. If IO MWAIT Redirection is
338 /// enabled, reads to this address will be consumed by the power
339 /// management logic and decoded to MWAIT instructions. When IO port
340 /// address redirection is enabled, this is the IO port address reported
341 /// to the OS/software.
345 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
346 /// maximum C-State code name to be included when IO read to MWAIT
347 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3
348 /// is the max C-State to include 001b - C6 is the max C-State to include
349 /// 010b - C7 is the max C-State to include.
351 UINT32 CStateRange
:3;
356 /// All bit fields as a 32-bit value
360 /// All bit fields as a 64-bit value
363 } MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER
;
367 Enable Misc. Processor Features (R/W) Allows a variety of processor
368 functions to be enabled and disabled.
370 @param ECX MSR_NEHALEM_IA32_MISC_ENABLE (0x000001A0)
371 @param EAX Lower 32-bits of MSR value.
372 Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.
373 @param EDX Upper 32-bits of MSR value.
374 Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.
378 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER Msr;
380 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE);
381 AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64);
383 @note MSR_NEHALEM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
385 #define MSR_NEHALEM_IA32_MISC_ENABLE 0x000001A0
388 MSR information returned for MSR index #MSR_NEHALEM_IA32_MISC_ENABLE
392 /// Individual bit fields
396 /// [Bit 0] Thread. Fast-Strings Enable See Table 35-2.
398 UINT32 FastStrings
:1;
401 /// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See
402 /// Table 35-2. Default value is 1.
404 UINT32 AutomaticThermalControlCircuit
:1;
407 /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2.
409 UINT32 PerformanceMonitoring
:1;
412 /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2.
416 /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See
422 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
428 /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2.
433 /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2.
435 UINT32 LimitCpuidMaxval
:1;
437 /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2.
439 UINT32 xTPR_Message_Disable
:1;
443 /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2.
448 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
449 /// that support Intel Turbo Boost Technology, the turbo mode feature is
450 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
451 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
452 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
453 /// the power-on default value is used by BIOS to detect hardware support
454 /// of turbo mode. If power-on default value is 1, turbo mode is available
455 /// in the processor. If power-on default value is 0, turbo mode is not
458 UINT32 TurboModeDisable
:1;
459 UINT32 Reserved10
:25;
462 /// All bit fields as a 64-bit value
465 } MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER
;
471 @param ECX MSR_NEHALEM_TEMPERATURE_TARGET (0x000001A2)
472 @param EAX Lower 32-bits of MSR value.
473 Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.
474 @param EDX Upper 32-bits of MSR value.
475 Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.
479 MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER Msr;
481 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET);
482 AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64);
484 @note MSR_NEHALEM_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
486 #define MSR_NEHALEM_TEMPERATURE_TARGET 0x000001A2
489 MSR information returned for MSR index #MSR_NEHALEM_TEMPERATURE_TARGET
493 /// Individual bit fields
498 /// [Bits 23:16] Temperature Target (R) The minimum temperature at which
499 /// PROCHOT# will be asserted. The value is degree C.
501 UINT32 TemperatureTarget
:8;
506 /// All bit fields as a 32-bit value
510 /// All bit fields as a 64-bit value
513 } MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER
;
517 Miscellaneous Feature Control (R/W).
519 @param ECX MSR_NEHALEM_MISC_FEATURE_CONTROL (0x000001A4)
520 @param EAX Lower 32-bits of MSR value.
521 Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.
522 @param EDX Upper 32-bits of MSR value.
523 Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.
527 MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER Msr;
529 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL);
530 AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64);
532 @note MSR_NEHALEM_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
534 #define MSR_NEHALEM_MISC_FEATURE_CONTROL 0x000001A4
537 MSR information returned for MSR index #MSR_NEHALEM_MISC_FEATURE_CONTROL
541 /// Individual bit fields
545 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
546 /// L2 hardware prefetcher, which fetches additional lines of code or data
547 /// into the L2 cache.
549 UINT32 L2HardwarePrefetcherDisable
:1;
551 /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,
552 /// disables the adjacent cache line prefetcher, which fetches the cache
553 /// line that comprises a cache line pair (128 bytes).
555 UINT32 L2AdjacentCacheLinePrefetcherDisable
:1;
557 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables
558 /// the L1 data cache prefetcher, which fetches the next cache line into
561 UINT32 DCUHardwarePrefetcherDisable
:1;
563 /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1
564 /// data cache IP prefetcher, which uses sequential load history (based on
565 /// instruction Pointer of previous loads) to determine whether to
566 /// prefetch additional lines.
568 UINT32 DCUIPPrefetcherDisable
:1;
573 /// All bit fields as a 32-bit value
577 /// All bit fields as a 64-bit value
580 } MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER
;
584 Thread. Offcore Response Event Select Register (R/W).
586 @param ECX MSR_NEHALEM_OFFCORE_RSP_0 (0x000001A6)
587 @param EAX Lower 32-bits of MSR value.
588 @param EDX Upper 32-bits of MSR value.
594 Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0);
595 AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr);
597 @note MSR_NEHALEM_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
599 #define MSR_NEHALEM_OFFCORE_RSP_0 0x000001A6
603 See http://biosbits.org.
605 @param ECX MSR_NEHALEM_MISC_PWR_MGMT (0x000001AA)
606 @param EAX Lower 32-bits of MSR value.
607 Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.
608 @param EDX Upper 32-bits of MSR value.
609 Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.
613 MSR_NEHALEM_MISC_PWR_MGMT_REGISTER Msr;
615 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT);
616 AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64);
618 @note MSR_NEHALEM_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
620 #define MSR_NEHALEM_MISC_PWR_MGMT 0x000001AA
623 MSR information returned for MSR index #MSR_NEHALEM_MISC_PWR_MGMT
627 /// Individual bit fields
631 /// [Bit 0] Package. EIST Hardware Coordination Disable (R/W) When 0,
632 /// enables hardware coordination of Enhanced Intel Speedstep Technology
633 /// request from processor cores; When 1, disables hardware coordination
634 /// of Enhanced Intel Speedstep Technology requests.
636 UINT32 EISTHardwareCoordinationDisable
:1;
638 /// [Bit 1] Thread. Energy/Performance Bias Enable (R/W) This bit makes
639 /// the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with
640 /// Ring 0 privileges. This bit's status (1 or 0) is also reflected by
641 /// CPUID.(EAX=06h):ECX[3].
643 UINT32 EnergyPerformanceBiasEnable
:1;
648 /// All bit fields as a 32-bit value
652 /// All bit fields as a 64-bit value
655 } MSR_NEHALEM_MISC_PWR_MGMT_REGISTER
;
659 See http://biosbits.org.
661 @param ECX MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT (0x000001AC)
662 @param EAX Lower 32-bits of MSR value.
663 Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.
664 @param EDX Upper 32-bits of MSR value.
665 Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.
669 MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER Msr;
671 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT);
672 AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64);
674 @note MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT is defined as MSR_TURBO_POWER_CURRENT_LIMIT in SDM.
676 #define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT 0x000001AC
679 MSR information returned for MSR index #MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT
683 /// Individual bit fields
687 /// [Bits 14:0] Package. TDP Limit (R/W) TDP limit in 1/8 Watt
692 /// [Bit 15] Package. TDP Limit Override Enable (R/W) A value = 0
693 /// indicates override is not active, and a value = 1 indicates active.
695 UINT32 TDPLimitOverrideEnable
:1;
697 /// [Bits 30:16] Package. TDC Limit (R/W) TDC limit in 1/8 Amp
702 /// [Bit 31] Package. TDC Limit Override Enable (R/W) A value = 0
703 /// indicates override is not active, and a value = 1 indicates active.
705 UINT32 TDCLimitOverrideEnable
:1;
709 /// All bit fields as a 32-bit value
713 /// All bit fields as a 64-bit value
716 } MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER
;
720 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
721 RW if MSR_PLATFORM_INFO.[28] = 1.
723 @param ECX MSR_NEHALEM_TURBO_RATIO_LIMIT (0x000001AD)
724 @param EAX Lower 32-bits of MSR value.
725 Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.
726 @param EDX Upper 32-bits of MSR value.
727 Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.
731 MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER Msr;
733 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT);
735 @note MSR_NEHALEM_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
737 #define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x000001AD
740 MSR information returned for MSR index #MSR_NEHALEM_TURBO_RATIO_LIMIT
744 /// Individual bit fields
748 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
749 /// limit of 1 core active.
753 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
754 /// limit of 2 core active.
758 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
759 /// limit of 3 core active.
763 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
764 /// limit of 4 core active.
770 /// All bit fields as a 32-bit value
774 /// All bit fields as a 64-bit value
777 } MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER
;
781 Core. Last Branch Record Filtering Select Register (R/W) See Section
782 17.7.2, "Filtering of Last Branch Records.".
784 @param ECX MSR_NEHALEM_LBR_SELECT (0x000001C8)
785 @param EAX Lower 32-bits of MSR value.
786 Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.
787 @param EDX Upper 32-bits of MSR value.
788 Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.
792 MSR_NEHALEM_LBR_SELECT_REGISTER Msr;
794 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT);
795 AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64);
797 @note MSR_NEHALEM_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
799 #define MSR_NEHALEM_LBR_SELECT 0x000001C8
802 MSR information returned for MSR index #MSR_NEHALEM_LBR_SELECT
806 /// Individual bit fields
810 /// [Bit 0] CPL_EQ_0.
814 /// [Bit 1] CPL_NEQ_0.
822 /// [Bit 3] NEAR_REL_CALL.
824 UINT32 NEAR_REL_CALL
:1;
826 /// [Bit 4] NEAR_IND_CALL.
828 UINT32 NEAR_IND_CALL
:1;
830 /// [Bit 5] NEAR_RET.
834 /// [Bit 6] NEAR_IND_JMP.
836 UINT32 NEAR_IND_JMP
:1;
838 /// [Bit 7] NEAR_REL_JMP.
840 UINT32 NEAR_REL_JMP
:1;
842 /// [Bit 8] FAR_BRANCH.
849 /// All bit fields as a 32-bit value
853 /// All bit fields as a 64-bit value
856 } MSR_NEHALEM_LBR_SELECT_REGISTER
;
860 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
861 that points to the MSR containing the most recent branch record. See
862 MSR_LASTBRANCH_0_FROM_IP (at 680H).
864 @param ECX MSR_NEHALEM_LASTBRANCH_TOS (0x000001C9)
865 @param EAX Lower 32-bits of MSR value.
866 @param EDX Upper 32-bits of MSR value.
872 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS);
873 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr);
875 @note MSR_NEHALEM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
877 #define MSR_NEHALEM_LASTBRANCH_TOS 0x000001C9
881 Thread. Last Exception Record From Linear IP (R) Contains a pointer to the
882 last branch instruction that the processor executed prior to the last
883 exception that was generated or the last interrupt that was handled.
885 @param ECX MSR_NEHALEM_LER_FROM_LIP (0x000001DD)
886 @param EAX Lower 32-bits of MSR value.
887 @param EDX Upper 32-bits of MSR value.
893 Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP);
895 @note MSR_NEHALEM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
897 #define MSR_NEHALEM_LER_FROM_LIP 0x000001DD
901 Thread. Last Exception Record To Linear IP (R) This area contains a pointer
902 to the target of the last branch instruction that the processor executed
903 prior to the last exception that was generated or the last interrupt that
906 @param ECX MSR_NEHALEM_LER_TO_LIP (0x000001DE)
907 @param EAX Lower 32-bits of MSR value.
908 @param EDX Upper 32-bits of MSR value.
914 Msr = AsmReadMsr64 (MSR_NEHALEM_LER_TO_LIP);
916 @note MSR_NEHALEM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
918 #define MSR_NEHALEM_LER_TO_LIP 0x000001DE
922 Core. Power Control Register. See http://biosbits.org.
924 @param ECX MSR_NEHALEM_POWER_CTL (0x000001FC)
925 @param EAX Lower 32-bits of MSR value.
926 Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.
927 @param EDX Upper 32-bits of MSR value.
928 Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.
932 MSR_NEHALEM_POWER_CTL_REGISTER Msr;
934 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_POWER_CTL);
935 AsmWriteMsr64 (MSR_NEHALEM_POWER_CTL, Msr.Uint64);
937 @note MSR_NEHALEM_POWER_CTL is defined as MSR_POWER_CTL in SDM.
939 #define MSR_NEHALEM_POWER_CTL 0x000001FC
942 MSR information returned for MSR index #MSR_NEHALEM_POWER_CTL
946 /// Individual bit fields
951 /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the
952 /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology
953 /// operating point when all execution cores enter MWAIT (C1).
960 /// All bit fields as a 32-bit value
964 /// All bit fields as a 64-bit value
967 } MSR_NEHALEM_POWER_CTL_REGISTER
;
973 @param ECX MSR_NEHALEM_PERF_GLOBAL_STATUS (0x0000038E)
974 @param EAX Lower 32-bits of MSR value.
975 Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.
976 @param EDX Upper 32-bits of MSR value.
977 Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.
981 MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER Msr;
983 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STATUS);
985 @note MSR_NEHALEM_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.
987 #define MSR_NEHALEM_PERF_GLOBAL_STATUS 0x0000038E
990 MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STATUS
994 /// Individual bit fields
1000 /// [Bit 61] UNC_Ovf Uncore overflowed if 1.
1002 UINT32 Ovf_Uncore
:1;
1006 /// All bit fields as a 64-bit value
1009 } MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER
;
1015 @param ECX MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL (0x00000390)
1016 @param EAX Lower 32-bits of MSR value.
1017 Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.
1018 @param EDX Upper 32-bits of MSR value.
1019 Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.
1021 <b>Example usage</b>
1023 MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
1025 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL);
1026 AsmWriteMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
1028 @note MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.
1030 #define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL 0x00000390
1033 MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL
1037 /// Individual bit fields
1040 UINT32 Reserved1
:32;
1041 UINT32 Reserved2
:29;
1043 /// [Bit 61] CLR_UNC_Ovf Set 1 to clear UNC_Ovf.
1045 UINT32 Ovf_Uncore
:1;
1049 /// All bit fields as a 64-bit value
1052 } MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER
;
1056 Thread. See Section 18.8.1.1, "Processor Event Based Sampling (PEBS).".
1058 @param ECX MSR_NEHALEM_PEBS_ENABLE (0x000003F1)
1059 @param EAX Lower 32-bits of MSR value.
1060 Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.
1061 @param EDX Upper 32-bits of MSR value.
1062 Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.
1064 <b>Example usage</b>
1066 MSR_NEHALEM_PEBS_ENABLE_REGISTER Msr;
1068 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_ENABLE);
1069 AsmWriteMsr64 (MSR_NEHALEM_PEBS_ENABLE, Msr.Uint64);
1071 @note MSR_NEHALEM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1073 #define MSR_NEHALEM_PEBS_ENABLE 0x000003F1
1076 MSR information returned for MSR index #MSR_NEHALEM_PEBS_ENABLE
1080 /// Individual bit fields
1084 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1086 UINT32 PEBS_EN_PMC0
:1;
1088 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
1090 UINT32 PEBS_EN_PMC1
:1;
1092 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
1094 UINT32 PEBS_EN_PMC2
:1;
1096 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
1098 UINT32 PEBS_EN_PMC3
:1;
1099 UINT32 Reserved1
:28;
1101 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
1103 UINT32 LL_EN_PMC0
:1;
1105 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
1107 UINT32 LL_EN_PMC1
:1;
1109 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
1111 UINT32 LL_EN_PMC2
:1;
1113 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
1115 UINT32 LL_EN_PMC3
:1;
1116 UINT32 Reserved2
:28;
1119 /// All bit fields as a 64-bit value
1122 } MSR_NEHALEM_PEBS_ENABLE_REGISTER
;
1126 Thread. See Section 18.8.1.2, "Load Latency Performance Monitoring
1129 @param ECX MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)
1130 @param EAX Lower 32-bits of MSR value.
1131 Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.
1132 @param EDX Upper 32-bits of MSR value.
1133 Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.
1135 <b>Example usage</b>
1137 MSR_NEHALEM_PEBS_LD_LAT_REGISTER Msr;
1139 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_LD_LAT);
1140 AsmWriteMsr64 (MSR_NEHALEM_PEBS_LD_LAT, Msr.Uint64);
1142 @note MSR_NEHALEM_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.
1144 #define MSR_NEHALEM_PEBS_LD_LAT 0x000003F6
1147 MSR information returned for MSR index #MSR_NEHALEM_PEBS_LD_LAT
1151 /// Individual bit fields
1155 /// [Bits 15:0] Minimum threshold latency value of tagged load operation
1156 /// that will be counted. (R/W).
1158 UINT32 MinimumThreshold
:16;
1159 UINT32 Reserved1
:16;
1160 UINT32 Reserved2
:32;
1163 /// All bit fields as a 32-bit value
1167 /// All bit fields as a 64-bit value
1170 } MSR_NEHALEM_PEBS_LD_LAT_REGISTER
;
1174 Package. Note: C-state values are processor specific C-state code names,
1175 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
1176 Residency Counter. (R/O) Value since last reset that this package is in
1177 processor-specific C3 states. Count at the same frequency as the TSC.
1179 @param ECX MSR_NEHALEM_PKG_C3_RESIDENCY (0x000003F8)
1180 @param EAX Lower 32-bits of MSR value.
1181 @param EDX Upper 32-bits of MSR value.
1183 <b>Example usage</b>
1187 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY);
1188 AsmWriteMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY, Msr);
1190 @note MSR_NEHALEM_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
1192 #define MSR_NEHALEM_PKG_C3_RESIDENCY 0x000003F8
1196 Package. Note: C-state values are processor specific C-state code names,
1197 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
1198 Residency Counter. (R/O) Value since last reset that this package is in
1199 processor-specific C6 states. Count at the same frequency as the TSC.
1201 @param ECX MSR_NEHALEM_PKG_C6_RESIDENCY (0x000003F9)
1202 @param EAX Lower 32-bits of MSR value.
1203 @param EDX Upper 32-bits of MSR value.
1205 <b>Example usage</b>
1209 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY);
1210 AsmWriteMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY, Msr);
1212 @note MSR_NEHALEM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1214 #define MSR_NEHALEM_PKG_C6_RESIDENCY 0x000003F9
1218 Package. Note: C-state values are processor specific C-state code names,
1219 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7
1220 Residency Counter. (R/O) Value since last reset that this package is in
1221 processor-specific C7 states. Count at the same frequency as the TSC.
1223 @param ECX MSR_NEHALEM_PKG_C7_RESIDENCY (0x000003FA)
1224 @param EAX Lower 32-bits of MSR value.
1225 @param EDX Upper 32-bits of MSR value.
1227 <b>Example usage</b>
1231 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY);
1232 AsmWriteMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY, Msr);
1234 @note MSR_NEHALEM_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
1236 #define MSR_NEHALEM_PKG_C7_RESIDENCY 0x000003FA
1240 Core. Note: C-state values are processor specific C-state code names,
1241 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
1242 Residency Counter. (R/O) Value since last reset that this core is in
1243 processor-specific C3 states. Count at the same frequency as the TSC.
1245 @param ECX MSR_NEHALEM_CORE_C3_RESIDENCY (0x000003FC)
1246 @param EAX Lower 32-bits of MSR value.
1247 @param EDX Upper 32-bits of MSR value.
1249 <b>Example usage</b>
1253 Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY);
1254 AsmWriteMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY, Msr);
1256 @note MSR_NEHALEM_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.
1258 #define MSR_NEHALEM_CORE_C3_RESIDENCY 0x000003FC
1262 Core. Note: C-state values are processor specific C-state code names,
1263 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
1264 Residency Counter. (R/O) Value since last reset that this core is in
1265 processor-specific C6 states. Count at the same frequency as the TSC.
1267 @param ECX MSR_NEHALEM_CORE_C6_RESIDENCY (0x000003FD)
1268 @param EAX Lower 32-bits of MSR value.
1269 @param EDX Upper 32-bits of MSR value.
1271 <b>Example usage</b>
1275 Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY);
1276 AsmWriteMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY, Msr);
1278 @note MSR_NEHALEM_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
1280 #define MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD
1284 Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last
1285 branch record registers on the last branch record stack. The From_IP part of
1286 the stack contains pointers to the source instruction. See also: - Last
1287 Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in
1290 @param ECX MSR_NEHALEM_LASTBRANCH_n_FROM_IP
1291 @param EAX Lower 32-bits of MSR value.
1292 @param EDX Upper 32-bits of MSR value.
1294 <b>Example usage</b>
1298 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
1299 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);
1301 @note MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
1302 MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
1303 MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
1304 MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
1305 MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
1306 MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
1307 MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
1308 MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
1309 MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.
1310 MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.
1311 MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
1312 MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
1313 MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
1314 MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
1315 MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
1316 MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
1319 #define MSR_NEHALEM_LASTBRANCH_0_FROM_IP 0x00000680
1320 #define MSR_NEHALEM_LASTBRANCH_1_FROM_IP 0x00000681
1321 #define MSR_NEHALEM_LASTBRANCH_2_FROM_IP 0x00000682
1322 #define MSR_NEHALEM_LASTBRANCH_3_FROM_IP 0x00000683
1323 #define MSR_NEHALEM_LASTBRANCH_4_FROM_IP 0x00000684
1324 #define MSR_NEHALEM_LASTBRANCH_5_FROM_IP 0x00000685
1325 #define MSR_NEHALEM_LASTBRANCH_6_FROM_IP 0x00000686
1326 #define MSR_NEHALEM_LASTBRANCH_7_FROM_IP 0x00000687
1327 #define MSR_NEHALEM_LASTBRANCH_8_FROM_IP 0x00000688
1328 #define MSR_NEHALEM_LASTBRANCH_9_FROM_IP 0x00000689
1329 #define MSR_NEHALEM_LASTBRANCH_10_FROM_IP 0x0000068A
1330 #define MSR_NEHALEM_LASTBRANCH_11_FROM_IP 0x0000068B
1331 #define MSR_NEHALEM_LASTBRANCH_12_FROM_IP 0x0000068C
1332 #define MSR_NEHALEM_LASTBRANCH_13_FROM_IP 0x0000068D
1333 #define MSR_NEHALEM_LASTBRANCH_14_FROM_IP 0x0000068E
1334 #define MSR_NEHALEM_LASTBRANCH_15_FROM_IP 0x0000068F
1339 Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch
1340 record registers on the last branch record stack. This part of the stack
1341 contains pointers to the destination instruction.
1343 @param ECX MSR_NEHALEM_LASTBRANCH_n_TO_IP
1344 @param EAX Lower 32-bits of MSR value.
1345 @param EDX Upper 32-bits of MSR value.
1347 <b>Example usage</b>
1351 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
1352 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);
1354 @note MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
1355 MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
1356 MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
1357 MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
1358 MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
1359 MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
1360 MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
1361 MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
1362 MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.
1363 MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.
1364 MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
1365 MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
1366 MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
1367 MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
1368 MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
1369 MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
1372 #define MSR_NEHALEM_LASTBRANCH_0_TO_IP 0x000006C0
1373 #define MSR_NEHALEM_LASTBRANCH_1_TO_IP 0x000006C1
1374 #define MSR_NEHALEM_LASTBRANCH_2_TO_IP 0x000006C2
1375 #define MSR_NEHALEM_LASTBRANCH_3_TO_IP 0x000006C3
1376 #define MSR_NEHALEM_LASTBRANCH_4_TO_IP 0x000006C4
1377 #define MSR_NEHALEM_LASTBRANCH_5_TO_IP 0x000006C5
1378 #define MSR_NEHALEM_LASTBRANCH_6_TO_IP 0x000006C6
1379 #define MSR_NEHALEM_LASTBRANCH_7_TO_IP 0x000006C7
1380 #define MSR_NEHALEM_LASTBRANCH_8_TO_IP 0x000006C8
1381 #define MSR_NEHALEM_LASTBRANCH_9_TO_IP 0x000006C9
1382 #define MSR_NEHALEM_LASTBRANCH_10_TO_IP 0x000006CA
1383 #define MSR_NEHALEM_LASTBRANCH_11_TO_IP 0x000006CB
1384 #define MSR_NEHALEM_LASTBRANCH_12_TO_IP 0x000006CC
1385 #define MSR_NEHALEM_LASTBRANCH_13_TO_IP 0x000006CD
1386 #define MSR_NEHALEM_LASTBRANCH_14_TO_IP 0x000006CE
1387 #define MSR_NEHALEM_LASTBRANCH_15_TO_IP 0x000006CF
1394 @param ECX MSR_NEHALEM_GQ_SNOOP_MESF (0x00000301)
1395 @param EAX Lower 32-bits of MSR value.
1396 Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.
1397 @param EDX Upper 32-bits of MSR value.
1398 Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.
1400 <b>Example usage</b>
1402 MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER Msr;
1404 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF);
1405 AsmWriteMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF, Msr.Uint64);
1407 @note MSR_NEHALEM_GQ_SNOOP_MESF is defined as MSR_GQ_SNOOP_MESF in SDM.
1409 #define MSR_NEHALEM_GQ_SNOOP_MESF 0x00000301
1412 MSR information returned for MSR index #MSR_NEHALEM_GQ_SNOOP_MESF
1416 /// Individual bit fields
1420 /// [Bit 0] From M to S (R/W).
1424 /// [Bit 1] From E to S (R/W).
1428 /// [Bit 2] From S to S (R/W).
1432 /// [Bit 3] From F to S (R/W).
1436 /// [Bit 4] From M to I (R/W).
1440 /// [Bit 5] From E to I (R/W).
1444 /// [Bit 6] From S to I (R/W).
1448 /// [Bit 7] From F to I (R/W).
1451 UINT32 Reserved1
:24;
1452 UINT32 Reserved2
:32;
1455 /// All bit fields as a 32-bit value
1459 /// All bit fields as a 64-bit value
1462 } MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
;
1466 Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
1469 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)
1470 @param EAX Lower 32-bits of MSR value.
1471 @param EDX Upper 32-bits of MSR value.
1473 <b>Example usage</b>
1477 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL);
1478 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL, Msr);
1480 @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_CTRL in SDM.
1482 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL 0x00000391
1486 Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
1489 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)
1490 @param EAX Lower 32-bits of MSR value.
1491 @param EDX Upper 32-bits of MSR value.
1493 <b>Example usage</b>
1497 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS);
1498 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS, Msr);
1500 @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS is defined as MSR_UNCORE_PERF_GLOBAL_STATUS in SDM.
1502 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS 0x00000392
1506 Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
1509 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)
1510 @param EAX Lower 32-bits of MSR value.
1511 @param EDX Upper 32-bits of MSR value.
1513 <b>Example usage</b>
1517 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL);
1518 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL, Msr);
1520 @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_OVF_CTRL in SDM.
1522 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393
1526 Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
1529 @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)
1530 @param EAX Lower 32-bits of MSR value.
1531 @param EDX Upper 32-bits of MSR value.
1533 <b>Example usage</b>
1537 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0);
1538 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0, Msr);
1540 @note MSR_NEHALEM_UNCORE_FIXED_CTR0 is defined as MSR_UNCORE_FIXED_CTR0 in SDM.
1542 #define MSR_NEHALEM_UNCORE_FIXED_CTR0 0x00000394
1546 Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
1549 @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)
1550 @param EAX Lower 32-bits of MSR value.
1551 @param EDX Upper 32-bits of MSR value.
1553 <b>Example usage</b>
1557 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL);
1558 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL, Msr);
1560 @note MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL is defined as MSR_UNCORE_FIXED_CTR_CTRL in SDM.
1562 #define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL 0x00000395
1566 Package. See Section 18.8.2.3, "Uncore Address/Opcode Match MSR.".
1568 @param ECX MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)
1569 @param EAX Lower 32-bits of MSR value.
1570 @param EDX Upper 32-bits of MSR value.
1572 <b>Example usage</b>
1576 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH);
1577 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH, Msr);
1579 @note MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH is defined as MSR_UNCORE_ADDR_OPCODE_MATCH in SDM.
1581 #define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH 0x00000396
1585 Package. See Section 18.8.2.2, "Uncore Performance Event Configuration
1588 @param ECX MSR_NEHALEM_UNCORE_PMCi
1589 @param EAX Lower 32-bits of MSR value.
1590 @param EDX Upper 32-bits of MSR value.
1592 <b>Example usage</b>
1596 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);
1597 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);
1599 @note MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM.
1600 MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM.
1601 MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM.
1602 MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM.
1603 MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM.
1604 MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM.
1605 MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM.
1606 MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.
1609 #define MSR_NEHALEM_UNCORE_PMC0 0x000003B0
1610 #define MSR_NEHALEM_UNCORE_PMC1 0x000003B1
1611 #define MSR_NEHALEM_UNCORE_PMC2 0x000003B2
1612 #define MSR_NEHALEM_UNCORE_PMC3 0x000003B3
1613 #define MSR_NEHALEM_UNCORE_PMC4 0x000003B4
1614 #define MSR_NEHALEM_UNCORE_PMC5 0x000003B5
1615 #define MSR_NEHALEM_UNCORE_PMC6 0x000003B6
1616 #define MSR_NEHALEM_UNCORE_PMC7 0x000003B7
1620 Package. See Section 18.8.2.2, "Uncore Performance Event Configuration
1623 @param ECX MSR_NEHALEM_UNCORE_PERFEVTSELi
1624 @param EAX Lower 32-bits of MSR value.
1625 @param EDX Upper 32-bits of MSR value.
1627 <b>Example usage</b>
1631 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);
1632 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);
1634 @note MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM.
1635 MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM.
1636 MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM.
1637 MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM.
1638 MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM.
1639 MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM.
1640 MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM.
1641 MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.
1644 #define MSR_NEHALEM_UNCORE_PERFEVTSEL0 0x000003C0
1645 #define MSR_NEHALEM_UNCORE_PERFEVTSEL1 0x000003C1
1646 #define MSR_NEHALEM_UNCORE_PERFEVTSEL2 0x000003C2
1647 #define MSR_NEHALEM_UNCORE_PERFEVTSEL3 0x000003C3
1648 #define MSR_NEHALEM_UNCORE_PERFEVTSEL4 0x000003C4
1649 #define MSR_NEHALEM_UNCORE_PERFEVTSEL5 0x000003C5
1650 #define MSR_NEHALEM_UNCORE_PERFEVTSEL6 0x000003C6
1651 #define MSR_NEHALEM_UNCORE_PERFEVTSEL7 0x000003C7
1656 Package. Uncore W-box perfmon fixed counter.
1658 @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR (0x00000394)
1659 @param EAX Lower 32-bits of MSR value.
1660 @param EDX Upper 32-bits of MSR value.
1662 <b>Example usage</b>
1666 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR);
1667 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR, Msr);
1669 @note MSR_NEHALEM_W_PMON_FIXED_CTR is defined as MSR_W_PMON_FIXED_CTR in SDM.
1671 #define MSR_NEHALEM_W_PMON_FIXED_CTR 0x00000394
1675 Package. Uncore U-box perfmon fixed counter control MSR.
1677 @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR_CTL (0x00000395)
1678 @param EAX Lower 32-bits of MSR value.
1679 @param EDX Upper 32-bits of MSR value.
1681 <b>Example usage</b>
1685 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL);
1686 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL, Msr);
1688 @note MSR_NEHALEM_W_PMON_FIXED_CTR_CTL is defined as MSR_W_PMON_FIXED_CTR_CTL in SDM.
1690 #define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL 0x00000395
1694 Package. Uncore U-box perfmon global control MSR.
1696 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_CTRL (0x00000C00)
1697 @param EAX Lower 32-bits of MSR value.
1698 @param EDX Upper 32-bits of MSR value.
1700 <b>Example usage</b>
1704 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL);
1705 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL, Msr);
1707 @note MSR_NEHALEM_U_PMON_GLOBAL_CTRL is defined as MSR_U_PMON_GLOBAL_CTRL in SDM.
1709 #define MSR_NEHALEM_U_PMON_GLOBAL_CTRL 0x00000C00
1713 Package. Uncore U-box perfmon global status MSR.
1715 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_STATUS (0x00000C01)
1716 @param EAX Lower 32-bits of MSR value.
1717 @param EDX Upper 32-bits of MSR value.
1719 <b>Example usage</b>
1723 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS);
1724 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS, Msr);
1726 @note MSR_NEHALEM_U_PMON_GLOBAL_STATUS is defined as MSR_U_PMON_GLOBAL_STATUS in SDM.
1728 #define MSR_NEHALEM_U_PMON_GLOBAL_STATUS 0x00000C01
1732 Package. Uncore U-box perfmon global overflow control MSR.
1734 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL (0x00000C02)
1735 @param EAX Lower 32-bits of MSR value.
1736 @param EDX Upper 32-bits of MSR value.
1738 <b>Example usage</b>
1742 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL);
1743 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL, Msr);
1745 @note MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL is defined as MSR_U_PMON_GLOBAL_OVF_CTRL in SDM.
1747 #define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL 0x00000C02
1751 Package. Uncore U-box perfmon event select MSR.
1753 @param ECX MSR_NEHALEM_U_PMON_EVNT_SEL (0x00000C10)
1754 @param EAX Lower 32-bits of MSR value.
1755 @param EDX Upper 32-bits of MSR value.
1757 <b>Example usage</b>
1761 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL);
1762 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL, Msr);
1764 @note MSR_NEHALEM_U_PMON_EVNT_SEL is defined as MSR_U_PMON_EVNT_SEL in SDM.
1766 #define MSR_NEHALEM_U_PMON_EVNT_SEL 0x00000C10
1770 Package. Uncore U-box perfmon counter MSR.
1772 @param ECX MSR_NEHALEM_U_PMON_CTR (0x00000C11)
1773 @param EAX Lower 32-bits of MSR value.
1774 @param EDX Upper 32-bits of MSR value.
1776 <b>Example usage</b>
1780 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_CTR);
1781 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_CTR, Msr);
1783 @note MSR_NEHALEM_U_PMON_CTR is defined as MSR_U_PMON_CTR in SDM.
1785 #define MSR_NEHALEM_U_PMON_CTR 0x00000C11
1789 Package. Uncore B-box 0 perfmon local box control MSR.
1791 @param ECX MSR_NEHALEM_B0_PMON_BOX_CTRL (0x00000C20)
1792 @param EAX Lower 32-bits of MSR value.
1793 @param EDX Upper 32-bits of MSR value.
1795 <b>Example usage</b>
1799 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL);
1800 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL, Msr);
1802 @note MSR_NEHALEM_B0_PMON_BOX_CTRL is defined as MSR_B0_PMON_BOX_CTRL in SDM.
1804 #define MSR_NEHALEM_B0_PMON_BOX_CTRL 0x00000C20
1808 Package. Uncore B-box 0 perfmon local box status MSR.
1810 @param ECX MSR_NEHALEM_B0_PMON_BOX_STATUS (0x00000C21)
1811 @param EAX Lower 32-bits of MSR value.
1812 @param EDX Upper 32-bits of MSR value.
1814 <b>Example usage</b>
1818 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS);
1819 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS, Msr);
1821 @note MSR_NEHALEM_B0_PMON_BOX_STATUS is defined as MSR_B0_PMON_BOX_STATUS in SDM.
1823 #define MSR_NEHALEM_B0_PMON_BOX_STATUS 0x00000C21
1827 Package. Uncore B-box 0 perfmon local box overflow control MSR.
1829 @param ECX MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL (0x00000C22)
1830 @param EAX Lower 32-bits of MSR value.
1831 @param EDX Upper 32-bits of MSR value.
1833 <b>Example usage</b>
1837 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL);
1838 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL, Msr);
1840 @note MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL is defined as MSR_B0_PMON_BOX_OVF_CTRL in SDM.
1842 #define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL 0x00000C22
1846 Package. Uncore B-box 0 perfmon event select MSR.
1848 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL0 (0x00000C30)
1849 @param EAX Lower 32-bits of MSR value.
1850 @param EDX Upper 32-bits of MSR value.
1852 <b>Example usage</b>
1856 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0);
1857 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0, Msr);
1859 @note MSR_NEHALEM_B0_PMON_EVNT_SEL0 is defined as MSR_B0_PMON_EVNT_SEL0 in SDM.
1861 #define MSR_NEHALEM_B0_PMON_EVNT_SEL0 0x00000C30
1865 Package. Uncore B-box 0 perfmon counter MSR.
1867 @param ECX MSR_NEHALEM_B0_PMON_CTR0 (0x00000C31)
1868 @param EAX Lower 32-bits of MSR value.
1869 @param EDX Upper 32-bits of MSR value.
1871 <b>Example usage</b>
1875 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR0);
1876 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR0, Msr);
1878 @note MSR_NEHALEM_B0_PMON_CTR0 is defined as MSR_B0_PMON_CTR0 in SDM.
1880 #define MSR_NEHALEM_B0_PMON_CTR0 0x00000C31
1884 Package. Uncore B-box 0 perfmon event select MSR.
1886 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL1 (0x00000C32)
1887 @param EAX Lower 32-bits of MSR value.
1888 @param EDX Upper 32-bits of MSR value.
1890 <b>Example usage</b>
1894 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1);
1895 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1, Msr);
1897 @note MSR_NEHALEM_B0_PMON_EVNT_SEL1 is defined as MSR_B0_PMON_EVNT_SEL1 in SDM.
1899 #define MSR_NEHALEM_B0_PMON_EVNT_SEL1 0x00000C32
1903 Package. Uncore B-box 0 perfmon counter MSR.
1905 @param ECX MSR_NEHALEM_B0_PMON_CTR1 (0x00000C33)
1906 @param EAX Lower 32-bits of MSR value.
1907 @param EDX Upper 32-bits of MSR value.
1909 <b>Example usage</b>
1913 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR1);
1914 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR1, Msr);
1916 @note MSR_NEHALEM_B0_PMON_CTR1 is defined as MSR_B0_PMON_CTR1 in SDM.
1918 #define MSR_NEHALEM_B0_PMON_CTR1 0x00000C33
1922 Package. Uncore B-box 0 perfmon event select MSR.
1924 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL2 (0x00000C34)
1925 @param EAX Lower 32-bits of MSR value.
1926 @param EDX Upper 32-bits of MSR value.
1928 <b>Example usage</b>
1932 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2);
1933 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2, Msr);
1935 @note MSR_NEHALEM_B0_PMON_EVNT_SEL2 is defined as MSR_B0_PMON_EVNT_SEL2 in SDM.
1937 #define MSR_NEHALEM_B0_PMON_EVNT_SEL2 0x00000C34
1941 Package. Uncore B-box 0 perfmon counter MSR.
1943 @param ECX MSR_NEHALEM_B0_PMON_CTR2 (0x00000C35)
1944 @param EAX Lower 32-bits of MSR value.
1945 @param EDX Upper 32-bits of MSR value.
1947 <b>Example usage</b>
1951 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR2);
1952 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR2, Msr);
1954 @note MSR_NEHALEM_B0_PMON_CTR2 is defined as MSR_B0_PMON_CTR2 in SDM.
1956 #define MSR_NEHALEM_B0_PMON_CTR2 0x00000C35
1960 Package. Uncore B-box 0 perfmon event select MSR.
1962 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL3 (0x00000C36)
1963 @param EAX Lower 32-bits of MSR value.
1964 @param EDX Upper 32-bits of MSR value.
1966 <b>Example usage</b>
1970 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3);
1971 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3, Msr);
1973 @note MSR_NEHALEM_B0_PMON_EVNT_SEL3 is defined as MSR_B0_PMON_EVNT_SEL3 in SDM.
1975 #define MSR_NEHALEM_B0_PMON_EVNT_SEL3 0x00000C36
1979 Package. Uncore B-box 0 perfmon counter MSR.
1981 @param ECX MSR_NEHALEM_B0_PMON_CTR3 (0x00000C37)
1982 @param EAX Lower 32-bits of MSR value.
1983 @param EDX Upper 32-bits of MSR value.
1985 <b>Example usage</b>
1989 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR3);
1990 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR3, Msr);
1992 @note MSR_NEHALEM_B0_PMON_CTR3 is defined as MSR_B0_PMON_CTR3 in SDM.
1994 #define MSR_NEHALEM_B0_PMON_CTR3 0x00000C37
1998 Package. Uncore S-box 0 perfmon local box control MSR.
2000 @param ECX MSR_NEHALEM_S0_PMON_BOX_CTRL (0x00000C40)
2001 @param EAX Lower 32-bits of MSR value.
2002 @param EDX Upper 32-bits of MSR value.
2004 <b>Example usage</b>
2008 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL);
2009 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL, Msr);
2011 @note MSR_NEHALEM_S0_PMON_BOX_CTRL is defined as MSR_S0_PMON_BOX_CTRL in SDM.
2013 #define MSR_NEHALEM_S0_PMON_BOX_CTRL 0x00000C40
2017 Package. Uncore S-box 0 perfmon local box status MSR.
2019 @param ECX MSR_NEHALEM_S0_PMON_BOX_STATUS (0x00000C41)
2020 @param EAX Lower 32-bits of MSR value.
2021 @param EDX Upper 32-bits of MSR value.
2023 <b>Example usage</b>
2027 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS);
2028 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS, Msr);
2030 @note MSR_NEHALEM_S0_PMON_BOX_STATUS is defined as MSR_S0_PMON_BOX_STATUS in SDM.
2032 #define MSR_NEHALEM_S0_PMON_BOX_STATUS 0x00000C41
2036 Package. Uncore S-box 0 perfmon local box overflow control MSR.
2038 @param ECX MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL (0x00000C42)
2039 @param EAX Lower 32-bits of MSR value.
2040 @param EDX Upper 32-bits of MSR value.
2042 <b>Example usage</b>
2046 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL);
2047 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL, Msr);
2049 @note MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL is defined as MSR_S0_PMON_BOX_OVF_CTRL in SDM.
2051 #define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL 0x00000C42
2055 Package. Uncore S-box 0 perfmon event select MSR.
2057 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL0 (0x00000C50)
2058 @param EAX Lower 32-bits of MSR value.
2059 @param EDX Upper 32-bits of MSR value.
2061 <b>Example usage</b>
2065 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0);
2066 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0, Msr);
2068 @note MSR_NEHALEM_S0_PMON_EVNT_SEL0 is defined as MSR_S0_PMON_EVNT_SEL0 in SDM.
2070 #define MSR_NEHALEM_S0_PMON_EVNT_SEL0 0x00000C50
2074 Package. Uncore S-box 0 perfmon counter MSR.
2076 @param ECX MSR_NEHALEM_S0_PMON_CTR0 (0x00000C51)
2077 @param EAX Lower 32-bits of MSR value.
2078 @param EDX Upper 32-bits of MSR value.
2080 <b>Example usage</b>
2084 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR0);
2085 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR0, Msr);
2087 @note MSR_NEHALEM_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.
2089 #define MSR_NEHALEM_S0_PMON_CTR0 0x00000C51
2093 Package. Uncore S-box 0 perfmon event select MSR.
2095 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL1 (0x00000C52)
2096 @param EAX Lower 32-bits of MSR value.
2097 @param EDX Upper 32-bits of MSR value.
2099 <b>Example usage</b>
2103 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1);
2104 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1, Msr);
2106 @note MSR_NEHALEM_S0_PMON_EVNT_SEL1 is defined as MSR_S0_PMON_EVNT_SEL1 in SDM.
2108 #define MSR_NEHALEM_S0_PMON_EVNT_SEL1 0x00000C52
2112 Package. Uncore S-box 0 perfmon counter MSR.
2114 @param ECX MSR_NEHALEM_S0_PMON_CTR1 (0x00000C53)
2115 @param EAX Lower 32-bits of MSR value.
2116 @param EDX Upper 32-bits of MSR value.
2118 <b>Example usage</b>
2122 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR1);
2123 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR1, Msr);
2125 @note MSR_NEHALEM_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.
2127 #define MSR_NEHALEM_S0_PMON_CTR1 0x00000C53
2131 Package. Uncore S-box 0 perfmon event select MSR.
2133 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL2 (0x00000C54)
2134 @param EAX Lower 32-bits of MSR value.
2135 @param EDX Upper 32-bits of MSR value.
2137 <b>Example usage</b>
2141 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2);
2142 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2, Msr);
2144 @note MSR_NEHALEM_S0_PMON_EVNT_SEL2 is defined as MSR_S0_PMON_EVNT_SEL2 in SDM.
2146 #define MSR_NEHALEM_S0_PMON_EVNT_SEL2 0x00000C54
2150 Package. Uncore S-box 0 perfmon counter MSR.
2152 @param ECX MSR_NEHALEM_S0_PMON_CTR2 (0x00000C55)
2153 @param EAX Lower 32-bits of MSR value.
2154 @param EDX Upper 32-bits of MSR value.
2156 <b>Example usage</b>
2160 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR2);
2161 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR2, Msr);
2163 @note MSR_NEHALEM_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.
2165 #define MSR_NEHALEM_S0_PMON_CTR2 0x00000C55
2169 Package. Uncore S-box 0 perfmon event select MSR.
2171 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL3 (0x00000C56)
2172 @param EAX Lower 32-bits of MSR value.
2173 @param EDX Upper 32-bits of MSR value.
2175 <b>Example usage</b>
2179 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3);
2180 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3, Msr);
2182 @note MSR_NEHALEM_S0_PMON_EVNT_SEL3 is defined as MSR_S0_PMON_EVNT_SEL3 in SDM.
2184 #define MSR_NEHALEM_S0_PMON_EVNT_SEL3 0x00000C56
2188 Package. Uncore S-box 0 perfmon counter MSR.
2190 @param ECX MSR_NEHALEM_S0_PMON_CTR3 (0x00000C57)
2191 @param EAX Lower 32-bits of MSR value.
2192 @param EDX Upper 32-bits of MSR value.
2194 <b>Example usage</b>
2198 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR3);
2199 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR3, Msr);
2201 @note MSR_NEHALEM_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.
2203 #define MSR_NEHALEM_S0_PMON_CTR3 0x00000C57
2207 Package. Uncore B-box 1 perfmon local box control MSR.
2209 @param ECX MSR_NEHALEM_B1_PMON_BOX_CTRL (0x00000C60)
2210 @param EAX Lower 32-bits of MSR value.
2211 @param EDX Upper 32-bits of MSR value.
2213 <b>Example usage</b>
2217 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL);
2218 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL, Msr);
2220 @note MSR_NEHALEM_B1_PMON_BOX_CTRL is defined as MSR_B1_PMON_BOX_CTRL in SDM.
2222 #define MSR_NEHALEM_B1_PMON_BOX_CTRL 0x00000C60
2226 Package. Uncore B-box 1 perfmon local box status MSR.
2228 @param ECX MSR_NEHALEM_B1_PMON_BOX_STATUS (0x00000C61)
2229 @param EAX Lower 32-bits of MSR value.
2230 @param EDX Upper 32-bits of MSR value.
2232 <b>Example usage</b>
2236 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS);
2237 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS, Msr);
2239 @note MSR_NEHALEM_B1_PMON_BOX_STATUS is defined as MSR_B1_PMON_BOX_STATUS in SDM.
2241 #define MSR_NEHALEM_B1_PMON_BOX_STATUS 0x00000C61
2245 Package. Uncore B-box 1 perfmon local box overflow control MSR.
2247 @param ECX MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL (0x00000C62)
2248 @param EAX Lower 32-bits of MSR value.
2249 @param EDX Upper 32-bits of MSR value.
2251 <b>Example usage</b>
2255 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL);
2256 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL, Msr);
2258 @note MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL is defined as MSR_B1_PMON_BOX_OVF_CTRL in SDM.
2260 #define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL 0x00000C62
2264 Package. Uncore B-box 1 perfmon event select MSR.
2266 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL0 (0x00000C70)
2267 @param EAX Lower 32-bits of MSR value.
2268 @param EDX Upper 32-bits of MSR value.
2270 <b>Example usage</b>
2274 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0);
2275 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0, Msr);
2277 @note MSR_NEHALEM_B1_PMON_EVNT_SEL0 is defined as MSR_B1_PMON_EVNT_SEL0 in SDM.
2279 #define MSR_NEHALEM_B1_PMON_EVNT_SEL0 0x00000C70
2283 Package. Uncore B-box 1 perfmon counter MSR.
2285 @param ECX MSR_NEHALEM_B1_PMON_CTR0 (0x00000C71)
2286 @param EAX Lower 32-bits of MSR value.
2287 @param EDX Upper 32-bits of MSR value.
2289 <b>Example usage</b>
2293 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR0);
2294 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR0, Msr);
2296 @note MSR_NEHALEM_B1_PMON_CTR0 is defined as MSR_B1_PMON_CTR0 in SDM.
2298 #define MSR_NEHALEM_B1_PMON_CTR0 0x00000C71
2302 Package. Uncore B-box 1 perfmon event select MSR.
2304 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL1 (0x00000C72)
2305 @param EAX Lower 32-bits of MSR value.
2306 @param EDX Upper 32-bits of MSR value.
2308 <b>Example usage</b>
2312 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1);
2313 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1, Msr);
2315 @note MSR_NEHALEM_B1_PMON_EVNT_SEL1 is defined as MSR_B1_PMON_EVNT_SEL1 in SDM.
2317 #define MSR_NEHALEM_B1_PMON_EVNT_SEL1 0x00000C72
2321 Package. Uncore B-box 1 perfmon counter MSR.
2323 @param ECX MSR_NEHALEM_B1_PMON_CTR1 (0x00000C73)
2324 @param EAX Lower 32-bits of MSR value.
2325 @param EDX Upper 32-bits of MSR value.
2327 <b>Example usage</b>
2331 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR1);
2332 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR1, Msr);
2334 @note MSR_NEHALEM_B1_PMON_CTR1 is defined as MSR_B1_PMON_CTR1 in SDM.
2336 #define MSR_NEHALEM_B1_PMON_CTR1 0x00000C73
2340 Package. Uncore B-box 1 perfmon event select MSR.
2342 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL2 (0x00000C74)
2343 @param EAX Lower 32-bits of MSR value.
2344 @param EDX Upper 32-bits of MSR value.
2346 <b>Example usage</b>
2350 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2);
2351 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2, Msr);
2353 @note MSR_NEHALEM_B1_PMON_EVNT_SEL2 is defined as MSR_B1_PMON_EVNT_SEL2 in SDM.
2355 #define MSR_NEHALEM_B1_PMON_EVNT_SEL2 0x00000C74
2359 Package. Uncore B-box 1 perfmon counter MSR.
2361 @param ECX MSR_NEHALEM_B1_PMON_CTR2 (0x00000C75)
2362 @param EAX Lower 32-bits of MSR value.
2363 @param EDX Upper 32-bits of MSR value.
2365 <b>Example usage</b>
2369 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR2);
2370 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR2, Msr);
2372 @note MSR_NEHALEM_B1_PMON_CTR2 is defined as MSR_B1_PMON_CTR2 in SDM.
2374 #define MSR_NEHALEM_B1_PMON_CTR2 0x00000C75
2378 Package. Uncore B-box 1vperfmon event select MSR.
2380 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL3 (0x00000C76)
2381 @param EAX Lower 32-bits of MSR value.
2382 @param EDX Upper 32-bits of MSR value.
2384 <b>Example usage</b>
2388 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3);
2389 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3, Msr);
2391 @note MSR_NEHALEM_B1_PMON_EVNT_SEL3 is defined as MSR_B1_PMON_EVNT_SEL3 in SDM.
2393 #define MSR_NEHALEM_B1_PMON_EVNT_SEL3 0x00000C76
2397 Package. Uncore B-box 1 perfmon counter MSR.
2399 @param ECX MSR_NEHALEM_B1_PMON_CTR3 (0x00000C77)
2400 @param EAX Lower 32-bits of MSR value.
2401 @param EDX Upper 32-bits of MSR value.
2403 <b>Example usage</b>
2407 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR3);
2408 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR3, Msr);
2410 @note MSR_NEHALEM_B1_PMON_CTR3 is defined as MSR_B1_PMON_CTR3 in SDM.
2412 #define MSR_NEHALEM_B1_PMON_CTR3 0x00000C77
2416 Package. Uncore W-box perfmon local box control MSR.
2418 @param ECX MSR_NEHALEM_W_PMON_BOX_CTRL (0x00000C80)
2419 @param EAX Lower 32-bits of MSR value.
2420 @param EDX Upper 32-bits of MSR value.
2422 <b>Example usage</b>
2426 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL);
2427 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL, Msr);
2429 @note MSR_NEHALEM_W_PMON_BOX_CTRL is defined as MSR_W_PMON_BOX_CTRL in SDM.
2431 #define MSR_NEHALEM_W_PMON_BOX_CTRL 0x00000C80
2435 Package. Uncore W-box perfmon local box status MSR.
2437 @param ECX MSR_NEHALEM_W_PMON_BOX_STATUS (0x00000C81)
2438 @param EAX Lower 32-bits of MSR value.
2439 @param EDX Upper 32-bits of MSR value.
2441 <b>Example usage</b>
2445 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS);
2446 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS, Msr);
2448 @note MSR_NEHALEM_W_PMON_BOX_STATUS is defined as MSR_W_PMON_BOX_STATUS in SDM.
2450 #define MSR_NEHALEM_W_PMON_BOX_STATUS 0x00000C81
2454 Package. Uncore W-box perfmon local box overflow control MSR.
2456 @param ECX MSR_NEHALEM_W_PMON_BOX_OVF_CTRL (0x00000C82)
2457 @param EAX Lower 32-bits of MSR value.
2458 @param EDX Upper 32-bits of MSR value.
2460 <b>Example usage</b>
2464 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL);
2465 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL, Msr);
2467 @note MSR_NEHALEM_W_PMON_BOX_OVF_CTRL is defined as MSR_W_PMON_BOX_OVF_CTRL in SDM.
2469 #define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL 0x00000C82
2473 Package. Uncore W-box perfmon event select MSR.
2475 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL0 (0x00000C90)
2476 @param EAX Lower 32-bits of MSR value.
2477 @param EDX Upper 32-bits of MSR value.
2479 <b>Example usage</b>
2483 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0);
2484 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0, Msr);
2486 @note MSR_NEHALEM_W_PMON_EVNT_SEL0 is defined as MSR_W_PMON_EVNT_SEL0 in SDM.
2488 #define MSR_NEHALEM_W_PMON_EVNT_SEL0 0x00000C90
2492 Package. Uncore W-box perfmon counter MSR.
2494 @param ECX MSR_NEHALEM_W_PMON_CTR0 (0x00000C91)
2495 @param EAX Lower 32-bits of MSR value.
2496 @param EDX Upper 32-bits of MSR value.
2498 <b>Example usage</b>
2502 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR0);
2503 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR0, Msr);
2505 @note MSR_NEHALEM_W_PMON_CTR0 is defined as MSR_W_PMON_CTR0 in SDM.
2507 #define MSR_NEHALEM_W_PMON_CTR0 0x00000C91
2511 Package. Uncore W-box perfmon event select MSR.
2513 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL1 (0x00000C92)
2514 @param EAX Lower 32-bits of MSR value.
2515 @param EDX Upper 32-bits of MSR value.
2517 <b>Example usage</b>
2521 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1);
2522 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1, Msr);
2524 @note MSR_NEHALEM_W_PMON_EVNT_SEL1 is defined as MSR_W_PMON_EVNT_SEL1 in SDM.
2526 #define MSR_NEHALEM_W_PMON_EVNT_SEL1 0x00000C92
2530 Package. Uncore W-box perfmon counter MSR.
2532 @param ECX MSR_NEHALEM_W_PMON_CTR1 (0x00000C93)
2533 @param EAX Lower 32-bits of MSR value.
2534 @param EDX Upper 32-bits of MSR value.
2536 <b>Example usage</b>
2540 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR1);
2541 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR1, Msr);
2543 @note MSR_NEHALEM_W_PMON_CTR1 is defined as MSR_W_PMON_CTR1 in SDM.
2545 #define MSR_NEHALEM_W_PMON_CTR1 0x00000C93
2549 Package. Uncore W-box perfmon event select MSR.
2551 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL2 (0x00000C94)
2552 @param EAX Lower 32-bits of MSR value.
2553 @param EDX Upper 32-bits of MSR value.
2555 <b>Example usage</b>
2559 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2);
2560 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2, Msr);
2562 @note MSR_NEHALEM_W_PMON_EVNT_SEL2 is defined as MSR_W_PMON_EVNT_SEL2 in SDM.
2564 #define MSR_NEHALEM_W_PMON_EVNT_SEL2 0x00000C94
2568 Package. Uncore W-box perfmon counter MSR.
2570 @param ECX MSR_NEHALEM_W_PMON_CTR2 (0x00000C95)
2571 @param EAX Lower 32-bits of MSR value.
2572 @param EDX Upper 32-bits of MSR value.
2574 <b>Example usage</b>
2578 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR2);
2579 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR2, Msr);
2581 @note MSR_NEHALEM_W_PMON_CTR2 is defined as MSR_W_PMON_CTR2 in SDM.
2583 #define MSR_NEHALEM_W_PMON_CTR2 0x00000C95
2587 Package. Uncore W-box perfmon event select MSR.
2589 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL3 (0x00000C96)
2590 @param EAX Lower 32-bits of MSR value.
2591 @param EDX Upper 32-bits of MSR value.
2593 <b>Example usage</b>
2597 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3);
2598 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3, Msr);
2600 @note MSR_NEHALEM_W_PMON_EVNT_SEL3 is defined as MSR_W_PMON_EVNT_SEL3 in SDM.
2602 #define MSR_NEHALEM_W_PMON_EVNT_SEL3 0x00000C96
2606 Package. Uncore W-box perfmon counter MSR.
2608 @param ECX MSR_NEHALEM_W_PMON_CTR3 (0x00000C97)
2609 @param EAX Lower 32-bits of MSR value.
2610 @param EDX Upper 32-bits of MSR value.
2612 <b>Example usage</b>
2616 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR3);
2617 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR3, Msr);
2619 @note MSR_NEHALEM_W_PMON_CTR3 is defined as MSR_W_PMON_CTR3 in SDM.
2621 #define MSR_NEHALEM_W_PMON_CTR3 0x00000C97
2625 Package. Uncore M-box 0 perfmon local box control MSR.
2627 @param ECX MSR_NEHALEM_M0_PMON_BOX_CTRL (0x00000CA0)
2628 @param EAX Lower 32-bits of MSR value.
2629 @param EDX Upper 32-bits of MSR value.
2631 <b>Example usage</b>
2635 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL);
2636 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL, Msr);
2638 @note MSR_NEHALEM_M0_PMON_BOX_CTRL is defined as MSR_M0_PMON_BOX_CTRL in SDM.
2640 #define MSR_NEHALEM_M0_PMON_BOX_CTRL 0x00000CA0
2644 Package. Uncore M-box 0 perfmon local box status MSR.
2646 @param ECX MSR_NEHALEM_M0_PMON_BOX_STATUS (0x00000CA1)
2647 @param EAX Lower 32-bits of MSR value.
2648 @param EDX Upper 32-bits of MSR value.
2650 <b>Example usage</b>
2654 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS);
2655 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS, Msr);
2657 @note MSR_NEHALEM_M0_PMON_BOX_STATUS is defined as MSR_M0_PMON_BOX_STATUS in SDM.
2659 #define MSR_NEHALEM_M0_PMON_BOX_STATUS 0x00000CA1
2663 Package. Uncore M-box 0 perfmon local box overflow control MSR.
2665 @param ECX MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL (0x00000CA2)
2666 @param EAX Lower 32-bits of MSR value.
2667 @param EDX Upper 32-bits of MSR value.
2669 <b>Example usage</b>
2673 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL);
2674 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL, Msr);
2676 @note MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL is defined as MSR_M0_PMON_BOX_OVF_CTRL in SDM.
2678 #define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL 0x00000CA2
2682 Package. Uncore M-box 0 perfmon time stamp unit select MSR.
2684 @param ECX MSR_NEHALEM_M0_PMON_TIMESTAMP (0x00000CA4)
2685 @param EAX Lower 32-bits of MSR value.
2686 @param EDX Upper 32-bits of MSR value.
2688 <b>Example usage</b>
2692 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP);
2693 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP, Msr);
2695 @note MSR_NEHALEM_M0_PMON_TIMESTAMP is defined as MSR_M0_PMON_TIMESTAMP in SDM.
2697 #define MSR_NEHALEM_M0_PMON_TIMESTAMP 0x00000CA4
2701 Package. Uncore M-box 0 perfmon DSP unit select MSR.
2703 @param ECX MSR_NEHALEM_M0_PMON_DSP (0x00000CA5)
2704 @param EAX Lower 32-bits of MSR value.
2705 @param EDX Upper 32-bits of MSR value.
2707 <b>Example usage</b>
2711 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_DSP);
2712 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_DSP, Msr);
2714 @note MSR_NEHALEM_M0_PMON_DSP is defined as MSR_M0_PMON_DSP in SDM.
2716 #define MSR_NEHALEM_M0_PMON_DSP 0x00000CA5
2720 Package. Uncore M-box 0 perfmon ISS unit select MSR.
2722 @param ECX MSR_NEHALEM_M0_PMON_ISS (0x00000CA6)
2723 @param EAX Lower 32-bits of MSR value.
2724 @param EDX Upper 32-bits of MSR value.
2726 <b>Example usage</b>
2730 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ISS);
2731 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ISS, Msr);
2733 @note MSR_NEHALEM_M0_PMON_ISS is defined as MSR_M0_PMON_ISS in SDM.
2735 #define MSR_NEHALEM_M0_PMON_ISS 0x00000CA6
2739 Package. Uncore M-box 0 perfmon MAP unit select MSR.
2741 @param ECX MSR_NEHALEM_M0_PMON_MAP (0x00000CA7)
2742 @param EAX Lower 32-bits of MSR value.
2743 @param EDX Upper 32-bits of MSR value.
2745 <b>Example usage</b>
2749 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MAP);
2750 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MAP, Msr);
2752 @note MSR_NEHALEM_M0_PMON_MAP is defined as MSR_M0_PMON_MAP in SDM.
2754 #define MSR_NEHALEM_M0_PMON_MAP 0x00000CA7
2758 Package. Uncore M-box 0 perfmon MIC THR select MSR.
2760 @param ECX MSR_NEHALEM_M0_PMON_MSC_THR (0x00000CA8)
2761 @param EAX Lower 32-bits of MSR value.
2762 @param EDX Upper 32-bits of MSR value.
2764 <b>Example usage</b>
2768 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR);
2769 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR, Msr);
2771 @note MSR_NEHALEM_M0_PMON_MSC_THR is defined as MSR_M0_PMON_MSC_THR in SDM.
2773 #define MSR_NEHALEM_M0_PMON_MSC_THR 0x00000CA8
2777 Package. Uncore M-box 0 perfmon PGT unit select MSR.
2779 @param ECX MSR_NEHALEM_M0_PMON_PGT (0x00000CA9)
2780 @param EAX Lower 32-bits of MSR value.
2781 @param EDX Upper 32-bits of MSR value.
2783 <b>Example usage</b>
2787 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PGT);
2788 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PGT, Msr);
2790 @note MSR_NEHALEM_M0_PMON_PGT is defined as MSR_M0_PMON_PGT in SDM.
2792 #define MSR_NEHALEM_M0_PMON_PGT 0x00000CA9
2796 Package. Uncore M-box 0 perfmon PLD unit select MSR.
2798 @param ECX MSR_NEHALEM_M0_PMON_PLD (0x00000CAA)
2799 @param EAX Lower 32-bits of MSR value.
2800 @param EDX Upper 32-bits of MSR value.
2802 <b>Example usage</b>
2806 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PLD);
2807 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PLD, Msr);
2809 @note MSR_NEHALEM_M0_PMON_PLD is defined as MSR_M0_PMON_PLD in SDM.
2811 #define MSR_NEHALEM_M0_PMON_PLD 0x00000CAA
2815 Package. Uncore M-box 0 perfmon ZDP unit select MSR.
2817 @param ECX MSR_NEHALEM_M0_PMON_ZDP (0x00000CAB)
2818 @param EAX Lower 32-bits of MSR value.
2819 @param EDX Upper 32-bits of MSR value.
2821 <b>Example usage</b>
2825 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ZDP);
2826 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ZDP, Msr);
2828 @note MSR_NEHALEM_M0_PMON_ZDP is defined as MSR_M0_PMON_ZDP in SDM.
2830 #define MSR_NEHALEM_M0_PMON_ZDP 0x00000CAB
2834 Package. Uncore M-box 0 perfmon event select MSR.
2836 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL0 (0x00000CB0)
2837 @param EAX Lower 32-bits of MSR value.
2838 @param EDX Upper 32-bits of MSR value.
2840 <b>Example usage</b>
2844 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0);
2845 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0, Msr);
2847 @note MSR_NEHALEM_M0_PMON_EVNT_SEL0 is defined as MSR_M0_PMON_EVNT_SEL0 in SDM.
2849 #define MSR_NEHALEM_M0_PMON_EVNT_SEL0 0x00000CB0
2853 Package. Uncore M-box 0 perfmon counter MSR.
2855 @param ECX MSR_NEHALEM_M0_PMON_CTR0 (0x00000CB1)
2856 @param EAX Lower 32-bits of MSR value.
2857 @param EDX Upper 32-bits of MSR value.
2859 <b>Example usage</b>
2863 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR0);
2864 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR0, Msr);
2866 @note MSR_NEHALEM_M0_PMON_CTR0 is defined as MSR_M0_PMON_CTR0 in SDM.
2868 #define MSR_NEHALEM_M0_PMON_CTR0 0x00000CB1
2872 Package. Uncore M-box 0 perfmon event select MSR.
2874 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL1 (0x00000CB2)
2875 @param EAX Lower 32-bits of MSR value.
2876 @param EDX Upper 32-bits of MSR value.
2878 <b>Example usage</b>
2882 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1);
2883 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1, Msr);
2885 @note MSR_NEHALEM_M0_PMON_EVNT_SEL1 is defined as MSR_M0_PMON_EVNT_SEL1 in SDM.
2887 #define MSR_NEHALEM_M0_PMON_EVNT_SEL1 0x00000CB2
2891 Package. Uncore M-box 0 perfmon counter MSR.
2893 @param ECX MSR_NEHALEM_M0_PMON_CTR1 (0x00000CB3)
2894 @param EAX Lower 32-bits of MSR value.
2895 @param EDX Upper 32-bits of MSR value.
2897 <b>Example usage</b>
2901 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR1);
2902 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR1, Msr);
2904 @note MSR_NEHALEM_M0_PMON_CTR1 is defined as MSR_M0_PMON_CTR1 in SDM.
2906 #define MSR_NEHALEM_M0_PMON_CTR1 0x00000CB3
2910 Package. Uncore M-box 0 perfmon event select MSR.
2912 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL2 (0x00000CB4)
2913 @param EAX Lower 32-bits of MSR value.
2914 @param EDX Upper 32-bits of MSR value.
2916 <b>Example usage</b>
2920 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2);
2921 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2, Msr);
2923 @note MSR_NEHALEM_M0_PMON_EVNT_SEL2 is defined as MSR_M0_PMON_EVNT_SEL2 in SDM.
2925 #define MSR_NEHALEM_M0_PMON_EVNT_SEL2 0x00000CB4
2929 Package. Uncore M-box 0 perfmon counter MSR.
2931 @param ECX MSR_NEHALEM_M0_PMON_CTR2 (0x00000CB5)
2932 @param EAX Lower 32-bits of MSR value.
2933 @param EDX Upper 32-bits of MSR value.
2935 <b>Example usage</b>
2939 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR2);
2940 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR2, Msr);
2942 @note MSR_NEHALEM_M0_PMON_CTR2 is defined as MSR_M0_PMON_CTR2 in SDM.
2944 #define MSR_NEHALEM_M0_PMON_CTR2 0x00000CB5
2948 Package. Uncore M-box 0 perfmon event select MSR.
2950 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL3 (0x00000CB6)
2951 @param EAX Lower 32-bits of MSR value.
2952 @param EDX Upper 32-bits of MSR value.
2954 <b>Example usage</b>
2958 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3);
2959 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3, Msr);
2961 @note MSR_NEHALEM_M0_PMON_EVNT_SEL3 is defined as MSR_M0_PMON_EVNT_SEL3 in SDM.
2963 #define MSR_NEHALEM_M0_PMON_EVNT_SEL3 0x00000CB6
2967 Package. Uncore M-box 0 perfmon counter MSR.
2969 @param ECX MSR_NEHALEM_M0_PMON_CTR3 (0x00000CB7)
2970 @param EAX Lower 32-bits of MSR value.
2971 @param EDX Upper 32-bits of MSR value.
2973 <b>Example usage</b>
2977 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR3);
2978 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR3, Msr);
2980 @note MSR_NEHALEM_M0_PMON_CTR3 is defined as MSR_M0_PMON_CTR3 in SDM.
2982 #define MSR_NEHALEM_M0_PMON_CTR3 0x00000CB7
2986 Package. Uncore M-box 0 perfmon event select MSR.
2988 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL4 (0x00000CB8)
2989 @param EAX Lower 32-bits of MSR value.
2990 @param EDX Upper 32-bits of MSR value.
2992 <b>Example usage</b>
2996 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4);
2997 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4, Msr);
2999 @note MSR_NEHALEM_M0_PMON_EVNT_SEL4 is defined as MSR_M0_PMON_EVNT_SEL4 in SDM.
3001 #define MSR_NEHALEM_M0_PMON_EVNT_SEL4 0x00000CB8
3005 Package. Uncore M-box 0 perfmon counter MSR.
3007 @param ECX MSR_NEHALEM_M0_PMON_CTR4 (0x00000CB9)
3008 @param EAX Lower 32-bits of MSR value.
3009 @param EDX Upper 32-bits of MSR value.
3011 <b>Example usage</b>
3015 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR4);
3016 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR4, Msr);
3018 @note MSR_NEHALEM_M0_PMON_CTR4 is defined as MSR_M0_PMON_CTR4 in SDM.
3020 #define MSR_NEHALEM_M0_PMON_CTR4 0x00000CB9
3024 Package. Uncore M-box 0 perfmon event select MSR.
3026 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL5 (0x00000CBA)
3027 @param EAX Lower 32-bits of MSR value.
3028 @param EDX Upper 32-bits of MSR value.
3030 <b>Example usage</b>
3034 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5);
3035 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5, Msr);
3037 @note MSR_NEHALEM_M0_PMON_EVNT_SEL5 is defined as MSR_M0_PMON_EVNT_SEL5 in SDM.
3039 #define MSR_NEHALEM_M0_PMON_EVNT_SEL5 0x00000CBA
3043 Package. Uncore M-box 0 perfmon counter MSR.
3045 @param ECX MSR_NEHALEM_M0_PMON_CTR5 (0x00000CBB)
3046 @param EAX Lower 32-bits of MSR value.
3047 @param EDX Upper 32-bits of MSR value.
3049 <b>Example usage</b>
3053 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR5);
3054 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR5, Msr);
3056 @note MSR_NEHALEM_M0_PMON_CTR5 is defined as MSR_M0_PMON_CTR5 in SDM.
3058 #define MSR_NEHALEM_M0_PMON_CTR5 0x00000CBB
3062 Package. Uncore S-box 1 perfmon local box control MSR.
3064 @param ECX MSR_NEHALEM_S1_PMON_BOX_CTRL (0x00000CC0)
3065 @param EAX Lower 32-bits of MSR value.
3066 @param EDX Upper 32-bits of MSR value.
3068 <b>Example usage</b>
3072 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL);
3073 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL, Msr);
3075 @note MSR_NEHALEM_S1_PMON_BOX_CTRL is defined as MSR_S1_PMON_BOX_CTRL in SDM.
3077 #define MSR_NEHALEM_S1_PMON_BOX_CTRL 0x00000CC0
3081 Package. Uncore S-box 1 perfmon local box status MSR.
3083 @param ECX MSR_NEHALEM_S1_PMON_BOX_STATUS (0x00000CC1)
3084 @param EAX Lower 32-bits of MSR value.
3085 @param EDX Upper 32-bits of MSR value.
3087 <b>Example usage</b>
3091 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS);
3092 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS, Msr);
3094 @note MSR_NEHALEM_S1_PMON_BOX_STATUS is defined as MSR_S1_PMON_BOX_STATUS in SDM.
3096 #define MSR_NEHALEM_S1_PMON_BOX_STATUS 0x00000CC1
3100 Package. Uncore S-box 1 perfmon local box overflow control MSR.
3102 @param ECX MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL (0x00000CC2)
3103 @param EAX Lower 32-bits of MSR value.
3104 @param EDX Upper 32-bits of MSR value.
3106 <b>Example usage</b>
3110 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL);
3111 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL, Msr);
3113 @note MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL is defined as MSR_S1_PMON_BOX_OVF_CTRL in SDM.
3115 #define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL 0x00000CC2
3119 Package. Uncore S-box 1 perfmon event select MSR.
3121 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL0 (0x00000CD0)
3122 @param EAX Lower 32-bits of MSR value.
3123 @param EDX Upper 32-bits of MSR value.
3125 <b>Example usage</b>
3129 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0);
3130 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0, Msr);
3132 @note MSR_NEHALEM_S1_PMON_EVNT_SEL0 is defined as MSR_S1_PMON_EVNT_SEL0 in SDM.
3134 #define MSR_NEHALEM_S1_PMON_EVNT_SEL0 0x00000CD0
3138 Package. Uncore S-box 1 perfmon counter MSR.
3140 @param ECX MSR_NEHALEM_S1_PMON_CTR0 (0x00000CD1)
3141 @param EAX Lower 32-bits of MSR value.
3142 @param EDX Upper 32-bits of MSR value.
3144 <b>Example usage</b>
3148 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR0);
3149 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR0, Msr);
3151 @note MSR_NEHALEM_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.
3153 #define MSR_NEHALEM_S1_PMON_CTR0 0x00000CD1
3157 Package. Uncore S-box 1 perfmon event select MSR.
3159 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL1 (0x00000CD2)
3160 @param EAX Lower 32-bits of MSR value.
3161 @param EDX Upper 32-bits of MSR value.
3163 <b>Example usage</b>
3167 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1);
3168 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1, Msr);
3170 @note MSR_NEHALEM_S1_PMON_EVNT_SEL1 is defined as MSR_S1_PMON_EVNT_SEL1 in SDM.
3172 #define MSR_NEHALEM_S1_PMON_EVNT_SEL1 0x00000CD2
3176 Package. Uncore S-box 1 perfmon counter MSR.
3178 @param ECX MSR_NEHALEM_S1_PMON_CTR1 (0x00000CD3)
3179 @param EAX Lower 32-bits of MSR value.
3180 @param EDX Upper 32-bits of MSR value.
3182 <b>Example usage</b>
3186 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR1);
3187 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR1, Msr);
3189 @note MSR_NEHALEM_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.
3191 #define MSR_NEHALEM_S1_PMON_CTR1 0x00000CD3
3195 Package. Uncore S-box 1 perfmon event select MSR.
3197 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL2 (0x00000CD4)
3198 @param EAX Lower 32-bits of MSR value.
3199 @param EDX Upper 32-bits of MSR value.
3201 <b>Example usage</b>
3205 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2);
3206 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2, Msr);
3208 @note MSR_NEHALEM_S1_PMON_EVNT_SEL2 is defined as MSR_S1_PMON_EVNT_SEL2 in SDM.
3210 #define MSR_NEHALEM_S1_PMON_EVNT_SEL2 0x00000CD4
3214 Package. Uncore S-box 1 perfmon counter MSR.
3216 @param ECX MSR_NEHALEM_S1_PMON_CTR2 (0x00000CD5)
3217 @param EAX Lower 32-bits of MSR value.
3218 @param EDX Upper 32-bits of MSR value.
3220 <b>Example usage</b>
3224 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR2);
3225 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR2, Msr);
3227 @note MSR_NEHALEM_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.
3229 #define MSR_NEHALEM_S1_PMON_CTR2 0x00000CD5
3233 Package. Uncore S-box 1 perfmon event select MSR.
3235 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL3 (0x00000CD6)
3236 @param EAX Lower 32-bits of MSR value.
3237 @param EDX Upper 32-bits of MSR value.
3239 <b>Example usage</b>
3243 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3);
3244 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3, Msr);
3246 @note MSR_NEHALEM_S1_PMON_EVNT_SEL3 is defined as MSR_S1_PMON_EVNT_SEL3 in SDM.
3248 #define MSR_NEHALEM_S1_PMON_EVNT_SEL3 0x00000CD6
3252 Package. Uncore S-box 1 perfmon counter MSR.
3254 @param ECX MSR_NEHALEM_S1_PMON_CTR3 (0x00000CD7)
3255 @param EAX Lower 32-bits of MSR value.
3256 @param EDX Upper 32-bits of MSR value.
3258 <b>Example usage</b>
3262 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR3);
3263 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR3, Msr);
3265 @note MSR_NEHALEM_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.
3267 #define MSR_NEHALEM_S1_PMON_CTR3 0x00000CD7
3271 Package. Uncore M-box 1 perfmon local box control MSR.
3273 @param ECX MSR_NEHALEM_M1_PMON_BOX_CTRL (0x00000CE0)
3274 @param EAX Lower 32-bits of MSR value.
3275 @param EDX Upper 32-bits of MSR value.
3277 <b>Example usage</b>
3281 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL);
3282 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL, Msr);
3284 @note MSR_NEHALEM_M1_PMON_BOX_CTRL is defined as MSR_M1_PMON_BOX_CTRL in SDM.
3286 #define MSR_NEHALEM_M1_PMON_BOX_CTRL 0x00000CE0
3290 Package. Uncore M-box 1 perfmon local box status MSR.
3292 @param ECX MSR_NEHALEM_M1_PMON_BOX_STATUS (0x00000CE1)
3293 @param EAX Lower 32-bits of MSR value.
3294 @param EDX Upper 32-bits of MSR value.
3296 <b>Example usage</b>
3300 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS);
3301 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS, Msr);
3303 @note MSR_NEHALEM_M1_PMON_BOX_STATUS is defined as MSR_M1_PMON_BOX_STATUS in SDM.
3305 #define MSR_NEHALEM_M1_PMON_BOX_STATUS 0x00000CE1
3309 Package. Uncore M-box 1 perfmon local box overflow control MSR.
3311 @param ECX MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL (0x00000CE2)
3312 @param EAX Lower 32-bits of MSR value.
3313 @param EDX Upper 32-bits of MSR value.
3315 <b>Example usage</b>
3319 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL);
3320 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL, Msr);
3322 @note MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL is defined as MSR_M1_PMON_BOX_OVF_CTRL in SDM.
3324 #define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL 0x00000CE2
3328 Package. Uncore M-box 1 perfmon time stamp unit select MSR.
3330 @param ECX MSR_NEHALEM_M1_PMON_TIMESTAMP (0x00000CE4)
3331 @param EAX Lower 32-bits of MSR value.
3332 @param EDX Upper 32-bits of MSR value.
3334 <b>Example usage</b>
3338 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP);
3339 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP, Msr);
3341 @note MSR_NEHALEM_M1_PMON_TIMESTAMP is defined as MSR_M1_PMON_TIMESTAMP in SDM.
3343 #define MSR_NEHALEM_M1_PMON_TIMESTAMP 0x00000CE4
3347 Package. Uncore M-box 1 perfmon DSP unit select MSR.
3349 @param ECX MSR_NEHALEM_M1_PMON_DSP (0x00000CE5)
3350 @param EAX Lower 32-bits of MSR value.
3351 @param EDX Upper 32-bits of MSR value.
3353 <b>Example usage</b>
3357 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_DSP);
3358 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_DSP, Msr);
3360 @note MSR_NEHALEM_M1_PMON_DSP is defined as MSR_M1_PMON_DSP in SDM.
3362 #define MSR_NEHALEM_M1_PMON_DSP 0x00000CE5
3366 Package. Uncore M-box 1 perfmon ISS unit select MSR.
3368 @param ECX MSR_NEHALEM_M1_PMON_ISS (0x00000CE6)
3369 @param EAX Lower 32-bits of MSR value.
3370 @param EDX Upper 32-bits of MSR value.
3372 <b>Example usage</b>
3376 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ISS);
3377 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ISS, Msr);
3379 @note MSR_NEHALEM_M1_PMON_ISS is defined as MSR_M1_PMON_ISS in SDM.
3381 #define MSR_NEHALEM_M1_PMON_ISS 0x00000CE6
3385 Package. Uncore M-box 1 perfmon MAP unit select MSR.
3387 @param ECX MSR_NEHALEM_M1_PMON_MAP (0x00000CE7)
3388 @param EAX Lower 32-bits of MSR value.
3389 @param EDX Upper 32-bits of MSR value.
3391 <b>Example usage</b>
3395 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MAP);
3396 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MAP, Msr);
3398 @note MSR_NEHALEM_M1_PMON_MAP is defined as MSR_M1_PMON_MAP in SDM.
3400 #define MSR_NEHALEM_M1_PMON_MAP 0x00000CE7
3404 Package. Uncore M-box 1 perfmon MIC THR select MSR.
3406 @param ECX MSR_NEHALEM_M1_PMON_MSC_THR (0x00000CE8)
3407 @param EAX Lower 32-bits of MSR value.
3408 @param EDX Upper 32-bits of MSR value.
3410 <b>Example usage</b>
3414 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR);
3415 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR, Msr);
3417 @note MSR_NEHALEM_M1_PMON_MSC_THR is defined as MSR_M1_PMON_MSC_THR in SDM.
3419 #define MSR_NEHALEM_M1_PMON_MSC_THR 0x00000CE8
3423 Package. Uncore M-box 1 perfmon PGT unit select MSR.
3425 @param ECX MSR_NEHALEM_M1_PMON_PGT (0x00000CE9)
3426 @param EAX Lower 32-bits of MSR value.
3427 @param EDX Upper 32-bits of MSR value.
3429 <b>Example usage</b>
3433 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PGT);
3434 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PGT, Msr);
3436 @note MSR_NEHALEM_M1_PMON_PGT is defined as MSR_M1_PMON_PGT in SDM.
3438 #define MSR_NEHALEM_M1_PMON_PGT 0x00000CE9
3442 Package. Uncore M-box 1 perfmon PLD unit select MSR.
3444 @param ECX MSR_NEHALEM_M1_PMON_PLD (0x00000CEA)
3445 @param EAX Lower 32-bits of MSR value.
3446 @param EDX Upper 32-bits of MSR value.
3448 <b>Example usage</b>
3452 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PLD);
3453 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PLD, Msr);
3455 @note MSR_NEHALEM_M1_PMON_PLD is defined as MSR_M1_PMON_PLD in SDM.
3457 #define MSR_NEHALEM_M1_PMON_PLD 0x00000CEA
3461 Package. Uncore M-box 1 perfmon ZDP unit select MSR.
3463 @param ECX MSR_NEHALEM_M1_PMON_ZDP (0x00000CEB)
3464 @param EAX Lower 32-bits of MSR value.
3465 @param EDX Upper 32-bits of MSR value.
3467 <b>Example usage</b>
3471 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ZDP);
3472 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ZDP, Msr);
3474 @note MSR_NEHALEM_M1_PMON_ZDP is defined as MSR_M1_PMON_ZDP in SDM.
3476 #define MSR_NEHALEM_M1_PMON_ZDP 0x00000CEB
3480 Package. Uncore M-box 1 perfmon event select MSR.
3482 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL0 (0x00000CF0)
3483 @param EAX Lower 32-bits of MSR value.
3484 @param EDX Upper 32-bits of MSR value.
3486 <b>Example usage</b>
3490 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0);
3491 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0, Msr);
3493 @note MSR_NEHALEM_M1_PMON_EVNT_SEL0 is defined as MSR_M1_PMON_EVNT_SEL0 in SDM.
3495 #define MSR_NEHALEM_M1_PMON_EVNT_SEL0 0x00000CF0
3499 Package. Uncore M-box 1 perfmon counter MSR.
3501 @param ECX MSR_NEHALEM_M1_PMON_CTR0 (0x00000CF1)
3502 @param EAX Lower 32-bits of MSR value.
3503 @param EDX Upper 32-bits of MSR value.
3505 <b>Example usage</b>
3509 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR0);
3510 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR0, Msr);
3512 @note MSR_NEHALEM_M1_PMON_CTR0 is defined as MSR_M1_PMON_CTR0 in SDM.
3514 #define MSR_NEHALEM_M1_PMON_CTR0 0x00000CF1
3518 Package. Uncore M-box 1 perfmon event select MSR.
3520 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL1 (0x00000CF2)
3521 @param EAX Lower 32-bits of MSR value.
3522 @param EDX Upper 32-bits of MSR value.
3524 <b>Example usage</b>
3528 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1);
3529 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1, Msr);
3531 @note MSR_NEHALEM_M1_PMON_EVNT_SEL1 is defined as MSR_M1_PMON_EVNT_SEL1 in SDM.
3533 #define MSR_NEHALEM_M1_PMON_EVNT_SEL1 0x00000CF2
3537 Package. Uncore M-box 1 perfmon counter MSR.
3539 @param ECX MSR_NEHALEM_M1_PMON_CTR1 (0x00000CF3)
3540 @param EAX Lower 32-bits of MSR value.
3541 @param EDX Upper 32-bits of MSR value.
3543 <b>Example usage</b>
3547 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR1);
3548 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR1, Msr);
3550 @note MSR_NEHALEM_M1_PMON_CTR1 is defined as MSR_M1_PMON_CTR1 in SDM.
3552 #define MSR_NEHALEM_M1_PMON_CTR1 0x00000CF3
3556 Package. Uncore M-box 1 perfmon event select MSR.
3558 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL2 (0x00000CF4)
3559 @param EAX Lower 32-bits of MSR value.
3560 @param EDX Upper 32-bits of MSR value.
3562 <b>Example usage</b>
3566 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2);
3567 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2, Msr);
3569 @note MSR_NEHALEM_M1_PMON_EVNT_SEL2 is defined as MSR_M1_PMON_EVNT_SEL2 in SDM.
3571 #define MSR_NEHALEM_M1_PMON_EVNT_SEL2 0x00000CF4
3575 Package. Uncore M-box 1 perfmon counter MSR.
3577 @param ECX MSR_NEHALEM_M1_PMON_CTR2 (0x00000CF5)
3578 @param EAX Lower 32-bits of MSR value.
3579 @param EDX Upper 32-bits of MSR value.
3581 <b>Example usage</b>
3585 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR2);
3586 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR2, Msr);
3588 @note MSR_NEHALEM_M1_PMON_CTR2 is defined as MSR_M1_PMON_CTR2 in SDM.
3590 #define MSR_NEHALEM_M1_PMON_CTR2 0x00000CF5
3594 Package. Uncore M-box 1 perfmon event select MSR.
3596 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL3 (0x00000CF6)
3597 @param EAX Lower 32-bits of MSR value.
3598 @param EDX Upper 32-bits of MSR value.
3600 <b>Example usage</b>
3604 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3);
3605 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3, Msr);
3607 @note MSR_NEHALEM_M1_PMON_EVNT_SEL3 is defined as MSR_M1_PMON_EVNT_SEL3 in SDM.
3609 #define MSR_NEHALEM_M1_PMON_EVNT_SEL3 0x00000CF6
3613 Package. Uncore M-box 1 perfmon counter MSR.
3615 @param ECX MSR_NEHALEM_M1_PMON_CTR3 (0x00000CF7)
3616 @param EAX Lower 32-bits of MSR value.
3617 @param EDX Upper 32-bits of MSR value.
3619 <b>Example usage</b>
3623 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR3);
3624 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR3, Msr);
3626 @note MSR_NEHALEM_M1_PMON_CTR3 is defined as MSR_M1_PMON_CTR3 in SDM.
3628 #define MSR_NEHALEM_M1_PMON_CTR3 0x00000CF7
3632 Package. Uncore M-box 1 perfmon event select MSR.
3634 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL4 (0x00000CF8)
3635 @param EAX Lower 32-bits of MSR value.
3636 @param EDX Upper 32-bits of MSR value.
3638 <b>Example usage</b>
3642 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4);
3643 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4, Msr);
3645 @note MSR_NEHALEM_M1_PMON_EVNT_SEL4 is defined as MSR_M1_PMON_EVNT_SEL4 in SDM.
3647 #define MSR_NEHALEM_M1_PMON_EVNT_SEL4 0x00000CF8
3651 Package. Uncore M-box 1 perfmon counter MSR.
3653 @param ECX MSR_NEHALEM_M1_PMON_CTR4 (0x00000CF9)
3654 @param EAX Lower 32-bits of MSR value.
3655 @param EDX Upper 32-bits of MSR value.
3657 <b>Example usage</b>
3661 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR4);
3662 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR4, Msr);
3664 @note MSR_NEHALEM_M1_PMON_CTR4 is defined as MSR_M1_PMON_CTR4 in SDM.
3666 #define MSR_NEHALEM_M1_PMON_CTR4 0x00000CF9
3670 Package. Uncore M-box 1 perfmon event select MSR.
3672 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL5 (0x00000CFA)
3673 @param EAX Lower 32-bits of MSR value.
3674 @param EDX Upper 32-bits of MSR value.
3676 <b>Example usage</b>
3680 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5);
3681 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5, Msr);
3683 @note MSR_NEHALEM_M1_PMON_EVNT_SEL5 is defined as MSR_M1_PMON_EVNT_SEL5 in SDM.
3685 #define MSR_NEHALEM_M1_PMON_EVNT_SEL5 0x00000CFA
3689 Package. Uncore M-box 1 perfmon counter MSR.
3691 @param ECX MSR_NEHALEM_M1_PMON_CTR5 (0x00000CFB)
3692 @param EAX Lower 32-bits of MSR value.
3693 @param EDX Upper 32-bits of MSR value.
3695 <b>Example usage</b>
3699 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR5);
3700 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR5, Msr);
3702 @note MSR_NEHALEM_M1_PMON_CTR5 is defined as MSR_M1_PMON_CTR5 in SDM.
3704 #define MSR_NEHALEM_M1_PMON_CTR5 0x00000CFB
3708 Package. Uncore C-box 0 perfmon local box control MSR.
3710 @param ECX MSR_NEHALEM_C0_PMON_BOX_CTRL (0x00000D00)
3711 @param EAX Lower 32-bits of MSR value.
3712 @param EDX Upper 32-bits of MSR value.
3714 <b>Example usage</b>
3718 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL);
3719 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL, Msr);
3721 @note MSR_NEHALEM_C0_PMON_BOX_CTRL is defined as MSR_C0_PMON_BOX_CTRL in SDM.
3723 #define MSR_NEHALEM_C0_PMON_BOX_CTRL 0x00000D00
3727 Package. Uncore C-box 0 perfmon local box status MSR.
3729 @param ECX MSR_NEHALEM_C0_PMON_BOX_STATUS (0x00000D01)
3730 @param EAX Lower 32-bits of MSR value.
3731 @param EDX Upper 32-bits of MSR value.
3733 <b>Example usage</b>
3737 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS);
3738 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS, Msr);
3740 @note MSR_NEHALEM_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.
3742 #define MSR_NEHALEM_C0_PMON_BOX_STATUS 0x00000D01
3746 Package. Uncore C-box 0 perfmon local box overflow control MSR.
3748 @param ECX MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL (0x00000D02)
3749 @param EAX Lower 32-bits of MSR value.
3750 @param EDX Upper 32-bits of MSR value.
3752 <b>Example usage</b>
3756 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL);
3757 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL, Msr);
3759 @note MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL is defined as MSR_C0_PMON_BOX_OVF_CTRL in SDM.
3761 #define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL 0x00000D02
3765 Package. Uncore C-box 0 perfmon event select MSR.
3767 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL0 (0x00000D10)
3768 @param EAX Lower 32-bits of MSR value.
3769 @param EDX Upper 32-bits of MSR value.
3771 <b>Example usage</b>
3775 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0);
3776 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0, Msr);
3778 @note MSR_NEHALEM_C0_PMON_EVNT_SEL0 is defined as MSR_C0_PMON_EVNT_SEL0 in SDM.
3780 #define MSR_NEHALEM_C0_PMON_EVNT_SEL0 0x00000D10
3784 Package. Uncore C-box 0 perfmon counter MSR.
3786 @param ECX MSR_NEHALEM_C0_PMON_CTR0 (0x00000D11)
3787 @param EAX Lower 32-bits of MSR value.
3788 @param EDX Upper 32-bits of MSR value.
3790 <b>Example usage</b>
3794 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR0);
3795 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR0, Msr);
3797 @note MSR_NEHALEM_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
3799 #define MSR_NEHALEM_C0_PMON_CTR0 0x00000D11
3803 Package. Uncore C-box 0 perfmon event select MSR.
3805 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL1 (0x00000D12)
3806 @param EAX Lower 32-bits of MSR value.
3807 @param EDX Upper 32-bits of MSR value.
3809 <b>Example usage</b>
3813 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1);
3814 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1, Msr);
3816 @note MSR_NEHALEM_C0_PMON_EVNT_SEL1 is defined as MSR_C0_PMON_EVNT_SEL1 in SDM.
3818 #define MSR_NEHALEM_C0_PMON_EVNT_SEL1 0x00000D12
3822 Package. Uncore C-box 0 perfmon counter MSR.
3824 @param ECX MSR_NEHALEM_C0_PMON_CTR1 (0x00000D13)
3825 @param EAX Lower 32-bits of MSR value.
3826 @param EDX Upper 32-bits of MSR value.
3828 <b>Example usage</b>
3832 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR1);
3833 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR1, Msr);
3835 @note MSR_NEHALEM_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
3837 #define MSR_NEHALEM_C0_PMON_CTR1 0x00000D13
3841 Package. Uncore C-box 0 perfmon event select MSR.
3843 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL2 (0x00000D14)
3844 @param EAX Lower 32-bits of MSR value.
3845 @param EDX Upper 32-bits of MSR value.
3847 <b>Example usage</b>
3851 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2);
3852 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2, Msr);
3854 @note MSR_NEHALEM_C0_PMON_EVNT_SEL2 is defined as MSR_C0_PMON_EVNT_SEL2 in SDM.
3856 #define MSR_NEHALEM_C0_PMON_EVNT_SEL2 0x00000D14
3860 Package. Uncore C-box 0 perfmon counter MSR.
3862 @param ECX MSR_NEHALEM_C0_PMON_CTR2 (0x00000D15)
3863 @param EAX Lower 32-bits of MSR value.
3864 @param EDX Upper 32-bits of MSR value.
3866 <b>Example usage</b>
3870 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR2);
3871 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR2, Msr);
3873 @note MSR_NEHALEM_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
3875 #define MSR_NEHALEM_C0_PMON_CTR2 0x00000D15
3879 Package. Uncore C-box 0 perfmon event select MSR.
3881 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL3 (0x00000D16)
3882 @param EAX Lower 32-bits of MSR value.
3883 @param EDX Upper 32-bits of MSR value.
3885 <b>Example usage</b>
3889 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3);
3890 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3, Msr);
3892 @note MSR_NEHALEM_C0_PMON_EVNT_SEL3 is defined as MSR_C0_PMON_EVNT_SEL3 in SDM.
3894 #define MSR_NEHALEM_C0_PMON_EVNT_SEL3 0x00000D16
3898 Package. Uncore C-box 0 perfmon counter MSR.
3900 @param ECX MSR_NEHALEM_C0_PMON_CTR3 (0x00000D17)
3901 @param EAX Lower 32-bits of MSR value.
3902 @param EDX Upper 32-bits of MSR value.
3904 <b>Example usage</b>
3908 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR3);
3909 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR3, Msr);
3911 @note MSR_NEHALEM_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
3913 #define MSR_NEHALEM_C0_PMON_CTR3 0x00000D17
3917 Package. Uncore C-box 0 perfmon event select MSR.
3919 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL4 (0x00000D18)
3920 @param EAX Lower 32-bits of MSR value.
3921 @param EDX Upper 32-bits of MSR value.
3923 <b>Example usage</b>
3927 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4);
3928 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4, Msr);
3930 @note MSR_NEHALEM_C0_PMON_EVNT_SEL4 is defined as MSR_C0_PMON_EVNT_SEL4 in SDM.
3932 #define MSR_NEHALEM_C0_PMON_EVNT_SEL4 0x00000D18
3936 Package. Uncore C-box 0 perfmon counter MSR.
3938 @param ECX MSR_NEHALEM_C0_PMON_CTR4 (0x00000D19)
3939 @param EAX Lower 32-bits of MSR value.
3940 @param EDX Upper 32-bits of MSR value.
3942 <b>Example usage</b>
3946 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR4);
3947 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR4, Msr);
3949 @note MSR_NEHALEM_C0_PMON_CTR4 is defined as MSR_C0_PMON_CTR4 in SDM.
3951 #define MSR_NEHALEM_C0_PMON_CTR4 0x00000D19
3955 Package. Uncore C-box 0 perfmon event select MSR.
3957 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL5 (0x00000D1A)
3958 @param EAX Lower 32-bits of MSR value.
3959 @param EDX Upper 32-bits of MSR value.
3961 <b>Example usage</b>
3965 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5);
3966 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5, Msr);
3968 @note MSR_NEHALEM_C0_PMON_EVNT_SEL5 is defined as MSR_C0_PMON_EVNT_SEL5 in SDM.
3970 #define MSR_NEHALEM_C0_PMON_EVNT_SEL5 0x00000D1A
3974 Package. Uncore C-box 0 perfmon counter MSR.
3976 @param ECX MSR_NEHALEM_C0_PMON_CTR5 (0x00000D1B)
3977 @param EAX Lower 32-bits of MSR value.
3978 @param EDX Upper 32-bits of MSR value.
3980 <b>Example usage</b>
3984 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR5);
3985 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR5, Msr);
3987 @note MSR_NEHALEM_C0_PMON_CTR5 is defined as MSR_C0_PMON_CTR5 in SDM.
3989 #define MSR_NEHALEM_C0_PMON_CTR5 0x00000D1B
3993 Package. Uncore C-box 4 perfmon local box control MSR.
3995 @param ECX MSR_NEHALEM_C4_PMON_BOX_CTRL (0x00000D20)
3996 @param EAX Lower 32-bits of MSR value.
3997 @param EDX Upper 32-bits of MSR value.
3999 <b>Example usage</b>
4003 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL);
4004 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL, Msr);
4006 @note MSR_NEHALEM_C4_PMON_BOX_CTRL is defined as MSR_C4_PMON_BOX_CTRL in SDM.
4008 #define MSR_NEHALEM_C4_PMON_BOX_CTRL 0x00000D20
4012 Package. Uncore C-box 4 perfmon local box status MSR.
4014 @param ECX MSR_NEHALEM_C4_PMON_BOX_STATUS (0x00000D21)
4015 @param EAX Lower 32-bits of MSR value.
4016 @param EDX Upper 32-bits of MSR value.
4018 <b>Example usage</b>
4022 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS);
4023 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS, Msr);
4025 @note MSR_NEHALEM_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.
4027 #define MSR_NEHALEM_C4_PMON_BOX_STATUS 0x00000D21
4031 Package. Uncore C-box 4 perfmon local box overflow control MSR.
4033 @param ECX MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL (0x00000D22)
4034 @param EAX Lower 32-bits of MSR value.
4035 @param EDX Upper 32-bits of MSR value.
4037 <b>Example usage</b>
4041 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL);
4042 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL, Msr);
4044 @note MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL is defined as MSR_C4_PMON_BOX_OVF_CTRL in SDM.
4046 #define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL 0x00000D22
4050 Package. Uncore C-box 4 perfmon event select MSR.
4052 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL0 (0x00000D30)
4053 @param EAX Lower 32-bits of MSR value.
4054 @param EDX Upper 32-bits of MSR value.
4056 <b>Example usage</b>
4060 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0);
4061 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0, Msr);
4063 @note MSR_NEHALEM_C4_PMON_EVNT_SEL0 is defined as MSR_C4_PMON_EVNT_SEL0 in SDM.
4065 #define MSR_NEHALEM_C4_PMON_EVNT_SEL0 0x00000D30
4069 Package. Uncore C-box 4 perfmon counter MSR.
4071 @param ECX MSR_NEHALEM_C4_PMON_CTR0 (0x00000D31)
4072 @param EAX Lower 32-bits of MSR value.
4073 @param EDX Upper 32-bits of MSR value.
4075 <b>Example usage</b>
4079 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR0);
4080 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR0, Msr);
4082 @note MSR_NEHALEM_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
4084 #define MSR_NEHALEM_C4_PMON_CTR0 0x00000D31
4088 Package. Uncore C-box 4 perfmon event select MSR.
4090 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL1 (0x00000D32)
4091 @param EAX Lower 32-bits of MSR value.
4092 @param EDX Upper 32-bits of MSR value.
4094 <b>Example usage</b>
4098 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1);
4099 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1, Msr);
4101 @note MSR_NEHALEM_C4_PMON_EVNT_SEL1 is defined as MSR_C4_PMON_EVNT_SEL1 in SDM.
4103 #define MSR_NEHALEM_C4_PMON_EVNT_SEL1 0x00000D32
4107 Package. Uncore C-box 4 perfmon counter MSR.
4109 @param ECX MSR_NEHALEM_C4_PMON_CTR1 (0x00000D33)
4110 @param EAX Lower 32-bits of MSR value.
4111 @param EDX Upper 32-bits of MSR value.
4113 <b>Example usage</b>
4117 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR1);
4118 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR1, Msr);
4120 @note MSR_NEHALEM_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
4122 #define MSR_NEHALEM_C4_PMON_CTR1 0x00000D33
4126 Package. Uncore C-box 4 perfmon event select MSR.
4128 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL2 (0x00000D34)
4129 @param EAX Lower 32-bits of MSR value.
4130 @param EDX Upper 32-bits of MSR value.
4132 <b>Example usage</b>
4136 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2);
4137 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2, Msr);
4139 @note MSR_NEHALEM_C4_PMON_EVNT_SEL2 is defined as MSR_C4_PMON_EVNT_SEL2 in SDM.
4141 #define MSR_NEHALEM_C4_PMON_EVNT_SEL2 0x00000D34
4145 Package. Uncore C-box 4 perfmon counter MSR.
4147 @param ECX MSR_NEHALEM_C4_PMON_CTR2 (0x00000D35)
4148 @param EAX Lower 32-bits of MSR value.
4149 @param EDX Upper 32-bits of MSR value.
4151 <b>Example usage</b>
4155 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR2);
4156 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR2, Msr);
4158 @note MSR_NEHALEM_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
4160 #define MSR_NEHALEM_C4_PMON_CTR2 0x00000D35
4164 Package. Uncore C-box 4 perfmon event select MSR.
4166 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL3 (0x00000D36)
4167 @param EAX Lower 32-bits of MSR value.
4168 @param EDX Upper 32-bits of MSR value.
4170 <b>Example usage</b>
4174 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3);
4175 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3, Msr);
4177 @note MSR_NEHALEM_C4_PMON_EVNT_SEL3 is defined as MSR_C4_PMON_EVNT_SEL3 in SDM.
4179 #define MSR_NEHALEM_C4_PMON_EVNT_SEL3 0x00000D36
4183 Package. Uncore C-box 4 perfmon counter MSR.
4185 @param ECX MSR_NEHALEM_C4_PMON_CTR3 (0x00000D37)
4186 @param EAX Lower 32-bits of MSR value.
4187 @param EDX Upper 32-bits of MSR value.
4189 <b>Example usage</b>
4193 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR3);
4194 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR3, Msr);
4196 @note MSR_NEHALEM_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
4198 #define MSR_NEHALEM_C4_PMON_CTR3 0x00000D37
4202 Package. Uncore C-box 4 perfmon event select MSR.
4204 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL4 (0x00000D38)
4205 @param EAX Lower 32-bits of MSR value.
4206 @param EDX Upper 32-bits of MSR value.
4208 <b>Example usage</b>
4212 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4);
4213 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4, Msr);
4215 @note MSR_NEHALEM_C4_PMON_EVNT_SEL4 is defined as MSR_C4_PMON_EVNT_SEL4 in SDM.
4217 #define MSR_NEHALEM_C4_PMON_EVNT_SEL4 0x00000D38
4221 Package. Uncore C-box 4 perfmon counter MSR.
4223 @param ECX MSR_NEHALEM_C4_PMON_CTR4 (0x00000D39)
4224 @param EAX Lower 32-bits of MSR value.
4225 @param EDX Upper 32-bits of MSR value.
4227 <b>Example usage</b>
4231 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR4);
4232 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR4, Msr);
4234 @note MSR_NEHALEM_C4_PMON_CTR4 is defined as MSR_C4_PMON_CTR4 in SDM.
4236 #define MSR_NEHALEM_C4_PMON_CTR4 0x00000D39
4240 Package. Uncore C-box 4 perfmon event select MSR.
4242 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL5 (0x00000D3A)
4243 @param EAX Lower 32-bits of MSR value.
4244 @param EDX Upper 32-bits of MSR value.
4246 <b>Example usage</b>
4250 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5);
4251 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5, Msr);
4253 @note MSR_NEHALEM_C4_PMON_EVNT_SEL5 is defined as MSR_C4_PMON_EVNT_SEL5 in SDM.
4255 #define MSR_NEHALEM_C4_PMON_EVNT_SEL5 0x00000D3A
4259 Package. Uncore C-box 4 perfmon counter MSR.
4261 @param ECX MSR_NEHALEM_C4_PMON_CTR5 (0x00000D3B)
4262 @param EAX Lower 32-bits of MSR value.
4263 @param EDX Upper 32-bits of MSR value.
4265 <b>Example usage</b>
4269 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR5);
4270 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR5, Msr);
4272 @note MSR_NEHALEM_C4_PMON_CTR5 is defined as MSR_C4_PMON_CTR5 in SDM.
4274 #define MSR_NEHALEM_C4_PMON_CTR5 0x00000D3B
4278 Package. Uncore C-box 2 perfmon local box control MSR.
4280 @param ECX MSR_NEHALEM_C2_PMON_BOX_CTRL (0x00000D40)
4281 @param EAX Lower 32-bits of MSR value.
4282 @param EDX Upper 32-bits of MSR value.
4284 <b>Example usage</b>
4288 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL);
4289 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL, Msr);
4291 @note MSR_NEHALEM_C2_PMON_BOX_CTRL is defined as MSR_C2_PMON_BOX_CTRL in SDM.
4293 #define MSR_NEHALEM_C2_PMON_BOX_CTRL 0x00000D40
4297 Package. Uncore C-box 2 perfmon local box status MSR.
4299 @param ECX MSR_NEHALEM_C2_PMON_BOX_STATUS (0x00000D41)
4300 @param EAX Lower 32-bits of MSR value.
4301 @param EDX Upper 32-bits of MSR value.
4303 <b>Example usage</b>
4307 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS);
4308 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS, Msr);
4310 @note MSR_NEHALEM_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.
4312 #define MSR_NEHALEM_C2_PMON_BOX_STATUS 0x00000D41
4316 Package. Uncore C-box 2 perfmon local box overflow control MSR.
4318 @param ECX MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL (0x00000D42)
4319 @param EAX Lower 32-bits of MSR value.
4320 @param EDX Upper 32-bits of MSR value.
4322 <b>Example usage</b>
4326 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL);
4327 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL, Msr);
4329 @note MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL is defined as MSR_C2_PMON_BOX_OVF_CTRL in SDM.
4331 #define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL 0x00000D42
4335 Package. Uncore C-box 2 perfmon event select MSR.
4337 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL0 (0x00000D50)
4338 @param EAX Lower 32-bits of MSR value.
4339 @param EDX Upper 32-bits of MSR value.
4341 <b>Example usage</b>
4345 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0);
4346 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0, Msr);
4348 @note MSR_NEHALEM_C2_PMON_EVNT_SEL0 is defined as MSR_C2_PMON_EVNT_SEL0 in SDM.
4350 #define MSR_NEHALEM_C2_PMON_EVNT_SEL0 0x00000D50
4354 Package. Uncore C-box 2 perfmon counter MSR.
4356 @param ECX MSR_NEHALEM_C2_PMON_CTR0 (0x00000D51)
4357 @param EAX Lower 32-bits of MSR value.
4358 @param EDX Upper 32-bits of MSR value.
4360 <b>Example usage</b>
4364 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR0);
4365 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR0, Msr);
4367 @note MSR_NEHALEM_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
4369 #define MSR_NEHALEM_C2_PMON_CTR0 0x00000D51
4373 Package. Uncore C-box 2 perfmon event select MSR.
4375 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL1 (0x00000D52)
4376 @param EAX Lower 32-bits of MSR value.
4377 @param EDX Upper 32-bits of MSR value.
4379 <b>Example usage</b>
4383 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1);
4384 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1, Msr);
4386 @note MSR_NEHALEM_C2_PMON_EVNT_SEL1 is defined as MSR_C2_PMON_EVNT_SEL1 in SDM.
4388 #define MSR_NEHALEM_C2_PMON_EVNT_SEL1 0x00000D52
4392 Package. Uncore C-box 2 perfmon counter MSR.
4394 @param ECX MSR_NEHALEM_C2_PMON_CTR1 (0x00000D53)
4395 @param EAX Lower 32-bits of MSR value.
4396 @param EDX Upper 32-bits of MSR value.
4398 <b>Example usage</b>
4402 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR1);
4403 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR1, Msr);
4405 @note MSR_NEHALEM_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
4407 #define MSR_NEHALEM_C2_PMON_CTR1 0x00000D53
4411 Package. Uncore C-box 2 perfmon event select MSR.
4413 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL2 (0x00000D54)
4414 @param EAX Lower 32-bits of MSR value.
4415 @param EDX Upper 32-bits of MSR value.
4417 <b>Example usage</b>
4421 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2);
4422 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2, Msr);
4424 @note MSR_NEHALEM_C2_PMON_EVNT_SEL2 is defined as MSR_C2_PMON_EVNT_SEL2 in SDM.
4426 #define MSR_NEHALEM_C2_PMON_EVNT_SEL2 0x00000D54
4430 Package. Uncore C-box 2 perfmon counter MSR.
4432 @param ECX MSR_NEHALEM_C2_PMON_CTR2 (0x00000D55)
4433 @param EAX Lower 32-bits of MSR value.
4434 @param EDX Upper 32-bits of MSR value.
4436 <b>Example usage</b>
4440 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR2);
4441 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR2, Msr);
4443 @note MSR_NEHALEM_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
4445 #define MSR_NEHALEM_C2_PMON_CTR2 0x00000D55
4449 Package. Uncore C-box 2 perfmon event select MSR.
4451 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL3 (0x00000D56)
4452 @param EAX Lower 32-bits of MSR value.
4453 @param EDX Upper 32-bits of MSR value.
4455 <b>Example usage</b>
4459 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3);
4460 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3, Msr);
4462 @note MSR_NEHALEM_C2_PMON_EVNT_SEL3 is defined as MSR_C2_PMON_EVNT_SEL3 in SDM.
4464 #define MSR_NEHALEM_C2_PMON_EVNT_SEL3 0x00000D56
4468 Package. Uncore C-box 2 perfmon counter MSR.
4470 @param ECX MSR_NEHALEM_C2_PMON_CTR3 (0x00000D57)
4471 @param EAX Lower 32-bits of MSR value.
4472 @param EDX Upper 32-bits of MSR value.
4474 <b>Example usage</b>
4478 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR3);
4479 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR3, Msr);
4481 @note MSR_NEHALEM_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
4483 #define MSR_NEHALEM_C2_PMON_CTR3 0x00000D57
4487 Package. Uncore C-box 2 perfmon event select MSR.
4489 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL4 (0x00000D58)
4490 @param EAX Lower 32-bits of MSR value.
4491 @param EDX Upper 32-bits of MSR value.
4493 <b>Example usage</b>
4497 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4);
4498 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4, Msr);
4500 @note MSR_NEHALEM_C2_PMON_EVNT_SEL4 is defined as MSR_C2_PMON_EVNT_SEL4 in SDM.
4502 #define MSR_NEHALEM_C2_PMON_EVNT_SEL4 0x00000D58
4506 Package. Uncore C-box 2 perfmon counter MSR.
4508 @param ECX MSR_NEHALEM_C2_PMON_CTR4 (0x00000D59)
4509 @param EAX Lower 32-bits of MSR value.
4510 @param EDX Upper 32-bits of MSR value.
4512 <b>Example usage</b>
4516 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR4);
4517 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR4, Msr);
4519 @note MSR_NEHALEM_C2_PMON_CTR4 is defined as MSR_C2_PMON_CTR4 in SDM.
4521 #define MSR_NEHALEM_C2_PMON_CTR4 0x00000D59
4525 Package. Uncore C-box 2 perfmon event select MSR.
4527 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL5 (0x00000D5A)
4528 @param EAX Lower 32-bits of MSR value.
4529 @param EDX Upper 32-bits of MSR value.
4531 <b>Example usage</b>
4535 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5);
4536 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5, Msr);
4538 @note MSR_NEHALEM_C2_PMON_EVNT_SEL5 is defined as MSR_C2_PMON_EVNT_SEL5 in SDM.
4540 #define MSR_NEHALEM_C2_PMON_EVNT_SEL5 0x00000D5A
4544 Package. Uncore C-box 2 perfmon counter MSR.
4546 @param ECX MSR_NEHALEM_C2_PMON_CTR5 (0x00000D5B)
4547 @param EAX Lower 32-bits of MSR value.
4548 @param EDX Upper 32-bits of MSR value.
4550 <b>Example usage</b>
4554 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR5);
4555 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR5, Msr);
4557 @note MSR_NEHALEM_C2_PMON_CTR5 is defined as MSR_C2_PMON_CTR5 in SDM.
4559 #define MSR_NEHALEM_C2_PMON_CTR5 0x00000D5B
4563 Package. Uncore C-box 6 perfmon local box control MSR.
4565 @param ECX MSR_NEHALEM_C6_PMON_BOX_CTRL (0x00000D60)
4566 @param EAX Lower 32-bits of MSR value.
4567 @param EDX Upper 32-bits of MSR value.
4569 <b>Example usage</b>
4573 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL);
4574 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL, Msr);
4576 @note MSR_NEHALEM_C6_PMON_BOX_CTRL is defined as MSR_C6_PMON_BOX_CTRL in SDM.
4578 #define MSR_NEHALEM_C6_PMON_BOX_CTRL 0x00000D60
4582 Package. Uncore C-box 6 perfmon local box status MSR.
4584 @param ECX MSR_NEHALEM_C6_PMON_BOX_STATUS (0x00000D61)
4585 @param EAX Lower 32-bits of MSR value.
4586 @param EDX Upper 32-bits of MSR value.
4588 <b>Example usage</b>
4592 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS);
4593 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS, Msr);
4595 @note MSR_NEHALEM_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.
4597 #define MSR_NEHALEM_C6_PMON_BOX_STATUS 0x00000D61
4601 Package. Uncore C-box 6 perfmon local box overflow control MSR.
4603 @param ECX MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL (0x00000D62)
4604 @param EAX Lower 32-bits of MSR value.
4605 @param EDX Upper 32-bits of MSR value.
4607 <b>Example usage</b>
4611 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL);
4612 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL, Msr);
4614 @note MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL is defined as MSR_C6_PMON_BOX_OVF_CTRL in SDM.
4616 #define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL 0x00000D62
4620 Package. Uncore C-box 6 perfmon event select MSR.
4622 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL0 (0x00000D70)
4623 @param EAX Lower 32-bits of MSR value.
4624 @param EDX Upper 32-bits of MSR value.
4626 <b>Example usage</b>
4630 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0);
4631 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0, Msr);
4633 @note MSR_NEHALEM_C6_PMON_EVNT_SEL0 is defined as MSR_C6_PMON_EVNT_SEL0 in SDM.
4635 #define MSR_NEHALEM_C6_PMON_EVNT_SEL0 0x00000D70
4639 Package. Uncore C-box 6 perfmon counter MSR.
4641 @param ECX MSR_NEHALEM_C6_PMON_CTR0 (0x00000D71)
4642 @param EAX Lower 32-bits of MSR value.
4643 @param EDX Upper 32-bits of MSR value.
4645 <b>Example usage</b>
4649 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR0);
4650 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR0, Msr);
4652 @note MSR_NEHALEM_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
4654 #define MSR_NEHALEM_C6_PMON_CTR0 0x00000D71
4658 Package. Uncore C-box 6 perfmon event select MSR.
4660 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL1 (0x00000D72)
4661 @param EAX Lower 32-bits of MSR value.
4662 @param EDX Upper 32-bits of MSR value.
4664 <b>Example usage</b>
4668 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1);
4669 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1, Msr);
4671 @note MSR_NEHALEM_C6_PMON_EVNT_SEL1 is defined as MSR_C6_PMON_EVNT_SEL1 in SDM.
4673 #define MSR_NEHALEM_C6_PMON_EVNT_SEL1 0x00000D72
4677 Package. Uncore C-box 6 perfmon counter MSR.
4679 @param ECX MSR_NEHALEM_C6_PMON_CTR1 (0x00000D73)
4680 @param EAX Lower 32-bits of MSR value.
4681 @param EDX Upper 32-bits of MSR value.
4683 <b>Example usage</b>
4687 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR1);
4688 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR1, Msr);
4690 @note MSR_NEHALEM_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
4692 #define MSR_NEHALEM_C6_PMON_CTR1 0x00000D73
4696 Package. Uncore C-box 6 perfmon event select MSR.
4698 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL2 (0x00000D74)
4699 @param EAX Lower 32-bits of MSR value.
4700 @param EDX Upper 32-bits of MSR value.
4702 <b>Example usage</b>
4706 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2);
4707 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2, Msr);
4709 @note MSR_NEHALEM_C6_PMON_EVNT_SEL2 is defined as MSR_C6_PMON_EVNT_SEL2 in SDM.
4711 #define MSR_NEHALEM_C6_PMON_EVNT_SEL2 0x00000D74
4715 Package. Uncore C-box 6 perfmon counter MSR.
4717 @param ECX MSR_NEHALEM_C6_PMON_CTR2 (0x00000D75)
4718 @param EAX Lower 32-bits of MSR value.
4719 @param EDX Upper 32-bits of MSR value.
4721 <b>Example usage</b>
4725 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR2);
4726 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR2, Msr);
4728 @note MSR_NEHALEM_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
4730 #define MSR_NEHALEM_C6_PMON_CTR2 0x00000D75
4734 Package. Uncore C-box 6 perfmon event select MSR.
4736 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL3 (0x00000D76)
4737 @param EAX Lower 32-bits of MSR value.
4738 @param EDX Upper 32-bits of MSR value.
4740 <b>Example usage</b>
4744 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3);
4745 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3, Msr);
4747 @note MSR_NEHALEM_C6_PMON_EVNT_SEL3 is defined as MSR_C6_PMON_EVNT_SEL3 in SDM.
4749 #define MSR_NEHALEM_C6_PMON_EVNT_SEL3 0x00000D76
4753 Package. Uncore C-box 6 perfmon counter MSR.
4755 @param ECX MSR_NEHALEM_C6_PMON_CTR3 (0x00000D77)
4756 @param EAX Lower 32-bits of MSR value.
4757 @param EDX Upper 32-bits of MSR value.
4759 <b>Example usage</b>
4763 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR3);
4764 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR3, Msr);
4766 @note MSR_NEHALEM_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
4768 #define MSR_NEHALEM_C6_PMON_CTR3 0x00000D77
4772 Package. Uncore C-box 6 perfmon event select MSR.
4774 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL4 (0x00000D78)
4775 @param EAX Lower 32-bits of MSR value.
4776 @param EDX Upper 32-bits of MSR value.
4778 <b>Example usage</b>
4782 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4);
4783 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4, Msr);
4785 @note MSR_NEHALEM_C6_PMON_EVNT_SEL4 is defined as MSR_C6_PMON_EVNT_SEL4 in SDM.
4787 #define MSR_NEHALEM_C6_PMON_EVNT_SEL4 0x00000D78
4791 Package. Uncore C-box 6 perfmon counter MSR.
4793 @param ECX MSR_NEHALEM_C6_PMON_CTR4 (0x00000D79)
4794 @param EAX Lower 32-bits of MSR value.
4795 @param EDX Upper 32-bits of MSR value.
4797 <b>Example usage</b>
4801 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR4);
4802 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR4, Msr);
4804 @note MSR_NEHALEM_C6_PMON_CTR4 is defined as MSR_C6_PMON_CTR4 in SDM.
4806 #define MSR_NEHALEM_C6_PMON_CTR4 0x00000D79
4810 Package. Uncore C-box 6 perfmon event select MSR.
4812 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL5 (0x00000D7A)
4813 @param EAX Lower 32-bits of MSR value.
4814 @param EDX Upper 32-bits of MSR value.
4816 <b>Example usage</b>
4820 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5);
4821 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5, Msr);
4823 @note MSR_NEHALEM_C6_PMON_EVNT_SEL5 is defined as MSR_C6_PMON_EVNT_SEL5 in SDM.
4825 #define MSR_NEHALEM_C6_PMON_EVNT_SEL5 0x00000D7A
4829 Package. Uncore C-box 6 perfmon counter MSR.
4831 @param ECX MSR_NEHALEM_C6_PMON_CTR5 (0x00000D7B)
4832 @param EAX Lower 32-bits of MSR value.
4833 @param EDX Upper 32-bits of MSR value.
4835 <b>Example usage</b>
4839 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR5);
4840 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR5, Msr);
4842 @note MSR_NEHALEM_C6_PMON_CTR5 is defined as MSR_C6_PMON_CTR5 in SDM.
4844 #define MSR_NEHALEM_C6_PMON_CTR5 0x00000D7B
4848 Package. Uncore C-box 1 perfmon local box control MSR.
4850 @param ECX MSR_NEHALEM_C1_PMON_BOX_CTRL (0x00000D80)
4851 @param EAX Lower 32-bits of MSR value.
4852 @param EDX Upper 32-bits of MSR value.
4854 <b>Example usage</b>
4858 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL);
4859 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL, Msr);
4861 @note MSR_NEHALEM_C1_PMON_BOX_CTRL is defined as MSR_C1_PMON_BOX_CTRL in SDM.
4863 #define MSR_NEHALEM_C1_PMON_BOX_CTRL 0x00000D80
4867 Package. Uncore C-box 1 perfmon local box status MSR.
4869 @param ECX MSR_NEHALEM_C1_PMON_BOX_STATUS (0x00000D81)
4870 @param EAX Lower 32-bits of MSR value.
4871 @param EDX Upper 32-bits of MSR value.
4873 <b>Example usage</b>
4877 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS);
4878 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS, Msr);
4880 @note MSR_NEHALEM_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.
4882 #define MSR_NEHALEM_C1_PMON_BOX_STATUS 0x00000D81
4886 Package. Uncore C-box 1 perfmon local box overflow control MSR.
4888 @param ECX MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL (0x00000D82)
4889 @param EAX Lower 32-bits of MSR value.
4890 @param EDX Upper 32-bits of MSR value.
4892 <b>Example usage</b>
4896 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL);
4897 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL, Msr);
4899 @note MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL is defined as MSR_C1_PMON_BOX_OVF_CTRL in SDM.
4901 #define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL 0x00000D82
4905 Package. Uncore C-box 1 perfmon event select MSR.
4907 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL0 (0x00000D90)
4908 @param EAX Lower 32-bits of MSR value.
4909 @param EDX Upper 32-bits of MSR value.
4911 <b>Example usage</b>
4915 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0);
4916 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0, Msr);
4918 @note MSR_NEHALEM_C1_PMON_EVNT_SEL0 is defined as MSR_C1_PMON_EVNT_SEL0 in SDM.
4920 #define MSR_NEHALEM_C1_PMON_EVNT_SEL0 0x00000D90
4924 Package. Uncore C-box 1 perfmon counter MSR.
4926 @param ECX MSR_NEHALEM_C1_PMON_CTR0 (0x00000D91)
4927 @param EAX Lower 32-bits of MSR value.
4928 @param EDX Upper 32-bits of MSR value.
4930 <b>Example usage</b>
4934 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR0);
4935 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR0, Msr);
4937 @note MSR_NEHALEM_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
4939 #define MSR_NEHALEM_C1_PMON_CTR0 0x00000D91
4943 Package. Uncore C-box 1 perfmon event select MSR.
4945 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL1 (0x00000D92)
4946 @param EAX Lower 32-bits of MSR value.
4947 @param EDX Upper 32-bits of MSR value.
4949 <b>Example usage</b>
4953 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1);
4954 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1, Msr);
4956 @note MSR_NEHALEM_C1_PMON_EVNT_SEL1 is defined as MSR_C1_PMON_EVNT_SEL1 in SDM.
4958 #define MSR_NEHALEM_C1_PMON_EVNT_SEL1 0x00000D92
4962 Package. Uncore C-box 1 perfmon counter MSR.
4964 @param ECX MSR_NEHALEM_C1_PMON_CTR1 (0x00000D93)
4965 @param EAX Lower 32-bits of MSR value.
4966 @param EDX Upper 32-bits of MSR value.
4968 <b>Example usage</b>
4972 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR1);
4973 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR1, Msr);
4975 @note MSR_NEHALEM_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
4977 #define MSR_NEHALEM_C1_PMON_CTR1 0x00000D93
4981 Package. Uncore C-box 1 perfmon event select MSR.
4983 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL2 (0x00000D94)
4984 @param EAX Lower 32-bits of MSR value.
4985 @param EDX Upper 32-bits of MSR value.
4987 <b>Example usage</b>
4991 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2);
4992 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2, Msr);
4994 @note MSR_NEHALEM_C1_PMON_EVNT_SEL2 is defined as MSR_C1_PMON_EVNT_SEL2 in SDM.
4996 #define MSR_NEHALEM_C1_PMON_EVNT_SEL2 0x00000D94
5000 Package. Uncore C-box 1 perfmon counter MSR.
5002 @param ECX MSR_NEHALEM_C1_PMON_CTR2 (0x00000D95)
5003 @param EAX Lower 32-bits of MSR value.
5004 @param EDX Upper 32-bits of MSR value.
5006 <b>Example usage</b>
5010 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR2);
5011 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR2, Msr);
5013 @note MSR_NEHALEM_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
5015 #define MSR_NEHALEM_C1_PMON_CTR2 0x00000D95
5019 Package. Uncore C-box 1 perfmon event select MSR.
5021 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL3 (0x00000D96)
5022 @param EAX Lower 32-bits of MSR value.
5023 @param EDX Upper 32-bits of MSR value.
5025 <b>Example usage</b>
5029 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3);
5030 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3, Msr);
5032 @note MSR_NEHALEM_C1_PMON_EVNT_SEL3 is defined as MSR_C1_PMON_EVNT_SEL3 in SDM.
5034 #define MSR_NEHALEM_C1_PMON_EVNT_SEL3 0x00000D96
5038 Package. Uncore C-box 1 perfmon counter MSR.
5040 @param ECX MSR_NEHALEM_C1_PMON_CTR3 (0x00000D97)
5041 @param EAX Lower 32-bits of MSR value.
5042 @param EDX Upper 32-bits of MSR value.
5044 <b>Example usage</b>
5048 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR3);
5049 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR3, Msr);
5051 @note MSR_NEHALEM_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
5053 #define MSR_NEHALEM_C1_PMON_CTR3 0x00000D97
5057 Package. Uncore C-box 1 perfmon event select MSR.
5059 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL4 (0x00000D98)
5060 @param EAX Lower 32-bits of MSR value.
5061 @param EDX Upper 32-bits of MSR value.
5063 <b>Example usage</b>
5067 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4);
5068 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4, Msr);
5070 @note MSR_NEHALEM_C1_PMON_EVNT_SEL4 is defined as MSR_C1_PMON_EVNT_SEL4 in SDM.
5072 #define MSR_NEHALEM_C1_PMON_EVNT_SEL4 0x00000D98
5076 Package. Uncore C-box 1 perfmon counter MSR.
5078 @param ECX MSR_NEHALEM_C1_PMON_CTR4 (0x00000D99)
5079 @param EAX Lower 32-bits of MSR value.
5080 @param EDX Upper 32-bits of MSR value.
5082 <b>Example usage</b>
5086 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR4);
5087 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR4, Msr);
5089 @note MSR_NEHALEM_C1_PMON_CTR4 is defined as MSR_C1_PMON_CTR4 in SDM.
5091 #define MSR_NEHALEM_C1_PMON_CTR4 0x00000D99
5095 Package. Uncore C-box 1 perfmon event select MSR.
5097 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL5 (0x00000D9A)
5098 @param EAX Lower 32-bits of MSR value.
5099 @param EDX Upper 32-bits of MSR value.
5101 <b>Example usage</b>
5105 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5);
5106 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5, Msr);
5108 @note MSR_NEHALEM_C1_PMON_EVNT_SEL5 is defined as MSR_C1_PMON_EVNT_SEL5 in SDM.
5110 #define MSR_NEHALEM_C1_PMON_EVNT_SEL5 0x00000D9A
5114 Package. Uncore C-box 1 perfmon counter MSR.
5116 @param ECX MSR_NEHALEM_C1_PMON_CTR5 (0x00000D9B)
5117 @param EAX Lower 32-bits of MSR value.
5118 @param EDX Upper 32-bits of MSR value.
5120 <b>Example usage</b>
5124 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR5);
5125 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR5, Msr);
5127 @note MSR_NEHALEM_C1_PMON_CTR5 is defined as MSR_C1_PMON_CTR5 in SDM.
5129 #define MSR_NEHALEM_C1_PMON_CTR5 0x00000D9B
5133 Package. Uncore C-box 5 perfmon local box control MSR.
5135 @param ECX MSR_NEHALEM_C5_PMON_BOX_CTRL (0x00000DA0)
5136 @param EAX Lower 32-bits of MSR value.
5137 @param EDX Upper 32-bits of MSR value.
5139 <b>Example usage</b>
5143 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL);
5144 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL, Msr);
5146 @note MSR_NEHALEM_C5_PMON_BOX_CTRL is defined as MSR_C5_PMON_BOX_CTRL in SDM.
5148 #define MSR_NEHALEM_C5_PMON_BOX_CTRL 0x00000DA0
5152 Package. Uncore C-box 5 perfmon local box status MSR.
5154 @param ECX MSR_NEHALEM_C5_PMON_BOX_STATUS (0x00000DA1)
5155 @param EAX Lower 32-bits of MSR value.
5156 @param EDX Upper 32-bits of MSR value.
5158 <b>Example usage</b>
5162 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS);
5163 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS, Msr);
5165 @note MSR_NEHALEM_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.
5167 #define MSR_NEHALEM_C5_PMON_BOX_STATUS 0x00000DA1
5171 Package. Uncore C-box 5 perfmon local box overflow control MSR.
5173 @param ECX MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL (0x00000DA2)
5174 @param EAX Lower 32-bits of MSR value.
5175 @param EDX Upper 32-bits of MSR value.
5177 <b>Example usage</b>
5181 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL);
5182 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL, Msr);
5184 @note MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL is defined as MSR_C5_PMON_BOX_OVF_CTRL in SDM.
5186 #define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL 0x00000DA2
5190 Package. Uncore C-box 5 perfmon event select MSR.
5192 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL0 (0x00000DB0)
5193 @param EAX Lower 32-bits of MSR value.
5194 @param EDX Upper 32-bits of MSR value.
5196 <b>Example usage</b>
5200 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0);
5201 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0, Msr);
5203 @note MSR_NEHALEM_C5_PMON_EVNT_SEL0 is defined as MSR_C5_PMON_EVNT_SEL0 in SDM.
5205 #define MSR_NEHALEM_C5_PMON_EVNT_SEL0 0x00000DB0
5209 Package. Uncore C-box 5 perfmon counter MSR.
5211 @param ECX MSR_NEHALEM_C5_PMON_CTR0 (0x00000DB1)
5212 @param EAX Lower 32-bits of MSR value.
5213 @param EDX Upper 32-bits of MSR value.
5215 <b>Example usage</b>
5219 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR0);
5220 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR0, Msr);
5222 @note MSR_NEHALEM_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
5224 #define MSR_NEHALEM_C5_PMON_CTR0 0x00000DB1
5228 Package. Uncore C-box 5 perfmon event select MSR.
5230 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL1 (0x00000DB2)
5231 @param EAX Lower 32-bits of MSR value.
5232 @param EDX Upper 32-bits of MSR value.
5234 <b>Example usage</b>
5238 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1);
5239 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1, Msr);
5241 @note MSR_NEHALEM_C5_PMON_EVNT_SEL1 is defined as MSR_C5_PMON_EVNT_SEL1 in SDM.
5243 #define MSR_NEHALEM_C5_PMON_EVNT_SEL1 0x00000DB2
5247 Package. Uncore C-box 5 perfmon counter MSR.
5249 @param ECX MSR_NEHALEM_C5_PMON_CTR1 (0x00000DB3)
5250 @param EAX Lower 32-bits of MSR value.
5251 @param EDX Upper 32-bits of MSR value.
5253 <b>Example usage</b>
5257 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR1);
5258 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR1, Msr);
5260 @note MSR_NEHALEM_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
5262 #define MSR_NEHALEM_C5_PMON_CTR1 0x00000DB3
5266 Package. Uncore C-box 5 perfmon event select MSR.
5268 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL2 (0x00000DB4)
5269 @param EAX Lower 32-bits of MSR value.
5270 @param EDX Upper 32-bits of MSR value.
5272 <b>Example usage</b>
5276 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2);
5277 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2, Msr);
5279 @note MSR_NEHALEM_C5_PMON_EVNT_SEL2 is defined as MSR_C5_PMON_EVNT_SEL2 in SDM.
5281 #define MSR_NEHALEM_C5_PMON_EVNT_SEL2 0x00000DB4
5285 Package. Uncore C-box 5 perfmon counter MSR.
5287 @param ECX MSR_NEHALEM_C5_PMON_CTR2 (0x00000DB5)
5288 @param EAX Lower 32-bits of MSR value.
5289 @param EDX Upper 32-bits of MSR value.
5291 <b>Example usage</b>
5295 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR2);
5296 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR2, Msr);
5298 @note MSR_NEHALEM_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
5300 #define MSR_NEHALEM_C5_PMON_CTR2 0x00000DB5
5304 Package. Uncore C-box 5 perfmon event select MSR.
5306 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL3 (0x00000DB6)
5307 @param EAX Lower 32-bits of MSR value.
5308 @param EDX Upper 32-bits of MSR value.
5310 <b>Example usage</b>
5314 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3);
5315 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3, Msr);
5317 @note MSR_NEHALEM_C5_PMON_EVNT_SEL3 is defined as MSR_C5_PMON_EVNT_SEL3 in SDM.
5319 #define MSR_NEHALEM_C5_PMON_EVNT_SEL3 0x00000DB6
5323 Package. Uncore C-box 5 perfmon counter MSR.
5325 @param ECX MSR_NEHALEM_C5_PMON_CTR3 (0x00000DB7)
5326 @param EAX Lower 32-bits of MSR value.
5327 @param EDX Upper 32-bits of MSR value.
5329 <b>Example usage</b>
5333 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR3);
5334 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR3, Msr);
5336 @note MSR_NEHALEM_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
5338 #define MSR_NEHALEM_C5_PMON_CTR3 0x00000DB7
5342 Package. Uncore C-box 5 perfmon event select MSR.
5344 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL4 (0x00000DB8)
5345 @param EAX Lower 32-bits of MSR value.
5346 @param EDX Upper 32-bits of MSR value.
5348 <b>Example usage</b>
5352 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4);
5353 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4, Msr);
5355 @note MSR_NEHALEM_C5_PMON_EVNT_SEL4 is defined as MSR_C5_PMON_EVNT_SEL4 in SDM.
5357 #define MSR_NEHALEM_C5_PMON_EVNT_SEL4 0x00000DB8
5361 Package. Uncore C-box 5 perfmon counter MSR.
5363 @param ECX MSR_NEHALEM_C5_PMON_CTR4 (0x00000DB9)
5364 @param EAX Lower 32-bits of MSR value.
5365 @param EDX Upper 32-bits of MSR value.
5367 <b>Example usage</b>
5371 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR4);
5372 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR4, Msr);
5374 @note MSR_NEHALEM_C5_PMON_CTR4 is defined as MSR_C5_PMON_CTR4 in SDM.
5376 #define MSR_NEHALEM_C5_PMON_CTR4 0x00000DB9
5380 Package. Uncore C-box 5 perfmon event select MSR.
5382 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL5 (0x00000DBA)
5383 @param EAX Lower 32-bits of MSR value.
5384 @param EDX Upper 32-bits of MSR value.
5386 <b>Example usage</b>
5390 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5);
5391 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5, Msr);
5393 @note MSR_NEHALEM_C5_PMON_EVNT_SEL5 is defined as MSR_C5_PMON_EVNT_SEL5 in SDM.
5395 #define MSR_NEHALEM_C5_PMON_EVNT_SEL5 0x00000DBA
5399 Package. Uncore C-box 5 perfmon counter MSR.
5401 @param ECX MSR_NEHALEM_C5_PMON_CTR5 (0x00000DBB)
5402 @param EAX Lower 32-bits of MSR value.
5403 @param EDX Upper 32-bits of MSR value.
5405 <b>Example usage</b>
5409 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR5);
5410 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR5, Msr);
5412 @note MSR_NEHALEM_C5_PMON_CTR5 is defined as MSR_C5_PMON_CTR5 in SDM.
5414 #define MSR_NEHALEM_C5_PMON_CTR5 0x00000DBB
5418 Package. Uncore C-box 3 perfmon local box control MSR.
5420 @param ECX MSR_NEHALEM_C3_PMON_BOX_CTRL (0x00000DC0)
5421 @param EAX Lower 32-bits of MSR value.
5422 @param EDX Upper 32-bits of MSR value.
5424 <b>Example usage</b>
5428 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL);
5429 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL, Msr);
5431 @note MSR_NEHALEM_C3_PMON_BOX_CTRL is defined as MSR_C3_PMON_BOX_CTRL in SDM.
5433 #define MSR_NEHALEM_C3_PMON_BOX_CTRL 0x00000DC0
5437 Package. Uncore C-box 3 perfmon local box status MSR.
5439 @param ECX MSR_NEHALEM_C3_PMON_BOX_STATUS (0x00000DC1)
5440 @param EAX Lower 32-bits of MSR value.
5441 @param EDX Upper 32-bits of MSR value.
5443 <b>Example usage</b>
5447 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS);
5448 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS, Msr);
5450 @note MSR_NEHALEM_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.
5452 #define MSR_NEHALEM_C3_PMON_BOX_STATUS 0x00000DC1
5456 Package. Uncore C-box 3 perfmon local box overflow control MSR.
5458 @param ECX MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL (0x00000DC2)
5459 @param EAX Lower 32-bits of MSR value.
5460 @param EDX Upper 32-bits of MSR value.
5462 <b>Example usage</b>
5466 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL);
5467 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL, Msr);
5469 @note MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL is defined as MSR_C3_PMON_BOX_OVF_CTRL in SDM.
5471 #define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL 0x00000DC2
5475 Package. Uncore C-box 3 perfmon event select MSR.
5477 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL0 (0x00000DD0)
5478 @param EAX Lower 32-bits of MSR value.
5479 @param EDX Upper 32-bits of MSR value.
5481 <b>Example usage</b>
5485 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0);
5486 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0, Msr);
5488 @note MSR_NEHALEM_C3_PMON_EVNT_SEL0 is defined as MSR_C3_PMON_EVNT_SEL0 in SDM.
5490 #define MSR_NEHALEM_C3_PMON_EVNT_SEL0 0x00000DD0
5494 Package. Uncore C-box 3 perfmon counter MSR.
5496 @param ECX MSR_NEHALEM_C3_PMON_CTR0 (0x00000DD1)
5497 @param EAX Lower 32-bits of MSR value.
5498 @param EDX Upper 32-bits of MSR value.
5500 <b>Example usage</b>
5504 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR0);
5505 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR0, Msr);
5507 @note MSR_NEHALEM_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
5509 #define MSR_NEHALEM_C3_PMON_CTR0 0x00000DD1
5513 Package. Uncore C-box 3 perfmon event select MSR.
5515 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL1 (0x00000DD2)
5516 @param EAX Lower 32-bits of MSR value.
5517 @param EDX Upper 32-bits of MSR value.
5519 <b>Example usage</b>
5523 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1);
5524 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1, Msr);
5526 @note MSR_NEHALEM_C3_PMON_EVNT_SEL1 is defined as MSR_C3_PMON_EVNT_SEL1 in SDM.
5528 #define MSR_NEHALEM_C3_PMON_EVNT_SEL1 0x00000DD2
5532 Package. Uncore C-box 3 perfmon counter MSR.
5534 @param ECX MSR_NEHALEM_C3_PMON_CTR1 (0x00000DD3)
5535 @param EAX Lower 32-bits of MSR value.
5536 @param EDX Upper 32-bits of MSR value.
5538 <b>Example usage</b>
5542 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR1);
5543 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR1, Msr);
5545 @note MSR_NEHALEM_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
5547 #define MSR_NEHALEM_C3_PMON_CTR1 0x00000DD3
5551 Package. Uncore C-box 3 perfmon event select MSR.
5553 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL2 (0x00000DD4)
5554 @param EAX Lower 32-bits of MSR value.
5555 @param EDX Upper 32-bits of MSR value.
5557 <b>Example usage</b>
5561 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2);
5562 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2, Msr);
5564 @note MSR_NEHALEM_C3_PMON_EVNT_SEL2 is defined as MSR_C3_PMON_EVNT_SEL2 in SDM.
5566 #define MSR_NEHALEM_C3_PMON_EVNT_SEL2 0x00000DD4
5570 Package. Uncore C-box 3 perfmon counter MSR.
5572 @param ECX MSR_NEHALEM_C3_PMON_CTR2 (0x00000DD5)
5573 @param EAX Lower 32-bits of MSR value.
5574 @param EDX Upper 32-bits of MSR value.
5576 <b>Example usage</b>
5580 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR2);
5581 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR2, Msr);
5583 @note MSR_NEHALEM_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
5585 #define MSR_NEHALEM_C3_PMON_CTR2 0x00000DD5
5589 Package. Uncore C-box 3 perfmon event select MSR.
5591 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL3 (0x00000DD6)
5592 @param EAX Lower 32-bits of MSR value.
5593 @param EDX Upper 32-bits of MSR value.
5595 <b>Example usage</b>
5599 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3);
5600 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3, Msr);
5602 @note MSR_NEHALEM_C3_PMON_EVNT_SEL3 is defined as MSR_C3_PMON_EVNT_SEL3 in SDM.
5604 #define MSR_NEHALEM_C3_PMON_EVNT_SEL3 0x00000DD6
5608 Package. Uncore C-box 3 perfmon counter MSR.
5610 @param ECX MSR_NEHALEM_C3_PMON_CTR3 (0x00000DD7)
5611 @param EAX Lower 32-bits of MSR value.
5612 @param EDX Upper 32-bits of MSR value.
5614 <b>Example usage</b>
5618 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR3);
5619 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR3, Msr);
5621 @note MSR_NEHALEM_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
5623 #define MSR_NEHALEM_C3_PMON_CTR3 0x00000DD7
5627 Package. Uncore C-box 3 perfmon event select MSR.
5629 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL4 (0x00000DD8)
5630 @param EAX Lower 32-bits of MSR value.
5631 @param EDX Upper 32-bits of MSR value.
5633 <b>Example usage</b>
5637 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4);
5638 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4, Msr);
5640 @note MSR_NEHALEM_C3_PMON_EVNT_SEL4 is defined as MSR_C3_PMON_EVNT_SEL4 in SDM.
5642 #define MSR_NEHALEM_C3_PMON_EVNT_SEL4 0x00000DD8
5646 Package. Uncore C-box 3 perfmon counter MSR.
5648 @param ECX MSR_NEHALEM_C3_PMON_CTR4 (0x00000DD9)
5649 @param EAX Lower 32-bits of MSR value.
5650 @param EDX Upper 32-bits of MSR value.
5652 <b>Example usage</b>
5656 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR4);
5657 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR4, Msr);
5659 @note MSR_NEHALEM_C3_PMON_CTR4 is defined as MSR_C3_PMON_CTR4 in SDM.
5661 #define MSR_NEHALEM_C3_PMON_CTR4 0x00000DD9
5665 Package. Uncore C-box 3 perfmon event select MSR.
5667 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL5 (0x00000DDA)
5668 @param EAX Lower 32-bits of MSR value.
5669 @param EDX Upper 32-bits of MSR value.
5671 <b>Example usage</b>
5675 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5);
5676 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5, Msr);
5678 @note MSR_NEHALEM_C3_PMON_EVNT_SEL5 is defined as MSR_C3_PMON_EVNT_SEL5 in SDM.
5680 #define MSR_NEHALEM_C3_PMON_EVNT_SEL5 0x00000DDA
5684 Package. Uncore C-box 3 perfmon counter MSR.
5686 @param ECX MSR_NEHALEM_C3_PMON_CTR5 (0x00000DDB)
5687 @param EAX Lower 32-bits of MSR value.
5688 @param EDX Upper 32-bits of MSR value.
5690 <b>Example usage</b>
5694 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR5);
5695 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR5, Msr);
5697 @note MSR_NEHALEM_C3_PMON_CTR5 is defined as MSR_C3_PMON_CTR5 in SDM.
5699 #define MSR_NEHALEM_C3_PMON_CTR5 0x00000DDB
5703 Package. Uncore C-box 7 perfmon local box control MSR.
5705 @param ECX MSR_NEHALEM_C7_PMON_BOX_CTRL (0x00000DE0)
5706 @param EAX Lower 32-bits of MSR value.
5707 @param EDX Upper 32-bits of MSR value.
5709 <b>Example usage</b>
5713 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL);
5714 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL, Msr);
5716 @note MSR_NEHALEM_C7_PMON_BOX_CTRL is defined as MSR_C7_PMON_BOX_CTRL in SDM.
5718 #define MSR_NEHALEM_C7_PMON_BOX_CTRL 0x00000DE0
5722 Package. Uncore C-box 7 perfmon local box status MSR.
5724 @param ECX MSR_NEHALEM_C7_PMON_BOX_STATUS (0x00000DE1)
5725 @param EAX Lower 32-bits of MSR value.
5726 @param EDX Upper 32-bits of MSR value.
5728 <b>Example usage</b>
5732 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS);
5733 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS, Msr);
5735 @note MSR_NEHALEM_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.
5737 #define MSR_NEHALEM_C7_PMON_BOX_STATUS 0x00000DE1
5741 Package. Uncore C-box 7 perfmon local box overflow control MSR.
5743 @param ECX MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL (0x00000DE2)
5744 @param EAX Lower 32-bits of MSR value.
5745 @param EDX Upper 32-bits of MSR value.
5747 <b>Example usage</b>
5751 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL);
5752 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL, Msr);
5754 @note MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL is defined as MSR_C7_PMON_BOX_OVF_CTRL in SDM.
5756 #define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL 0x00000DE2
5760 Package. Uncore C-box 7 perfmon event select MSR.
5762 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL0 (0x00000DF0)
5763 @param EAX Lower 32-bits of MSR value.
5764 @param EDX Upper 32-bits of MSR value.
5766 <b>Example usage</b>
5770 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0);
5771 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0, Msr);
5773 @note MSR_NEHALEM_C7_PMON_EVNT_SEL0 is defined as MSR_C7_PMON_EVNT_SEL0 in SDM.
5775 #define MSR_NEHALEM_C7_PMON_EVNT_SEL0 0x00000DF0
5779 Package. Uncore C-box 7 perfmon counter MSR.
5781 @param ECX MSR_NEHALEM_C7_PMON_CTR0 (0x00000DF1)
5782 @param EAX Lower 32-bits of MSR value.
5783 @param EDX Upper 32-bits of MSR value.
5785 <b>Example usage</b>
5789 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR0);
5790 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR0, Msr);
5792 @note MSR_NEHALEM_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
5794 #define MSR_NEHALEM_C7_PMON_CTR0 0x00000DF1
5798 Package. Uncore C-box 7 perfmon event select MSR.
5800 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL1 (0x00000DF2)
5801 @param EAX Lower 32-bits of MSR value.
5802 @param EDX Upper 32-bits of MSR value.
5804 <b>Example usage</b>
5808 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1);
5809 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1, Msr);
5811 @note MSR_NEHALEM_C7_PMON_EVNT_SEL1 is defined as MSR_C7_PMON_EVNT_SEL1 in SDM.
5813 #define MSR_NEHALEM_C7_PMON_EVNT_SEL1 0x00000DF2
5817 Package. Uncore C-box 7 perfmon counter MSR.
5819 @param ECX MSR_NEHALEM_C7_PMON_CTR1 (0x00000DF3)
5820 @param EAX Lower 32-bits of MSR value.
5821 @param EDX Upper 32-bits of MSR value.
5823 <b>Example usage</b>
5827 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR1);
5828 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR1, Msr);
5830 @note MSR_NEHALEM_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
5832 #define MSR_NEHALEM_C7_PMON_CTR1 0x00000DF3
5836 Package. Uncore C-box 7 perfmon event select MSR.
5838 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL2 (0x00000DF4)
5839 @param EAX Lower 32-bits of MSR value.
5840 @param EDX Upper 32-bits of MSR value.
5842 <b>Example usage</b>
5846 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2);
5847 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2, Msr);
5849 @note MSR_NEHALEM_C7_PMON_EVNT_SEL2 is defined as MSR_C7_PMON_EVNT_SEL2 in SDM.
5851 #define MSR_NEHALEM_C7_PMON_EVNT_SEL2 0x00000DF4
5855 Package. Uncore C-box 7 perfmon counter MSR.
5857 @param ECX MSR_NEHALEM_C7_PMON_CTR2 (0x00000DF5)
5858 @param EAX Lower 32-bits of MSR value.
5859 @param EDX Upper 32-bits of MSR value.
5861 <b>Example usage</b>
5865 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR2);
5866 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR2, Msr);
5868 @note MSR_NEHALEM_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
5870 #define MSR_NEHALEM_C7_PMON_CTR2 0x00000DF5
5874 Package. Uncore C-box 7 perfmon event select MSR.
5876 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL3 (0x00000DF6)
5877 @param EAX Lower 32-bits of MSR value.
5878 @param EDX Upper 32-bits of MSR value.
5880 <b>Example usage</b>
5884 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3);
5885 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3, Msr);
5887 @note MSR_NEHALEM_C7_PMON_EVNT_SEL3 is defined as MSR_C7_PMON_EVNT_SEL3 in SDM.
5889 #define MSR_NEHALEM_C7_PMON_EVNT_SEL3 0x00000DF6
5893 Package. Uncore C-box 7 perfmon counter MSR.
5895 @param ECX MSR_NEHALEM_C7_PMON_CTR3 (0x00000DF7)
5896 @param EAX Lower 32-bits of MSR value.
5897 @param EDX Upper 32-bits of MSR value.
5899 <b>Example usage</b>
5903 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR3);
5904 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR3, Msr);
5906 @note MSR_NEHALEM_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
5908 #define MSR_NEHALEM_C7_PMON_CTR3 0x00000DF7
5912 Package. Uncore C-box 7 perfmon event select MSR.
5914 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL4 (0x00000DF8)
5915 @param EAX Lower 32-bits of MSR value.
5916 @param EDX Upper 32-bits of MSR value.
5918 <b>Example usage</b>
5922 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4);
5923 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4, Msr);
5925 @note MSR_NEHALEM_C7_PMON_EVNT_SEL4 is defined as MSR_C7_PMON_EVNT_SEL4 in SDM.
5927 #define MSR_NEHALEM_C7_PMON_EVNT_SEL4 0x00000DF8
5931 Package. Uncore C-box 7 perfmon counter MSR.
5933 @param ECX MSR_NEHALEM_C7_PMON_CTR4 (0x00000DF9)
5934 @param EAX Lower 32-bits of MSR value.
5935 @param EDX Upper 32-bits of MSR value.
5937 <b>Example usage</b>
5941 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR4);
5942 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR4, Msr);
5944 @note MSR_NEHALEM_C7_PMON_CTR4 is defined as MSR_C7_PMON_CTR4 in SDM.
5946 #define MSR_NEHALEM_C7_PMON_CTR4 0x00000DF9
5950 Package. Uncore C-box 7 perfmon event select MSR.
5952 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL5 (0x00000DFA)
5953 @param EAX Lower 32-bits of MSR value.
5954 @param EDX Upper 32-bits of MSR value.
5956 <b>Example usage</b>
5960 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5);
5961 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5, Msr);
5963 @note MSR_NEHALEM_C7_PMON_EVNT_SEL5 is defined as MSR_C7_PMON_EVNT_SEL5 in SDM.
5965 #define MSR_NEHALEM_C7_PMON_EVNT_SEL5 0x00000DFA
5969 Package. Uncore C-box 7 perfmon counter MSR.
5971 @param ECX MSR_NEHALEM_C7_PMON_CTR5 (0x00000DFB)
5972 @param EAX Lower 32-bits of MSR value.
5973 @param EDX Upper 32-bits of MSR value.
5975 <b>Example usage</b>
5979 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR5);
5980 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR5, Msr);
5982 @note MSR_NEHALEM_C7_PMON_CTR5 is defined as MSR_C7_PMON_CTR5 in SDM.
5984 #define MSR_NEHALEM_C7_PMON_CTR5 0x00000DFB
5988 Package. Uncore R-box 0 perfmon local box control MSR.
5990 @param ECX MSR_NEHALEM_R0_PMON_BOX_CTRL (0x00000E00)
5991 @param EAX Lower 32-bits of MSR value.
5992 @param EDX Upper 32-bits of MSR value.
5994 <b>Example usage</b>
5998 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL);
5999 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL, Msr);
6001 @note MSR_NEHALEM_R0_PMON_BOX_CTRL is defined as MSR_R0_PMON_BOX_CTRL in SDM.
6003 #define MSR_NEHALEM_R0_PMON_BOX_CTRL 0x00000E00
6007 Package. Uncore R-box 0 perfmon local box status MSR.
6009 @param ECX MSR_NEHALEM_R0_PMON_BOX_STATUS (0x00000E01)
6010 @param EAX Lower 32-bits of MSR value.
6011 @param EDX Upper 32-bits of MSR value.
6013 <b>Example usage</b>
6017 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS);
6018 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS, Msr);
6020 @note MSR_NEHALEM_R0_PMON_BOX_STATUS is defined as MSR_R0_PMON_BOX_STATUS in SDM.
6022 #define MSR_NEHALEM_R0_PMON_BOX_STATUS 0x00000E01
6026 Package. Uncore R-box 0 perfmon local box overflow control MSR.
6028 @param ECX MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL (0x00000E02)
6029 @param EAX Lower 32-bits of MSR value.
6030 @param EDX Upper 32-bits of MSR value.
6032 <b>Example usage</b>
6036 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL);
6037 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL, Msr);
6039 @note MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL is defined as MSR_R0_PMON_BOX_OVF_CTRL in SDM.
6041 #define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL 0x00000E02
6045 Package. Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.
6047 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P0 (0x00000E04)
6048 @param EAX Lower 32-bits of MSR value.
6049 @param EDX Upper 32-bits of MSR value.
6051 <b>Example usage</b>
6055 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0);
6056 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0, Msr);
6058 @note MSR_NEHALEM_R0_PMON_IPERF0_P0 is defined as MSR_R0_PMON_IPERF0_P0 in SDM.
6060 #define MSR_NEHALEM_R0_PMON_IPERF0_P0 0x00000E04
6064 Package. Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.
6066 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P1 (0x00000E05)
6067 @param EAX Lower 32-bits of MSR value.
6068 @param EDX Upper 32-bits of MSR value.
6070 <b>Example usage</b>
6074 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1);
6075 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1, Msr);
6077 @note MSR_NEHALEM_R0_PMON_IPERF0_P1 is defined as MSR_R0_PMON_IPERF0_P1 in SDM.
6079 #define MSR_NEHALEM_R0_PMON_IPERF0_P1 0x00000E05
6083 Package. Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.
6085 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P2 (0x00000E06)
6086 @param EAX Lower 32-bits of MSR value.
6087 @param EDX Upper 32-bits of MSR value.
6089 <b>Example usage</b>
6093 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2);
6094 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2, Msr);
6096 @note MSR_NEHALEM_R0_PMON_IPERF0_P2 is defined as MSR_R0_PMON_IPERF0_P2 in SDM.
6098 #define MSR_NEHALEM_R0_PMON_IPERF0_P2 0x00000E06
6102 Package. Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.
6104 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P3 (0x00000E07)
6105 @param EAX Lower 32-bits of MSR value.
6106 @param EDX Upper 32-bits of MSR value.
6108 <b>Example usage</b>
6112 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3);
6113 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3, Msr);
6115 @note MSR_NEHALEM_R0_PMON_IPERF0_P3 is defined as MSR_R0_PMON_IPERF0_P3 in SDM.
6117 #define MSR_NEHALEM_R0_PMON_IPERF0_P3 0x00000E07
6121 Package. Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.
6123 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P4 (0x00000E08)
6124 @param EAX Lower 32-bits of MSR value.
6125 @param EDX Upper 32-bits of MSR value.
6127 <b>Example usage</b>
6131 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4);
6132 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4, Msr);
6134 @note MSR_NEHALEM_R0_PMON_IPERF0_P4 is defined as MSR_R0_PMON_IPERF0_P4 in SDM.
6136 #define MSR_NEHALEM_R0_PMON_IPERF0_P4 0x00000E08
6140 Package. Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.
6142 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P5 (0x00000E09)
6143 @param EAX Lower 32-bits of MSR value.
6144 @param EDX Upper 32-bits of MSR value.
6146 <b>Example usage</b>
6150 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5);
6151 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5, Msr);
6153 @note MSR_NEHALEM_R0_PMON_IPERF0_P5 is defined as MSR_R0_PMON_IPERF0_P5 in SDM.
6155 #define MSR_NEHALEM_R0_PMON_IPERF0_P5 0x00000E09
6159 Package. Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.
6161 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P6 (0x00000E0A)
6162 @param EAX Lower 32-bits of MSR value.
6163 @param EDX Upper 32-bits of MSR value.
6165 <b>Example usage</b>
6169 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6);
6170 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6, Msr);
6172 @note MSR_NEHALEM_R0_PMON_IPERF0_P6 is defined as MSR_R0_PMON_IPERF0_P6 in SDM.
6174 #define MSR_NEHALEM_R0_PMON_IPERF0_P6 0x00000E0A
6178 Package. Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.
6180 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P7 (0x00000E0B)
6181 @param EAX Lower 32-bits of MSR value.
6182 @param EDX Upper 32-bits of MSR value.
6184 <b>Example usage</b>
6188 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7);
6189 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7, Msr);
6191 @note MSR_NEHALEM_R0_PMON_IPERF0_P7 is defined as MSR_R0_PMON_IPERF0_P7 in SDM.
6193 #define MSR_NEHALEM_R0_PMON_IPERF0_P7 0x00000E0B
6197 Package. Uncore R-box 0 perfmon QLX unit Port 0 select MSR.
6199 @param ECX MSR_NEHALEM_R0_PMON_QLX_P0 (0x00000E0C)
6200 @param EAX Lower 32-bits of MSR value.
6201 @param EDX Upper 32-bits of MSR value.
6203 <b>Example usage</b>
6207 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0);
6208 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0, Msr);
6210 @note MSR_NEHALEM_R0_PMON_QLX_P0 is defined as MSR_R0_PMON_QLX_P0 in SDM.
6212 #define MSR_NEHALEM_R0_PMON_QLX_P0 0x00000E0C
6216 Package. Uncore R-box 0 perfmon QLX unit Port 1 select MSR.
6218 @param ECX MSR_NEHALEM_R0_PMON_QLX_P1 (0x00000E0D)
6219 @param EAX Lower 32-bits of MSR value.
6220 @param EDX Upper 32-bits of MSR value.
6222 <b>Example usage</b>
6226 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1);
6227 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1, Msr);
6229 @note MSR_NEHALEM_R0_PMON_QLX_P1 is defined as MSR_R0_PMON_QLX_P1 in SDM.
6231 #define MSR_NEHALEM_R0_PMON_QLX_P1 0x00000E0D
6235 Package. Uncore R-box 0 perfmon QLX unit Port 2 select MSR.
6237 @param ECX MSR_NEHALEM_R0_PMON_QLX_P2 (0x00000E0E)
6238 @param EAX Lower 32-bits of MSR value.
6239 @param EDX Upper 32-bits of MSR value.
6241 <b>Example usage</b>
6245 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2);
6246 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2, Msr);
6248 @note MSR_NEHALEM_R0_PMON_QLX_P2 is defined as MSR_R0_PMON_QLX_P2 in SDM.
6250 #define MSR_NEHALEM_R0_PMON_QLX_P2 0x00000E0E
6254 Package. Uncore R-box 0 perfmon QLX unit Port 3 select MSR.
6256 @param ECX MSR_NEHALEM_R0_PMON_QLX_P3 (0x00000E0F)
6257 @param EAX Lower 32-bits of MSR value.
6258 @param EDX Upper 32-bits of MSR value.
6260 <b>Example usage</b>
6264 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3);
6265 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3, Msr);
6267 @note MSR_NEHALEM_R0_PMON_QLX_P3 is defined as MSR_R0_PMON_QLX_P3 in SDM.
6269 #define MSR_NEHALEM_R0_PMON_QLX_P3 0x00000E0F
6273 Package. Uncore R-box 0 perfmon event select MSR.
6275 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL0 (0x00000E10)
6276 @param EAX Lower 32-bits of MSR value.
6277 @param EDX Upper 32-bits of MSR value.
6279 <b>Example usage</b>
6283 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0);
6284 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0, Msr);
6286 @note MSR_NEHALEM_R0_PMON_EVNT_SEL0 is defined as MSR_R0_PMON_EVNT_SEL0 in SDM.
6288 #define MSR_NEHALEM_R0_PMON_EVNT_SEL0 0x00000E10
6292 Package. Uncore R-box 0 perfmon counter MSR.
6294 @param ECX MSR_NEHALEM_R0_PMON_CTR0 (0x00000E11)
6295 @param EAX Lower 32-bits of MSR value.
6296 @param EDX Upper 32-bits of MSR value.
6298 <b>Example usage</b>
6302 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR0);
6303 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR0, Msr);
6305 @note MSR_NEHALEM_R0_PMON_CTR0 is defined as MSR_R0_PMON_CTR0 in SDM.
6307 #define MSR_NEHALEM_R0_PMON_CTR0 0x00000E11
6311 Package. Uncore R-box 0 perfmon event select MSR.
6313 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL1 (0x00000E12)
6314 @param EAX Lower 32-bits of MSR value.
6315 @param EDX Upper 32-bits of MSR value.
6317 <b>Example usage</b>
6321 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1);
6322 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1, Msr);
6324 @note MSR_NEHALEM_R0_PMON_EVNT_SEL1 is defined as MSR_R0_PMON_EVNT_SEL1 in SDM.
6326 #define MSR_NEHALEM_R0_PMON_EVNT_SEL1 0x00000E12
6330 Package. Uncore R-box 0 perfmon counter MSR.
6332 @param ECX MSR_NEHALEM_R0_PMON_CTR1 (0x00000E13)
6333 @param EAX Lower 32-bits of MSR value.
6334 @param EDX Upper 32-bits of MSR value.
6336 <b>Example usage</b>
6340 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR1);
6341 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR1, Msr);
6343 @note MSR_NEHALEM_R0_PMON_CTR1 is defined as MSR_R0_PMON_CTR1 in SDM.
6345 #define MSR_NEHALEM_R0_PMON_CTR1 0x00000E13
6349 Package. Uncore R-box 0 perfmon event select MSR.
6351 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL2 (0x00000E14)
6352 @param EAX Lower 32-bits of MSR value.
6353 @param EDX Upper 32-bits of MSR value.
6355 <b>Example usage</b>
6359 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2);
6360 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2, Msr);
6362 @note MSR_NEHALEM_R0_PMON_EVNT_SEL2 is defined as MSR_R0_PMON_EVNT_SEL2 in SDM.
6364 #define MSR_NEHALEM_R0_PMON_EVNT_SEL2 0x00000E14
6368 Package. Uncore R-box 0 perfmon counter MSR.
6370 @param ECX MSR_NEHALEM_R0_PMON_CTR2 (0x00000E15)
6371 @param EAX Lower 32-bits of MSR value.
6372 @param EDX Upper 32-bits of MSR value.
6374 <b>Example usage</b>
6378 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR2);
6379 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR2, Msr);
6381 @note MSR_NEHALEM_R0_PMON_CTR2 is defined as MSR_R0_PMON_CTR2 in SDM.
6383 #define MSR_NEHALEM_R0_PMON_CTR2 0x00000E15
6387 Package. Uncore R-box 0 perfmon event select MSR.
6389 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL3 (0x00000E16)
6390 @param EAX Lower 32-bits of MSR value.
6391 @param EDX Upper 32-bits of MSR value.
6393 <b>Example usage</b>
6397 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3);
6398 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3, Msr);
6400 @note MSR_NEHALEM_R0_PMON_EVNT_SEL3 is defined as MSR_R0_PMON_EVNT_SEL3 in SDM.
6402 #define MSR_NEHALEM_R0_PMON_EVNT_SEL3 0x00000E16
6406 Package. Uncore R-box 0 perfmon counter MSR.
6408 @param ECX MSR_NEHALEM_R0_PMON_CTR3 (0x00000E17)
6409 @param EAX Lower 32-bits of MSR value.
6410 @param EDX Upper 32-bits of MSR value.
6412 <b>Example usage</b>
6416 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR3);
6417 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR3, Msr);
6419 @note MSR_NEHALEM_R0_PMON_CTR3 is defined as MSR_R0_PMON_CTR3 in SDM.
6421 #define MSR_NEHALEM_R0_PMON_CTR3 0x00000E17
6425 Package. Uncore R-box 0 perfmon event select MSR.
6427 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL4 (0x00000E18)
6428 @param EAX Lower 32-bits of MSR value.
6429 @param EDX Upper 32-bits of MSR value.
6431 <b>Example usage</b>
6435 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4);
6436 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4, Msr);
6438 @note MSR_NEHALEM_R0_PMON_EVNT_SEL4 is defined as MSR_R0_PMON_EVNT_SEL4 in SDM.
6440 #define MSR_NEHALEM_R0_PMON_EVNT_SEL4 0x00000E18
6444 Package. Uncore R-box 0 perfmon counter MSR.
6446 @param ECX MSR_NEHALEM_R0_PMON_CTR4 (0x00000E19)
6447 @param EAX Lower 32-bits of MSR value.
6448 @param EDX Upper 32-bits of MSR value.
6450 <b>Example usage</b>
6454 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR4);
6455 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR4, Msr);
6457 @note MSR_NEHALEM_R0_PMON_CTR4 is defined as MSR_R0_PMON_CTR4 in SDM.
6459 #define MSR_NEHALEM_R0_PMON_CTR4 0x00000E19
6463 Package. Uncore R-box 0 perfmon event select MSR.
6465 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL5 (0x00000E1A)
6466 @param EAX Lower 32-bits of MSR value.
6467 @param EDX Upper 32-bits of MSR value.
6469 <b>Example usage</b>
6473 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5);
6474 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5, Msr);
6476 @note MSR_NEHALEM_R0_PMON_EVNT_SEL5 is defined as MSR_R0_PMON_EVNT_SEL5 in SDM.
6478 #define MSR_NEHALEM_R0_PMON_EVNT_SEL5 0x00000E1A
6482 Package. Uncore R-box 0 perfmon counter MSR.
6484 @param ECX MSR_NEHALEM_R0_PMON_CTR5 (0x00000E1B)
6485 @param EAX Lower 32-bits of MSR value.
6486 @param EDX Upper 32-bits of MSR value.
6488 <b>Example usage</b>
6492 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR5);
6493 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR5, Msr);
6495 @note MSR_NEHALEM_R0_PMON_CTR5 is defined as MSR_R0_PMON_CTR5 in SDM.
6497 #define MSR_NEHALEM_R0_PMON_CTR5 0x00000E1B
6501 Package. Uncore R-box 0 perfmon event select MSR.
6503 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL6 (0x00000E1C)
6504 @param EAX Lower 32-bits of MSR value.
6505 @param EDX Upper 32-bits of MSR value.
6507 <b>Example usage</b>
6511 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6);
6512 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6, Msr);
6514 @note MSR_NEHALEM_R0_PMON_EVNT_SEL6 is defined as MSR_R0_PMON_EVNT_SEL6 in SDM.
6516 #define MSR_NEHALEM_R0_PMON_EVNT_SEL6 0x00000E1C
6520 Package. Uncore R-box 0 perfmon counter MSR.
6522 @param ECX MSR_NEHALEM_R0_PMON_CTR6 (0x00000E1D)
6523 @param EAX Lower 32-bits of MSR value.
6524 @param EDX Upper 32-bits of MSR value.
6526 <b>Example usage</b>
6530 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR6);
6531 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR6, Msr);
6533 @note MSR_NEHALEM_R0_PMON_CTR6 is defined as MSR_R0_PMON_CTR6 in SDM.
6535 #define MSR_NEHALEM_R0_PMON_CTR6 0x00000E1D
6539 Package. Uncore R-box 0 perfmon event select MSR.
6541 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL7 (0x00000E1E)
6542 @param EAX Lower 32-bits of MSR value.
6543 @param EDX Upper 32-bits of MSR value.
6545 <b>Example usage</b>
6549 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7);
6550 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7, Msr);
6552 @note MSR_NEHALEM_R0_PMON_EVNT_SEL7 is defined as MSR_R0_PMON_EVNT_SEL7 in SDM.
6554 #define MSR_NEHALEM_R0_PMON_EVNT_SEL7 0x00000E1E
6558 Package. Uncore R-box 0 perfmon counter MSR.
6560 @param ECX MSR_NEHALEM_R0_PMON_CTR7 (0x00000E1F)
6561 @param EAX Lower 32-bits of MSR value.
6562 @param EDX Upper 32-bits of MSR value.
6564 <b>Example usage</b>
6568 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR7);
6569 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR7, Msr);
6571 @note MSR_NEHALEM_R0_PMON_CTR7 is defined as MSR_R0_PMON_CTR7 in SDM.
6573 #define MSR_NEHALEM_R0_PMON_CTR7 0x00000E1F
6577 Package. Uncore R-box 1 perfmon local box control MSR.
6579 @param ECX MSR_NEHALEM_R1_PMON_BOX_CTRL (0x00000E20)
6580 @param EAX Lower 32-bits of MSR value.
6581 @param EDX Upper 32-bits of MSR value.
6583 <b>Example usage</b>
6587 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL);
6588 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL, Msr);
6590 @note MSR_NEHALEM_R1_PMON_BOX_CTRL is defined as MSR_R1_PMON_BOX_CTRL in SDM.
6592 #define MSR_NEHALEM_R1_PMON_BOX_CTRL 0x00000E20
6596 Package. Uncore R-box 1 perfmon local box status MSR.
6598 @param ECX MSR_NEHALEM_R1_PMON_BOX_STATUS (0x00000E21)
6599 @param EAX Lower 32-bits of MSR value.
6600 @param EDX Upper 32-bits of MSR value.
6602 <b>Example usage</b>
6606 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS);
6607 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS, Msr);
6609 @note MSR_NEHALEM_R1_PMON_BOX_STATUS is defined as MSR_R1_PMON_BOX_STATUS in SDM.
6611 #define MSR_NEHALEM_R1_PMON_BOX_STATUS 0x00000E21
6615 Package. Uncore R-box 1 perfmon local box overflow control MSR.
6617 @param ECX MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL (0x00000E22)
6618 @param EAX Lower 32-bits of MSR value.
6619 @param EDX Upper 32-bits of MSR value.
6621 <b>Example usage</b>
6625 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL);
6626 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL, Msr);
6628 @note MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL is defined as MSR_R1_PMON_BOX_OVF_CTRL in SDM.
6630 #define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL 0x00000E22
6634 Package. Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.
6636 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P8 (0x00000E24)
6637 @param EAX Lower 32-bits of MSR value.
6638 @param EDX Upper 32-bits of MSR value.
6640 <b>Example usage</b>
6644 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8);
6645 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8, Msr);
6647 @note MSR_NEHALEM_R1_PMON_IPERF1_P8 is defined as MSR_R1_PMON_IPERF1_P8 in SDM.
6649 #define MSR_NEHALEM_R1_PMON_IPERF1_P8 0x00000E24
6653 Package. Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.
6655 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P9 (0x00000E25)
6656 @param EAX Lower 32-bits of MSR value.
6657 @param EDX Upper 32-bits of MSR value.
6659 <b>Example usage</b>
6663 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9);
6664 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9, Msr);
6666 @note MSR_NEHALEM_R1_PMON_IPERF1_P9 is defined as MSR_R1_PMON_IPERF1_P9 in SDM.
6668 #define MSR_NEHALEM_R1_PMON_IPERF1_P9 0x00000E25
6672 Package. Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.
6674 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P10 (0x00000E26)
6675 @param EAX Lower 32-bits of MSR value.
6676 @param EDX Upper 32-bits of MSR value.
6678 <b>Example usage</b>
6682 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10);
6683 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10, Msr);
6685 @note MSR_NEHALEM_R1_PMON_IPERF1_P10 is defined as MSR_R1_PMON_IPERF1_P10 in SDM.
6687 #define MSR_NEHALEM_R1_PMON_IPERF1_P10 0x00000E26
6691 Package. Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.
6693 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P11 (0x00000E27)
6694 @param EAX Lower 32-bits of MSR value.
6695 @param EDX Upper 32-bits of MSR value.
6697 <b>Example usage</b>
6701 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11);
6702 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11, Msr);
6704 @note MSR_NEHALEM_R1_PMON_IPERF1_P11 is defined as MSR_R1_PMON_IPERF1_P11 in SDM.
6706 #define MSR_NEHALEM_R1_PMON_IPERF1_P11 0x00000E27
6710 Package. Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.
6712 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P12 (0x00000E28)
6713 @param EAX Lower 32-bits of MSR value.
6714 @param EDX Upper 32-bits of MSR value.
6716 <b>Example usage</b>
6720 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12);
6721 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12, Msr);
6723 @note MSR_NEHALEM_R1_PMON_IPERF1_P12 is defined as MSR_R1_PMON_IPERF1_P12 in SDM.
6725 #define MSR_NEHALEM_R1_PMON_IPERF1_P12 0x00000E28
6729 Package. Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.
6731 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P13 (0x00000E29)
6732 @param EAX Lower 32-bits of MSR value.
6733 @param EDX Upper 32-bits of MSR value.
6735 <b>Example usage</b>
6739 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13);
6740 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13, Msr);
6742 @note MSR_NEHALEM_R1_PMON_IPERF1_P13 is defined as MSR_R1_PMON_IPERF1_P13 in SDM.
6744 #define MSR_NEHALEM_R1_PMON_IPERF1_P13 0x00000E29
6748 Package. Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.
6750 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P14 (0x00000E2A)
6751 @param EAX Lower 32-bits of MSR value.
6752 @param EDX Upper 32-bits of MSR value.
6754 <b>Example usage</b>
6758 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14);
6759 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14, Msr);
6761 @note MSR_NEHALEM_R1_PMON_IPERF1_P14 is defined as MSR_R1_PMON_IPERF1_P14 in SDM.
6763 #define MSR_NEHALEM_R1_PMON_IPERF1_P14 0x00000E2A
6767 Package. Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.
6769 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P15 (0x00000E2B)
6770 @param EAX Lower 32-bits of MSR value.
6771 @param EDX Upper 32-bits of MSR value.
6773 <b>Example usage</b>
6777 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15);
6778 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15, Msr);
6780 @note MSR_NEHALEM_R1_PMON_IPERF1_P15 is defined as MSR_R1_PMON_IPERF1_P15 in SDM.
6782 #define MSR_NEHALEM_R1_PMON_IPERF1_P15 0x00000E2B
6786 Package. Uncore R-box 1 perfmon QLX unit Port 4 select MSR.
6788 @param ECX MSR_NEHALEM_R1_PMON_QLX_P4 (0x00000E2C)
6789 @param EAX Lower 32-bits of MSR value.
6790 @param EDX Upper 32-bits of MSR value.
6792 <b>Example usage</b>
6796 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4);
6797 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4, Msr);
6799 @note MSR_NEHALEM_R1_PMON_QLX_P4 is defined as MSR_R1_PMON_QLX_P4 in SDM.
6801 #define MSR_NEHALEM_R1_PMON_QLX_P4 0x00000E2C
6805 Package. Uncore R-box 1 perfmon QLX unit Port 5 select MSR.
6807 @param ECX MSR_NEHALEM_R1_PMON_QLX_P5 (0x00000E2D)
6808 @param EAX Lower 32-bits of MSR value.
6809 @param EDX Upper 32-bits of MSR value.
6811 <b>Example usage</b>
6815 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5);
6816 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5, Msr);
6818 @note MSR_NEHALEM_R1_PMON_QLX_P5 is defined as MSR_R1_PMON_QLX_P5 in SDM.
6820 #define MSR_NEHALEM_R1_PMON_QLX_P5 0x00000E2D
6824 Package. Uncore R-box 1 perfmon QLX unit Port 6 select MSR.
6826 @param ECX MSR_NEHALEM_R1_PMON_QLX_P6 (0x00000E2E)
6827 @param EAX Lower 32-bits of MSR value.
6828 @param EDX Upper 32-bits of MSR value.
6830 <b>Example usage</b>
6834 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6);
6835 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6, Msr);
6837 @note MSR_NEHALEM_R1_PMON_QLX_P6 is defined as MSR_R1_PMON_QLX_P6 in SDM.
6839 #define MSR_NEHALEM_R1_PMON_QLX_P6 0x00000E2E
6843 Package. Uncore R-box 1 perfmon QLX unit Port 7 select MSR.
6845 @param ECX MSR_NEHALEM_R1_PMON_QLX_P7 (0x00000E2F)
6846 @param EAX Lower 32-bits of MSR value.
6847 @param EDX Upper 32-bits of MSR value.
6849 <b>Example usage</b>
6853 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7);
6854 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7, Msr);
6856 @note MSR_NEHALEM_R1_PMON_QLX_P7 is defined as MSR_R1_PMON_QLX_P7 in SDM.
6858 #define MSR_NEHALEM_R1_PMON_QLX_P7 0x00000E2F
6862 Package. Uncore R-box 1 perfmon event select MSR.
6864 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL8 (0x00000E30)
6865 @param EAX Lower 32-bits of MSR value.
6866 @param EDX Upper 32-bits of MSR value.
6868 <b>Example usage</b>
6872 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8);
6873 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8, Msr);
6875 @note MSR_NEHALEM_R1_PMON_EVNT_SEL8 is defined as MSR_R1_PMON_EVNT_SEL8 in SDM.
6877 #define MSR_NEHALEM_R1_PMON_EVNT_SEL8 0x00000E30
6881 Package. Uncore R-box 1 perfmon counter MSR.
6883 @param ECX MSR_NEHALEM_R1_PMON_CTR8 (0x00000E31)
6884 @param EAX Lower 32-bits of MSR value.
6885 @param EDX Upper 32-bits of MSR value.
6887 <b>Example usage</b>
6891 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR8);
6892 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR8, Msr);
6894 @note MSR_NEHALEM_R1_PMON_CTR8 is defined as MSR_R1_PMON_CTR8 in SDM.
6896 #define MSR_NEHALEM_R1_PMON_CTR8 0x00000E31
6900 Package. Uncore R-box 1 perfmon event select MSR.
6902 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL9 (0x00000E32)
6903 @param EAX Lower 32-bits of MSR value.
6904 @param EDX Upper 32-bits of MSR value.
6906 <b>Example usage</b>
6910 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9);
6911 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9, Msr);
6913 @note MSR_NEHALEM_R1_PMON_EVNT_SEL9 is defined as MSR_R1_PMON_EVNT_SEL9 in SDM.
6915 #define MSR_NEHALEM_R1_PMON_EVNT_SEL9 0x00000E32
6919 Package. Uncore R-box 1 perfmon counter MSR.
6921 @param ECX MSR_NEHALEM_R1_PMON_CTR9 (0x00000E33)
6922 @param EAX Lower 32-bits of MSR value.
6923 @param EDX Upper 32-bits of MSR value.
6925 <b>Example usage</b>
6929 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR9);
6930 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR9, Msr);
6932 @note MSR_NEHALEM_R1_PMON_CTR9 is defined as MSR_R1_PMON_CTR9 in SDM.
6934 #define MSR_NEHALEM_R1_PMON_CTR9 0x00000E33
6938 Package. Uncore R-box 1 perfmon event select MSR.
6940 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL10 (0x00000E34)
6941 @param EAX Lower 32-bits of MSR value.
6942 @param EDX Upper 32-bits of MSR value.
6944 <b>Example usage</b>
6948 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10);
6949 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10, Msr);
6951 @note MSR_NEHALEM_R1_PMON_EVNT_SEL10 is defined as MSR_R1_PMON_EVNT_SEL10 in SDM.
6953 #define MSR_NEHALEM_R1_PMON_EVNT_SEL10 0x00000E34
6957 Package. Uncore R-box 1 perfmon counter MSR.
6959 @param ECX MSR_NEHALEM_R1_PMON_CTR10 (0x00000E35)
6960 @param EAX Lower 32-bits of MSR value.
6961 @param EDX Upper 32-bits of MSR value.
6963 <b>Example usage</b>
6967 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR10);
6968 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR10, Msr);
6970 @note MSR_NEHALEM_R1_PMON_CTR10 is defined as MSR_R1_PMON_CTR10 in SDM.
6972 #define MSR_NEHALEM_R1_PMON_CTR10 0x00000E35
6976 Package. Uncore R-box 1 perfmon event select MSR.
6978 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL11 (0x00000E36)
6979 @param EAX Lower 32-bits of MSR value.
6980 @param EDX Upper 32-bits of MSR value.
6982 <b>Example usage</b>
6986 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11);
6987 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11, Msr);
6989 @note MSR_NEHALEM_R1_PMON_EVNT_SEL11 is defined as MSR_R1_PMON_EVNT_SEL11 in SDM.
6991 #define MSR_NEHALEM_R1_PMON_EVNT_SEL11 0x00000E36
6995 Package. Uncore R-box 1 perfmon counter MSR.
6997 @param ECX MSR_NEHALEM_R1_PMON_CTR11 (0x00000E37)
6998 @param EAX Lower 32-bits of MSR value.
6999 @param EDX Upper 32-bits of MSR value.
7001 <b>Example usage</b>
7005 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR11);
7006 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR11, Msr);
7008 @note MSR_NEHALEM_R1_PMON_CTR11 is defined as MSR_R1_PMON_CTR11 in SDM.
7010 #define MSR_NEHALEM_R1_PMON_CTR11 0x00000E37
7014 Package. Uncore R-box 1 perfmon event select MSR.
7016 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL12 (0x00000E38)
7017 @param EAX Lower 32-bits of MSR value.
7018 @param EDX Upper 32-bits of MSR value.
7020 <b>Example usage</b>
7024 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12);
7025 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12, Msr);
7027 @note MSR_NEHALEM_R1_PMON_EVNT_SEL12 is defined as MSR_R1_PMON_EVNT_SEL12 in SDM.
7029 #define MSR_NEHALEM_R1_PMON_EVNT_SEL12 0x00000E38
7033 Package. Uncore R-box 1 perfmon counter MSR.
7035 @param ECX MSR_NEHALEM_R1_PMON_CTR12 (0x00000E39)
7036 @param EAX Lower 32-bits of MSR value.
7037 @param EDX Upper 32-bits of MSR value.
7039 <b>Example usage</b>
7043 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR12);
7044 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR12, Msr);
7046 @note MSR_NEHALEM_R1_PMON_CTR12 is defined as MSR_R1_PMON_CTR12 in SDM.
7048 #define MSR_NEHALEM_R1_PMON_CTR12 0x00000E39
7052 Package. Uncore R-box 1 perfmon event select MSR.
7054 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL13 (0x00000E3A)
7055 @param EAX Lower 32-bits of MSR value.
7056 @param EDX Upper 32-bits of MSR value.
7058 <b>Example usage</b>
7062 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13);
7063 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13, Msr);
7065 @note MSR_NEHALEM_R1_PMON_EVNT_SEL13 is defined as MSR_R1_PMON_EVNT_SEL13 in SDM.
7067 #define MSR_NEHALEM_R1_PMON_EVNT_SEL13 0x00000E3A
7071 Package. Uncore R-box 1perfmon counter MSR.
7073 @param ECX MSR_NEHALEM_R1_PMON_CTR13 (0x00000E3B)
7074 @param EAX Lower 32-bits of MSR value.
7075 @param EDX Upper 32-bits of MSR value.
7077 <b>Example usage</b>
7081 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR13);
7082 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR13, Msr);
7084 @note MSR_NEHALEM_R1_PMON_CTR13 is defined as MSR_R1_PMON_CTR13 in SDM.
7086 #define MSR_NEHALEM_R1_PMON_CTR13 0x00000E3B
7090 Package. Uncore R-box 1 perfmon event select MSR.
7092 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL14 (0x00000E3C)
7093 @param EAX Lower 32-bits of MSR value.
7094 @param EDX Upper 32-bits of MSR value.
7096 <b>Example usage</b>
7100 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14);
7101 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14, Msr);
7103 @note MSR_NEHALEM_R1_PMON_EVNT_SEL14 is defined as MSR_R1_PMON_EVNT_SEL14 in SDM.
7105 #define MSR_NEHALEM_R1_PMON_EVNT_SEL14 0x00000E3C
7109 Package. Uncore R-box 1 perfmon counter MSR.
7111 @param ECX MSR_NEHALEM_R1_PMON_CTR14 (0x00000E3D)
7112 @param EAX Lower 32-bits of MSR value.
7113 @param EDX Upper 32-bits of MSR value.
7115 <b>Example usage</b>
7119 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR14);
7120 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR14, Msr);
7122 @note MSR_NEHALEM_R1_PMON_CTR14 is defined as MSR_R1_PMON_CTR14 in SDM.
7124 #define MSR_NEHALEM_R1_PMON_CTR14 0x00000E3D
7128 Package. Uncore R-box 1 perfmon event select MSR.
7130 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL15 (0x00000E3E)
7131 @param EAX Lower 32-bits of MSR value.
7132 @param EDX Upper 32-bits of MSR value.
7134 <b>Example usage</b>
7138 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15);
7139 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15, Msr);
7141 @note MSR_NEHALEM_R1_PMON_EVNT_SEL15 is defined as MSR_R1_PMON_EVNT_SEL15 in SDM.
7143 #define MSR_NEHALEM_R1_PMON_EVNT_SEL15 0x00000E3E
7147 Package. Uncore R-box 1 perfmon counter MSR.
7149 @param ECX MSR_NEHALEM_R1_PMON_CTR15 (0x00000E3F)
7150 @param EAX Lower 32-bits of MSR value.
7151 @param EDX Upper 32-bits of MSR value.
7153 <b>Example usage</b>
7157 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR15);
7158 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR15, Msr);
7160 @note MSR_NEHALEM_R1_PMON_CTR15 is defined as MSR_R1_PMON_CTR15 in SDM.
7162 #define MSR_NEHALEM_R1_PMON_CTR15 0x00000E3F
7166 Package. Uncore B-box 0 perfmon local box match MSR.
7168 @param ECX MSR_NEHALEM_B0_PMON_MATCH (0x00000E45)
7169 @param EAX Lower 32-bits of MSR value.
7170 @param EDX Upper 32-bits of MSR value.
7172 <b>Example usage</b>
7176 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MATCH);
7177 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MATCH, Msr);
7179 @note MSR_NEHALEM_B0_PMON_MATCH is defined as MSR_B0_PMON_MATCH in SDM.
7181 #define MSR_NEHALEM_B0_PMON_MATCH 0x00000E45
7185 Package. Uncore B-box 0 perfmon local box mask MSR.
7187 @param ECX MSR_NEHALEM_B0_PMON_MASK (0x00000E46)
7188 @param EAX Lower 32-bits of MSR value.
7189 @param EDX Upper 32-bits of MSR value.
7191 <b>Example usage</b>
7195 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MASK);
7196 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MASK, Msr);
7198 @note MSR_NEHALEM_B0_PMON_MASK is defined as MSR_B0_PMON_MASK in SDM.
7200 #define MSR_NEHALEM_B0_PMON_MASK 0x00000E46
7204 Package. Uncore S-box 0 perfmon local box match MSR.
7206 @param ECX MSR_NEHALEM_S0_PMON_MATCH (0x00000E49)
7207 @param EAX Lower 32-bits of MSR value.
7208 @param EDX Upper 32-bits of MSR value.
7210 <b>Example usage</b>
7214 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MATCH);
7215 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MATCH, Msr);
7217 @note MSR_NEHALEM_S0_PMON_MATCH is defined as MSR_S0_PMON_MATCH in SDM.
7219 #define MSR_NEHALEM_S0_PMON_MATCH 0x00000E49
7223 Package. Uncore S-box 0 perfmon local box mask MSR.
7225 @param ECX MSR_NEHALEM_S0_PMON_MASK (0x00000E4A)
7226 @param EAX Lower 32-bits of MSR value.
7227 @param EDX Upper 32-bits of MSR value.
7229 <b>Example usage</b>
7233 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MASK);
7234 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MASK, Msr);
7236 @note MSR_NEHALEM_S0_PMON_MASK is defined as MSR_S0_PMON_MASK in SDM.
7238 #define MSR_NEHALEM_S0_PMON_MASK 0x00000E4A
7242 Package. Uncore B-box 1 perfmon local box match MSR.
7244 @param ECX MSR_NEHALEM_B1_PMON_MATCH (0x00000E4D)
7245 @param EAX Lower 32-bits of MSR value.
7246 @param EDX Upper 32-bits of MSR value.
7248 <b>Example usage</b>
7252 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MATCH);
7253 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MATCH, Msr);
7255 @note MSR_NEHALEM_B1_PMON_MATCH is defined as MSR_B1_PMON_MATCH in SDM.
7257 #define MSR_NEHALEM_B1_PMON_MATCH 0x00000E4D
7261 Package. Uncore B-box 1 perfmon local box mask MSR.
7263 @param ECX MSR_NEHALEM_B1_PMON_MASK (0x00000E4E)
7264 @param EAX Lower 32-bits of MSR value.
7265 @param EDX Upper 32-bits of MSR value.
7267 <b>Example usage</b>
7271 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MASK);
7272 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MASK, Msr);
7274 @note MSR_NEHALEM_B1_PMON_MASK is defined as MSR_B1_PMON_MASK in SDM.
7276 #define MSR_NEHALEM_B1_PMON_MASK 0x00000E4E
7280 Package. Uncore M-box 0 perfmon local box address match/mask config MSR.
7282 @param ECX MSR_NEHALEM_M0_PMON_MM_CONFIG (0x00000E54)
7283 @param EAX Lower 32-bits of MSR value.
7284 @param EDX Upper 32-bits of MSR value.
7286 <b>Example usage</b>
7290 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG);
7291 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG, Msr);
7293 @note MSR_NEHALEM_M0_PMON_MM_CONFIG is defined as MSR_M0_PMON_MM_CONFIG in SDM.
7295 #define MSR_NEHALEM_M0_PMON_MM_CONFIG 0x00000E54
7299 Package. Uncore M-box 0 perfmon local box address match MSR.
7301 @param ECX MSR_NEHALEM_M0_PMON_ADDR_MATCH (0x00000E55)
7302 @param EAX Lower 32-bits of MSR value.
7303 @param EDX Upper 32-bits of MSR value.
7305 <b>Example usage</b>
7309 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH);
7310 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH, Msr);
7312 @note MSR_NEHALEM_M0_PMON_ADDR_MATCH is defined as MSR_M0_PMON_ADDR_MATCH in SDM.
7314 #define MSR_NEHALEM_M0_PMON_ADDR_MATCH 0x00000E55
7318 Package. Uncore M-box 0 perfmon local box address mask MSR.
7320 @param ECX MSR_NEHALEM_M0_PMON_ADDR_MASK (0x00000E56)
7321 @param EAX Lower 32-bits of MSR value.
7322 @param EDX Upper 32-bits of MSR value.
7324 <b>Example usage</b>
7328 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK);
7329 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK, Msr);
7331 @note MSR_NEHALEM_M0_PMON_ADDR_MASK is defined as MSR_M0_PMON_ADDR_MASK in SDM.
7333 #define MSR_NEHALEM_M0_PMON_ADDR_MASK 0x00000E56
7337 Package. Uncore S-box 1 perfmon local box match MSR.
7339 @param ECX MSR_NEHALEM_S1_PMON_MATCH (0x00000E59)
7340 @param EAX Lower 32-bits of MSR value.
7341 @param EDX Upper 32-bits of MSR value.
7343 <b>Example usage</b>
7347 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MATCH);
7348 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MATCH, Msr);
7350 @note MSR_NEHALEM_S1_PMON_MATCH is defined as MSR_S1_PMON_MATCH in SDM.
7352 #define MSR_NEHALEM_S1_PMON_MATCH 0x00000E59
7356 Package. Uncore S-box 1 perfmon local box mask MSR.
7358 @param ECX MSR_NEHALEM_S1_PMON_MASK (0x00000E5A)
7359 @param EAX Lower 32-bits of MSR value.
7360 @param EDX Upper 32-bits of MSR value.
7362 <b>Example usage</b>
7366 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MASK);
7367 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MASK, Msr);
7369 @note MSR_NEHALEM_S1_PMON_MASK is defined as MSR_S1_PMON_MASK in SDM.
7371 #define MSR_NEHALEM_S1_PMON_MASK 0x00000E5A
7375 Package. Uncore M-box 1 perfmon local box address match/mask config MSR.
7377 @param ECX MSR_NEHALEM_M1_PMON_MM_CONFIG (0x00000E5C)
7378 @param EAX Lower 32-bits of MSR value.
7379 @param EDX Upper 32-bits of MSR value.
7381 <b>Example usage</b>
7385 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG);
7386 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG, Msr);
7388 @note MSR_NEHALEM_M1_PMON_MM_CONFIG is defined as MSR_M1_PMON_MM_CONFIG in SDM.
7390 #define MSR_NEHALEM_M1_PMON_MM_CONFIG 0x00000E5C
7394 Package. Uncore M-box 1 perfmon local box address match MSR.
7396 @param ECX MSR_NEHALEM_M1_PMON_ADDR_MATCH (0x00000E5D)
7397 @param EAX Lower 32-bits of MSR value.
7398 @param EDX Upper 32-bits of MSR value.
7400 <b>Example usage</b>
7404 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH);
7405 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH, Msr);
7407 @note MSR_NEHALEM_M1_PMON_ADDR_MATCH is defined as MSR_M1_PMON_ADDR_MATCH in SDM.
7409 #define MSR_NEHALEM_M1_PMON_ADDR_MATCH 0x00000E5D
7413 Package. Uncore M-box 1 perfmon local box address mask MSR.
7415 @param ECX MSR_NEHALEM_M1_PMON_ADDR_MASK (0x00000E5E)
7416 @param EAX Lower 32-bits of MSR value.
7417 @param EDX Upper 32-bits of MSR value.
7419 <b>Example usage</b>
7423 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK);
7424 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK, Msr);
7426 @note MSR_NEHALEM_M1_PMON_ADDR_MASK is defined as MSR_M1_PMON_ADDR_MASK in SDM.
7428 #define MSR_NEHALEM_M1_PMON_ADDR_MASK 0x00000E5E